TW202205930A - Circuit boards and circuit modules using the same - Google Patents
Circuit boards and circuit modules using the same Download PDFInfo
- Publication number
- TW202205930A TW202205930A TW110121590A TW110121590A TW202205930A TW 202205930 A TW202205930 A TW 202205930A TW 110121590 A TW110121590 A TW 110121590A TW 110121590 A TW110121590 A TW 110121590A TW 202205930 A TW202205930 A TW 202205930A
- Authority
- TW
- Taiwan
- Prior art keywords
- thermally conductive
- conductive block
- wiring pattern
- electronic component
- wiring
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Communication Control (AREA)
Abstract
Description
本發明係關於電路基板及使用其之電路模組,尤其關於用以搭載DCDC(Direct Current/Direct Current;直流/直流)轉換器、雷射二極體、電源用電感器等之發熱量大之電子零件的電路基板及使用其之電路模組。The present invention relates to a circuit board and a circuit module using the same, and particularly to a circuit board for mounting a DCDC (Direct Current/Direct Current) converter, a laser diode, a power supply inductor, etc. with a large amount of heat. Circuit boards for electronic parts and circuit modules using them.
在多層基板之表面搭載發熱量大之電子零件的情形時,其存在有設置用以使熱釋放至多層基板之背面側之散熱路徑的情形。例如,於專利文獻1提案有如下之構造:將金屬塊埋入在俯視時與發熱量較大之電子零件重疊之位置,以複數個通孔導體連接金屬塊之表面與電子零件,並且以另外的複數個通孔導體連接金屬塊之背面與被設置在多層基板之背面的散熱圖案。被設置在多層基板之背面的散熱圖案,經由焊料等而被連接於主機板上之散熱路徑。通常,主機板上之散熱路徑係接地圖案。藉此,由於自電子零件所產生之熱會經由金屬塊而被散熱至主機板側,因此即便於電子零件之發熱量較大之情形時,仍可得到較高的散熱效率。
[先前技術文獻]
[專利文獻]When an electronic component with a large amount of heat is mounted on the surface of the multilayer substrate, there is a case where a heat dissipation path for releasing the heat to the back side of the multilayer substrate is provided. For example,
專利文獻1:日本專利特開2019-46954號公報Patent Document 1: Japanese Patent Laid-Open No. 2019-46954
(發明所欲解決之問題)(The problem that the invention intends to solve)
然而,於專利文獻1所記載之電路基板中,由於成為散熱對象之電子零件與主機板上之散熱路徑會電性地短路,因此無法一邊將二者電性地絕緣一邊進行散熱。例如,於搭載雷射二極體或電源用電感器等不僅發熱量大且與接地圖案之連接被禁止的類型之電子零件的情形時,則無法採用專利文獻1所記載之構造。However, in the circuit board described in
因此,本發明之目的,在於提供可一邊將成為散熱對象之電子零件與主機板上之散熱路徑電性地絕緣,一邊得到高散熱效率的電路基板及使用其之電路模組。 (解決問題之技術手段)Therefore, an object of the present invention is to provide a circuit board and a circuit module using the same which can obtain high heat dissipation efficiency while electrically insulating the electronic components to be heat dissipation objects from the heat dissipation paths on the motherboard. (Technical means to solve problems)
本發明之電路基板,其特徵在於,其具備有:基板,其由複數層配線層與複數層絕緣層交互地被層積而成,該複數層配線層至少包含第一及第二配線層,而該複數層絕緣層至少包含位在第一及第二配線層之間的第一絕緣層;導熱塊,其由被埋入第一絕緣層之絕緣性陶瓷材料所構成;第一配線圖案,其位於第一配線層,與導熱塊之一表面相接;以及第二配線圖案,其位於第二配線層,與導熱塊之另一表面相接;而導熱塊之一表面具有複數個第一凹部,第一配線圖案之一部分被埋入複數個第一凹部。The circuit board of the present invention is characterized by comprising: a board formed by alternately laminating a plurality of wiring layers and a plurality of insulating layers, the plurality of wiring layers including at least first and second wiring layers, The plurality of insulating layers include at least a first insulating layer located between the first and second wiring layers; a thermally conductive block made of insulating ceramic material embedded in the first insulating layer; a first wiring pattern, It is located on the first wiring layer and is in contact with one surface of the thermally conductive block; and the second wiring pattern is located in the second wiring layer and is in contact with the other surface of the thermally conductive block; and one surface of the thermally conductive block has a plurality of first In the concave portion, a portion of the first wiring pattern is embedded in the plurality of first concave portions.
根據本發明,由於導熱塊由絕緣性陶瓷材料所構成,因此可一邊確保第一配線圖案與第二配線圖案之絕緣,一邊進行經由導熱塊的散熱。而且,由於第一配線圖案被埋入導熱塊之凹部,因此亦難以發生因二者間之熱膨脹係數的差所導致的剝離。According to the present invention, since the thermally conductive block is made of an insulating ceramic material, heat dissipation through the thermally conductive block can be performed while ensuring insulation between the first wiring pattern and the second wiring pattern. Furthermore, since the first wiring pattern is buried in the concave portion of the thermally conductive block, peeling due to the difference in thermal expansion coefficient between the two is also less likely to occur.
於本發明中,亦可為第一及第二配線圖案之至少一者經由被設置在第一絕緣層之複數個通孔而於複數個部位與導熱塊之一表面或另一表面相接。藉此,可確保被埋入導熱塊之平面位置處的平坦性。In the present invention, at least one of the first and second wiring patterns may be connected to one surface or the other surface of the thermally conductive block at a plurality of locations through a plurality of through holes provided in the first insulating layer. Thereby, the flatness at the plane position embedded in the thermally conductive block can be ensured.
於本發明中,亦可為第一配線圖案經由被設置在第一絕緣層之既定的通孔而與導熱塊之一表面相接,且既定的通孔與複數個第一凹部重疊。藉此,由於第一配線圖案與導熱塊之接觸面積增大,因此可得到更高之散熱特性。In the present invention, the first wiring pattern may be in contact with a surface of the thermally conductive block through a predetermined through hole provided in the first insulating layer, and the predetermined through hole overlaps with the plurality of first recesses. Thereby, since the contact area between the first wiring pattern and the thermally conductive block is increased, higher heat dissipation characteristics can be obtained.
於本發明中,亦可為導熱塊之另一表面具有複數個第二凹部,且第二配線圖案之一部分被埋入複數個第二凹部。藉此,難以發生第二配線圖案與導熱塊之界面處的剝離。於該情形時,亦可為複數個第一凹部之平面位置與複數個第二凹部之平面位置互不相同。藉此,即便於凹部之深度較大之情形時,仍可確保第一配線圖案與第二配線圖案的絕緣。此外,於該情形時,亦可為複數個第一凹部之平均深度與複數個第二凹部之平均深度的和,大於導熱塊的厚度。藉此,其可更有效地防止第一及第二配線圖案的剝離,並且可得到更高之散熱性。In the present invention, the other surface of the thermally conductive block may also have a plurality of second concave portions, and a portion of the second wiring pattern may be embedded in the plurality of second concave portions. Thereby, peeling at the interface of the second wiring pattern and the thermally conductive block hardly occurs. In this case, the plane positions of the plurality of first concave portions and the plane positions of the plurality of second concave portions may be different from each other. Thereby, even when the depth of the concave portion is large, the insulation of the first wiring pattern and the second wiring pattern can be ensured. In addition, in this case, the sum of the average depth of the plurality of first concave portions and the average depth of the plurality of second concave portions may be greater than the thickness of the thermally conductive block. Thereby, it can prevent peeling of the 1st and 2nd wiring pattern more effectively, and can obtain higher heat dissipation.
於本發明中,亦可為絕緣性陶瓷材料由氮化矽所構成。藉此,即便於使導熱塊之厚度薄至例如150μm以下之情形時,仍難以發生破損。In the present invention, the insulating ceramic material may be composed of silicon nitride. Thereby, even when the thickness of the thermally conductive block is reduced to, for example, 150 μm or less, it is difficult to break.
於本發明中,亦可為導熱塊之一表面與另一表面的表面粗度互不相同。藉此,可一邊抑制導熱塊之製造成本,一邊在表面粗度較小之面上防止孔洞的發生,並於表面粗度較大之面上防止因熱膨脹係數的差所導致的剝離。In the present invention, the surface roughness of one surface and the other surface of the thermally conductive block may be different from each other. Thereby, while suppressing the manufacturing cost of a thermally conductive block, generation|occurence|production of a hole can be prevented on the surface with a small surface roughness, and peeling by the difference of a thermal expansion coefficient can be prevented on the surface with a large surface roughness.
本發明之電路基板亦可進一步具備有:第一電子零件,其被埋入第一絕緣層;而第一電子零件具有供信號端子設置之主面,且信號端子被連接至第一配線圖案。藉此,可使電路基板更高功能化。於該情形時,亦可使導熱塊較第一電子零件薄。藉此,當搭載第一電子零件時,導熱塊則不會成為阻礙。The circuit board of the present invention may further include: a first electronic component embedded in the first insulating layer; and the first electronic component has a main surface on which a signal terminal is provided, and the signal terminal is connected to the first wiring pattern. Thereby, the circuit board can be further functionalized. In this case, the thermally conductive block can also be made thinner than the first electronic component. Thereby, when the first electronic component is mounted, the thermally conductive block does not become a hindrance.
本發明之電路模組,其特徵在於,其具備有:上述之電路基板;及第二電子零件,其被搭載於第一配線圖案露出之電子零件搭載區域;而第一電子零件與第二電子零件經由第一配線圖案相互地被連接。The circuit module of the present invention is characterized by comprising: the above-mentioned circuit board; and a second electronic component mounted on the electronic component mounting area exposed by the first wiring pattern; and the first electronic component and the second electronic component The components are connected to each other via the first wiring pattern.
根據本發明,由於第一配線圖案與第二配線圖案被絕緣,因此可經由第一配線圖案將電流自第一電子零件供給至第二電子零件。According to the present invention, since the first wiring pattern and the second wiring pattern are insulated from each other, current can be supplied from the first electronic component to the second electronic component via the first wiring pattern.
於本發明中,亦可為第二電子零件係雷射二極體或電源用電感器。雷射二極體與電源用電感器雖為發熱量大且與接地圖案之連接被禁止之類型的電子零件,但即便為如此之電子零件,仍可經由電路基板而效率良好地散熱。 (對照先前技術之功效) In the present invention, the second electronic component may be a laser diode or a power supply inductor. Laser diodes and power supply inductors are electronic components that generate a large amount of heat and are prohibited from being connected to the ground pattern, but even such electronic components can be efficiently dissipated through the circuit board. (Compared to the efficacy of the prior art)
如此,根據本發明,可提供可一邊將成為散熱對象之電子零件與主機板上之散熱路徑電性地絕緣,一邊得到高散熱效率的電路基板及使用其之電路模組。In this way, according to the present invention, it is possible to provide a circuit board and a circuit module using the same that can obtain high heat dissipation efficiency while electrically insulating the electronic components to be heat dissipation objects from the heat dissipation paths on the motherboard.
以下,一邊參照添附圖式,一邊對本發明之較佳實施形態詳細地進行說明。Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
圖1係用以說明本發明之較佳實施形態之電路基板1之構造的示意性剖視圖。FIG. 1 is a schematic cross-sectional view for explaining the structure of a
如圖1所示,本實施形態之電路基板1具備有基板10、被埋入基板10之電子零件30及導熱塊40。於基板10之上表面10a側設置有電子零件搭載區域A,且電子零件30對被搭載於電子零件搭載區域A之電子零件進行控制。電子零件30具備有一對信號端子31、32與電源端子33等。As shown in FIG. 1 , the
基板10具有三層絕緣層11~13被層積之構造,且於各絕緣層11~13之表面設置有由銅(Cu)等所構成之配線層L1~L4。雖未特別限定,但位於最上層之絕緣層11及位於最下層之絕緣層13亦可為使玻璃環氧樹脂等之樹脂材料含浸於玻璃纖維等之芯材而得的芯層。相對於此,絕緣層12由絕緣層12a、12b所構成,且亦可為由不包含玻璃布等之芯材之樹脂材料所構成者。尤其,絕緣層11、13之熱膨脹係數較佳者係小於絕緣層12之熱膨脹係數。The
於配線層L1形成有配線圖案P11~P13,於配線層L2形成有配線圖案P21~P24,於配線層L3形成有配線圖案P34,而於配線層L4形成有配線圖案P41、P44。配線層L1位於基板10之上表面10a側,其一部分由阻焊劑21所覆蓋。然而,配線圖案P11的整個面及配線圖案P12之一部分未由阻焊劑21所覆蓋,而被ENEPIG(Electroless Nickel Electroless Palladium Immersion Gold;化學鍍鎳鈀浸金)皮膜19所覆蓋。自阻焊劑21露出之配線圖案P11,位於電子零件搭載區域A。又,自阻焊劑21露出之配線圖案P12構成焊墊B。另一方面,配線層L4位於基板10之背面10b側,其一部分由阻焊劑22所覆蓋。然而,配線圖案P41、 P44之一部分未由阻焊劑22所覆蓋,而被ENEPIG皮膜19所覆蓋。Wiring patterns P11 to P13 are formed on wiring layer L1, wiring patterns P21 to P24 are formed on wiring layer L2, wiring pattern P34 is formed on wiring layer L3, and wiring patterns P41 and P44 are formed on wiring layer L4. The wiring layer L1 is located on the side of the
導熱塊40係構成用以使熱自上表面10a側釋放至背面10b側之散熱路徑的片狀零件,具有面向上表面10a側之表面41、及面向背面10b側之表面42。導熱塊40由絕緣性陶瓷材料所構成。作為絕緣性陶瓷材料,雖只要為具有絕緣性且熱傳導率較絕緣層12夠高之材料即可,其雖無特別之限制,但可選擇氮化鋁(AlN)或氮化矽(SiN)。氮化鋁雖具有熱傳導率非常高之特徵,但由於具脆性,因此難以將厚度設為150μm以下。相對於此,氮化矽雖熱傳導率較氮化鋁低,但因為彎曲強度較高,所以具有即便在將厚度加工至150μm以下之情形時仍難以發生破損之特徵。於本實施形態中,由於導熱塊40之厚度T2較電子零件30之厚度T1薄,因此於電子零件30被薄型化至150μm以下之情形時,作為導熱塊40之材料較佳者係選擇氮化矽。The heat-conducting
配線層L1與配線層L2經由貫通絕緣層11所設之複數個通孔導體而被連接。例如,配線圖案P11與配線圖案P21經由作為配線圖案P11之一部分的通孔導體V11而被連接,配線圖案P12與配線圖案P22經由作為配線圖案P12之一部分的通孔導體V12而被連接,配線圖案P13與配線圖案P23經由作為配線圖案P13之一部分的通孔導體V13而被連接,而配線圖案P13與配線圖案P24經由作為配線圖案P13之一部分的通孔導體V14而被連接。The wiring layer L1 and the wiring layer L2 are connected via a plurality of via-hole conductors provided through the
配線層L2、配線層L3、電子零件30及導熱塊40經由複數個通孔導體而被連接。例如,配線圖案P21與導熱塊40之表面41經由作為配線圖案P21之一部分的通孔導體V20而被連接,配線圖案P21與電子零件30之信號端子31經由作為配線圖案P21之一部分的通孔導體V21而被連接,配線圖案P22與電子零件30之信號端子32經由作為配線圖案P22之一部分的通孔導體V22而被連接,配線圖案P23與電子零件30之電源端子33經由作為配線圖案P23之一部分的通孔導體V23而被連接,而配線圖案P24與配線圖案P34經由作為配線圖案P24之一部分且貫通絕緣層12、13所設之通孔導體V24而被連接。此處,電子零件30之端子31~33由於為微距,因此若設置有端子31~32之主面30a與絕緣層12a之表面的距離較大,便難以以微距來形成埋入通孔導體V21~V23之通孔,但於本實施形態中,由於導熱塊40之厚度T2較電子零件30之厚度T1薄,因此可使電子零件30之主面30a與絕緣層12a之表面的距離變小。The wiring layer L2, the wiring layer L3, the
配線層L4、配線層L3及導熱塊40經由複數個通孔導體而被連接。例如,配線圖案P41與導熱塊40之表面42經由作為配線圖案P41之一部分的通孔導體V30而被連接,而配線圖案P44與配線圖案P34經由作為配線圖案P44之一部分且貫通絕緣層13所設之通孔導體V34而被連接。The wiring layer L4, the wiring layer L3, and the thermally
圖2係導熱塊40之放大圖。FIG. 2 is an enlarged view of the thermally
如圖2所示,導熱塊40之表面41具有平坦部41a與複數個凹部41b。同樣地,導熱塊40之表面42具有平坦部42a與複數個凹部42b。而且,作為配線圖案P21之一部分的通孔導體V20,前端部被埋入凹部41b,而作為配線圖案P41之一部分的通孔導體V30,前端部被埋入凹部42b。通孔導體V20、V30其一部分亦可分別與平坦部41a、42a相接。As shown in FIG. 2 , the
此處,構成通孔導體V20、V30之銅與構成導熱塊40之絕緣性陶瓷材料,由於熱膨脹係數互不相同,因此應力會因溫度變化而施加於二者的界面。然而,於本實施形態中,由於通孔導體V20、V30之一部分被埋入導熱塊40之凹部41b、42b,因此藉由錨定效果,而難以發生因熱膨脹係數的差所導致之界面處的剝離。而且,通孔導體V20與通孔導體V30之距離變得更近,因此,熱傳導性亦提升。此外,於不存在通孔導體V20、V30之區域,由於絕緣層12介存於導熱塊40與配線圖案P21、P41之間,因此亦可確保導熱塊40被埋入之平面位置處的平坦性。Here, the copper constituting the via-hole conductors V20 and V30 and the insulating ceramic material constituting the thermally
在圖2所示之例子中,雖然凹部41b之平面位置與凹部42b之平面位置互不相同,但於本發明中並非必須者,二者之平面位置亦可為一致者。然而,於凹部41b之平面位置與凹部42b之平面位置互不相同之情形時,例如圖3所示般,即便於凹部41b、42b之深度較深之情形時,尤其於凹部41b之平均深度與凹部42b之平均深度的和大於導熱塊40之厚度之情形時,通孔導體V20與通孔導體V30亦不會短路。如此,若使凹部41b、42b之深度變深,而將通孔導體V20、V30埋入其內部,便可得到更高之錨定效果,並且更加提升熱傳導性。In the example shown in FIG. 2 , although the plane position of the
又,如圖4所示,亦可藉由將與複數個凹部41b重疊之大口徑的通孔形成在絕緣層12a,不僅凹部41b,而亦使平坦部41a之大部分與配線圖案P21接觸。此外,如圖5所示,亦可藉由將與複數個凹部41b、42b重疊之大口徑的通孔形成在絕緣層12a、12b,而使平坦部41a、42a之大部分分別與配線圖案P21、P41接觸。藉此,可更加提高散熱性。Furthermore, as shown in FIG. 4 , by forming large-diameter through holes overlapping the plurality of
圖6係用以說明使用電路基板1之電路模組2之構造的示意性剖視圖。FIG. 6 is a schematic cross-sectional view for explaining the structure of the
如圖6所示,電路模組2由圖1所示之電路基板1、及被搭載於電路基板1之電子零件搭載區域A之電子零件50所構成。雖未被特別限定,但電子零件50可例如為雷射二極體。由於雷射二極體之發熱量大,並且於特性上與接地圖案之連接被禁止,因此無法如一般電子零件般藉由與接地圖案連接而散熱。其相同之電子零件,可列舉電源用電感器。As shown in FIG. 6 , the
圖6所示之電子零件50由信號端子51、52之2端子所構成。其中,信號端子51被形成於電子零件50之背面,經由焊料60而被連接於位在電子零件搭載區域A之配線圖案P11。由於信號端子51係形成在電子零件50之整個背面上,因此,藉由電子零件50之動作所產生之熱,可效率良好地傳遞至配線圖案P11。另一方面,信號端子52被形成於電子零件50之上表面,經由接線61而被連接於由配線圖案P12所構成的焊墊B。而且,於電子零件50為雷射二極體之情形時,雷射光藉由施加於信號端子51、52的信號所生成。信號端子51經由焊料60、配線圖案P11、通孔導體V11、配線圖案P21及通孔導體V21而被連接於電子零件30之信號端子31。又,信號端子52經由接線61、配線圖案P12、通孔導體V12、配線圖案P22及通孔導體V22而被連接於電子零件30之信號端子32。The
自電子零件50被傳遞至配線圖案P11的熱,經由複數個通孔導體V11、配線圖案P21及複數個通孔導體V20而被傳遞至導熱塊40。而且,被傳遞至導熱塊40的熱,經由複數個通孔導體V30而被傳遞至配線圖案P41,該配線圖案P41係作為散熱圖案而發揮功能。於實際使用時,配線圖案P41係經由焊料62而被連接於主機板3之接地圖案G。藉此,因電子零件50之動作所產生的熱,經由導熱塊40而效率良好地被散熱至主機板3。The heat transferred from the
而且,於本實施形態中,由於導熱塊40由絕緣性陶瓷材料所構成,因此即便通孔導體V20與通孔導體V30皆與導熱塊40相接,仍可確保二者的絕緣。藉此,可將配線圖案P11設為信號線,並將配線圖案P41設為接地圖案。而且,於本實施形態中,由於導熱塊40被埋入與電子零件30相同之層,因此層數不會為了要埋入導熱塊40而增加。又,由於在導熱塊40之表面41、42設置有複數個凹部41b、42b,因此可防止導熱塊40與通孔導體V20、V30之界面處的剝離。此外,於本實施形態中,由於導熱塊40的厚度T2較電子零件30之厚度T1薄,因此亦可使通孔導體V21~V23的深度變小。Furthermore, in the present embodiment, since the thermally
其次,對本實施形態之電路基板1之製造方法進行說明。Next, the manufacturing method of the
圖7至圖20係用以說明本實施形態之電路基板1之製造方法的步驟圖。FIG. 7 to FIG. 20 are step diagrams for explaining the manufacturing method of the
首先,如圖7所示,準備如下的基材(工件板):於包含玻璃纖維等之芯材之絕緣層13的一表面形成有金屬膜L3a,而於另一表面形成有金屬膜L4a。First, as shown in FIG. 7 , a base material (work plate) is prepared in which a metal film L3a is formed on one surface of an insulating
其次,如圖8所示,使用微影法等將金屬膜L3a圖案化(Patterning),藉此形成配線層L3。其次,如圖9所示,以埋入配線層L3之方式,藉由真空壓接等將例如未硬化(B階段狀態)之樹脂片等層積於絕緣層13之表面,藉此形成絕緣層12b。Next, as shown in FIG. 8, the wiring layer L3 is formed by patterning the metal film L3a using a lithography method or the like. Next, as shown in FIG. 9, an insulating layer is formed by laminating, for example, an uncured (B-stage state) resin sheet or the like on the surface of the insulating
其次,如圖10所示,在將導熱塊40載置於絕緣層12b之表面後,如圖11所示將電子零件30載置於絕緣層12b之表面。電子零件30例如為裸晶狀態之半導體IC,且以面朝上之方式被搭載為端子形成面朝向上側。導熱塊40及電子零件30的載置順序雖亦可顛倒,但藉由先載置導熱塊40,則可防止電子零件30之端子形成面與導熱塊40的接觸。又,於本實施形態中,由於導熱塊40較電子零件30薄,因此藉由先載置導熱塊40,當載置電子零件30時所使用的吸附頭,便不會與導熱塊40產生干涉。藉此,可使導熱塊40與電子零件30之空間接近至500μm以下。Next, as shown in FIG. 10 , after placing the thermally
此處,存在有在導熱塊40之表面42的表面粗度較大之情形時,於絕緣層12b與導熱塊40的表面42之間產生孔洞之情形。尤其,於藉由燒成來製作由氮化矽所構成之導熱塊40的情形時,燒成後之導熱塊40的表面粗度Rz約為40μm,而存在有若直接將其載置於絕緣層12b時便會產生孔洞的可能性。為了防止該情形,較佳係藉由研磨等而使導熱塊40之表面42平滑化,具體而言,較佳係將導熱塊40之表面42的表面粗度Rz設為20μm以下。此處,表面粗度Rz係由JIS(Japanese Industrial Standards;日本產業標準) B 0601:1994所規定之十點平均粗度來定義。相對於此,關於導熱塊40之表面41,由於如後述般由未硬化或半硬化狀態之絕緣層12a所覆蓋,因此即便表面粗度較大亦難以產生孔洞。因此,有關導熱塊40之表面41,藉由研磨等使其平滑化的必要性較低。亦即,導熱塊40之表面41的表面粗度亦可大於表面42的表面粗度。若省略對導熱塊40之表面41的平滑化處理,則可削減導熱塊40的製造成本。又,若導熱塊40之表面41的表面粗度較大,則可防止因熱膨脹係數的差所導致的剝離。Here, when the surface roughness of the
其次,如圖12所示,以覆蓋電子零件30及導熱塊40的方式來形成絕緣層12a及金屬膜L2a。絕緣層12a之形成,較佳係例如於塗佈未硬化或半硬化狀態之熱硬化性樹脂後,在未硬化樹脂之情形時進行加熱而使其半硬化,而且使用加壓手段而與金屬膜L2a一起硬化成形。作為絕緣層12a,較佳係不包含會妨礙電子零件30及導熱塊40之埋入之纖維的樹脂片。Next, as shown in FIG. 12 , the insulating
其次,如圖13所示,例如於使用微影法等周知之方法並利用蝕刻來去除金屬膜L2a之一部分後,對金屬膜L2a已被去除之既定部位進行周知之噴砂加工或雷射加工,藉此形成通孔80~82。其中,通孔80貫通絕緣層12a、12b而被設置,配線層L3露出於通孔80之底部。又,通孔81使導熱塊40之表面41露出,而通孔82使電子零件30之信號端子31、32及電源端子33露出。此時,以於導熱塊40之表面41形成凹部41b之方式,來設定噴砂加工或雷射加工的條件。例如,藉由進行改變雷射之能量或珠擊粒徑的二階段加工、或雷射加工與噴砂加工的組合加工,來形成凹部41b。Next, as shown in FIG. 13, after removing a part of the metal film L2a by etching using a known method such as lithography, for example, a known sandblasting or laser processing is performed on a predetermined portion of the metal film L2a from which the metal film L2a has been removed. Thereby, through
其次,如圖14所示,藉由實施無電解電鍍及電解電鍍,而於絕緣層12a之表面形成金屬膜L2b,並且於通孔80~82之內部形成通孔導體V20~V24。因此,通孔導體V20~V24係金屬膜L2b之一部分。藉此,通孔導體V20與導熱塊40之表面41相接,通孔導體V21、V22與電子零件30之信號端子31、32相接,通孔導體V23與電子零件30之電源端子33相接,而通孔導體V24與配線層L3相接。其中,通孔導體V20之一部分被埋入在導熱塊40所設置之複數個凹部41b。當進行無電解電鍍及電解電鍍時導熱塊40雖暴露於電解液中,但作為導熱塊40之材料若使用氮化矽,便會與使用氮化鋁之情形不同,而幾乎不會產生朝向電解液池的溶出。其後,如圖15所示,使用微影法等對金屬膜L2b進行成形,藉此形成配線層L2。Next, as shown in FIG. 14, by performing electroless plating and electrolytic plating, a metal film L2b is formed on the surface of the insulating
其次,如圖16所示,以埋入配線層L2之方式,對層積有絕緣層11與金屬膜L1a之片材進行真空熱加壓。使用於絕緣層11之材料及厚度亦可與絕緣層13相同。Next, as shown in FIG. 16 , the sheet on which the insulating
其次,如圖17所示,例如於使用微影法等周知之方法並藉由蝕刻來去除金屬膜L1a、L4a之一部分後,對金屬膜L1a、L4a已被去除之既定部位進行周知之噴砂加工或雷射加工,藉此於絕緣層11形成通孔91~94,並於絕緣層13形成通孔95、96。其中,通孔91~94貫通絕緣層11而被設置,配線圖案P21~P24分別露出於通孔91~94之底部。又,通孔95貫通絕緣層13、12b而被設置,導熱塊40之表面42露出於通孔95之底部。此外,通孔96貫通絕緣層13而被設置,配線圖案P34露出於通孔96之底部。此時,設定噴砂加工或雷射加工的條件以於導熱塊40之表面42形成凹部42b。例如,藉由進行改變雷射之能量或珠擊粒徑的二階段加工、或雷射加工與噴砂加工的組合加工,來形成凹部42b。Next, as shown in FIG. 17, after removing part of the metal films L1a and L4a by etching using a known method such as lithography, for example, a known sandblasting process is performed on the predetermined portions where the metal films L1a and L4a have been removed. Or laser processing, whereby through
其次,如圖18所示,藉由實施無電解電鍍及電解電鍍,而於絕緣層11、13之表面分別形成金屬膜L1b、L4b,並且於通孔91~96之內部分別形成通孔導體V11~V14、V30、V34。藉此,通孔導體V11~V14分別與配線圖案P11~P14相接,通孔導體V30與導熱塊40之表面42相接,而通孔導體V34與配線圖案P34相接。其中,通孔導體V30之一部分被埋入在導熱塊40所設置之複數個凹部42b。其後,如圖19所示,使用微影法等將金屬膜L1b、L4b圖形化,藉此形成配線層L1、L4。Next, as shown in FIG. 18, by performing electroless plating and electrolytic plating, metal films L1b and L4b are formed on the surfaces of the insulating
然後,如圖20所示,於在絕緣層11、13之表面分別形成阻焊劑21、22後,若藉由對自阻焊劑21、22露出之配線圖案P11、P12、P41、P44進行零件安裝用之表面處理來形成ENEPIG皮膜19,則完成圖1所示之電路基板1。Then, as shown in FIG. 20, after the solder resists 21, 22 are formed on the surfaces of the insulating
再者,於上述實施形態中,雖電子零件30與導熱塊40雖被埋入同一層,但於本發明中其並非必須者,二者亦可被埋入互不相同之層。於該情形時,既可如圖21所示般,電子零件30之一部分與導熱塊40之一部分於俯視時有重疊,亦可如圖22所示般,電子零件30之全部與導熱塊40之一部分於俯視時有重疊。Furthermore, in the above-mentioned embodiment, although the
以上,雖已對本發明之較佳實施形態進行說明,但本發明並不限定於上述之實施形態,其可在不脫離本發明主旨之範圍內進行各種變更,且該等當然亦包含於本發明之範圍內。The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention, and these are of course also included in the present invention within the range.
例如,於上述實施形態中,雖然被搭載於電路基板1之電子零件50之一信號端子51位於背面側,而另一信號端子52位於上表面側,但被搭載於電路基板1之電子零件並不存在具有如此構成的必要,兩信號端子亦可位於上表面側或背面側。For example, in the above-described embodiment, one
又,內置於基板10之導熱塊的數量,亦可並非限定於一個,亦可將複數個導熱塊埋入基板10。In addition, the number of thermally conductive blocks built into the
此外,在上述之電路基板1之製造方法中,雖然與通孔81、95之形成同時地在導熱塊40形成凹部41b、42b,但亦可將預先形成有凹部41b、42b之導熱塊埋入絕緣層12。In addition, in the above-mentioned manufacturing method of the
又,如圖23所示之變形例的電路基板1A,其亦可以包圍電子零件50來配置導熱塊40。藉此,則可提升電路基板1A之機械強度。Moreover, the
1、1A:電路基板
2:電路模組
3:主機板
10:基板
10a:基板之上表面
10b:基板之背面
11~13、12a、12b:絕緣層
19:ENEPIG皮膜
21、22:阻焊劑
30:電子零件
30a:電子零件之主面
31、32:信號端子
33:電源端子
40:導熱塊
41、42:導熱塊之表面
41a、42a:平坦部
41b、42b:凹部
50:電子零件
51、52:信號端子
60、62:焊料
61:接線
80~82、91~96:通孔
A:電子零件搭載區域
B:焊墊
G:接地圖案
L1~L4:配線層
L1a、L1b、L2a、L2b、L3a、L4a、L4b:金屬膜
P11~P14、P21~P24、P34、P41、P44:配線圖案
V11~V14、V20~V24、V30、V34:通孔導體
T1:(電子零件之)厚度
T2:(導熱塊之)厚度1. 1A: circuit substrate
2: circuit module
3: Motherboard
10:
圖1係用以說明本發明之較佳實施形態之電路基板1之構造的示意性剖視圖。
圖2係導熱塊40的放大圖。
圖3係表示將導熱塊40之凹部41b、42b設為較深之例子的圖。
圖4係表示在絕緣層12a形成大口徑之通孔之例子的圖。
圖5係表示在絕緣層12a、12b形成大口徑之通孔之例子的圖。
圖6係用以說明使用電路基板1之電路模組2之構造的示意性剖視圖。
圖7係用以說明電路基板1之製造方法的步驟圖。
圖8係用以說明電路基板1之製造方法的步驟圖。
圖9係用以說明電路基板1之製造方法的步驟圖。
圖10係用以說明電路基板1之製造方法的步驟圖。
圖11係用以說明電路基板1之製造方法的步驟圖。
圖12係用以說明電路基板1之製造方法的步驟圖。
圖13係用以說明電路基板1之製造方法的步驟圖。
圖14係用以說明電路基板1之製造方法的步驟圖。
圖15係用以說明電路基板1之製造方法的步驟圖。
圖16係用以說明電路基板1之製造方法的步驟圖。
圖17係用以說明電路基板1之製造方法的步驟圖。
圖18係用以說明電路基板1之製造方法的步驟圖。
圖19係用以說明電路基板1之製造方法的步驟圖。
圖20係用以說明電路基板1之製造方法的步驟圖。
圖21係用以說明電子零件30與導熱塊40位於互不相同之層之第一例的示意圖。
圖22係用以說明電子零件30與導熱塊40位於互不相同之層之第二例的示意圖。
圖23係用以說明變形例之電路基板1A之構造的示意性剖視圖。FIG. 1 is a schematic cross-sectional view for explaining the structure of a
1:電路基板 1: circuit board
10:基板 10: Substrate
10a:基板之上表面 10a: upper surface of substrate
10b:基板之背面 10b: Backside of substrate
11~13、12a、12b:絕緣層 11~13, 12a, 12b: insulating layer
19:ENEPIG皮膜 19: ENEPIG film
21、22:阻焊劑 21, 22: Solder resist
30:電子零件 30: Electronic Parts
30a:電子零件之主面 30a: Main surface of electronic parts
31、32:信號端子 31, 32: Signal terminals
33:電源端子 33: Power terminal
40:導熱塊 40: Thermal block
41、42:導熱塊之表面 41, 42: The surface of the thermally conductive block
A:電子零件搭載區域 A: Electronic parts mounting area
B:焊墊 B: Solder pad
L1~L4:配線層 L1~L4: wiring layer
P11~P13、P21~P24、P34、P41、P44:配線圖案 P11~P13, P21~P24, P34, P41, P44: Wiring pattern
V11~V14、V20~V24、V30、V34:通孔導體 V11~V14, V20~V24, V30, V34: Through-hole conductors
T1:(電子零件之)厚度 T1: Thickness (of electronic parts)
T2:(導熱塊之)厚度 T2: (the thickness of the thermal conductive block)
Claims (13)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020-118352 | 2020-07-09 | ||
JP2020118352A JP7384121B2 (en) | 2020-07-09 | 2020-07-09 | Circuit board and circuit module using the same |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202205930A true TW202205930A (en) | 2022-02-01 |
TWI817140B TWI817140B (en) | 2023-10-01 |
Family
ID=79552856
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW110121590A TWI817140B (en) | 2020-07-09 | 2021-06-15 | Circuit boards and circuit modules using the same |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP7384121B2 (en) |
TW (1) | TWI817140B (en) |
WO (1) | WO2022009527A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI814426B (en) * | 2022-05-31 | 2023-09-01 | 大陸商鵬鼎控股(深圳)股份有限公司 | Circuit board and method for manufacturing thereof |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2024010021A1 (en) * | 2022-07-05 | 2024-01-11 | 京セラ株式会社 | Substrate, electronic device, electronic module, and module device |
WO2024010022A1 (en) * | 2022-07-05 | 2024-01-11 | 京セラ株式会社 | Substrate, electronic device, electronic module, and module device |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7405102B2 (en) | 2006-06-09 | 2008-07-29 | Freescale Semiconductor, Inc. | Methods and apparatus for thermal management in a multi-layer embedded chip structure |
TWI328423B (en) * | 2007-09-14 | 2010-08-01 | Unimicron Technology Corp | Circuit board structure having heat-dissipating structure |
JP2014168053A (en) | 2013-01-31 | 2014-09-11 | Kyocera Corp | Circuit board and electronic apparatus including the same |
US9220184B2 (en) | 2013-03-15 | 2015-12-22 | Hamilton Sundstrand Corporation | Advanced cooling for power module switches |
DE102013019617B4 (en) | 2013-11-25 | 2015-07-02 | Tesat-Spacecom Gmbh & Co.Kg | High voltage electrical component for use in a satellite and satellite therewith |
JP2018207081A (en) | 2017-06-09 | 2018-12-27 | イビデン株式会社 | Printed wiring board and manufacturing method therefor |
US11398354B2 (en) * | 2018-10-31 | 2022-07-26 | Tdk Corporation | Thin film capacitor, manufacturing method therefor, and substrate with built-in electronic component |
-
2020
- 2020-07-09 JP JP2020118352A patent/JP7384121B2/en active Active
-
2021
- 2021-05-18 WO PCT/JP2021/018728 patent/WO2022009527A1/en active Application Filing
- 2021-06-15 TW TW110121590A patent/TWI817140B/en active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI814426B (en) * | 2022-05-31 | 2023-09-01 | 大陸商鵬鼎控股(深圳)股份有限公司 | Circuit board and method for manufacturing thereof |
Also Published As
Publication number | Publication date |
---|---|
JP2022015483A (en) | 2022-01-21 |
JP7384121B2 (en) | 2023-11-21 |
TWI817140B (en) | 2023-10-01 |
WO2022009527A1 (en) | 2022-01-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW202205930A (en) | Circuit boards and circuit modules using the same | |
JP6506719B2 (en) | METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD HAVING ULTRA-SMALL RADIATOR | |
CN105472865B (en) | Circuit board including heat transfer structure | |
KR20100006685A (en) | Manufacturing method of printed circuit board having electro component | |
JP2017520902A (en) | Circuit board and circuit board assembly | |
JP2013229548A (en) | Electronic component built-in substrate and manufacturing method of the same | |
JP2008124247A (en) | Substrate with built-in component and its manufacturing method | |
KR20180010091A (en) | Metal printed circuit board and method for manufacturing the same | |
US11672076B2 (en) | Component carrier with protruding thermally conductive tongue and corresponding method of manufacturing | |
WO2007105880A1 (en) | Manufacturing method of radiant heat circuit board | |
TWI744943B (en) | Electronic component embedded substrate and circuit module using the same | |
KR20090123032A (en) | Method of manufacturing printed circuit board embedded with semiconductor chip | |
KR20160038359A (en) | Circuit Board including the heat dissipation structure | |
WO2013125033A1 (en) | Circuit board manufacturing method | |
US11545412B2 (en) | Package structure and manufacturing method thereof | |
KR100803960B1 (en) | Package on package substrate and the manufacturing method thereof | |
JP2006165242A (en) | Printed-wiring board and its manufacturing method | |
KR100917028B1 (en) | Anodized metal board its preparation manufacturing method | |
KR20120009258A (en) | Radiant heat printed circuit board and fabicating method of the same | |
KR101205431B1 (en) | Method of manufacturing a copper-core printed circuit board with efficient heat dissipation | |
JP7161629B1 (en) | Substrate with built-in component and method for manufacturing the same | |
KR102070516B1 (en) | Method for manufacturing metal printed circuit board | |
EP3996473A1 (en) | Component carrier with electronic components and thermally conductive blocks on both sides | |
KR100827310B1 (en) | Printed Circuit Board and the method of manufacturing thereof | |
JP2018207081A (en) | Printed wiring board and manufacturing method therefor |