TW202203416A - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TW202203416A
TW202203416A TW110107200A TW110107200A TW202203416A TW 202203416 A TW202203416 A TW 202203416A TW 110107200 A TW110107200 A TW 110107200A TW 110107200 A TW110107200 A TW 110107200A TW 202203416 A TW202203416 A TW 202203416A
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Taiwan
Prior art keywords
substrate
connection
package
semiconductor
pads
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TW110107200A
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English (en)
Inventor
高永權
姜芸炳
柳在炅
李澤勳
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南韓商三星電子股份有限公司
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Publication of TW202203416A publication Critical patent/TW202203416A/zh

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Abstract

本發明提供一種半導體封裝，包含：封裝基底；連接基底，位於封裝基底上且在連接基底的下部隅角上具有面向封裝基底的頂部表面的凹口；半導體晶片，位於連接基底上；多個第一連接端子，將連接基底連接至半導體晶片；以及多個第二連接端子，將封裝基底連接至連接基底。凹口與第二連接端子側向間隔開。

Description

半導體封裝
本發明概念是關於一種半導體封裝及/或其製造方法，且更特定言之，是關於一種具有更高可靠性的半導體封裝。
當前的電子產品市場對攜帶型元件的需求日益增長，其中經由減小安裝於攜帶型元件上的電子部件的大小及重量，可以實現更高的可攜性。為了實現電子部件的大小及重量的減小，不僅需要減小安裝部件的每一大小的技術，而且需要使用例如晶圓上晶片（chip-on-wafer；CoW）多晶片封裝將一定數目的個別元件整合於單個封裝上的技術，其中多個晶粒並排地併入矽***件上以實現更好地互連密度。然而，在製造此類CoW結構時，***件可能經歷導致例如底部填充層斷裂的應力。
本發明概念的一些實例實施例提供一種具有更高可靠性的半導體封裝。
本發明概念的目標不限於上文所提及的，且所屬領域中具有通常知識者將根據以下描述清楚地理解上文尚未提及的其他目標。
根據本發明概念的一些實例實施例，一種半導體封裝可包含：封裝基底；連接基底，位於封裝基底上，連接基底在所述連接基底的下部隅角上具有凹口，凹口面向封裝基底的頂部表面；半導體晶片，位於連接基底上；以及多個連接端子，將封裝基底連接至連接基底以使得凹口與多個連接端子側向間隔開。
根據本發明概念的一些實例實施例，一種半導體封裝可包含：封裝基底；連接基底，位於封裝基底上，連接基底包含基礎基底；多個上部接墊，位於基礎基底的頂部表面上；多個下部接墊，位於基礎基底的底部表面上；以及多個穿孔，穿透基礎基底且將上部接墊連接至下部接墊；連接基底，包含位於其下部隅角上的凹口，使得凹口的寬度大於連接基底的側壁與上部接墊中的最外者之間的距離；晶片堆疊，位於連接基底上，晶片堆疊包含豎直堆疊的多個第一半導體晶片；第二半導體晶片，與連接基底上的晶片堆疊間隔開；多個第一連接端子，將連接基底連接至晶片堆疊且將連接基底連接至第二半導體晶片；第一底部填充層，填充晶片堆疊與連接基底之間的間隙以及第二半導體晶片與連接基底之間的間隙；模塑層，位於連接基底上，模塑層覆蓋晶片堆疊及第二半導體晶片；多個第二連接端子，將封裝基底連接至連接基底；第二底部填充層，填充封裝基底與連接基底之間的間隙；以及熱輻射結構，位於封裝基底上，熱輻射結構覆蓋連接基底、晶片堆疊以及第二半導體晶片。
其他實例實施例的細節包含於描述及圖式中。
下文現將結合隨附圖式來描述根據本發明概念的一些實例實施例的半導體封裝及其製造方法。
圖1示出繪示根據本發明概念的一些實例實施例的半導體封裝的簡化平面圖。圖2示出繪示根據本發明概念的一些實例實施例的半導體封裝的沿著圖1的線I-I'截取的橫截面圖。圖3、圖4、圖5以及圖6示出繪示圖2的區段P的放大視圖。
參考圖1及圖2，半導體封裝可包含第一半導體晶片100、第二半導體晶片200、連接基底110、封裝基底500以及熱輻射結構600。
第一半導體晶片100及第二半導體晶片200可安置於連接基底110的頂部表面上。第一半導體晶片100及第二半導體晶片200可經由第一連接端子50連接至連接基底110。
第一半導體晶片100可具有位於其底部表面上的晶片接墊11，且第二半導體晶片200中的每一者可包含位於其底部表面上的晶片接墊21。第一連接端子50可附接至第一半導體晶片100的晶片接墊11及第二半導體晶片200的晶片接墊21。第一連接端子50可為焊球、導電凸塊以及導電柱中的一或多者。第一連接端子50可包含銅、錫以及鉛中的一或多者。第一連接端子50可具有例如約30微米至約70微米的厚度。
第一半導體晶片100可為包含諸如微機電系統（microelectromechanical system；MEMS）元件、光電子元件、中央處理單元（central processing unit；CPU）、圖形處理單元（graphic processing unit；GPU）、行動應用或數位信號處理器（digital signal processor；DSP）的處理器的邏輯晶片。第一半導體晶片100可具有介於約700微米至約775微米範圍內的厚度。
第二半導體晶片200可與第一半導體晶片100間隔開且安置於連接基底110上。第二半導體晶片200中的每一者可包含豎直堆疊的多個記憶體晶片20。多個記憶體晶片20可經由晶片接墊21、晶片穿孔25以及連接凸塊35彼此電連接。記憶體晶片20可堆疊於連接基底110上以便允許其側壁彼此對準。黏合層30可設置於記憶體晶片20之間。黏合層30可為例如包含介電材料的聚合物帶。黏合層30可***於連接凸塊35之間，且因此可阻止（或替代地，防止）連接凸塊35之間的電短路。
連接基底110上可設置有覆蓋第一半導體晶片100及第二半導體晶片200的模塑層120。模塑層120可具有與連接基底110的側壁對準的側壁。模塑層120可具有與第一半導體晶片100及第二半導體晶片200的頂部表面實質上共面的頂部表面。模塑層120可包含諸如環氧樹脂模塑化合物（epoxy molding compound；EMC）的介電聚合物。
第一底部填充層160可***於第一半導體晶片100與連接基底110之間以及第二半導體晶片200與連接基底110之間。第一底部填充層160可填充第一連接端子50之間的間隙。第一底部填充層160可包含例如熱固化樹脂或光固化樹脂。第一底部填充層160可更包含無機填充劑或有機填充劑。在一些實例實施例中，可忽略第一底部填充層160，且實際上，模塑層120可填充連接基底110與第一半導體晶片100及第二半導體晶片200的底部表面之間的間隙。
連接基底110可安置於封裝基底500上且經由第二連接端子150連接至封裝基底500。連接基底110可包含晶片區及圍繞所述晶片區的邊緣區。第一半導體晶片100及第二半導體晶片200可安置於連接基底110的晶片區上。
舉例而言，參考圖2及圖3，連接基底110可分別包含基礎基底111、穿孔113、包含連接線117的重佈線層以及下部接墊115及上部接墊119。
基礎基底111可為矽基底或絕緣層上矽（silicon-on-insulator；SOI）基底。替代地，基礎基底111可為玻璃基底、陶瓷基底、聚合物基底或可提供適當保護功能及/或互連功能的任何合適的基底。基礎基底111可包含主動電子元件及/或被動電子元件。鈍化介電層可安置於基礎基底111的頂部表面及底部表面中的每一者上。
穿孔113可穿透基礎基底111，且穿孔113及連接線117可包含諸如鎢（W）、鋁（Al）或銅（Cu）的金屬材料。
下部接墊115可安置於連接基底110的底部表面110a上，且上部接墊119可安置於連接基底110的頂部表面110b上。下部接墊115可經由連接線117及穿孔113電連接至上部接墊119。
第二連接端子150可附接至連接基底110的下部接墊115。第二連接端子150可經由下部接墊115、穿孔113以及連接線117電連接至上部接墊119。第二連接端子150可為由錫、鉛以及/或銅形成的焊球。第二連接端子150可具有約40微米至約80微米的厚度。
參考圖2及圖3，連接基底110可在其下部隅角上具有凹口RS。舉例而言，凹口RS可形成於基礎基底111的下部隅角上且可面向封裝基底500。連接基底110的晶片區可具有約100微米至約110微米的厚度T1，且其側壁可具有約30微米至約50微米的最小厚度T2。
凹口RS可與第二連接端子150側向間隔開。凹口RS可與連接基底110的上部接墊119中的至少一者豎直重疊。連接基底110可具有面向彼此的第一側壁及第二側壁，且形成於第一側壁及第二側壁上的凹口RS可彼此鏡像對稱。
如圖3中所繪示，凹口RS可具有圓形表面，且當自連接基底110的底部表面110a查看時，凹口RS的深度可隨著離開連接基底110的側壁而減小。當自連接基底110的底部表面110a查看時，凹口RS可具有約70微米至約90微米的最大深度。
凹口RS可具有大於連接基底110的側壁與連接基底110的最外上部接墊119之間的距離a1的寬度A1。舉例而言，凹口RS的寬度A1可介於約100微米至約120微米範圍內。
在一些實例實施例中，參考圖4，凹口RS可具有階梯狀表面。在一些實例實施例中，參考圖5，凹口RS可具有非連續表面。舉例而言，凹口RS可具有第一彎曲表面及第二彎曲表面，所述第一彎曲表面及第二彎曲表面具有彼此不同的半徑曲率。在一些實例實施例中，參考圖6，連接基底110可具有具有第一厚度的第一部分以及具有第二厚度的第二部分，且連接基底110的凹口RS可由第一部分及第二部分界定。
連接基底110與封裝基底500之間可具有填充第二連接端子150之間的間隙的第二底部填充層260。第二底部填充層260可填充連接基底110的凹口RS且可部分地覆蓋連接基底110的側壁。第二底部填充層260可與凹口RS的表面直接接觸。第二底部填充層260可包含例如熱固化樹脂或光固化樹脂。第二底部填充層260可更包含無機填充劑或有機填充劑。
封裝基底500可為例如印刷電路板、可撓性基底或條帶基底。舉例而言，封裝基底500可為可撓性印刷電路板、剛性印刷電路板以及其組合中的一者，所述板中的每一者包含形成於其中的內部線路521。
封裝基底500可具有面向彼此的頂部表面及底部表面，且可包含上部耦合接墊511、外部耦合接墊513以及內部線路521。上部耦合接墊511可配置於封裝基底500的頂部表面上，且外部耦合接墊513可配置於封裝基底500的底部表面上。上部耦合接墊511可經由內部線路521電連接至外部耦合接墊513。外部耦合端子550可附接至外部耦合接墊513。球狀柵格陣列（ball grid array；BGA）可設置為外部耦合端子550。
熱輻射結構600可包含導熱材料。導熱材料可包含金屬材料（例如，銅及/或鋁）或含碳材料（例如，石墨烯、石墨以及/或碳奈米管）。熱輻射結構600可具有相對較高的熱導率。舉例而言，單個金屬層或多個堆疊金屬層可用作熱輻射結構600。另舉例而言，熱輻射結構600可包含散熱片或散熱管。另舉例而言，熱輻射結構600可經組態以使用水冷卻。
導熱層700可***於半導體封裝與熱輻射結構600之間。導熱層700可與半導體封裝的頂部表面及熱輻射結構600的底部表面接觸。導熱層700可包含熱界面材料（thermal interface material；TIM）。熱界面材料可包含例如聚合物及導熱顆粒。導熱顆粒可分佈於聚合物中。當半導體封裝操作時，自半導體封裝產生的熱量可經由導熱層700轉移至熱輻射結構600。
圖7至圖12示出繪示根據本發明概念的一些實例實施例的製造半導體封裝的方法的橫截面圖。
參考圖7，基底W可設置於載體基底CS上。黏合層ADL可用於將基底W附接至載體基底CS上。
基底W可包含晶片區CR及圍繞晶片區CR中的每一者的切割道區SR。晶片區CR可沿著列及行二維地配置。
基底W可包含基礎基底111、穿孔113、包含連接線117的重佈線層以及下部接墊115及上部接墊119。下部接墊115可形成於基底W的底部表面上，而重佈線層可形成於基底W的頂部表面上。重佈線層可包含將上部接墊119連接至穿孔113的連接線117。下部接墊115可經由連接線117及穿孔113電連接至上部接墊119。
黏合層ADL可設置於基底W與載體基底CS之間，且可保護下部接墊115。
參考圖8，第一半導體晶片100及多個第二半導體晶片200可附接至基底W的每一晶片區CR上。
舉例而言，第一半導體晶片100可包含位於其底部表面上的晶片接墊11，且第二半導體晶片200中的每一者可包含位於其底部表面上的晶片接墊21。第一半導體晶片100及第二半導體晶片200可經安置以允許其晶片接墊11及晶片接墊21面向基底W的頂部表面。第一半導體晶片100的晶片接墊11及第二半導體晶片200的晶片接墊21可經由第一連接端子50連接至基底W的上部接墊119。
在附接第一半導體晶片100及第二半導體晶片200之後，第一底部填充層160可填充晶片區CR中的每一者上的第一連接端子50之間的間隙。
隨後，模塑層120可形成於基底W上，從而覆蓋第一半導體晶片100及第二半導體晶片200的頂部表面模塑層120可比第一半導體晶片100及第二半導體晶片200更厚，且可填充第一半導體晶片100與第二半導體晶片200之間的間隙。模塑層120可包含諸如環氧樹脂模塑化合物（EMC）的介電聚合物。
參考圖9，在形成模塑層120之後，可對模塑層120執行薄化製程。薄化製程可包含研磨製程、化學機械研磨製程或蝕刻製程。在薄化製程之後，模塑層120的頂部表面可位於與第一半導體晶片100及第二半導體晶片200的頂部表面的層級實質上相同的層級處。
在對模塑層120執行薄化製程之後，支撐帶TP可附接至模塑層120以及第一半導體晶片100及第二半導體晶片200的頂部表面。另外，可將黏合層ADL自基底W的底部表面移除。
在基底W的底部表面上，可沿著切割道區SR執行雷射開槽製程。雷射開槽製程可包含藉由允許切割道區SR接收穿經基底W的隱形雷射L而在基底W的底部表面上形成凹口RS。舉例而言，歸因於雷射開槽製程，凹口RS可經形成以具有圓形底部表面。凹口RS可具有取決於雷射開槽製程中所使用的雷射光束的寬度及/或強度的表面。可沿著切割道區SR以線性或鋸齒形方式輻照隱形雷射L。隱形雷射L可具有介於約900奈米至約1,700奈米範圍內的波長，但本發明概念不限於此。
藉助於實例描述執行雷射開槽製程以形成凹口RS，但本發明概念不限於此，且凹口RS可藉由刀片鋸切製程、濕式蝕刻製程或乾式蝕刻製程形成。
凹口RS可形成於切割道區SR上及晶片區CR的邊緣上。凹口RS可與基底W的底部表面上的下部接墊115側向間隔開。凹口RS可與形成於基底W的頂部表面上的上部接墊119中的至少一者豎直重疊。
凹口RS可具有大於切割道區SR的寬度的寬度W1。舉例而言，凹口RS的寬度W1可介於約220微米至約240微米範圍內。凹口RS可具有隨著離開切割道區SR而減小的深度。舉例而言，凹口RS的深度可介於約70微米至約90微米範圍內。
參考圖10，第二連接端子150可附接至基底W的下部接墊115，且第二連接端子150可經由連接線117及穿孔113電連接至上部接墊119。第二連接端子150可為由錫、鉛以及/或銅形成的焊球。
參考圖11，基底W可在其底部表面上設置覆蓋第二連接端子150的黏合模具層130，且鋸切帶TP可附接至黏合模具層130上。
可沿著切割道區SR執行鋸切製程，藉此使晶片區CR彼此分離。鋸切製程可包含使用刀片BL或雷射來切割基底W。基底W的晶片區CR可在鋸切帶TP上分離成多個半導體晶片。在鋸切製程期間，切割寬度W2可小於凹口RS的寬度W1。舉例而言，鋸切製程的切割寬度W2可介於約30微米至約40微米範圍內。
藉助於實例示出鋸切帶TP附接至黏合模具層130上，且鋸切製程自模塑層120開始，但本發明概念不限於此且可自黏合模具層130開始執行鋸切製程。
參考圖12，分離的半導體晶片可附接至封裝基底500上。
封裝基底500可具有面向彼此的頂部表面及底部表面，且可包含上部耦合接墊511、外部耦合接墊513以及內部線路521。
第二連接端子150可附接於封裝基底500的上部耦合接墊511與連接基底110的下部接墊115之間。外部耦合端子550可附接至外部耦合接墊513。球狀柵格陣列（BGA）可設置為外部耦合端子550。
在附接半導體晶片之後，第二底部填充層260可填充連接基底110與封裝基底500之間的間隙。根據一些實例實施例，因為連接基底110在其下部隅角上具有凹口RS，所以當第二底部填充層260形成時，可阻止（或替代地，防止）第二底部填充層260由於連接基底110的下部隅角上所聚集的應力而斷裂。
另外，因為凹口RS形成於連接基底110的下部隅角上，所以第二底部填充層260的體積可在連接基底110下方增大，使得可減少或防止第二底部填充層260自連接基底110的側壁向外突起。
參考圖2，在第二底部填充層260形成之後，可形成導熱層700及熱輻射結構600。
根據本發明概念的一些實例實施例，因為連接基底在其下部隅角上具有凹口，所以可阻止（或替代地，防止）底部填充層由於連接基底的下部隅角上所聚集的應力而斷裂。
此外，因為凹口RS形成於連接基底的下部隅角上，所以第二底部填充層的體積可在連接基底下方增大，使得可減少或防止底部填充層自連接基底的側壁向外突起。
儘管已結合隨附圖式中所示出的本發明概念的一些實例實施例來描述本發明概念，但所屬領域中具通常知識者應理解，可在不脫離本發明概念的技術精神及基本特徵的情況下進行各種改變及修改。所屬領域中具通常知識者將顯而易見，在不脫離本發明概念的範疇及精神的情況下，可對其進行各種替代、修改以及改變。
11、21:晶片接墊 20:記憶體晶片 25:晶片穿孔 30:黏合層 35:連接凸塊 50:第一連接端子 100:第一半導體晶片 110:連接基底 110a:底部表面 110b:頂部表面 111:基礎基底 113:穿孔 115:下部接墊 117連接線 119:上部接墊 120:模塑層 130:黏合模具層 150:第二連接端子 160:第一底部填充層 200:第二半導體晶片 260:第二底部填充層 500:封裝基底 511:上部耦合接墊 513:外部耦合接墊 521:內部線路 550:外部耦合端子 600:熱輻射結構 700:導熱層 a1:距離 A1、W1、W2:寬度 ADL:黏合層 BL:刀片 CR:晶片區 CS:載體基底 I-I':線 L:隱形雷射 P:區段 RS:凹口 SR:切割道區 T1、T2:厚度 TP:鋸切帶 W:基底
圖1示出繪示根據本發明概念的一些實例實施例的半導體封裝的簡化平面圖。 圖2示出繪示根據本發明概念的一些實例實施例的半導體封裝的沿著圖1的線I-I'截取的橫截面圖。 圖3、圖4、圖5以及圖6示出繪示圖2的區段P的放大視圖。 圖7至圖12示出繪示根據本發明概念的一些實例實施例的製造半導體封裝的方法的橫截面圖。
11、21:晶片接墊
20:記憶體晶片
25:晶片穿孔
30:黏合層
35:連接凸塊
50:第一連接端子
100:第一半導體晶片
110:連接基底
111:基礎基底
113:穿孔
115:下部接墊
117:連接線
119:上部接墊
120:模塑層
150:第二連接端子
160:第一底部填充層
200:第二半導體晶片
260:第二底部填充層
500:封裝基底
511:上部耦合接墊
513:外部耦合接墊
521:內部線路
550:外部耦合端子
600:熱輻射結構
700:導熱層
P:區段

Claims (10)

  1. 一種半導體封裝，包括： 封裝基底； 連接基底，位於所述封裝基底上，所述連接基底在所述連接基底的下部隅角上具有凹口，所述凹口面向所述封裝基底的頂部表面； 半導體晶片，位於所述連接基底上；以及 多個連接端子，將所述封裝基底連接至所述連接基底以使得所述凹口與所述多個連接端子側向間隔開。
  2. 如請求項1所述的半導體封裝，其中 所述連接基底包含位於所述連接基底的頂部表面上的多個上部接墊以及位於所述連接基底的底部表面上的多個下部接墊，所述上部接墊連接至所述半導體晶片，且所述下部接墊連接至所述封裝基底，且 所述凹口的寬度大於所述連接基底的側壁與所述上部接墊中的最外者之間的距離。
  3. 如請求項2所述的半導體封裝，其中所述凹口與所述上部接墊中的至少一者豎直重疊。
  4. 如請求項1所述的半導體封裝，其中所述凹口的寬度在約100微米至約120微米的範圍內。
  5. 如請求項1所述的半導體封裝，其中所述連接基底包含晶片區及圍繞所述晶片區的邊緣區，所述連接基底的側壁具有第一厚度，且所述連接基底的所述晶片區具有第二厚度，所述第二厚度大於所述第一厚度。
  6. 如請求項1所述的半導體封裝，其中所述凹口自所述連接基底的底部表面的深度自所述連接基底的側壁朝向所述半導體晶片逐漸減小。
  7. 如請求項1所述的半導體封裝，其中所述凹口自所述連接基底的底部表面的最大深度在約70微米至約90微米的範圍內。
  8. 如請求項1所述的半導體封裝，其中所述凹口具有圓形表面。
  9. 如請求項1所述的半導體封裝，其中所述凹口具有階梯狀表面。
  10. 如請求項1所述的半導體封裝，更包括： 多個第一連接端子，將所述連接基底連接至所述半導體晶片； 第一底部填充層，填充所述半導體晶片與所述連接基底之間的所述第一連接端子之間的間隙；以及 第二底部填充層，填充所述連接基底與所述封裝基底之間的間隙，所述凹口與所述第二底部填充層接觸。
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