TW202203414A - Protection circuit - Google Patents

Abstract

A protection circuit avoiding an ESD current entering a core circuit and including a detection circuit, a current releasing element, a first transistor, and a second transistor is provided. The detection circuit is coupled between a first pad and a second pad to detect whether an ESD event occurs. When the ESD event occurs, the detection circuit sets the level of a detection signal to a predetermined level. When the level of the detection signal is the predetermined level, the current releasing element is turned on to pass an ESD current. The first transistor is coupled between the core circuit and the second pad. The second transistor is coupled between the first transistor and the second pad. When the level of the detection signal is the predetermined level, the second transistor is turned on to turn off the first transistor.

Description

保護電路protect the circuit

本發明係有關於一種保護電路，特別是有關於一種用以避免一靜電放電(Electro-Static discharge；ESD)電流流入一核心電路的保護電路。The present invention relates to a protection circuit, and more particularly, to a protection circuit for preventing an electrostatic discharge (Electro-Static discharge; ESD) current from flowing into a core circuit.

因靜電放電(Electro-Static discharge；ESD)所造成之元件損害對積體電路產品來說已經成為最主要的可靠度問題之一。尤其是隨著尺寸不斷地縮小至深次微米之程度，金氧半導體之閘極氧化層也越來越薄，積體電路更容易因靜電放電現象而遭受破壞。在一般的工業標準中，積體電路產品之輸出入接腳(I/O pin)必需能夠通過2000伏特以上之人體模式靜電放電測試以及200伏特以上之機械模式靜電放電測試。因此，在積體電路產品中，靜電放電防護元件必需設置在所有輸出入銲墊(pad)附近，以保護內部之核心電路(core circuit)不受靜電放電電流之侵害。Component damage caused by electrostatic discharge (ESD) has become one of the most important reliability problems for integrated circuit products. In particular, as the size continues to shrink to the depth of sub-micron, the gate oxide layer of the metal oxide semiconductor is getting thinner and thinner, and the integrated circuit is more likely to be damaged by the phenomenon of electrostatic discharge. In general industry standards, the I/O pins of integrated circuit products must be able to pass the human body model electrostatic discharge test above 2000 volts and the mechanical model electrostatic discharge test above 200 volts. Therefore, in integrated circuit products, ESD protection components must be arranged near all the input and output pads to protect the internal core circuits from ESD currents.

本發明之一實施例提供一種保護電路，用以避免一靜電放電電流進入一核心電路。本發明之保護電路包括，一偵測電路、一電流釋放元件、一第一電晶體以及一第二電晶體。偵測電路耦接於一第一接觸墊以及一第二接觸墊之間，用以偵測一靜電放電事件是否發生。當靜電放電事件發生時，偵測電路設定一偵測信號為一預設位準。電流釋放元件耦接於第一及第二接觸墊之間。當偵測信號為該預設位準時，電流釋放元件導通，用以讓靜電放電電流流過。第一電晶體耦接於核心電路與第二接觸墊之間。第二電晶體耦接於第一電晶體與第二接觸墊之間。當偵測信號為預設位準時，第二電晶體導通，用以不導通第一電晶體。An embodiment of the present invention provides a protection circuit for preventing an electrostatic discharge current from entering a core circuit. The protection circuit of the present invention includes a detection circuit, a current release element, a first transistor and a second transistor. The detection circuit is coupled between a first contact pad and a second contact pad for detecting whether an electrostatic discharge event occurs. When an electrostatic discharge event occurs, the detection circuit sets a detection signal to a preset level. The current release element is coupled between the first and second contact pads. When the detection signal is at the preset level, the current discharge element is turned on to allow the electrostatic discharge current to flow. The first transistor is coupled between the core circuit and the second contact pad. The second transistor is coupled between the first transistor and the second contact pad. When the detection signal is at the preset level, the second transistor is turned on, so as to not turn on the first transistor.

為讓本發明之目的、特徵和優點能更明顯易懂，下文特舉出實施例，並配合所附圖式，做詳細之說明。本發明說明書提供不同的實施例來說明本發明不同實施方式的技術特徵。其中，實施例中的各元件之配置係為說明之用，並非用以限制本發明。另外，實施例中圖式標號之部分重覆，係為了簡化說明，並非意指不同實施例之間的關聯性。In order to make the objects, features and advantages of the present invention more obvious and easy to understand, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings. The present specification provides different embodiments to illustrate the technical features of different embodiments of the present invention. Wherein, the configuration of each element in the embodiment is for illustration, and not for limiting the present invention. In addition, parts of the reference numerals in the drawings in the embodiments are repeated for the purpose of simplifying the description, and do not mean the correlation between different embodiments.

第1圖為本發明之操作電路的示意圖。如圖所示，操作電路100包括一核心電路102以及一保護電路104。本發明並不限定核心電路102的種類。在一可能實施例中，核心電路102係為一非揮發性記憶體(non-volatile memory)，如一次性可編程晶片(one-time programmable chip)。在其它實施例中，核心電路102包括複數金屬熔線(metal-fuse)、複數多晶矽熔線(poly-fuse)、複數金屬反熔線(metal anti-fuse)、或是複數多晶矽反熔線(poly anti-fuse)。FIG. 1 is a schematic diagram of the operating circuit of the present invention. As shown, the operating circuit 100 includes a core circuit 102 and a protection circuit 104 . The present invention does not limit the type of the core circuit 102 . In a possible embodiment, the core circuit 102 is a non-volatile memory, such as a one-time programmable chip. In other embodiments, the core circuit 102 includes a plurality of metal-fuses, a plurality of polysilicon fuses (poly-fuses), a plurality of metal anti-fuses (metal anti-fuses), or a plurality of polysilicon antifuses ( poly anti-fuse).

保護電路104耦接於接觸墊106與108之間，並判斷是否發生一靜電放電事件。當一靜電放電事件發生於接觸墊106並且接觸墊108接收一接地電壓時，保護電路104進入一保護模式。在保護模式下，保護電路104將一靜電放電電流由接觸墊106釋放至接觸墊108，以避免靜電放電電流由接觸墊106進入核心電路102。此時，保護電路104可能命令核心電路102停止動作。本發明並不限定保護電路104如何命令核心電路102停止動作。在一可能實施例中，保護電路104停止提供一操作電壓(如一接地電壓)予核心電路102。由於核心路102缺少操作電壓，因而無法動作。The protection circuit 104 is coupled between the contact pads 106 and 108 and determines whether an electrostatic discharge event occurs. When an electrostatic discharge event occurs on the contact pad 106 and the contact pad 108 receives a ground voltage, the protection circuit 104 enters a protection mode. In the protection mode, the protection circuit 104 discharges an electrostatic discharge current from the contact pad 106 to the contact pad 108 to prevent the electrostatic discharge current from entering the core circuit 102 from the contact pad 106 . At this time, the protection circuit 104 may instruct the core circuit 102 to stop operating. The present invention does not limit how the protection circuit 104 instructs the core circuit 102 to stop operating. In a possible embodiment, the protection circuit 104 stops providing an operating voltage (eg, a ground voltage) to the core circuit 102 . Since the core circuit 102 lacks the operating voltage, it cannot operate.

當接觸墊106接收一第一操作電壓(如5V)並且接觸墊108接收一第二操作電壓(如0V)時，保護電路104進入一正常模式。在正常模式下(無靜電放電事件)，保護電路104活化核心電路102，使得核心電路102正常動作。在一可能實施例中，保護電路104重新提供一操作電壓(如一接地電壓)予核心電路102。在一些實施例中，核心電路102可能執行一寫入操作。When the contact pad 106 receives a first operating voltage (eg, 5V) and the contact pad 108 receives a second operating voltage (eg, 0V), the protection circuit 104 enters a normal mode. In the normal mode (no ESD event), the protection circuit 104 activates the core circuit 102 so that the core circuit 102 operates normally. In a possible embodiment, the protection circuit 104 provides an operating voltage (eg, a ground voltage) to the core circuit 102 again. In some embodiments, the core circuit 102 may perform a write operation.

在本實施例中，保護電路104包括一偵測電路110、一電流釋放元件112、電晶體114及116。偵測電路110耦接於接觸墊106與108之間，用以判斷一靜電放電事件是否發生。舉例而言，當接觸墊106的電位瞬間上升並且接觸墊108耦接至地時，表示一靜電放電事件發生。因此，偵測電路110設定一偵測信號V1為一第一預設位準，如一低位準或是一高位準。在其它實施例中，當接觸墊108的電位瞬間上升並且接觸墊106耦接至地時，偵測電路110也會設定偵測信號V1為第一預設位準。In this embodiment, the protection circuit 104 includes a detection circuit 110 , a current release element 112 , and transistors 114 and 116 . The detection circuit 110 is coupled between the contact pads 106 and 108 for determining whether an electrostatic discharge event occurs. For example, when the potential of the contact pad 106 rises instantaneously and the contact pad 108 is coupled to ground, it indicates that an electrostatic discharge event occurs. Therefore, the detection circuit 110 sets a detection signal V1 to a first predetermined level, such as a low level or a high level. In other embodiments, when the potential of the contact pad 108 rises instantaneously and the contact pad 106 is coupled to the ground, the detection circuit 110 also sets the detection signal V1 to the first predetermined level.

在一些實施例中，偵測電路110更產生一控制信號V2。當一靜電放電事件發生時，偵測電路110設定控制信號V2為一第二預設位準，如一高位準或是一低位準。在此例中，控制信號V2為偵測信號V1的反相信號。舉例而言，當偵測信號V1為一低位準時，控制信號V2為一高位準。當偵測信號V1為一高位準時，控制信號V2為一低位準。In some embodiments, the detection circuit 110 further generates a control signal V2. When an electrostatic discharge event occurs, the detection circuit 110 sets the control signal V2 to a second predetermined level, such as a high level or a low level. In this example, the control signal V2 is an inverted signal of the detection signal V1. For example, when the detection signal V1 is at a low level, the control signal V2 is at a high level. When the detection signal V1 is at a high level, the control signal V2 is at a low level.

本發明並不限定偵測電路110產生偵測信號V1及控制信號V2的順序。在一可能實施例中，偵測電路110先產生偵測信號V1，再產生控制信號V2。在此例中，偵測電路110反相偵測信號V1，用以產生控制信號V2。在另一可能實施例中，偵測電路110先產生控制信號V2，再產生偵測信號V1。在此例中，偵測電路110可能反相控制信號V2，用以產生偵測信號V1。The invention does not limit the sequence in which the detection circuit 110 generates the detection signal V1 and the control signal V2. In a possible embodiment, the detection circuit 110 generates the detection signal V1 first, and then generates the control signal V2. In this example, the detection circuit 110 inverts the detection signal V1 to generate the control signal V2. In another possible embodiment, the detection circuit 110 generates the control signal V2 first, and then generates the detection signal V1. In this example, the detection circuit 110 may invert the control signal V2 to generate the detection signal V1.

電流釋放元件112耦接於接觸墊106與108之間，並接收控制信號V2。當靜電放電事件發生時，偵測信號V1為第一預設位準(如低位準)。因此，控制信號V2為一第二預設位準(如高位準)。此時，電流釋放元件112導通，用以將靜電放電電流由接觸墊106釋放至接觸墊108或是由接觸墊108釋放至接觸墊106。在本實施例中，電流釋放元件112係為一N型電晶體Nesd。N型電晶體Nesd的閘極接收控制信號V2，其汲極耦接接觸墊106，其源極耦接接觸墊108。為了承受高壓，N型電晶體Nesd的通道尺寸大於電晶體114及116的通道尺寸。在其它實施例中，電流釋放元件112係為一P型電晶體。The current release element 112 is coupled between the contact pads 106 and 108 and receives the control signal V2. When an electrostatic discharge event occurs, the detection signal V1 is at a first predetermined level (eg, a low level). Therefore, the control signal V2 is a second predetermined level (eg, a high level). At this time, the current discharge element 112 is turned on to discharge the electrostatic discharge current from the contact pad 106 to the contact pad 108 or from the contact pad 108 to the contact pad 106 . In this embodiment, the current release element 112 is an N-type transistor Nesd. The gate of the N-type transistor Nesd receives the control signal V2 , its drain is coupled to the contact pad 106 , and its source is coupled to the contact pad 108 . In order to withstand the high voltage, the channel size of the N-type transistor Nesd is larger than that of the transistors 114 and 116 . In other embodiments, the current release element 112 is a P-type transistor.

電晶體116耦接於核心電路102與接觸墊108之間。在本實施例中，電晶體116係為一N型電晶體，其汲極(或稱第一電極)耦接核心電路102，其源極(或稱第二電極)耦接接觸墊108，其閘極耦接電晶體114並接收偵測信號V1。在一可能實施例中，當偵測信號V1為第一預設位準(如低位準)時，表示發生靜電放電事件。因此，電晶體116不導通，用以禁能核心電路102。在其它實施例中，在正常模式下(未發生靜電放電事件)，接觸墊108接收一接地電壓。此時，由於偵測信號V1不為第一預設位準，故電晶體116導通，用以活化核心電路102。在一可能實施例中，電晶體116提供接觸墊108所接收到的電壓(如一接地電壓)予核心電路102，使得核心電路102正常動作。The transistor 116 is coupled between the core circuit 102 and the contact pad 108 . In this embodiment, the transistor 116 is an N-type transistor, the drain (or the first electrode) is coupled to the core circuit 102, the source (or the second electrode) is coupled to the contact pad 108, and the The gate is coupled to the transistor 114 and receives the detection signal V1. In a possible embodiment, when the detection signal V1 is at a first predetermined level (eg, a low level), it indicates that an electrostatic discharge event occurs. Therefore, the transistor 116 is turned off to disable the core circuit 102 . In other embodiments, in the normal mode (no electrostatic discharge events occur), the contact pads 108 receive a ground voltage. At this time, since the detection signal V1 is not at the first preset level, the transistor 116 is turned on to activate the core circuit 102 . In a possible embodiment, the transistor 116 provides the voltage (eg, a ground voltage) received by the contact pad 108 to the core circuit 102 so that the core circuit 102 operates normally.

電晶體114耦接於電晶體116與接觸墊108之間。當偵測信號V1為第一預設位準時，由於控制信號V2為第二預設位準，故電晶體114導通，用以不導通電晶體116。在一可能實施例中，當偵測信號V1為第一預設位準時，電晶體114設定電晶體116的閘極電壓等於接觸墊108的電位(如一接地電壓)。The transistor 114 is coupled between the transistor 116 and the contact pad 108 . When the detection signal V1 is at the first predetermined level, since the control signal V2 is at the second predetermined level, the transistor 114 is turned on to turn off the transistor 116 . In a possible embodiment, when the detection signal V1 is at the first predetermined level, the transistor 114 sets the gate voltage of the transistor 116 to be equal to the potential of the contact pad 108 (eg, a ground voltage).

在本實施例中，電晶體114係為一N型電晶體，其汲極(或稱第三電極)耦接電晶體116的閘極，其源極(或稱第四電極)耦接接觸墊108，其閘極耦接N型電晶體Nesd的閘極。在正常模式下(未發生靜電放電事件)，接觸墊108接收一接地電壓。此時，由於偵測信號V2不為第二預設位準，故電晶體114不導通。In this embodiment, the transistor 114 is an N-type transistor, the drain electrode (or the third electrode) is coupled to the gate electrode of the transistor 116, and the source electrode (or the fourth electrode) is coupled to the contact pad 108, the gate of which is coupled to the gate of the N-type transistor Nesd. In normal mode (no electrostatic discharge events occur), the contact pads 108 receive a ground voltage. At this time, since the detection signal V2 is not at the second predetermined level, the transistor 114 is not turned on.

在一些實施例中，當靜電放電事件發生時，偵測電路110設定偵測信號V1為一第一預設位準。此時，雖然電晶體116不導通，但偵測信號V1可能因偵測電路110發生漏電流而逐漸上升，因而導通電晶體116，進而活化核心電路102。此時，如果靜電放電電流進入核心電路102，將損害核心電路102。因此，當偵測信號V1為第一預設位準時，電晶體114導通，用以設定電晶體116的閘極電壓等於接觸墊108的電位(如一接地電壓)，以避免電晶體116活化核心電路102。In some embodiments, when an electrostatic discharge event occurs, the detection circuit 110 sets the detection signal V1 to a first predetermined level. At this time, although the transistor 116 is not turned on, the detection signal V1 may gradually increase due to the leakage current of the detection circuit 110 , so that the transistor 116 is turned on, thereby activating the core circuit 102 . At this time, if the electrostatic discharge current enters the core circuit 102, the core circuit 102 will be damaged. Therefore, when the detection signal V1 is at the first preset level, the transistor 114 is turned on to set the gate voltage of the transistor 116 to be equal to the potential of the contact pad 108 (eg, a ground voltage) to prevent the transistor 116 from activating the core circuit 102.

第2圖為本發明之操作電路的另一示意圖。操作電路200包括一核心電路202以及一保護電路204。由於核心電路202的特性與第1圖的核心電路102的特性相似，故不再贅述。保護電路204耦接於接觸墊206與208之間。當一靜電放電事件發生於接觸墊206並且接觸墊208耦接至地時，保護電路204進入一保護模式。在此模式下，保護電路204將靜電放電電流由接觸墊206釋放至接觸墊208，並禁能核心電路202。當靜電放電事件未發生時，保護電路204進入一正常模式。在此模式下，保護電路204命令核心電路202正常動作。FIG. 2 is another schematic diagram of the operation circuit of the present invention. The operating circuit 200 includes a core circuit 202 and a protection circuit 204 . Since the characteristics of the core circuit 202 are similar to the characteristics of the core circuit 102 in FIG. 1 , detailed descriptions are omitted. The protection circuit 204 is coupled between the contact pads 206 and 208 . When an electrostatic discharge event occurs on contact pad 206 and contact pad 208 is coupled to ground, protection circuit 204 enters a protection mode. In this mode, the protection circuit 204 discharges the electrostatic discharge current from the contact pad 206 to the contact pad 208 and disables the core circuit 202 . When an ESD event does not occur, the protection circuit 204 enters a normal mode. In this mode, the protection circuit 204 commands the core circuit 202 to operate normally.

在本實施例中，保護電路204包括一偵測電路210、一電流釋放元件212、電晶體214、216以及一反相電路218。由於偵測電路210、電流釋放元件212、電晶體214及216的特性相似於第1圖的偵測電路110、電流釋放元件112、電晶體114及116的特性，故不再贅述。In this embodiment, the protection circuit 204 includes a detection circuit 210 , a current release element 212 , transistors 214 and 216 and an inverting circuit 218 . Since the characteristics of the detection circuit 210 , the current release element 212 , the transistors 214 and 216 are similar to those of the detection circuit 110 , the current release element 112 , and the transistors 114 and 116 in FIG. 1 , they are not described again.

反相電路218耦接於接觸墊206與208之間，並反相偵測信號V1，用以產生控制信號V3。在此例中，控制信號V3的位準相同於控制信號V2的位準。在本實施例中，反相電路218作為一緩衝器(buffer)，故控制信號V3的驅動能力高於控制信號V2的驅動能力。如圖所示，反相電路218包括一N型電晶體220以及一P型電晶體222。The inverting circuit 218 is coupled between the contact pads 206 and 208 and inverts the detection signal V1 to generate the control signal V3. In this example, the level of the control signal V3 is the same as the level of the control signal V2. In this embodiment, the inverter circuit 218 is used as a buffer, so the driving capability of the control signal V3 is higher than the driving capability of the control signal V2. As shown, the inverter circuit 218 includes an N-type transistor 220 and a P-type transistor 222 .

P型電晶體222的源極耦接接觸墊206，其汲極耦接電晶體214的閘極，其閘極作為反相電路218的輸入端，用以接收偵測信號V1。N型電晶體220的源極耦接接觸墊208，其汲極作為反相電路218的輸出端，並耦接電晶體214的閘極，其閘極接收偵測信號V1。當靜電放電事件發生時，偵測電路210設定偵測信號V1為一第一預設位準。此時，控制信號V3為第二預設位準。因此，電晶體214導通，用以設定電晶體216的閘極電壓等於接觸墊208的電位(如一接地電壓)，以避免電晶體216活化核心電路202。本發明並不限定反相電路的數量。在其它實施例中，保護電路204具有奇數個反相電路。該等反相電路串接於偵測電路210與電晶體214之間。The source electrode of the P-type transistor 222 is coupled to the contact pad 206 , and the drain electrode thereof is coupled to the gate electrode of the transistor 214 . The source of the N-type transistor 220 is coupled to the contact pad 208 , the drain thereof serves as the output terminal of the inverting circuit 218 , and is coupled to the gate of the transistor 214 , the gate of which receives the detection signal V1 . When an electrostatic discharge event occurs, the detection circuit 210 sets the detection signal V1 to a first predetermined level. At this time, the control signal V3 is the second preset level. Therefore, the transistor 214 is turned on to set the gate voltage of the transistor 216 equal to the potential of the contact pad 208 (eg, a ground voltage) to prevent the transistor 216 from activating the core circuit 202 . The present invention does not limit the number of inverter circuits. In other embodiments, the protection circuit 204 has an odd number of inverting circuits. The inverting circuits are connected in series between the detection circuit 210 and the transistor 214 .

第3圖為本發明之操作電路的另一示意圖。操作電路300包括一核心電路302以及一保護電路304。由於核心電路302的特性與第1圖的核心電路102的特性相似，故不再贅述。保護電路304耦接於接觸墊306與308之間。當一靜電放電事件發生於接觸墊306並且接觸墊308耦接至地時，保護電路304進入一保護模式。在此模式下，保護電路304將靜電放電電流由接觸墊306釋放至接觸墊308，並禁能核心電路302。當靜電放電事件未發生時，保護電路304進入一正常模式。在此模式下，保護電路304命令核心電路302正常動作。在本實施例中，保護電路304包括一偵測電路310、一電流釋放元件312、電晶體314、316、反相電路318及324。由於偵測電路310、電流釋放元件312、電晶體314及316的特性相似於第1圖的偵測電路110、電流釋放元件112、電晶體114及116的特性，故不再贅述。FIG. 3 is another schematic diagram of the operating circuit of the present invention. The operating circuit 300 includes a core circuit 302 and a protection circuit 304 . Since the characteristics of the core circuit 302 are similar to the characteristics of the core circuit 102 in FIG. 1 , detailed descriptions are omitted. The protection circuit 304 is coupled between the contact pads 306 and 308 . When an electrostatic discharge event occurs on contact pad 306 and contact pad 308 is coupled to ground, protection circuit 304 enters a protection mode. In this mode, the protection circuit 304 discharges the electrostatic discharge current from the contact pad 306 to the contact pad 308 and disables the core circuit 302 . When an ESD event does not occur, the protection circuit 304 enters a normal mode. In this mode, the protection circuit 304 commands the core circuit 302 to operate normally. In this embodiment, the protection circuit 304 includes a detection circuit 310 , a current release element 312 , transistors 314 and 316 , and inverting circuits 318 and 324 . Since the characteristics of the detection circuit 310 , the current release element 312 , the transistors 314 and 316 are similar to those of the detection circuit 110 , the current release element 112 , and the transistors 114 and 116 in FIG.

反相電路318及324串接於偵測電路310與電晶體314之間，用以處理控制信號V2，並產生控制信號V5。在本實施例中，反相電路318及324構成一緩衝電路，用以增加控制信號V2的驅動能力。在此例中，控制信號V5的驅動能力大於控制信號V2的驅動能力。本發明並不限定反相電路的數量。在其它實施例中，保護電路304具有偶數個反相電路。The inverting circuits 318 and 324 are connected in series between the detection circuit 310 and the transistor 314 for processing the control signal V2 and generating the control signal V5. In this embodiment, the inverting circuits 318 and 324 form a buffer circuit for increasing the driving capability of the control signal V2. In this example, the driving capability of the control signal V5 is greater than the driving capability of the control signal V2. The present invention does not limit the number of inverter circuits. In other embodiments, the protection circuit 304 has an even number of inverting circuits.

在本實施例中，反相電路318耦接於接觸墊306與308之間，並反相控制信號V2，用以產生控制信號V4。在此例中，控制信號V4的位準相同於偵測信號V1的位準。如圖所示，反相電路318包括一N型電晶體320以及一P型電晶體322。P型電晶體322的源極耦接接觸墊306，其汲極作為反相電路318的輸出端，用以提供控制信號V4，其閘極作為反相電路318的輸入端，用以接收控制信號V2。N型電晶體320的源極耦接接觸墊308，其汲極耦接P型電晶體322的汲極，其閘極耦接P型電晶體322的閘極。In this embodiment, the inverting circuit 318 is coupled between the contact pads 306 and 308 and inverts the control signal V2 to generate the control signal V4. In this example, the level of the control signal V4 is the same as the level of the detection signal V1. As shown, the inverter circuit 318 includes an N-type transistor 320 and a P-type transistor 322 . The source of the P-type transistor 322 is coupled to the contact pad 306 , its drain is used as the output terminal of the inverting circuit 318 to provide the control signal V4 , and its gate is used as the input terminal of the inverting circuit 318 to receive the control signal v2. The source of the N-type transistor 320 is coupled to the contact pad 308 , its drain is coupled to the drain of the P-type transistor 322 , and its gate is coupled to the gate of the P-type transistor 322 .

反相電路324耦接於接觸墊306與308之間，並反相控制信號V4，用以產生控制信號V5。在此例中，控制信號V5的位準相同於控制信號V2的位準。如圖所示，反相電路324包括一N型電晶體326以及一P型電晶體328。P型電晶體328的源極耦接接觸墊306，其汲極作為反相電路324的輸出端，並提供控制信號V5予電晶體314的閘極，其閘極作為反相電路324的輸入端，用以接收控制信號V4。N型電晶體326的源極耦接接觸墊308，其汲極耦接P型電晶體328的汲極，其閘極耦接P型電晶體328的閘極。The inverting circuit 324 is coupled between the contact pads 306 and 308 and inverts the control signal V4 to generate the control signal V5. In this example, the level of the control signal V5 is the same as the level of the control signal V2. As shown, the inverter circuit 324 includes an N-type transistor 326 and a P-type transistor 328 . The source of the P-type transistor 328 is coupled to the contact pad 306 , and its drain serves as the output terminal of the inverting circuit 324 , and provides the control signal V5 to the gate of the transistor 314 , and its gate serves as the input terminal of the inverting circuit 324 . , used to receive the control signal V4. The source of the N-type transistor 326 is coupled to the contact pad 308 , its drain is coupled to the drain of the P-type transistor 328 , and its gate is coupled to the gate of the P-type transistor 328 .

第4圖為本發明之偵測電路的示意圖。如圖所示，偵測電路400包括一電阻402、一電容404以及一反相電路408。在本實施例中，偵測電路400可作為第1圖的偵測電路110、第2圖的偵測電路210以及第3圖的偵測電路310。為方便說明，假設偵測電路400作為第1圖的偵測電路110。FIG. 4 is a schematic diagram of the detection circuit of the present invention. As shown, the detection circuit 400 includes a resistor 402 , a capacitor 404 and an inverting circuit 408 . In this embodiment, the detection circuit 400 can be used as the detection circuit 110 in FIG. 1 , the detection circuit 210 in FIG. 2 , and the detection circuit 310 in FIG. 3 . For convenience of description, it is assumed that the detection circuit 400 is used as the detection circuit 110 in FIG. 1 .

電阻402耦接於接觸墊106與共同節點414之間。電容404耦接於共同節點414與接觸墊108之間。在本實施例中，共同節點414的位準作為偵測信號V1。在一些實施例中，共同節點414直接連接第2圖的反相電路218的輸入端。Resistor 402 is coupled between contact pad 106 and common node 414 . The capacitor 404 is coupled between the common node 414 and the contact pad 108 . In this embodiment, the level of the common node 414 is used as the detection signal V1. In some embodiments, the common node 414 is directly connected to the input of the inverting circuit 218 of FIG. 2 .

當一靜電放電事件發生於接觸墊106並且接觸墊108耦接至地時，共同節點414的位準(即偵測信號V1)為一低位準。當接觸墊106接收到一第一操作電壓(如3.3V)並且接觸墊108接收到一第二操作電壓(如0V)時，共同節點414的位準(即偵測信號V1)為一高位準。在其它實施例中，電阻402及電容404可能串聯於第2圖的接觸墊206與208之間或是串聯於第3圖的接觸墊306與308之間。When an electrostatic discharge event occurs on the contact pad 106 and the contact pad 108 is coupled to ground, the level of the common node 414 (ie, the detection signal V1 ) is a low level. When the contact pad 106 receives a first operating voltage (eg, 3.3V) and the contact pad 108 receives a second operating voltage (eg, 0V), the level of the common node 414 (ie, the detection signal V1 ) is a high level . In other embodiments, the resistor 402 and the capacitor 404 may be connected in series between the contact pads 206 and 208 in FIG. 2 or between the contact pads 306 and 308 in FIG. 3 .

反相電路408反相偵測信號V1，用以產生控制信號V2。在本實施例中，反相電路408的輸入端耦接共同節點414，反相電路408的輸出端耦接第1圖的電流釋放元件112，用以提供控制信號V2予電流釋放元件112。在此例中，反相電路408的輸出端可能直接連接第1圖的電晶體114的閘極。在其它實施例中，反相電路408的輸出端可能耦接第2圖的電流釋放元件212或是第3圖的電流釋放元件312。The inverting circuit 408 inverts the detection signal V1 to generate the control signal V2. In this embodiment, the input terminal of the inverter circuit 408 is coupled to the common node 414 , and the output terminal of the inverter circuit 408 is coupled to the current release element 112 in FIG. 1 for providing the control signal V2 to the current release element 112 . In this example, the output terminal of the inverter circuit 408 may be directly connected to the gate of the transistor 114 in FIG. 1 . In other embodiments, the output terminal of the inverter circuit 408 may be coupled to the current release element 212 of FIG. 2 or the current release element 312 of FIG. 3 .

本發明並不限定反相電路408的架構。只要能夠反相偵測信號V1的電路，均可作為反相電路408。在本實施例中，反相電路408包括一P型電晶體410以及一N型電晶體412。P型電晶體410的閘極作為反相電路408的輸入端，用以接收偵測信號V1，其源極耦接接觸墊106，其汲極作為反相電路408的輸出端，用以輸出控制信號V2。N型電晶體412的閘極耦接P型電晶體410的閘極。N型電晶體412的汲極耦接P型電晶體410的汲極。N型電晶體412的源極耦接接觸墊108。在一些實施例中，反相電路408耦接於第2圖的接觸墊206與208之間或是第3圖的接觸墊306與308之間。The present invention does not limit the structure of the inverter circuit 408 . Any circuit capable of inverting the detection signal V1 can be used as the inverting circuit 408 . In this embodiment, the inverter circuit 408 includes a P-type transistor 410 and an N-type transistor 412 . The gate of the P-type transistor 410 is used as the input terminal of the inverting circuit 408 to receive the detection signal V1, its source is coupled to the contact pad 106, and its drain is used as the output terminal of the inverting circuit 408 to output control signal V2. The gate of the N-type transistor 412 is coupled to the gate of the P-type transistor 410 . The drain of the N-type transistor 412 is coupled to the drain of the P-type transistor 410 . The source of the N-type transistor 412 is coupled to the contact pad 108 . In some embodiments, the inverting circuit 408 is coupled between the contact pads 206 and 208 of FIG. 2 or between the contact pads 306 and 308 of FIG. 3 .

第5圖為本發明之偵測電路的另一示意圖。如圖所示，偵測電路500包括一電阻502、一電容504以及一反相電路508。在本實施例中，偵測電路500可作為第1圖的偵測電路110、第2圖的偵測電路210以及第3圖的偵測電路310。為方便說明，假設偵測電路500作為第1圖的偵測電路110。FIG. 5 is another schematic diagram of the detection circuit of the present invention. As shown in the figure, the detection circuit 500 includes a resistor 502 , a capacitor 504 and an inverting circuit 508 . In this embodiment, the detection circuit 500 can be used as the detection circuit 110 in FIG. 1 , the detection circuit 210 in FIG. 2 , and the detection circuit 310 in FIG. 3 . For convenience of description, it is assumed that the detection circuit 500 is used as the detection circuit 110 in FIG. 1 .

電容504耦接於接觸墊106與共同節點514之間。電阻502耦接於共同節點514與接觸墊108之間。在本實施例中，共同節點514的位準作為控制信號V2。當一靜電放電事件發生於接觸墊106並且接觸墊108耦接至地時，共同節點514的位準(即控制信號V2)為一高位準。當接觸墊106接收到一第一操作電壓(如3.3V)並且接觸墊108接收到一第二操作電壓(如0V)時，共同節點514的位準(即控制信號V2)為一低位準。在其它實施例中，電容504與電阻502可能串聯於第2圖的接觸墊206與208之間或是串聯於第3圖的接觸墊306與308之間。The capacitor 504 is coupled between the contact pad 106 and the common node 514 . Resistor 502 is coupled between common node 514 and contact pad 108 . In this embodiment, the level of the common node 514 is used as the control signal V2. When an electrostatic discharge event occurs on the contact pad 106 and the contact pad 108 is coupled to ground, the level of the common node 514 (ie, the control signal V2 ) is at a high level. When the contact pad 106 receives a first operating voltage (eg, 3.3V) and the contact pad 108 receives a second operating voltage (eg, 0V), the level of the common node 514 (ie, the control signal V2 ) is a low level. In other embodiments, the capacitor 504 and the resistor 502 may be connected in series between the contact pads 206 and 208 in FIG. 2 or between the contact pads 306 and 308 in FIG. 3 .

反相電路508反相控制信號V2，用以產生偵測信號V1。在本實施例中，反相電路508的輸入端耦接共同節點514，反相電路508的輸出端耦接第1圖的電晶體116的閘極。在其它實施例中，反相電路508的輸出端可能耦接第2圖的反相電路218的輸入端。The inverting circuit 508 inverts the control signal V2 to generate the detection signal V1. In this embodiment, the input terminal of the inverting circuit 508 is coupled to the common node 514 , and the output terminal of the inverting circuit 508 is coupled to the gate of the transistor 116 in FIG. 1 . In other embodiments, the output terminal of the inverting circuit 508 may be coupled to the input terminal of the inverting circuit 218 in FIG. 2 .

在本實施例中，反相電路508包括一P型電晶體510以及一N型電晶體512。P型電晶體510的閘極作為反相電路508的輸入端，用以接收控制信號V2，其源極耦接接觸墊106，其汲極作為反相電路508的輸出端，用以輸出偵測信號V1。N型電晶體512的閘極耦接P型電晶體510的閘極。N型電晶體512的汲極耦接P型電晶體510的源極。N型電晶體512的源極耦接接觸墊108。在一些實施例中，反相電路508耦接於第2圖的接觸墊206與208之間或是第3圖的接觸墊306與308之間。In this embodiment, the inverter circuit 508 includes a P-type transistor 510 and an N-type transistor 512 . The gate of the P-type transistor 510 is used as the input terminal of the inverting circuit 508 to receive the control signal V2, its source is coupled to the contact pad 106, and its drain is used as the output terminal of the inverting circuit 508 to output detection signal V1. The gate of the N-type transistor 512 is coupled to the gate of the P-type transistor 510 . The drain of the N-type transistor 512 is coupled to the source of the P-type transistor 510 . The source of the N-type transistor 512 is coupled to the contact pad 108 . In some embodiments, the inverting circuit 508 is coupled between the contact pads 206 and 208 of FIG. 2 or between the contact pads 306 and 308 of FIG. 3 .

除非另作定義，在此所有詞彙(包含技術與科學詞彙)均屬本發明所屬技術領域中具有通常知識者之一般理解。此外，除非明白表示，詞彙於一般字典中之定義應解釋為與其相關技術領域之文章中意義一致，而不應解釋為理想狀態或過分正式之語態。雖然“第一”、“第二”等術語可用於描述各種元件，但這些元件不應受這些術語的限制。這些術語只是用以區分一個元件和另一個元件。Unless otherwise defined, all terms (including technical and scientific terms) herein are commonly understood by those of ordinary skill in the art to which this invention belongs. Furthermore, unless expressly stated otherwise, the definitions of words in general dictionaries should be construed as consistent with their meanings in articles in the related technical field, and should not be construed as ideal states or overly formal voices. Although the terms "first", "second", etc. may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾。舉例來說，本發明實施例所述之系統、裝置或是方法可以硬體、軟體或硬體以及軟體的組合的實體實施例加以實現。因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. . For example, the system, apparatus, or method described in the embodiments of the present invention may be implemented in a physical embodiment of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention should be determined by the scope of the appended patent application.

100、200、300:操作電路 102、202、302:核心電路 104、204、304:保護電路 106、108、206、208、306、308:接觸墊 110、210、310、400、500:偵測電路 112、212、312:電流釋放元件 114、116、214、216、214、216、電晶體 V1:偵測信號 V2~V5:控制信號 Nesd、220、320、326、412、512:N型電晶體 222、322、328、410、510:P型電晶體 218、318、324、408、508:反相電路 402、502:電阻 404、504:電容 414、514:共同節點100, 200, 300: Operating circuit 102, 202, 302: Core circuit 104, 204, 304: Protection circuit 106, 108, 206, 208, 306, 308: Contact pads 110, 210, 310, 400, 500: detection circuit 112, 212, 312: Current release element 114, 116, 214, 216, 214, 216, transistors V1: Detection signal V2~V5: Control signal Nesd, 220, 320, 326, 412, 512: N-type transistors 222, 322, 328, 410, 510: P-type transistors 218, 318, 324, 408, 508: Inverting circuit 402, 502: Resistance 404, 504: Capacitor 414, 514: common node

第1圖為本發明之操作電路的示意圖。 第2圖為本發明之操作電路的另一示意圖。 第3圖為本發明之操作電路的另一示意圖。 第4圖為本發明之偵測電路的示意圖。 第5圖為本發明之偵測電路的另一示意圖。FIG. 1 is a schematic diagram of the operating circuit of the present invention. FIG. 2 is another schematic diagram of the operation circuit of the present invention. FIG. 3 is another schematic diagram of the operating circuit of the present invention. FIG. 4 is a schematic diagram of the detection circuit of the present invention. FIG. 5 is another schematic diagram of the detection circuit of the present invention.

100:操作電路100: Operating Circuit

102:核心電路102: Core circuit

104:保護電路104: Protection circuit

106、108:接觸墊106, 108: Contact pads

110:偵測電路110: Detection circuit

112:電流釋放元件112: Current release element

114、116:電晶體114, 116: Transistor

V1:偵測信號V1: Detection signal

V2:控制信號V2: Control signal

Nesd:N型電晶體Nesd: N-type transistor

Claims (10)

一種保護電路，用以避免一靜電放電電流進入一核心電路，該保護電路包括： 一偵測電路，耦接於一第一接觸墊以及一第二接觸墊之間，用以偵測一靜電放電事件是否發生，其中當該靜電放電事件發生時，該偵測電路設定一偵測信號為一預設位準； 一電流釋放元件，耦接於該第一及第二接觸墊之間，當該偵測信號為該預設位準時，該電流釋放元件導通，用以讓該靜電放電電流流過； 一第一電晶體，耦接於該核心電路與該第二接觸墊之間；以及 一第二電晶體，耦接於該第一電晶體與該第二接觸墊之間，當該偵測信號為該預設位準時，該第二電晶體導通，用以不導通該第一電晶體。A protection circuit for preventing an electrostatic discharge current from entering a core circuit, the protection circuit comprising: a detection circuit, coupled between a first contact pad and a second contact pad, for detecting whether an electrostatic discharge event occurs, wherein when the electrostatic discharge event occurs, the detection circuit sets a detection The signal is a preset level; a current discharge element coupled between the first and second contact pads, when the detection signal is at the preset level, the current discharge element is turned on to allow the electrostatic discharge current to flow; a first transistor coupled between the core circuit and the second contact pad; and a second transistor, coupled between the first transistor and the second contact pad, when the detection signal is at the preset level, the second transistor is turned on, so as to not turn on the first transistor crystal. 如請求項1之保護電路，其中該偵測電路包括： 一電阻，耦接於該第一接觸墊與一共同節點之間； 一電容，耦接於該共同節點與該第二接觸墊之間；以及 一第一反相電路，具有一第一輸入端以及一第一輸出端，該第一輸入端耦接該共同節點，該第一輸出端耦接該電流釋放元件。The protection circuit of claim 1, wherein the detection circuit comprises: a resistor coupled between the first contact pad and a common node; a capacitor coupled between the common node and the second contact pad; and A first inverter circuit has a first input terminal and a first output terminal, the first input terminal is coupled to the common node, and the first output terminal is coupled to the current release element. 如請求項2之保護電路，其中該第一電晶體具有一第一閘極、一第一電極以及一第二電極，該第一閘極接收該偵測信號，該第一電極耦接該核心電路，該第二電極耦接該第二接觸墊， 其中該第二電晶體具有一第二閘極、一第三電極以及一第四電極，該第三電極耦接該第一閘極，該第四電極耦接該第二接觸墊。The protection circuit of claim 2, wherein the first transistor has a first gate, a first electrode and a second electrode, the first gate receives the detection signal, and the first electrode is coupled to the core circuit, the second electrode is coupled to the second contact pad, The second transistor has a second gate, a third electrode and a fourth electrode, the third electrode is coupled to the first gate, and the fourth electrode is coupled to the second contact pad. 如請求項3之保護電路，其中該第二閘極直接耦接該第一輸出端。The protection circuit of claim 3, wherein the second gate is directly coupled to the first output. 如請求項3之保護電路，其中當該第二電晶體導通時，該第一閘極的電壓等於該第二接觸墊的電位。The protection circuit of claim 3, wherein when the second transistor is turned on, the voltage of the first gate is equal to the potential of the second contact pad. 如請求項3之保護電路，更包括： 一第二反相電路，具有一第二輸入端以及一第二輸出端，該第二輸入端耦接該共同節點，該第二輸出端耦接該第二閘極。Such as the protection circuit of claim 3, it also includes: A second inverter circuit has a second input terminal and a second output terminal, the second input terminal is coupled to the common node, and the second output terminal is coupled to the second gate. 如請求項3之保護電路，更包括： 一第二反相電路，具有一第二輸入端以及一第二輸出端，該第二輸入端耦接該第一輸出端；以及 一第三反相電路，具有一第三輸入端以及一第三輸出端，該第三輸入端耦接該第二輸出端，該第三輸出端耦接該第二閘極。Such as the protection circuit of claim 3, it also includes: a second inverting circuit having a second input terminal and a second output terminal, the second input terminal is coupled to the first output terminal; and A third inverting circuit has a third input terminal and a third output terminal, the third input terminal is coupled to the second output terminal, and the third output terminal is coupled to the second gate. 如請求項1之保護電路，其中該電流釋放元件、該第一電晶體及該第二電晶體為N型電晶體。The protection circuit of claim 1, wherein the current release element, the first transistor and the second transistor are N-type transistors. 如請求項1之保護電路，其中當該第一接觸墊接收一第一操作電壓並且該第二接觸墊接收一第二操作電壓時，該核心電路正常工作，並且該第一電晶體導通，該第二電晶體不導通。The protection circuit of claim 1, wherein when the first contact pad receives a first operating voltage and the second contact pad receives a second operating voltage, the core circuit operates normally, and the first transistor is turned on, the The second transistor does not conduct. 如請求項1之保護電路，其中當該第一接觸墊接收一第一操作電壓並且該第二接觸墊接收一第二操作電壓時，該偵測電路設定該偵測信號不為該預設位準。The protection circuit of claim 1, wherein when the first contact pad receives a first operating voltage and the second contact pad receives a second operating voltage, the detection circuit sets the detection signal to not be the default bit allow.

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