TW202201586A - One-sided electrical measurement technology for packaging substrate - Google Patents

One-sided electrical measurement technology for packaging substrate Download PDF

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TW202201586A
TW202201586A TW109121325A TW109121325A TW202201586A TW 202201586 A TW202201586 A TW 202201586A TW 109121325 A TW109121325 A TW 109121325A TW 109121325 A TW109121325 A TW 109121325A TW 202201586 A TW202201586 A TW 202201586A
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conductive
package substrate
layer
carrier
redistribution
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TW109121325A
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TWI737363B (en
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李光英
郭合傑
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祁昌股份有限公司
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Abstract

A method of one-sided electrical measurement for a packaging substrate, including the following steps: providing a carrier; coating a conductive adhesive layer on the carrier; forming a redistribution layer (RDL) attached on the carrier through the conductive adhesive layer, the redistribution layer including a plurality of superimposed dielectric layers, each of which includes a plurality of conductive vias covered by a plurality of conductive patterns such that a multi-layered redistribution circuit connecting the conductive patterns on different dielectric layers; and providing a pair of measuring probes with opposite electrical polarities to measure the resistance between two conductive vias to determine the conductivity between the two conductive vias.

Description

封裝基板之同側電性量測技術Same-Side Electrical Measurement Technology of Package Substrate

本發明係有關於一種用於封裝基板之電性量測技術，特別是指一種封裝基板以及用於封裝基板之同側電性量測方法。The present invention relates to an electrical property measurement technology for a package substrate, and more particularly to a package substrate and a same-side electrical property measurement method for the package substrate.

現有的半導體製程中，扇出式晶圓封裝（fan-out wafer level package，FOPLP）被認為是具有成本效益的下一代高集成封裝IC技術。圖1A係為一習知扇出式晶圓封裝之封裝基板10，其包括載板11、再分佈層（redistribution layer，RDL）13。再分佈層13具有一或複數個疊合之介電層14、15，每一介電層14、15具有複數個導電通孔16、17。該等複數個導電通孔16、17上覆蓋著導電圖案18、19，因而形成多層之再分佈電路，以連接不同介電層之導電圖案。參考圖1A與圖1B，封裝基板10接著與晶片20接合，再塗佈封裝材料30，以完成晶片20的封裝，如圖1B所示。In the existing semiconductor process, fan-out wafer level package (FOPLP) is considered as a cost-effective next-generation IC technology for highly integrated packaging. FIG. 1A shows a package substrate 10 of a conventional fan-out wafer package, which includes a carrier board 11 and a redistribution layer (RDL) 13 . The redistribution layer 13 has one or a plurality of stacked dielectric layers 14 and 15 , and each of the dielectric layers 14 and 15 has a plurality of conductive vias 16 and 17 . The plurality of conductive vias 16, 17 are covered with conductive patterns 18, 19, thereby forming a multi-layer redistribution circuit for connecting the conductive patterns of different dielectric layers. Referring to FIG. 1A and FIG. 1B , the packaging substrate 10 is then bonded to the chip 20 , and then the packaging material 30 is coated to complete the packaging of the chip 20 , as shown in FIG. 1B .

如上所述，如果要知道封裝基板10是否為良品，必須在封裝基板10與晶片20接合之後才能進行電性量測。如此一來，一旦封裝基板10之再分佈電路不正常工作時，必須連同已經接合的晶片20一起報廢，損失甚大。As described above, to know whether the package substrate 10 is a good product, the electrical measurement must be performed after the package substrate 10 is bonded to the chip 20 . As a result, once the redistribution circuit of the package substrate 10 does not work properly, it must be scrapped together with the bonded chip 20, resulting in great loss.

因此，如何能夠在封裝基板10與晶片20接合之前即對於封裝基板10之再分佈電路進行檢測之技術，以減少晶片20因為封裝基板10的故障而一起報廢之風險，進而提升封裝晶片之良率，已成為電子封裝產業與其相關電子產業的重要研發課題之一。Therefore, how to detect the redistribution circuit of the packaging substrate 10 before the packaging substrate 10 is bonded to the chip 20 can reduce the risk of the chips 20 being scrapped together due to the failure of the packaging substrate 10, thereby improving the yield of the packaging chip , has become one of the important research and development topics in the electronic packaging industry and its related electronic industries.

有鑑於此，本發明提供一種用於封裝基板之電性量測技術，藉由導電黏著層的使用，可以實現一種封裝基板以及用於封裝基板之同側電性量測方法。In view of this, the present invention provides an electrical property measurement technology for a package substrate. By using a conductive adhesive layer, a package substrate and a same-side electrical property measurement method for the package substrate can be realized.

為達上述目的，於一實施例中，本發明提出一種用於封裝基板之同側電性量測方法，包括以下步驟：提供載板；塗佈導電黏著層於載板上；形成再分佈層，透過導電黏著層而黏合於載板上，再分佈層具有一或複數個疊合之介電層，每一介電層具有複數個導電通孔，複數個導電通孔上覆蓋著導電圖案，因而形成多層之再分佈電路，以連接不同介電層之導電圖案；以及在再分佈層上提供一對電極性相反之量測探針，以量測再分佈層之同側上的任兩個導電通孔之間的電阻值，以判斷同側上任兩個導電通孔之間的導通性。In order to achieve the above object, in one embodiment, the present invention provides a method for measuring the same-side electrical properties of a package substrate, which includes the following steps: providing a carrier board; coating a conductive adhesive layer on the carrier board; forming a redistribution layer , adhered to the carrier board through the conductive adhesive layer, the redistribution layer has one or more stacked dielectric layers, each dielectric layer has a plurality of conductive through holes, and the plurality of conductive through holes are covered with conductive patterns, thus forming A multi-layer redistribution circuit to connect the conductive patterns of different dielectric layers; and a pair of measuring probes with opposite polarities are provided on the redistribution layer to measure any two conductive contacts on the same side of the redistribution layer The resistance value between the holes is used to judge the continuity between any two conductive vias on the same side.

於一實施例中，載板係由玻璃、塑膠、印刷電路板或其他介電材料所形成。In one embodiment, the carrier is formed of glass, plastic, printed circuit board, or other dielectric materials.

於一實施例中，複數個導電通孔與複數個導電圖案係由沉積製程、微影製程、與蝕刻製程而形成。In one embodiment, the plurality of conductive vias and the plurality of conductive patterns are formed by a deposition process, a lithography process, and an etching process.

於一實施例中，導電黏著層係可剝離，以將再分佈層與載板分離。In one embodiment, the conductive adhesive layer is peelable to separate the redistribution layer from the carrier.

於一實施例中，用於封裝基板之同側電性量測方法，更包括以下步驟：移除導電黏著層與載板；以及在再分佈層上提供一對電極性相反之量測探針，以量測再分佈層之同側上的任兩個導電通孔之間的電阻值，以判斷同側上任兩個導電通孔之間的絕緣性。In one embodiment, the method for measuring the electrical properties on the same side of a package substrate further includes the following steps: removing the conductive adhesive layer and the carrier board; and providing a pair of measuring probes with opposite electrical polarities on the redistribution layer , to measure the resistance value between any two conductive vias on the same side of the redistribution layer to judge the insulation between any two conductive vias on the same side.

於另一實施例中，本發明提出一種封裝基板，包括：載板；導電黏著層，係塗佈於載板上；以及再分佈層，透過導電黏著層而黏合於載板上，再分佈層具有一或複數個疊合之介電層，每一介電層具有複數個導電通孔，複數個導電通孔上覆蓋著導電圖案，因而形成多層之再分佈電路，以連接不同介電層之導電圖案。In another embodiment, the present invention provides a package substrate, comprising: a carrier board; a conductive adhesive layer, which is coated on the carrier board; and a redistribution layer, which is adhered to the carrier board through the conductive adhesive layer, and the redistribution layer There is one or a plurality of superimposed dielectric layers, each dielectric layer has a plurality of conductive vias, and the conductive patterns are covered on the plurality of conductive vias, thus forming a multi-layer redistribution circuit to connect the conductive patterns of different dielectric layers .

綜合上述，本發明提供一種用於封裝基板之電性量測技術，藉由導電黏著層的使用，可以實現一種封裝基板以及用於封裝基板之同側電性量測方法，進而在封裝基板與晶片接合之前即對於封裝基板之再分佈電路進行檢測，以減少晶片因為封裝基板的故障而一起報廢之風險，並且提升封裝晶片之良率。In view of the above, the present invention provides an electrical property measurement technology for a package substrate. With the use of a conductive adhesive layer, a package substrate and a same-side electrical property measurement method for the package substrate can be realized, and then the package substrate and the package substrate can be connected to the same side of the electrical property measurement method. The redistribution circuit of the package substrate is inspected before die bonding, so as to reduce the risk of chips being scrapped together due to the failure of the package substrate, and improve the yield of packaged chips.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

請配合參考圖2A，其顯示本發明封裝基板50的橫截面示意圖以及進行同側電性量測之實施例。在圖2A中，首先提供載板11。接著，塗佈導電黏著層12於載板11上。之後，形成再分佈層13，其透過導電黏著層12而黏合於載板11上。再分佈層13具有一或複數個疊合之介電層14、15。於一實施例中，可以使用兩層介電層14、15。然而，本發明之範圍並不受限於疊合之介電層之數目。於一實施例中，每一介電層具有複數個導電通孔16、17，其上方覆蓋著導電圖案18、19，因而形成多層之再分佈電路，以透過導電通孔16、17連接不同介電層14、15之導電圖案18、19。接著，在再分佈層13上提供一對電極性相反之量測探針40、41。藉由導電黏著層12之導電特性，可以量測再分佈層之同側上的任兩個導電通孔之間的電阻值，以判斷同側上任兩個導電通孔16之間的導通性。Please refer to FIG. 2A , which shows a schematic cross-sectional view of the package substrate 50 of the present invention and an embodiment of performing the same-side electrical measurement. In Fig. 2A, the carrier plate 11 is first provided. Next, the conductive adhesive layer 12 is coated on the carrier board 11 . After that, the redistribution layer 13 is formed, which is adhered to the carrier board 11 through the conductive adhesive layer 12 . The redistribution layer 13 has one or more stacked dielectric layers 14 and 15 . In one embodiment, two dielectric layers 14, 15 may be used. However, the scope of the present invention is not limited by the number of stacked dielectric layers. In one embodiment, each dielectric layer has a plurality of conductive vias 16 , 17 , which are covered with conductive patterns 18 , 19 , thereby forming a multi-layer redistribution circuit for connecting different dielectrics through the conductive vias 16 , 17 . Conductive patterns 18 , 19 of the electrical layers 14 , 15 . Next, a pair of measuring probes 40 and 41 with opposite polarities are provided on the redistribution layer 13 . The resistance value between any two conductive vias on the same side of the redistribution layer can be measured by the conductive properties of the conductive adhesive layer 12 to determine the continuity between any two conductive vias 16 on the same side.

於一實施例中，載板11係由玻璃、塑膠、印刷電路板或其他介電材料所形成。於一實施例中，介電層14、15係由沉積製程、微影製程、與蝕刻製程而形成。詳而言之，在介電層14形成後，形成複數個開口，再利用導電材料的沉積與研磨，形成複數個導電通孔16，其上方再接著形成導電圖案18。同理，在以沉積製程形成介電層15後，形成複數個開口，再利用導電材料的沉積與研磨，形成複數個導電通孔17，其上方再接著形成導電圖案19。In one embodiment, the carrier board 11 is formed of glass, plastic, printed circuit board or other dielectric materials. In one embodiment, the dielectric layers 14, 15 are formed by a deposition process, a lithography process, and an etching process. Specifically, after the dielectric layer 14 is formed, a plurality of openings are formed, and then a plurality of conductive vias 16 are formed by deposition and grinding of a conductive material, and a conductive pattern 18 is then formed thereon. Similarly, after the dielectric layer 15 is formed by the deposition process, a plurality of openings are formed, and then a plurality of conductive vias 17 are formed by deposition and grinding of conductive materials, and then conductive patterns 19 are formed thereon.

簡言之，複數個導電通孔16、17與複數個導電圖案18、19係由沉積製程、微影製程、與蝕刻製程而形成。上述相關的半導體製程已為本技術領域中的人士所知悉，其詳細製程在此不予贅述。In short, the plurality of conductive vias 16, 17 and the plurality of conductive patterns 18, 19 are formed by a deposition process, a lithography process, and an etching process. The above-mentioned related semiconductor manufacturing process is known to those skilled in the art, and the detailed manufacturing process thereof will not be repeated here.

於一實施例中，導電黏著層12係可剝離，以將再分佈層13與載板11分離。基於上述特性，請配合參考圖2B，其顯示本發明封裝基板60的橫截面示意圖以及進行同側電性量測之另一實施例。於一實施例中，可以從封裝基板60中移除導電黏著層12與載板11。接著，在再分佈層13上提供一對電極性相反之量測探針40、41，以量測再分佈層之同側上的任兩個導電通孔之間的電阻值。由於此時已經沒有導電黏著層12來傳導另一側的電流，可以藉以判斷同側上任兩個導電通孔16之間的絕緣性。In one embodiment, the conductive adhesive layer 12 is peelable to separate the redistribution layer 13 from the carrier 11 . Based on the above characteristics, please refer to FIG. 2B , which shows a schematic cross-sectional view of the package substrate 60 of the present invention and another embodiment of performing the same-side electrical measurement. In one embodiment, the conductive adhesive layer 12 and the carrier 11 may be removed from the package substrate 60 . Next, a pair of measuring probes 40 and 41 with opposite polarities are provided on the redistribution layer 13 to measure the resistance value between any two conductive vias on the same side of the redistribution layer. Since there is no conductive adhesive layer 12 to conduct the current on the other side, the insulation between any two conductive vias 16 on the same side can be judged.

因此，於另一實施例中，請配合參考圖2A，本發明提出一種封裝基板50，包括載板11；導電黏著層12，係塗佈於載板11上；以及再分佈層13，透過導電黏著層12而黏合於載板11上，再分佈層具有一或複數個疊合之介電層14、15，每一介電層14、15具有複數個導電通孔16、17，上方上覆蓋著導電圖案18、19，因而形成多層之再分佈電路，以連接不同介電層之導電圖案。藉由導電黏著層12之導電特性，可以在再分佈層13上提供一對電極性相反之量測探針40、41，以量測再分佈層之同側上的任兩個導電通孔16之間的電阻值，進而判斷同側上任兩個導電通孔16之間的導通性。Therefore, in another embodiment, please refer to FIG. 2A , the present invention provides a package substrate 50 including a carrier board 11 ; a conductive adhesive layer 12 , which is coated on the carrier board 11 ; and a redistribution layer 13 , which passes through the conductive The adhesive layer 12 is adhered to the carrier board 11, and the redistribution layer has one or a plurality of stacked dielectric layers 14, 15, each of the dielectric layers 14, 15 has a plurality of conductive vias 16, 17, and the top is covered with conductive holes The patterns 18, 19 thus form a multi-layer redistribution circuit to connect the conductive patterns of the different dielectric layers. With the conductive properties of the conductive adhesive layer 12 , a pair of measuring probes 40 and 41 with opposite polarities can be provided on the redistribution layer 13 to measure any two conductive vias 16 on the same side of the redistribution layer. The resistance value between the two conductive vias 16 on the same side is further judged.

於一實施例中，導電黏著層12係可剝離，以將再分佈層13與載板11分離，而形成圖2B所示之封裝基板60。由於此時已經沒有導電黏著層12來傳導另一側的電流，可以在再分佈層13上提供一對電極性相反之量測探針40、41，以量測再分佈層之同側上的任兩個導電通孔16之間的電阻值，進而判斷同側上任兩個導電通孔16之間的絕緣性。In one embodiment, the conductive adhesive layer 12 can be peeled off to separate the redistribution layer 13 from the carrier 11 to form the package substrate 60 shown in FIG. 2B . Since there is no conductive adhesive layer 12 to conduct current on the other side, a pair of measuring probes 40 and 41 with opposite polarities can be provided on the redistribution layer 13 to measure the current on the same side of the redistribution layer. The resistance value between any two conductive vias 16 is used to determine the insulation between any two conductive vias 16 on the same side.

綜合上述，本發明提供一種用於封裝基板之電性量測技術，藉由導電黏著層的使用，可以實現一種封裝基板以及用於封裝基板之同側電性量測方法，進而在封裝基板與晶片接合之前即對於封裝基板之再分佈電路進行檢測，以減少晶片因為封裝基板的故障而一起報廢之風險，並且提升封裝晶片之良率。In view of the above, the present invention provides an electrical property measurement technology for a package substrate. With the use of a conductive adhesive layer, a package substrate and a same-side electrical property measurement method for the package substrate can be realized, and then the package substrate and the package substrate can be connected to the same side of the electrical property measurement method. The redistribution circuit of the package substrate is inspected before die bonding, so as to reduce the risk of chips being scrapped together due to the failure of the package substrate, and improve the yield of packaged chips.

雖然本發明的技術內容已經以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神所作些許之更動與潤飾，皆應涵蓋於本發明的範疇內，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the technical content of the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person who is familiar with the art, makes some changes and modifications without departing from the spirit of the present invention, should be included in the present invention. Therefore, the protection scope of the present invention should be determined by the scope of the appended patent application.

10、50、60:封裝基板 11:載板 12:導電黏著層 13:再分佈層 14、15:介電層 16、17:導電通孔 18、19:導電圖案 20:晶片 30:封裝材料 40、41:量測探針10, 50, 60: Package substrate 11: Carrier board 12: Conductive adhesive layer 13: Redistribution layer 14, 15: Dielectric layer 16, 17: Conductive vias 18, 19: Conductive pattern 20: Wafer 30: Encapsulation material 40, 41: Measuring probe

圖1A係習知封裝基板的橫截面示意圖； 圖1B係習知已完成封裝之晶片的橫截面示意圖； 圖2A係本發明封裝基板的橫截面示意圖以及進行同側電性量測之實施例；以及 圖2B係本發明封裝基板的橫截面示意圖以及進行同側電性量測之另一實施例。1A is a schematic cross-sectional view of a conventional package substrate; 1B is a schematic cross-sectional view of a conventional packaged chip; FIG. 2A is a schematic cross-sectional view of the package substrate of the present invention and an embodiment of performing the same-side electrical measurement; and FIG. 2B is a schematic cross-sectional view of the package substrate of the present invention and another embodiment of performing the same-side electrical measurement.

50:封裝基板50: Package substrate

11:載板11: Carrier board

12:導電黏著層12: Conductive adhesive layer

13:再分佈層13: Redistribution layer

14、15:介電層14, 15: Dielectric layer

16、17:導電通孔16, 17: Conductive vias

18、19:導電圖案18, 19: Conductive pattern

40、41:量測探針40, 41: Measuring probe

Claims (9)

一種用於封裝基板之同側電性量測方法，包括以下步驟： 提供一載板； 塗佈一導電黏著層於該載板上； 形成一再分佈層，透過該導電黏著層而黏合於該載板上，該再分佈層具有一或複數個疊合之介電層，每一介電層具有複數個導電通孔，該複數個導電通孔上覆蓋著一導電圖案，因而形成多層之再分佈電路，以連接不同介電層之導電圖案；以及 在該再分佈層上提供一對電極性相反之量測探針，以量測該再分佈層之同側上的任兩個導電通孔之間的電阻值，以判斷該同側上該任兩個導電通孔之間的導通性。A method for measuring the same-side electrical properties of a package substrate, comprising the following steps: provide a carrier board; coating a conductive adhesive layer on the carrier; A redistribution layer is formed, which is adhered to the carrier board through the conductive adhesive layer, the redistribution layer has one or a plurality of stacked dielectric layers, each dielectric layer has a plurality of conductive vias, and the plurality of conductive vias covered with a conductive pattern, thereby forming a multi-layer redistribution circuit to connect the conductive patterns of different dielectric layers; and A pair of measuring probes with opposite polarities are provided on the redistribution layer to measure the resistance value between any two conductive vias on the same side of the redistribution layer, so as to determine the Conductivity between two conductive vias. 如請求項1所述之用於封裝基板之同側電性量測方法，其中該載板係由玻璃、塑膠、印刷電路板或其他介電材料所形成。The same-side electrical measurement method for a package substrate as claimed in claim 1, wherein the carrier board is formed of glass, plastic, printed circuit board or other dielectric materials. 如請求項1所述之用於封裝基板之同側電性量測方法，其中該複數個導電通孔與該複數個導電圖案係由沉積製程、微影製程、與蝕刻製程而形成。The same-side electrical measurement method for a package substrate as claimed in claim 1, wherein the plurality of conductive vias and the plurality of conductive patterns are formed by a deposition process, a lithography process, and an etching process. 如請求項1所述之用於封裝基板之同側電性量測方法，其中該導電黏著層係可剝離，以將該再分佈層與該載板分離。The same-side electrical measurement method for a package substrate as claimed in claim 1, wherein the conductive adhesive layer is peelable to separate the redistribution layer from the carrier. 如請求項4所述之用於封裝基板之同側電性量測方法，更包括以下步驟： 移除該導電黏著層與該載板；以及 在該再分佈層上提供一對電極性相反之量測探針，以量測該再分佈層之同側上的任兩個導電通孔之間的電阻值，以判斷該同側上該任兩個導電通孔之間的絕緣性。The same-side electrical property measurement method for a package substrate as described in claim 4, further comprising the following steps: removing the conductive adhesive layer and the carrier; and A pair of measuring probes with opposite polarities are provided on the redistribution layer to measure the resistance value between any two conductive vias on the same side of the redistribution layer, so as to determine the Insulation between two conductive vias. 一種封裝基板，包括： 一載板； 一導電黏著層，係塗佈於該載板上；以及 一再分佈層，透過該導電黏著層而黏合於該載板上，該再分佈層具有一或複數個疊合之介電層，每一介電層具有複數個導電通孔，該複數個導電通孔上覆蓋著一導電圖案，因而形成多層之再分佈電路，以連接不同介電層之導電圖案。A package substrate, comprising: a carrier board; a conductive adhesive layer coated on the carrier; and A redistribution layer is adhered to the carrier board through the conductive adhesive layer, the redistribution layer has one or a plurality of stacked dielectric layers, each dielectric layer has a plurality of conductive vias, and the plurality of conductive vias Covered with a conductive pattern, thus forming a multi-layer redistribution circuit to connect the conductive patterns of different dielectric layers. 如請求項6所述之封裝基板，其中該載板係由玻璃、塑膠、印刷電路板或其他介電材料所形成。The package substrate of claim 6, wherein the carrier is formed of glass, plastic, printed circuit board or other dielectric materials. 如請求項6所述之封裝基板，其中該複數個導電通孔與該複數個導電圖案係由沉積製程、微影製程、與蝕刻製程而形成。The package substrate of claim 6, wherein the plurality of conductive vias and the plurality of conductive patterns are formed by a deposition process, a lithography process, and an etching process. 如請求項6所述之封裝基板，其中該導電黏著層係可剝離，以將該再分佈層與該載板分離。The package substrate of claim 6, wherein the conductive adhesive layer is peelable to separate the redistribution layer from the carrier.
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