TW202145217A - Memory cell, memory device and method of forming the same - Google Patents

Memory cell, memory device and method of forming the same Download PDF

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TW202145217A
TW202145217A TW110108203A TW110108203A TW202145217A TW 202145217 A TW202145217 A TW 202145217A TW 110108203 A TW110108203 A TW 110108203A TW 110108203 A TW110108203 A TW 110108203A TW 202145217 A TW202145217 A TW 202145217A
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ferroelectric
ferroelectric layer
oxide semiconductor
valence
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TWI779510B (en
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呂俊頡
張志宇
楊柏峰
世海 楊
林佑明
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台灣積體電路製造股份有限公司
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Abstract

A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

Description

鐵電記憶元件及其形成方法Ferroelectric memory element and method of forming the same

半導體元件用於多種電子應用中，諸如個人電腦、蜂巢式電話、數位攝影機以及其他電子設備。通常藉由在半導體基底上方依序沈積絕緣層或介電層、導電層以及半導體層，且使用微影術及蝕刻技術來圖案化各種材料層以在其上形成電路構件及部件來製造半導體元件。Semiconductor components are used in a variety of electronic applications, such as personal computers, cellular telephones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate, and using lithography and etching techniques to pattern layers of various materials to form circuit components and components thereon .

半導體產業藉由持續減小最小特徵大小來持續改良各種電子構件（例如，電晶體、二極體、電阻器、電容器等）的整合密度，從而允許更多構件整合至給定區域中。然而，隨著最小特徵大小減小，出現應解決的額外問題。The semiconductor industry continues to improve the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continuing to reduce minimum feature sizes, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, additional issues arise that should be addressed.

以下揭露內容提供用以實施本發明的不同特徵的許多不同實施例或實例。下文描述構件及配置的特定實例以簡化本揭露。當然，這些構件及配置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或第二特徵上的形成可包括第一特徵及第二特徵直接接觸地形成的實施例，且亦可包括額外特徵可在第一特徵與第二特徵之間形成以使得第一特徵及第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複附圖標號及/或字母。此重複是出於簡單及清楚的目的，且本身並不表示所論述的各種實施例及/或組態之間的關係。The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are examples only and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include additional features that may be formed on the second feature. Embodiments in which a feature and a second feature are formed such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in various instances. This repetition is for simplicity and clarity, and does not in itself represent a relationship between the various embodiments and/or configurations discussed.

此外，為易於描述，可使用諸如「在...之下」、「在...下方」、「下部」、「在...上方」、「上部」以及類似術語的空間相對術語來描述如諸圖中所示出的一個元件或特徵相對於另一元件或特徵的關係。除圖式中所描繪的定向以外，空間相對術語意欲涵蓋元件在使用或操作中的不同定向。裝置可以其他方式定向（旋轉90度或位於其他定向），且本文中所使用的空間相對描述詞可同樣相應地進行解釋。Additionally, for ease of description, spatially relative terms such as "below", "below", "lower", "above", "upper" and similar terms may be used to describe The relationship of one element or feature to another element or feature as shown in the figures. In addition to the orientation depicted in the figures, spatially relative terms are intended to encompass different orientations of elements in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

各種實施例提供諸如3D記憶陣列的記憶元件。在一些實施例中，3D記憶陣列為包括多個垂直堆疊的記憶胞的鐵電場效電晶體（ferroelectric field effect transistor；FeFET）記憶體電路。在一些實施例中，各別記憶胞被視為FeFET，所述FeFET包括充當閘電極的字元線區、充當第一源極/汲極電極的位元線區以及充當第二源極/汲極電極的源極線區、做為閘介電質的鐵電材料以及做為通道區的氧化物半導體（oxide semiconductor；OS）。在一些實施例中，各別記憶胞被視為薄膜電晶體（thin film transistor；TFT）。Various embodiments provide memory elements such as 3D memory arrays. In some embodiments, the 3D memory array is a ferroelectric field effect transistor (FeFET) memory circuit including a plurality of vertically stacked memory cells. In some embodiments, the respective memory cells are considered FeFETs that include a wordline region serving as a gate electrode, a bitline region serving as a first source/drain electrode, and a second source/drain electrode The source line region of the electrode electrode, the ferroelectric material as the gate dielectric, and the oxide semiconductor (OS) as the channel region. In some embodiments, the respective memory cells are regarded as thin film transistors (TFTs).

圖1A、圖1B以及圖1C示出根據一些實施例的記憶陣列的實例。圖1A以部分三維圖示出簡化記憶陣列200的一部分的實例；圖1B示出記憶陣列200的電路圖；且圖1C示出根據一些實施例的記憶陣列200的自上而下視圖。記憶陣列200包括多個記憶胞202，所述多個記憶胞202可配置於列及行的網格中。記憶胞202可進一步垂直堆疊以提供三維記憶陣列，由此增加元件密度。記憶陣列200可安置在半導體晶粒的後段生產線（back end of line；BEOL）中。舉例而言，記憶陣列可安置在半導體晶粒的內連線層中，諸如，安置於在半導體基底上形成的一或多個主動元件（例如，電晶體）上方。1A, 1B, and 1C illustrate examples of memory arrays in accordance with some embodiments. FIG. 1A shows an example of a portion of a simplified memory array 200 in partial three-dimensional view; FIG. 1B shows a circuit diagram of memory array 200 ; and FIG. 1C shows a top-down view of memory array 200 in accordance with some embodiments. The memory array 200 includes a plurality of memory cells 202 that can be arranged in a grid of columns and rows. The memory cells 202 can be further stacked vertically to provide a three-dimensional memory array, thereby increasing device density. The memory array 200 may be disposed in a back end of line (BEOL) of semiconductor die. For example, a memory array may be disposed in an interconnect layer of a semiconductor die, such as over one or more active elements (eg, transistors) formed on a semiconductor substrate.

在一些實施例中，記憶陣列200為記憶陣列，諸如NOR記憶陣列或類似者。在一些實施例中，每一記憶胞202的閘極電耦接至各別字元線（例如，導線72），每一記憶胞202的第一源極/汲極區電耦接至各別位元線（例如，導線116B），且每一記憶胞202的第二源極/汲極區電耦接至各別源極線（例如，導線116A），所述各別源極線將第二源極/汲極區電耦接至地面。在記憶陣列200的同一水平列中的記憶胞202可共用共同字元線，而在記憶陣列200的同一垂直行中的記憶胞202可共用共同源極線及共同位元線。In some embodiments, the memory array 200 is a memory array, such as a NOR memory array or the like. In some embodiments, the gate of each memory cell 202 is electrically coupled to a respective word line (eg, wire 72 ), and the first source/drain region of each memory cell 202 is electrically coupled to a respective bit line (eg, wire 116B), and the second source/drain region of each memory cell 202 is electrically coupled to a respective source line (eg, wire 116A) that connects the first The two source/drain regions are electrically coupled to ground. The memory cells 202 in the same horizontal column of the memory array 200 can share a common word line, and the memory cells 202 in the same vertical row of the memory array 200 can share a common source line and a common bit line.

記憶陣列200包括多個垂直堆疊的導線72（例如，字元線），其中介電層52安置在導線72中的相鄰導線之間。導線72在與下伏基底（在圖1A及圖1B中未明確示出）的主表面平行的方向上延伸。導線72可具有階梯組態，使得下部導線72比上部導線72的端點長且橫向延伸超過上部導線72的端點。舉例而言，在圖1A中，示出導線72的多個堆疊層，其中最頂部導線72最短，而最底部導線72最長。導線72的各別長度可在朝著下伏基底的方向上增加。以此方式，可自記憶陣列200上方存取導線72中的每一者的一部分，且可分別電性接觸導線72的暴露部分。Memory array 200 includes a plurality of vertically stacked conductors 72 (eg, word lines) with dielectric layer 52 disposed between adjacent ones of conductors 72 . The wires 72 extend in a direction parallel to the major surface of the underlying substrate (not explicitly shown in FIGS. 1A and 1B ). The leads 72 may have a stepped configuration such that the lower leads 72 are longer than the endpoints of the upper leads 72 and extend laterally beyond the endpoints of the upper leads 72 . For example, in FIG. 1A , multiple stacked layers of wires 72 are shown, with the topmost wire 72 being the shortest and the bottommost wire 72 the longest. The respective lengths of the wires 72 may increase in the direction towards the underlying substrate. In this manner, a portion of each of the wires 72 can be accessed from above the memory array 200 and the exposed portions of the wires 72 can be electrically contacted, respectively.

記憶陣列200更包括交替配置的導電柱106（例如，電連接至位元線）及導電柱108（例如，電連接至源極線）導電柱106及導電柱108可各自在垂直於導線72的方向上延伸。介電材料98安置在導電柱106及導電柱108中的相鄰導電柱之間且隔離導電柱106及導電柱108中的相鄰導電柱。Memory array 200 further includes alternating conductive pillars 106 (eg, electrically connected to bit lines) and conductive pillars 108 (eg, electrically connected to source lines). extending in the direction. Dielectric material 98 is disposed between conductive pillars 106 and adjacent ones of conductive pillars 108 and isolates conductive pillars 106 and adjacent ones of conductive pillars 108 .

導電柱106及導電柱108的對與相交的導線72一起界定每一記憶胞202的邊界，且隔離柱102安置在導電柱106及導電柱108的相鄰對之間且隔離導電柱106及導電柱108的相鄰對。在一些實施例中，導電柱108電耦接至地面。儘管圖1A示出導電柱106相對於導電柱108的特定配置，但應瞭解，在其他實施例中，可交換導電柱106及導電柱108的配置。Pairs of conductive pillars 106 and 108, along with intersecting wires 72, define the boundaries of each memory cell 202, and isolation pillars 102 are disposed between adjacent pairs of conductive pillars 106 and 108 and isolate conductive pillars 106 and conductive pillars 102. Adjacent pairs of posts 108. In some embodiments, conductive pillar 108 is electrically coupled to ground. Although FIG. 1A shows a particular configuration of conductive pillars 106 relative to conductive pillars 108, it should be understood that in other embodiments, the configurations of conductive pillars 106 and conductive pillars 108 may be interchanged.

在一些實施例中，記憶陣列200亦可包括做為通道層92的氧化物半導體（OS）材料。通道層92可為記憶胞202提供通道區。舉例而言，在經由對應導線72施加適當電壓（例如高於對應記憶胞202的各別臨限電壓（Vth ））時，通道層92的與導線72相交的區可允許電流（例如在藉由箭頭206指示的方向上）自導電柱106流動至導電柱108。In some embodiments, the memory array 200 may also include an oxide semiconductor (OS) material as the channel layer 92 . The channel layer 92 may provide a channel area for the memory cells 202 . For example, the region of the channel layer 92 that intersects the wire 72 may allow current flow (eg, by borrowing a voltage higher than the respective threshold voltage (V th ) of the corresponding memory cell 202 ) when an appropriate voltage is applied via the corresponding wire 72 . flow from conductive pillar 106 to conductive pillar 108 in the direction indicated by arrow 206 .

在一些實施例中，鐵電層90'安置在通道層92與導線72及介電層52中的每一者之間，且鐵電層90'可充當每一記憶胞202的閘介電質。在一些實施例中，鐵電層90'包括鐵電材料，諸如氧化鉿、氧化鋯鉿、矽摻雜氧化鉿或類似物。In some embodiments, ferroelectric layer 90 ′ is disposed between channel layer 92 and each of wire 72 and dielectric layer 52 , and ferroelectric layer 90 ′ can serve as the gate dielectric for each memory cell 202 . In some embodiments, the ferroelectric layer 90' includes a ferroelectric material, such as hafnium oxide, zirconium hafnium oxide, silicon-doped hafnium oxide, or the like.

鐵電層90'可在兩個不同方向中的一者上極化，且可藉由在鐵電層90'上施加適當電壓差且產生適當電場來改變極化方向。極化可相對集中（例如，通常含有於記憶胞202的每一邊界內），且鐵電層90'的連續區可在多個記憶胞202上延伸。依據鐵電層90'的特定區的極化方向，對應記憶胞202的臨限電壓不同，且可儲存數位值（例如0或1）。舉例而言，在鐵電層90'的區具有第一電性極化方向時，對應記憶胞202可具有相對較低臨限電壓，且在鐵電層90'的區具有第二電性極化方向時，對應記憶胞202可具有相對較高臨限電壓。兩個臨限電壓之間的差可稱為臨限電壓偏移。較大臨限電壓偏移使得讀取儲存於對應記憶胞202中的數位值更容易（例如更不易出錯）。The ferroelectric layer 90' can be polarized in one of two different directions, and the direction of polarization can be changed by applying an appropriate voltage difference and generating an appropriate electric field across the ferroelectric layer 90'. The polarization can be relatively concentrated (eg, typically contained within each boundary of the memory cells 202 ), and a continuous region of the ferroelectric layer 90 ′ can extend over multiple memory cells 202 . According to the polarization direction of a specific region of the ferroelectric layer 90 ′, the threshold voltage of the corresponding memory cell 202 is different, and a digital value (eg, 0 or 1) can be stored. For example, when the region of the ferroelectric layer 90' has a first electrical polarization direction, the corresponding memory cell 202 may have a relatively low threshold voltage, and the region of the ferroelectric layer 90' has a second electrical polarization The corresponding memory cell 202 may have a relatively high threshold voltage when changing the direction. The difference between the two threshold voltages may be referred to as the threshold voltage offset. A larger threshold voltage offset makes it easier (eg, less error-prone) to read the digital value stored in the corresponding memory cell 202 .

在一些實施例中，鐵電層90'含有價數為5（例如氮（N））或價數為7（例如氟（F））或其組合的物質（例如，額外物質），以便消除或阻止鐵電層90'與通道層92之間的界面IF2中的陷阱或缺陷，且/或佔據鐵電層90'中的氧空缺且充當鈍化物以抑制氧、氫以及空缺的相互擴散，以提升鐵電層90'的固有疲勞效能及耐久性。In some embodiments, the ferroelectric layer 90' contains species (eg, additional species) with a valence of 5 (eg, nitrogen (N)) or a valence of 7 (eg, fluorine (F)), or a combination thereof, to eliminate or prevent traps or defects in the interface IF2 between the ferroelectric layer 90' and the channel layer 92, and/or occupy oxygen vacancies in the ferroelectric layer 90' and act as passivators to inhibit the interdiffusion of oxygen, hydrogen, and vacancies to The inherent fatigue performance and durability of the ferroelectric layer 90' are improved.

在此類實施例中，為對記憶胞202執行寫入操作，在鐵電層90'的對應於記憶胞202的一部分上施加寫入電壓。在一些實施例中，例如藉由施加適當電壓至對應導線72（例如字元線）及對應導電柱106/108（例如位元線/源極線）來施加寫入電壓。藉由在鐵電層90'的部分上施加寫入電壓，可改變鐵電層90'的區的極化方向。因此，對應記憶胞202的對應臨限電壓亦可自低臨限電壓切換至高臨限電壓，或反之亦然，且數位值可儲存於記憶胞202中。由於導線72與導電柱106及導電柱108相交，故可針對寫入操作選擇個別記憶胞202。In such embodiments, to perform a write operation on the memory cells 202, a write voltage is applied to a portion of the ferroelectric layer 90' corresponding to the memory cells 202. In some embodiments, the write voltage is applied, for example, by applying appropriate voltages to corresponding wires 72 (eg, word lines) and corresponding conductive pillars 106/108 (eg, bit lines/source lines). By applying a write voltage across portions of the ferroelectric layer 90', the polarization direction of the regions of the ferroelectric layer 90' can be changed. Therefore, the corresponding threshold voltage of the corresponding memory cell 202 can also be switched from a low threshold voltage to a high threshold voltage, or vice versa, and the digital value can be stored in the memory cell 202 . Since wires 72 intersect conductive pillars 106 and 108, individual memory cells 202 can be selected for write operations.

在此類實施例中，為對記憶胞202執行讀取操作，讀取電壓（低臨限電壓與高臨限電壓之間的電壓）施加至對應導線72（例如字元線）。依據鐵電層90'的對應區的極化方向，記憶胞202可或可不接通。因此，導電柱106可或可不經由導電柱108（例如耦接至地面的源極線）放電，且可判定儲存於記憶胞202中的數位值。由於導線72與導電柱106及導電柱108相交，故可針對讀取操作選擇個別記憶胞202。In such embodiments, to perform a read operation on a memory cell 202, a read voltage (a voltage between a low threshold voltage and a high threshold voltage) is applied to corresponding conductor lines 72 (eg, word lines). Depending on the polarization direction of the corresponding region of the ferroelectric layer 90', the memory cells 202 may or may not be turned on. Thus, conductive pillar 106 may or may not be discharged through conductive pillar 108 (eg, a source line coupled to ground), and the digital value stored in memory cell 202 may be determined. Since wires 72 intersect conductive pillars 106 and 108, individual memory cells 202 can be selected for read operations.

圖1A的部分三維圖進一步示出對應於記憶陣列200的參考橫截面的線，其在後續圖中使用。橫截面B-B'沿著導線72的縱向軸線且在例如與記憶胞202的電流流動的方向平行的方向上。橫截面C-C'垂直於橫截面B-B'且延伸穿過介電材料98及隔離柱102。橫截面D-D'垂直於橫截面B-B'且延伸穿過介電材料98及導電柱106。為了清楚起見，後續圖式參考這些參考橫截面。The partial three-dimensional view of FIG. 1A further illustrates lines corresponding to reference cross-sections of memory array 200, which are used in subsequent figures. Cross section BB' is along the longitudinal axis of wire 72 and in a direction parallel to the direction of current flow of memory cell 202, for example. Cross section CC' is perpendicular to cross section BB' and extends through dielectric material 98 and isolation pillar 102 . Cross-section DD' is perpendicular to cross-section BB' and extends through dielectric material 98 and conductive pillar 106 . For clarity, subsequent figures refer to these reference cross-sections.

在圖2中，提供基底50。基底50可為半導體基底，諸如塊狀半導體、絕緣層上半導體（semiconductor-on-insulator；SOI）基底或類似者，所述半導體基底可經摻雜（例如藉由p型摻雜劑或n型摻雜劑）或未經摻雜。基底50可為積體電路晶粒，諸如邏輯晶粒、記憶體晶粒、ASIC晶粒或類似晶粒。基底50可為互補金屬氧化物半導體（complementary metal oxide semiconductor；CMOS）晶粒且可稱為陣列下CMOS（CMOS under array；CUA）。基底50可為晶圓，諸如矽晶圓。通常，SOI基底為形成於絕緣層上的半導體材料層。絕緣層可為例如內埋氧化物（buried oxide；BOX）層、氧化矽層或類似物。絕緣層設置於基底上，通常矽基底或玻璃基底上。亦可使用其他基底，諸如多層基底或梯度基底。在一些實施例中，基底50的半導體材料可包括：矽；鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括矽-鍺、磷化砷鎵、砷化銦鋁、砷化鎵鋁、砷化銦鎵、磷化銦鎵及/或磷化砷銦鎵；或其組合。In Figure 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (eg, by p-type dopants or n-type dopant) or undoped. The substrate 50 may be an integrated circuit die, such as a logic die, memory die, ASIC die, or the like. The substrate 50 may be a complementary metal oxide semiconductor (CMOS) die and may be referred to as CMOS under array (CUA). The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on a substrate, usually a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; alloy semiconductors, Including silicon-germanium, gallium arsenide phosphide, indium aluminum arsenide, gallium aluminum arsenide, indium gallium arsenide, indium gallium phosphide and/or indium gallium arsenide phosphide; or combinations thereof.

圖2進一步示出可形成在基底50上方的電路。電路包括基底50的頂面處的電晶體。電晶體可包括基底50的頂面上方的閘介電層302及閘介電層302上方的閘電極304。源極/汲極區306在閘介電層302及閘電極304的相對側上安置在基底50中。閘極間隔件308沿著閘介電層302的側壁形成且使源極/汲極區306與閘電極304分隔開適當橫向距離。電晶體可包括鰭式場效電晶體（fin field effect transistor；FinFET）、奈米結構（例如，奈米片、奈米線、環繞式閘極或類似物）FET（奈米-FET）、平面FET、類似物或其組合，且可藉由先閘極製程或後閘極製程形成。FIG. 2 further illustrates circuits that may be formed over substrate 50 . The circuit includes transistors at the top surface of substrate 50 . The transistor may include a gate dielectric layer 302 over the top surface of the substrate 50 and a gate electrode 304 over the gate dielectric layer 302 . Source/drain regions 306 are disposed in substrate 50 on opposite sides of gate dielectric layer 302 and gate electrode 304 . Gate spacers 308 are formed along the sidewalls of the gate dielectric layer 302 and separate the source/drain regions 306 from the gate electrode 304 by a suitable lateral distance. Transistors may include fin field effect transistors (FinFETs), nanostructured (eg, nanochips, nanowires, wraparound gates, or the like) FETs (nano-FETs), planar FETs , the like, or a combination thereof, and may be formed by a gate-first process or a gate-last process.

第一層間介電質（inter-layer dielectric；ILD）310包圍且隔離源極/汲極區306、閘介電層302以及閘電極304，第二ILD 312在第一ILD 310上方。源極/汲極接觸窗314延伸穿過第二ILD 312及第一ILD 310且電耦接至源極/汲極區306，且閘極接觸窗316延伸穿過第二ILD 312且電耦接至閘電極304。內連線結構320在第二ILD 312、源極/汲極接觸窗314以及閘極接觸窗316上方。內連線結構320包括一或多個堆疊的介電層324及形成在例如一或多個介電層324中的導電特徵322。內連線結構320可電連接至閘極接觸窗316及源極/汲極接觸窗314以形成功能電路。在一些實施例中，藉由內連線結構320形成的功能電路可包括邏輯電路、記憶體電路、感測放大器、控制器、輸入/輸出電路、影像感測器電路、類似物或其組合。雖然圖2論述在基底50上方形成的電晶體，但其他主動元件（例如，二極體或類似物）及/或被動元件（例如，電容器、電阻器或類似物）亦可形成為功能電路的部分。A first inter-layer dielectric (ILD) 310 surrounds and isolates the source/drain regions 306 , the gate dielectric layer 302 and the gate electrode 304 , and the second ILD 312 is above the first ILD 310 . Source/drain contact 314 extends through second ILD 312 and first ILD 310 and is electrically coupled to source/drain region 306, and gate contact 316 extends through second ILD 312 and is electrically coupled to the gate electrode 304 . The interconnect structure 320 is over the second ILD 312 , the source/drain contacts 314 and the gate contacts 316 . The interconnect structure 320 includes one or more stacked dielectric layers 324 and conductive features 322 formed, for example, in the one or more dielectric layers 324 . The interconnect structure 320 can be electrically connected to the gate contact 316 and the source/drain contact 314 to form a functional circuit. In some embodiments, functional circuits formed by interconnect structure 320 may include logic circuits, memory circuits, sense amplifiers, controllers, input/output circuits, image sensor circuits, the like, or combinations thereof. Although FIG. 2 discusses transistors formed over substrate 50, other active elements (eg, diodes or the like) and/or passive elements (eg, capacitors, resistors, or the like) may also be formed as functional circuits part.

在圖3中，在圖2的結構上方形成多層堆疊58。出於簡單及清楚的目的，可自後續圖式中省略基底50、電晶體、ILD 310及ILD 312以及內連線結構320。雖然多層堆疊58示出為接觸內連線結構320的介電層324，但可在基底50與多層堆疊58之間安置任何數目的中間層。舉例而言，包括絕緣層（例如，低k介電層）中的導電特徵的一或多個內連線層可安置在基底50與多層堆疊58之間。在一些實施例中，可圖案化導電特徵以為基底50及/或記憶陣列200（參看圖1A及圖1B）上的主動元件提供功率、接地及/或信號線。在一些實施例中，包括絕緣層（例如，低k介電層）中的導電特徵的一或多個內連線層可安置在多層堆疊58上方。In FIG. 3 , a multi-layer stack 58 is formed over the structure of FIG. 2 . For simplicity and clarity, substrate 50, transistors, ILD 310 and ILD 312, and interconnect structure 320 may be omitted from subsequent figures. Although multilayer stack 58 is shown contacting dielectric layer 324 of interconnect structure 320 , any number of intervening layers may be disposed between substrate 50 and multilayer stack 58 . For example, one or more interconnect layers including conductive features in an insulating layer (eg, a low-k dielectric layer) may be disposed between substrate 50 and multilayer stack 58 . In some embodiments, the conductive features can be patterned to provide power, ground, and/or signal lines for active elements on substrate 50 and/or memory array 200 (see FIGS. 1A and 1B ). In some embodiments, one or more interconnect layers including conductive features in an insulating layer (eg, a low-k dielectric layer) may be disposed over multilayer stack 58 .

在圖3中，多層堆疊58包括犧牲層53A至犧牲層53D（統稱為犧牲層53）及介電層52A至介電層52E（統稱為介電層52）的交替層。可在後續步驟中圖案化且取代犧牲層53以界定導線72（例如，字元線）。犧牲層53可包括介電材料，諸如氧化矽、氮化矽、氮氧化矽、其組合或類似物。介電層52可包括絕緣材料，諸如氧化矽、氮化矽、氮氧化矽、其組合或類似物。犧牲層53及介電層52包括具有不同蝕刻選擇性的不同材料。在一些實施例中，犧牲層53包括氮化矽，且介電層52包括氧化矽。可使用例如化學氣相沈積（chemical vapor deposition；CVD）、原子層沈積（atomic layer deposition；ALD）、物理氣相沈積（physical vapor deposition；PVD）、電漿增強CVD（plasma enhanced CVD；PECVD）或類似者來形成犧牲層53及介電層52中的每一者。In FIG. 3, the multi-layer stack 58 includes alternating layers of sacrificial layers 53A-53D (collectively referred to as sacrificial layers 53) and dielectric layers 52A-52E (collectively referred to as dielectric layers 52). Sacrificial layer 53 may be patterned and replaced in subsequent steps to define conductive lines 72 (eg, word lines). The sacrificial layer 53 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. Dielectric layer 52 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. The sacrificial layer 53 and the dielectric layer 52 include different materials with different etch selectivities. In some embodiments, sacrificial layer 53 includes silicon nitride, and dielectric layer 52 includes silicon oxide. For example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD) or Each of sacrificial layer 53 and dielectric layer 52 is formed similarly.

雖然圖3示出特定數目的犧牲層53及介電層52，但其他實施例可包括不同數目的犧牲層53及介電層52。此外，雖然多層堆疊58示出為具有做為最頂部層及最底部層的介電層，但本揭露不限於此。在一些實施例中，多層堆疊58的最頂部層及最底部層中的至少一者為犧牲層。Although FIG. 3 shows a specific number of sacrificial layers 53 and dielectric layers 52 , other embodiments may include different numbers of sacrificial layers 53 and dielectric layers 52 . Furthermore, although the multi-layer stack 58 is shown as having dielectric layers as the topmost layer and the bottommost layer, the present disclosure is not so limited. In some embodiments, at least one of the topmost layer and the bottommost layer of the multilayer stack 58 is a sacrificial layer.

圖4至圖12為根據一些實施例的製造記憶陣列200的階梯結構中的中間階段的視圖。示出沿著圖1A中所示出的參考橫截面B-B'的圖4至圖12。4-12 are views of intermediate stages in fabricating a ladder structure of memory array 200 in accordance with some embodiments. Figures 4 to 12 are shown along the reference cross-section BB' shown in Figure 1A.

在圖4中，在多層堆疊58上方形成光阻56。在一些實施例中，光阻56藉由旋塗技術形成且藉由可接受的微影技術圖案化。圖案化所述光阻56可暴露區60中的多層堆疊58，同時遮蔽多層堆疊58的剩餘部分。舉例而言，多層堆疊58的最頂部層（例如，介電層52E）可在區60中暴露。In FIG. 4 , photoresist 56 is formed over multilayer stack 58 . In some embodiments, photoresist 56 is formed by spin coating techniques and patterned by acceptable lithography techniques. Patterning the photoresist 56 may expose the multilayer stack 58 in the region 60 while masking the remainder of the multilayer stack 58 . For example, the topmost layer of multilayer stack 58 (eg, dielectric layer 52E) may be exposed in region 60 .

在圖5中，使用光阻56做為罩幕來蝕刻區60中的多層堆疊58的暴露部分。蝕刻可為任何可接受的蝕刻製程，諸如乾式蝕刻（例如，反應性離子蝕刻（reactive ion etch；RIE）、中性束蝕刻（neutral beam etch；NBE）、類似蝕刻）、濕式蝕刻、類似蝕刻或其組合。蝕刻可為非等向性的。蝕刻可移除區60中的介電層52E及犧牲層53D的部分且界定開口61。由於介電層52E及犧牲層53D具有不同材料組成物，故用於移除這些層的暴露部分的蝕刻劑可不同。在一些實施例中，在蝕刻介電層52E時，犧牲層53D充當蝕刻終止層，且在蝕刻犧牲層53D時，介電層52D充當蝕刻終止層。因此，可在不移除多層堆疊58的剩餘層的情況下選擇性地移除介電層52E及犧牲層53D的部分，且開口61可延伸至所要深度。替代地，時間模式蝕刻製程可用於在開口61達到所要深度之後停止開口61的蝕刻。在所得結構中，介電層52D暴露於區60中。In FIG. 5, the exposed portions of the multilayer stack 58 in the region 60 are etched using the photoresist 56 as a mask. The etching can be any acceptable etching process, such as dry etching (eg, reactive ion etch (RIE), neutral beam etch (NBE), similar etch), wet etch, similar etch or a combination thereof. Etching can be anisotropic. Portions of dielectric layer 52E and sacrificial layer 53D in removable region 60 are etched and openings 61 are defined. Since dielectric layer 52E and sacrificial layer 53D have different material compositions, the etchants used to remove exposed portions of these layers may be different. In some embodiments, sacrificial layer 53D acts as an etch stop layer when dielectric layer 52E is etched, and dielectric layer 52D acts as an etch stop layer when sacrificial layer 53D is etched. Accordingly, portions of dielectric layer 52E and sacrificial layer 53D can be selectively removed without removing the remaining layers of multilayer stack 58, and openings 61 can extend to a desired depth. Alternatively, a time mode etch process can be used to stop the etching of openings 61 after openings 61 have reached a desired depth. In the resulting structure, dielectric layer 52D is exposed in region 60 .

在圖6中，修整光阻56以暴露多層堆疊58的額外部分。在一些實施例中，藉由使用可接受的移除技術（諸如橫向蝕刻）來修整光阻56。由於修整，光阻56的寬度減小，且可暴露區60及區62中部分的多層堆疊58。舉例而言，介電層52D的頂面可暴露於區60中，且介電層52E的頂面可暴露於區62中。In FIG. 6 , photoresist 56 is trimmed to expose additional portions of multilayer stack 58 . In some embodiments, photoresist 56 is trimmed by using acceptable removal techniques, such as lateral etching. Due to trimming, the width of photoresist 56 is reduced and portions of multilayer stack 58 in regions 60 and 62 may be exposed. For example, the top surface of dielectric layer 52D may be exposed in region 60 and the top surface of dielectric layer 52E may be exposed in region 62 .

在圖7中，藉由使用光阻56做為罩幕的可接受的蝕刻製程移除區60及區62中的介電層52E、犧牲層53D、介電層52D以及犧牲層53C的部分。蝕刻可為任何可接受的蝕刻製程，諸如乾式蝕刻（例如，RIE、NBE、類似蝕刻）、濕式蝕刻、類似蝕刻或其組合。蝕刻可為非等向性的。蝕刻可使開口61進一步延伸至多層堆疊58中。由於犧牲層53D及犧牲層53C以及介電層52E及介電層52D具有不同材料組成物，故用於移除這些層的暴露部分的蝕刻劑可不同。在一些實施例中，藉由使用光阻56做為罩幕且使用下伏犧牲層53D及犧牲層53C做為蝕刻終止層來移除區62及區60中的介電層52E及介電層52D的部分。之後，藉由使用光阻56做為罩幕且使用下伏介電層52D及介電層52C做為蝕刻終止層來移除區62及區60中的犧牲層53D及犧牲層53C的暴露部分。在所得結構中，介電層52C暴露於區60中，且介電層52D暴露於區62中。In FIG. 7, portions of dielectric layer 52E, sacrificial layer 53D, dielectric layer 52D, and sacrificial layer 53C in regions 60 and 62 are removed by an acceptable etch process using photoresist 56 as a mask. The etching can be any acceptable etching process, such as dry etching (eg, RIE, NBE, similar etching), wet etching, similar etching, or combinations thereof. Etching can be anisotropic. Etching may extend opening 61 further into multilayer stack 58 . Since sacrificial layer 53D and sacrificial layer 53C and dielectric layer 52E and dielectric layer 52D have different material compositions, the etchants used to remove exposed portions of these layers may be different. In some embodiments, dielectric layer 52E and dielectric layers in regions 62 and 60 are removed by using photoresist 56 as a mask and using underlying sacrificial layer 53D and sacrificial layer 53C as etch stop layers 52D part. Afterwards, the exposed portions of sacrificial layer 53D and sacrificial layer 53C in region 62 and region 60 are removed by using photoresist 56 as a mask and using underlying dielectric layer 52D and dielectric layer 52C as etch stop layers . In the resulting structure, dielectric layer 52C is exposed in region 60 and dielectric layer 52D is exposed in region 62 .

在圖8中，修整光阻56以暴露多層堆疊58的額外部分。在一些實施例中，藉由使用可接受的移除技術（諸如橫向蝕刻）來修整光阻56。由於修整，光阻56的寬度減小，且可暴露區60、區62以及區64中的多層堆疊58的部分。舉例而言，介電層52C的頂面可暴露於區60中；介電層52D的頂面可暴露於區62中；且介電層52E的頂面可暴露於區64中。In FIG. 8 , photoresist 56 is trimmed to expose additional portions of multilayer stack 58 . In some embodiments, photoresist 56 is trimmed by using acceptable removal techniques, such as lateral etching. Due to trimming, the width of photoresist 56 is reduced and portions of multilayer stack 58 in regions 60, 62, and 64 may be exposed. For example, the top surface of dielectric layer 52C may be exposed in region 60 ; the top surface of dielectric layer 52D may be exposed in region 62 ; and the top surface of dielectric layer 52E may be exposed in region 64 .

在圖9中，藉由使用光阻56做為罩幕的可接受的蝕刻製程移除區60、區62以及區64中的介電層52E、介電層52D以及介電層52C及犧牲層53D、犧牲層53C以及犧牲層53B的部分。蝕刻可為任何可接受的蝕刻製程，諸如乾式蝕刻（例如，RIE、NBE、類似蝕刻）、濕式蝕刻、類似蝕刻或其組合。蝕刻可為非等向性的。蝕刻可使開口61進一步延伸至多層堆疊58中。由於介電層52C至介電層52E及犧牲層53B至犧牲層53D具有不同材料組成物，故用於移除這些層的暴露部分的蝕刻劑可不同。在一些實施例中，藉由使用光阻56做為罩幕且使用下伏犧牲層53D、犧牲層53C以及犧牲層53B做為蝕刻終止層來移除區64、區62以及區60中的介電層52E、介電層52D以及介電層52C的部分。之後，藉由使用光阻56做為罩幕且使用下伏介電層52D、介電層52C及介電層52B做為蝕刻終止層來移除區64、區62以及區60中的犧牲層53D、犧牲層53C以及犧牲層53B的暴露部分。在所得結構中，介電層52B暴露於區60中；介電層52C暴露於區62中；且介電層52D暴露於區64中。9, dielectric layer 52E, dielectric layer 52D and dielectric layer 52C and sacrificial layers in region 60, region 62, and region 64 are removed by an acceptable etch process using photoresist 56 as a mask 53D, sacrificial layer 53C, and part of sacrificial layer 53B. The etching can be any acceptable etching process, such as dry etching (eg, RIE, NBE, similar etching), wet etching, similar etching, or combinations thereof. Etching can be anisotropic. Etching may extend opening 61 further into multilayer stack 58 . Since dielectric layers 52C to 52E and sacrificial layers 53B to 53D have different material compositions, the etchants used to remove exposed portions of these layers may be different. In some embodiments, the dielectrics in regions 64, 62, and 60 are removed by using photoresist 56 as a mask and using underlying sacrificial layer 53D, sacrificial layer 53C, and sacrificial layer 53B as etch stop layers Electrical layer 52E, dielectric layer 52D, and portions of dielectric layer 52C. Afterwards, the sacrificial layers in region 64, region 62, and region 60 are removed by using photoresist 56 as a mask and using underlying dielectric layer 52D, dielectric layer 52C, and dielectric layer 52B as etch stop layers 53D, the sacrificial layer 53C, and the exposed portion of the sacrificial layer 53B. In the resulting structure, dielectric layer 52B is exposed in region 60 ; dielectric layer 52C is exposed in region 62 ; and dielectric layer 52D is exposed in region 64 .

在圖10中，修整光阻56以暴露多層堆疊58的額外部分。在一些實施例中，藉由使用可接受的移除技術（諸如橫向蝕刻）來修整光阻56。由於修整，光阻56的寬度減小，且可暴露區60、區62、區64以及區66中的多層堆疊58的部分。舉例而言，介電層52B的頂面可暴露於區60中；介電層52C的頂面可暴露於區62中；且介電層52D的頂面可暴露於區64中；且介電層52E的頂面可暴露於區66中。In FIG. 10 , photoresist 56 is trimmed to expose additional portions of multilayer stack 58 . In some embodiments, photoresist 56 is trimmed by using acceptable removal techniques, such as lateral etching. Due to trimming, the width of photoresist 56 is reduced and portions of multi-layer stack 58 in region 60 , region 62 , region 64 , and region 66 may be exposed. For example, the top surface of dielectric layer 52B may be exposed in region 60; the top surface of dielectric layer 52C may be exposed in region 62; and the top surface of dielectric layer 52D may be exposed in region 64; and the dielectric The top surface of layer 52E may be exposed in region 66 .

在圖11中，藉由使用光阻56做為罩幕的可接受的蝕刻製程移除區60、區62、區64以及區66中的介電層52E、介電層52D、介電層52C以及介電層52B的部分。蝕刻可為任何可接受的蝕刻製程，諸如乾式蝕刻（例如，RIE、NBE、類似蝕刻）、濕式蝕刻、類似蝕刻或其組合。蝕刻可為非等向性的。蝕刻可使開口61進一步延伸至多層堆疊58中。在一些實施例中，藉由使用光阻56做為罩幕且使用下伏犧牲層53D、犧牲層53C、犧牲層53B以及犧牲層53A做為蝕刻停止層來移除區66、區64、區62以及區60中的介電層52E、介電層52D、介電層52C以及介電層52B的部分。在所得結構中，犧牲層53A暴露於區60中；犧牲層53B暴露於區62中；犧牲層53C暴露於區64中；且犧牲層53D暴露於區66中。之後，光阻56可藉由可接受的灰化或濕式剝離製程移除。In FIG. 11, regions 60, 62, 64, and dielectric layers 52E, 52D, 52C in region 66 are removed by an acceptable etch process using photoresist 56 as a mask and part of the dielectric layer 52B. The etching can be any acceptable etching process, such as dry etching (eg, RIE, NBE, similar etching), wet etching, similar etching, or combinations thereof. Etching can be anisotropic. Etching may extend opening 61 further into multilayer stack 58 . In some embodiments, regions 66 , 64 , regions are removed by using photoresist 56 as a mask and using underlying sacrificial layer 53D, sacrificial layer 53C, sacrificial layer 53B, and sacrificial layer 53A as etch stop layers 62 and portions of dielectric layer 52E, dielectric layer 52D, dielectric layer 52C, and dielectric layer 52B in region 60 . In the resulting structure, sacrificial layer 53A is exposed in region 60; sacrificial layer 53B is exposed in region 62; sacrificial layer 53C is exposed in region 64; and sacrificial layer 53D is exposed in region 66. Afterwards, photoresist 56 may be removed by acceptable ashing or wet strip processes.

在圖12中，金屬間介電質（inter-metal dielectric；IMD）70在多層堆疊58上方形成。IMD 70可由介電材料形成，且可藉由任何適合方法沈積，所述方法諸如CVD、PECVD、可流動CVD（flowable CVD；FCVD）或類似者。介電材料可包括磷矽酸鹽玻璃（phospho-silicate glass；PSG）、硼矽酸鹽玻璃（boro-silicate glass；BSG）、硼摻雜磷矽酸鹽玻璃（boron-doped phospho-silicate glass；BPSG）、未摻雜的矽酸鹽玻璃（undoped silicate glass；USG）或類似物。在一些實施例中，IMD 70可包括氧化物（例如，氧化矽或類似物）、氮化物（例如，氮化矽或類似物）、其組合或類似物。可使用由任何可接受的製程形成的其他介電材料。之後，執行移除製程以移除多層堆疊58上方的多餘介電材料。在一些實施例中，移除製程可為平坦化製程，諸如化學機械研磨（chemical mechanical polish；CMP）、回蝕製程、其組合或類似者。平坦化製程暴露多層堆疊58，使得在平坦化製程完成之後，多層堆疊58及IMD 70的頂面齊平。IMD 70沿著犧牲層53B至犧牲層53D的側壁及介電層52B至介電層52E的側壁延伸。另外，IMD 70可接觸犧牲層53A至犧牲層53D及介電層52E的頂面。In FIG. 12 , an inter-metal dielectric (IMD) 70 is formed over the multilayer stack 58 . IMD 70 may be formed from a dielectric material and may be deposited by any suitable method, such as CVD, PECVD, flowable CVD (FCVD), or the like. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass; BPSG), undoped silicate glass (USG), or the like. In some embodiments, IMD 70 may include oxides (eg, silicon oxide or the like), nitrides (eg, silicon nitride or the like), combinations thereof, or the like. Other dielectric materials formed by any acceptable process can be used. Afterwards, a removal process is performed to remove excess dielectric material over the multilayer stack 58 . In some embodiments, the removal process may be a planarization process, such as a chemical mechanical polish (CMP), an etch-back process, a combination thereof, or the like. The planarization process exposes the multi-layer stack 58 such that the top surfaces of the multi-layer stack 58 and IMD 70 are flush after the planarization process is complete. IMD 70 extends along the sidewalls of sacrificial layer 53B to sacrificial layer 53D and the sidewalls of dielectric layer 52B to dielectric layer 52E. Additionally, IMD 70 may contact sacrificial layer 53A to the top surfaces of sacrificial layer 53D and dielectric layer 52E.

如圖12中所繪示，由此形成中間及塊狀階梯結構。中間階梯結構包括犧牲層53及介電層52的交替層。隨後，用導線72取代犧牲層53，此將在圖16A及圖16B中詳細描述。下部導線72較長且橫向延伸超過上部導線72，且導線72中的每一者的寬度在朝著基底50的方向上增大（參看圖1A及圖30E）。As shown in FIG. 12, intermediate and block-like stepped structures are thereby formed. The intermediate stepped structure includes alternating layers of sacrificial layers 53 and dielectric layers 52 . Subsequently, the sacrificial layer 53 is replaced with wires 72, which will be described in detail in FIGS. 16A and 16B. The lower conductors 72 are longer and extend laterally beyond the upper conductors 72, and the width of each of the conductors 72 increases in the direction toward the substrate 50 (see Figures 1A and 30E).

圖13至圖16B為根據一些實施例的製造記憶陣列200的記憶體區中的中間階段的視圖。在圖13至圖16B中，圖案化塊狀多層堆疊58以形成穿過其中的溝渠86，且用導電材料取代犧牲層53以界定導線72。導線72可對應於記憶陣列200中的字元線，且導線72可為記憶陣列200的所得記憶胞進一步提供閘電極。沿著圖1A中所示出的參考橫截面C-C'示出圖13、圖14、圖15B以及圖16B。以部分三維圖示出圖15A及圖16A，其分別為藉由圖15B及圖16B中的虛線30所圍的部分的透視圖。13-16B are views of intermediate stages in the fabrication of a memory region of memory array 200 in accordance with some embodiments. In FIGS. 13-16B , the bulk multilayer stack 58 is patterned to form trenches 86 therethrough, and the sacrificial layer 53 is replaced with a conductive material to define the wires 72 . Conductors 72 may correspond to word lines in memory array 200 , and conductors 72 may further provide gate electrodes for the resulting memory cells of memory array 200 . 13, 14, 15B, and 16B are shown along the reference cross-section CC' shown in FIG. 1A. Figures 15A and 16A are shown in partial three-dimensional views, which are perspective views of the portion enclosed by the dashed line 30 in Figures 15B and 16B, respectively.

在圖13中，在多層堆疊58上方形成光阻圖案82及下伏硬罩幕圖案80。在一些實施例中，在多層堆疊58上方依序形成硬罩幕層及光阻層。硬罩幕層可包括例如可由CVD、PVD、ALD、PECVD或類似者沈積的氮化矽、氮氧化矽或類似物。舉例而言，光阻層藉由旋塗技術形成。In FIG. 13 , a photoresist pattern 82 and an underlying hard mask pattern 80 are formed over the multilayer stack 58 . In some embodiments, a hard mask layer and a photoresist layer are sequentially formed over the multilayer stack 58 . The hard mask layer may include, for example, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. For example, the photoresist layer is formed by spin coating.

之後，圖案化光阻層以形成光阻圖案82及光阻圖案82之間的溝渠86。舉例而言，藉由可接受的微影技術圖案化光阻。接著，藉由使用可接受的蝕刻製程（諸如藉由乾式蝕刻（例如，RIE、NBE、類似蝕刻）、濕式蝕刻、類似蝕刻或其組合）將光阻圖案82的圖案轉移至硬罩幕層以形成硬罩幕圖案80。蝕刻可為非等向性的。因此，形成延伸穿過硬罩幕層的溝渠86。之後，例如，可視情況藉由灰化製程移除光阻圖案82。After that, the photoresist layer is patterned to form the photoresist patterns 82 and the trenches 86 between the photoresist patterns 82 . For example, the photoresist is patterned by acceptable lithography techniques. Next, the pattern of photoresist pattern 82 is transferred to the hard mask layer by using an acceptable etching process, such as by dry etching (eg, RIE, NBE, similar etching), wet etching, similar etching, or a combination thereof to form a hard mask pattern 80 . Etching can be anisotropic. Thus, trenches 86 are formed that extend through the hard mask layer. After that, for example, the photoresist pattern 82 may be removed by an ashing process as appropriate.

在圖14、圖15A以及圖15B中，使用一或多個可接受的蝕刻製程（諸如藉由乾式蝕刻（例如，RIE、NBE、類似蝕刻）、濕式蝕刻、類似蝕刻或其組合）將硬罩幕圖案80的圖案轉移至多層堆疊58。蝕刻製程可為非等向性的。因此，溝渠86延伸穿過塊狀多層堆疊58，且相應地界定條形犧牲層53及條形介電層52。在一些實施例中，溝渠86延伸穿過塊狀階梯結構，且相應地界定條形階梯結構。接著，可藉由諸如濕式蝕刻製程、乾式蝕刻製程、平坦化製程、其組合或類似者的可接受的製程移除硬罩幕圖案80。In Figures 14, 15A, and 15B, the hard etch is etched using one or more acceptable etch processes, such as by dry etch (eg, RIE, NBE, similar etch), wet etch, similar etch, or a combination thereof. The pattern of mask pattern 80 is transferred to multilayer stack 58 . The etching process can be anisotropic. Thus, trenches 86 extend through bulk multilayer stack 58 and define strip sacrificial layers 53 and strip dielectric layers 52 accordingly. In some embodiments, the trenches 86 extend through the block-like stepped structures and correspondingly define the strip-like stepped structures. Next, the hard mask pattern 80 may be removed by an acceptable process such as a wet etch process, a dry etch process, a planarization process, a combination thereof, or the like.

在圖15A、圖15B、圖16A以及圖16B中，以導線72A至導線72D（統稱為導線72）取代部分的犧牲層53A至犧牲層53D（統稱為犧牲層53）。在一些實施例中，藉由諸如濕式蝕刻製程、乾式刻蝕製程或其兩者的可接受的製程移除部分的犧牲層53。在一些實施例中，圍繞在具有記憶陣列的陣列區的周邊區，其具有並未藉由所述取代製程移除的部分的犧牲層53。因此，犧牲層53的在部分的周邊區中亦可提供額外的支撐以防止陣列區中的介電層52塌陷。In FIGS. 15A , 15B, 16A, and 16B, portions of sacrificial layers 53A to 53D (collectively referred to as sacrificial layers 53 ) are replaced with wires 72A to 72D (collectively referred to as wires 72 ). In some embodiments, portions of the sacrificial layer 53 are removed by an acceptable process, such as a wet etch process, a dry etch process, or both. In some embodiments, the sacrificial layer 53 surrounds the perimeter region of the array region with the memory array, which has portions that are not removed by the replacement process. Therefore, the sacrificial layer 53 may also provide additional support in a portion of the peripheral region to prevent the collapse of the dielectric layer 52 in the array region.

之後，導線72填充至兩個相鄰介電層52之間的空間中。如局部放大圖中所繪示，每一導線72包括兩個阻障層71及阻障層75以及在阻障層71與阻障層75之間的金屬層73。特定言之，阻障層71或阻障層75安置在金屬層73與相鄰介電層52之間。阻障層71及阻障層75可防止金屬層擴散至相鄰介電層52。阻障層71及阻障層75亦可提供增大金屬層73與相鄰介電層52之間的黏著力的功能，且在一些實例中可稱為膠黏層。在一些實施例中，提供具有不同材料的阻障層及膠黏層兩者。阻障層71及阻障層75由第一導電材料形成，所述第一導電材料諸如金屬氮化物，諸如氮化鈦、氮化鉭、氮化鉬、氮化鋯、氮化鉿或類似物。金屬層73可由第二導電材料形成，所述第二導電材料諸如金屬，諸如鎢、釕、鉬、鈷、鋁、鎳、銅、銀、金、其合金或類似物。阻障層71、阻障層75以及金屬層73可各自藉由諸如CVD、PVD、ALD、PECVD或類似者的可接受的沈積製程形成。阻障層71及阻障層75的第一導電材料及金屬層73的第二導電材料進一步沈積在多層堆疊58的側壁上且填充在溝渠86中。之後，藉由回蝕製程移除溝渠86中的阻障層71及阻障層75的第一導電材料及金屬層73的第二導電材料。可執行可接受的回蝕製程以自介電層52的側壁及溝渠86的底部表面移除多餘材料。可接受的回蝕製程包括乾式蝕刻（例如，RIE、NBE、類似蝕刻）、濕式蝕刻、類似蝕刻或其組合。可接受的回蝕製程可為非等向性的。After that, the wires 72 are filled into the spaces between the two adjacent dielectric layers 52 . As shown in the partially enlarged view, each wire 72 includes two barrier layers 71 and 75 and a metal layer 73 between the barrier layers 71 and the barrier layers 75 . In particular, barrier layer 71 or barrier layer 75 is disposed between metal layer 73 and adjacent dielectric layer 52 . Barrier layer 71 and barrier layer 75 prevent the metal layer from diffusing to adjacent dielectric layers 52 . Barrier layer 71 and barrier layer 75 may also provide the function of increasing the adhesion between metal layer 73 and adjacent dielectric layers 52, and may be referred to as adhesive layers in some instances. In some embodiments, both the barrier layer and the adhesive layer are provided with different materials. Barrier layer 71 and barrier layer 75 are formed of a first conductive material, such as a metal nitride, such as titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, or the like . The metal layer 73 may be formed of a second conductive material such as a metal such as tungsten, ruthenium, molybdenum, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, or the like. Barrier layer 71, barrier layer 75, and metal layer 73 may each be formed by an acceptable deposition process such as CVD, PVD, ALD, PECVD, or the like. The first conductive material of barrier layer 71 and barrier layer 75 and the second conductive material of metal layer 73 are further deposited on the sidewalls of multilayer stack 58 and filled in trenches 86 . After that, the barrier layer 71 and the first conductive material of the barrier layer 75 and the second conductive material of the metal layer 73 in the trench 86 are removed by an etch-back process. An acceptable etch-back process may be performed to remove excess material from the sidewalls of dielectric layer 52 and the bottom surface of trench 86 . Acceptable etch-back processes include dry etch (eg, RIE, NBE, similar etch), wet etch, similar etch, or combinations thereof. An acceptable etch-back process may be anisotropic.

在一些實施例中，在取代製程後，隨後用導線72（參看圖1A）取代條形階梯結構的犧牲層53。In some embodiments, after the replacement process, the sacrificial layer 53 of the strip-shaped ladder structure is subsequently replaced with wires 72 (see FIG. 1A ).

在替代實施例中，在導電柱106及導電柱108（圖29A及圖29B中所繪示）形成之後，用導線72取代犧牲層53的部分。除了導電柱106及導電柱108、介電材料98、通道層92以及隔離柱102以外，周邊區中的部分的犧牲層53亦提供額外支撐以防止陣列區中的介電層52塌陷。In an alternate embodiment, after the formation of conductive pillars 106 and 108 (shown in FIGS. 29A and 29B ), portions of sacrificial layer 53 are replaced with wires 72 . In addition to conductive pillars 106 and 108, dielectric material 98, channel layer 92, and isolation pillars 102, portions of sacrificial layer 53 in the peripheral region provide additional support to prevent collapse of dielectric layer 52 in the array region.

圖17A至圖21示出在溝渠86中形成鐵電層90'及通道層92。以部分三維圖示出圖17A、圖18A、圖19A以及圖20A，其分別為藉由圖17B、圖18B、圖19B以及圖20B中的虛線30所圍的部分的透視圖。在圖17B、圖18B、圖19B以及圖20B中，提供沿著圖1A的線C-C'的橫截面圖。17A-21 illustrate the formation of the ferroelectric layer 90' and the channel layer 92 in the trench 86. As shown in FIG. Figures 17A, 18A, 19A, and 20A are shown in partial three-dimensional views, which are perspective views of the portion enclosed by dashed line 30 in Figures 17B, 18B, 19B, and 20B, respectively. In FIGS. 17B, 18B, 19B, and 20B, cross-sectional views along line CC' of FIG. 1A are provided.

圖18C及圖18D示出圖18B的區R1的局部放大圖。圖20C示出圖20B的區R1的局部放大圖。圖20D示出物質（例如，額外物質）濃度及氧濃度與通道層92、鐵電層90'以及導線72的深度的圖表。圖21示出根據一些實施例的形成記憶陣列200的鐵電層90'及通道層92的方法。18C and 18D are partial enlarged views of the region R1 of FIG. 18B . FIG. 20C shows a partial enlarged view of the region R1 of FIG. 20B . FIG. 20D shows a graph of species (eg, additional species) concentration and oxygen concentration versus depth of channel layer 92 , ferroelectric layer 90 ′, and wire 72 . 21 illustrates a method of forming the ferroelectric layer 90' and the channel layer 92 of the memory array 200 in accordance with some embodiments.

在圖17A、圖17B中且在圖21的動作S100處，鐵電層90可沿著導線72的側壁及介電層52E的頂面且沿著溝渠86的底部表面共形地沈積在溝渠86中。在一些實施例中，鐵電層90可進一步沈積在IMD 70上且沿著階梯區中的階梯結構中的每一階的側壁沈積。鐵電層90可包括能夠藉由在鐵電層90上施加適當電壓差而在兩個不同極化方向之間切換的材料。舉例而言，鐵電層90包括高k介電材料，諸如鉿（Hf）類介電材料或類似材料。在一些實施例中，鐵電層90包括氧化鉿、氧化鋯鉿、矽摻雜氧化鉿或類似物。In FIGS. 17A , 17B and at act S100 of FIG. 21 , ferroelectric layer 90 may be conformally deposited on trench 86 along the sidewalls of wire 72 and the top surface of dielectric layer 52E and along the bottom surface of trench 86 middle. In some embodiments, a ferroelectric layer 90 may be further deposited on the IMD 70 and along the sidewalls of each of the stepped structures in the stepped region. The ferroelectric layer 90 may comprise a material that can be switched between two different polarization directions by applying an appropriate voltage difference across the ferroelectric layer 90 . For example, the ferroelectric layer 90 includes a high-k dielectric material, such as a hafnium (Hf)-based dielectric material or the like. In some embodiments, the ferroelectric layer 90 includes hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like.

在一些實施例中，鐵電層90可包括氧化鈦鋇（BaTiO3 ）、氧化鈦鉛（PbTiO3 ）、氧化鋯鉛（PbZrO3 ）、氧化鈮鋰（LiNbO3 ）、氧化鈮鈉（NaNbO3 ）、氧化鈮鉀（KNbO3 ）、氧化鉭鉀（KTaO3 ）、氧化鈧鉍（BiScO3 ）、氧化鐵鉍（BiFeO3 ）、氧化鉺鉿（Hf1-x Erx O）、氧化鑭鉿（Hf1-x Lax O）、氧化釔鉿（Hf1-x Yx O）、氧化釓鉿（Hf1-x Gdx O）、氧化鋁鉿（Hf1-x Alx O）、氧化鋯鉿（Hf1-x Zrx O, HZO）、氧化鈦鉿（Hf1-x Tix O）、氧化鉭鉿（Hf1-x Tax O）或其組合，或類似物。在一些實施例中，鐵電層90可包括不同鐵電材料或不同類型的記憶體材料。在一些實施例中，形成鐵電層90的方法包括執行適合的沈積技術，諸如CVD、PECVD、金屬氧化物化學氣相沈積（metal oxide chemical vapor deposition；MOCVD）、ALD、RPALD、PEALD、MBD或類似者。In some embodiments, the ferroelectric layer 90 may include barium titanium oxide (BaTiO 3), lead oxide (PbTiO 3), lead zirconium oxide (PbZrO 3), lithium niobium oxide (LiNbO 3), sodium niobium oxide (NaNbO 3 ), potassium niobium oxide (KNbO 3), potassium tantalum oxide (KTaO 3), scandium oxide, bismuth (BiScO 3), iron oxide, bismuth (BiFeO 3), erbium oxide, hafnium (Hf 1-x Er x O ), hafnium lanthanum oxide (Hf 1-x La x O), yttrium hafnium oxide (Hf 1-x Y x O), hafnium oxide (Hf 1-x Gd x O), hafnium alumina (Hf 1-x Al x O), oxide zirconium hafnium (Hf 1-x Zr x O , HZO), titanium oxide, hafnium (Hf 1-x Ti x O ), tantalum oxide, hafnium (Hf 1-x Ta x O ) , or combinations thereof, or the like. In some embodiments, the ferroelectric layer 90 may include different ferroelectric materials or different types of memory materials. In some embodiments, the method of forming ferroelectric layer 90 includes performing a suitable deposition technique, such as CVD, PECVD, metal oxide chemical vapor deposition (MOCVD), ALD, RPALD, PEALD, MBD or similar.

在一些實施例中，鐵電層90具有約1奈米至20奈米的厚度，諸如5奈米至10奈米。其他厚度範圍（例如，大於20奈米或5奈米至15奈米）亦可適用。在一些實施例中，鐵電層90以完全非晶態形成。在替代實施例中，鐵電層90以部分結晶態形成；亦即，鐵電層90以混合的結晶-非晶態形成且具有一定程度的結構次序。在另外替代實施例中，鐵電層90以完全結晶態形成。在一些實施例中，鐵電層90為單層。在替代實施例中，鐵電層90為多層結構。In some embodiments, the ferroelectric layer 90 has a thickness of about 1 to 20 nanometers, such as 5 to 10 nanometers. Other thickness ranges (eg, greater than 20 nm or 5 nm to 15 nm) are also suitable. In some embodiments, the ferroelectric layer 90 is formed in a completely amorphous state. In an alternative embodiment, the ferroelectric layer 90 is formed in a partially crystalline state; that is, the ferroelectric layer 90 is formed in a mixed crystalline-amorphous state with some degree of structural order. In further alternative embodiments, the ferroelectric layer 90 is formed in a fully crystalline state. In some embodiments, the ferroelectric layer 90 is a single layer. In an alternative embodiment, the ferroelectric layer 90 is a multilayer structure.

在圖21的動作S102處，對鐵電層90執行第一回火製程。回火製程的溫度範圍在N2 、O2 或N2 /O2 環境中介於約250℃至約550℃範圍內，以便實現鐵電層90所要的晶格結構。在一些實施例中，在回火製程後，鐵電層90自非晶態轉變至部分結晶態或完全結晶態。在替代實施例中，在回火後，鐵電層90自部分結晶態轉變至完全結晶態。At act S102 of FIG. 21 , a first tempering process is performed on the ferroelectric layer 90 . The temperature range of the tempering process is in the range of about 250° C. to about 550° C. in an N 2 , O 2 or N 2 /O 2 environment in order to achieve the desired lattice structure of the ferroelectric layer 90 . In some embodiments, after the tempering process, the ferroelectric layer 90 transitions from an amorphous state to a partially crystalline state or a fully crystalline state. In an alternative embodiment, after tempering, the ferroelectric layer 90 transitions from a partially crystalline state to a fully crystalline state.

在圖20A至圖20D中且在圖21的動作S104處，對鐵電層90執行處理88以形成鐵電層90'。在一些實施例中，對鐵電層90執行處理88以將鐵電層90的至少一部分轉變為經處理的鐵電部分90A。經處理的鐵電部分90A用於增強元件的耐久效能。在一些實施例中，經處理的鐵電部分90A為如圖18C中所繪示的鐵電層90'的一部分。在另一實施例中，經處理的鐵電部分90A為如圖18D中所繪示的整個鐵電層90'。In FIGS. 20A-20D and at act S104 of FIG. 21 , process 88 is performed on the ferroelectric layer 90 to form the ferroelectric layer 90 ′. In some embodiments, processing 88 is performed on ferroelectric layer 90 to convert at least a portion of ferroelectric layer 90 into processed ferroelectric portion 90A. The treated ferroelectric portion 90A is used to enhance the durability performance of the element. In some embodiments, processed ferroelectric portion 90A is a portion of ferroelectric layer 90' as depicted in Figure 18C. In another embodiment, the processed ferroelectric portion 90A is the entire ferroelectric layer 90' as depicted in Figure 18D.

在一些實施例中，處理88藉由能量源將物質（例如，額外物質）引入於鐵電層90中。處理88的能量源可藉由包括熱擴散、電子束、紫外線（ultraviolet；UV）或其組合的離子植入製程、電漿製程或其他適合製程提供。處理88可為氮化處理製程，或鹵化處理製程。在一些實施例中，處理88引入價數為5（例如氮（N））、價數為7（例如氟（F））或其組合的物質（例如，額外物質），以消除或阻止稍後形成的鐵電層90'與通道層92之間的界面IF2中的陷阱或缺陷，且/或佔據稍後形成的鐵電層90'及/或通道層92中的氧空缺並充當鈍化物以抑制氧、氫以及空缺的相互擴散，以提升鐵電層90'的固有疲勞效能及耐久性。在一些實施例中，鐵電層90'可稱為含有物質（諸如氮或鹵素）的鐵電層。在替代實施例中，鐵電層90'亦可稱為摻雜鈍化物質（諸如氮或鹵素）的鐵電層。In some embodiments, process 88 introduces species (eg, additional species) into ferroelectric layer 90 via an energy source. The energy source for processing 88 may be provided by an ion implantation process, plasma process, or other suitable process including thermal diffusion, electron beam, ultraviolet (ultraviolet; UV), or a combination thereof. Treatment 88 may be a nitridation treatment process, or a halogenation treatment process. In some embodiments, treatment 88 introduces species (eg, additional species) with a valence of 5 (eg, nitrogen (N)), a valence of 7 (eg, fluorine (F)), or a combination thereof, to eliminate or prevent later Traps or defects in the interface IF2 between the formed ferroelectric layer 90' and the channel layer 92 and/or occupy oxygen vacancies in the later formed ferroelectric layer 90' and/or the channel layer 92 and act as a passivation to The interdiffusion of oxygen, hydrogen and vacancies is suppressed to improve the inherent fatigue performance and durability of the ferroelectric layer 90'. In some embodiments, the ferroelectric layer 90' may be referred to as a ferroelectric layer containing species such as nitrogen or halogen. In alternative embodiments, the ferroelectric layer 90' may also be referred to as a ferroelectric layer doped with passivation species such as nitrogen or halogen.

因此，經處理的鐵電部分90A為具有價數為5、7或其組合的物質的鐵電層90'的部分。在一些實施例中，離子植入製程或電漿製程在相對較低能量下執行，以防止損壞鐵電層90且增強中和效率。舉例而言，離子植入製程在約10千電子伏特至50千電子伏特的能量下以約1原子/平方公分至約1000原子/平方公分的劑量執行。舉例而言，電漿製程在電漿腔室中以約1000 sccm至約10000 sccm的氣體（例如，N2 、NH3 、CF4 或CFH3 ）流動速率、約15瓦特至約500瓦特的功率以及約1托至約760托的壓力在小於約400℃的溫度下執行約1秒至約360秒的時段。Thus, the treated ferroelectric portion 90A is the portion of the ferroelectric layer 90' having a species with a valence of 5, 7, or a combination thereof. In some embodiments, the ion implantation process or plasma process is performed at relatively low energy to prevent damage to the ferroelectric layer 90 and to enhance neutralization efficiency. For example, the ion implantation process is performed at an energy of about 10 keV to 50 keV at a dose of about 1 atom/cm2 to about 1000 atoms/cm2. For example, a plasma process in the plasma chamber to about 1000 sccm to about 10000 sccm of gas (e.g., N 2, NH 3, CF 4 , or CFH 3) flow rate of from about 15 watts to about 500 watts And a pressure of about 1 Torr to about 760 Torr is performed at a temperature of less than about 400° C. for a period of about 1 second to about 360 seconds.

如圖18C中所示出，鐵電層90'的物質濃度可介於約1E17/cm3 至約1E20/cm3 範圍內。在一些實施例中，鐵電層90'具有不同濃度的物質（例如，氟、氮或類似物），且物質的濃度可在朝著導線72的方向上降低。舉例而言，鐵電層90'可具有三部分結構，其包括底部鐵電部分90B、中間鐵電部分90M以及頂部鐵電部分90T。底部鐵電部分90B與導線72接觸，且中間鐵電部分90M位於底部鐵電部分90B與頂部鐵電部分90T之間。中間鐵電部分90M及頂部鐵電部分90T統稱為經處理的鐵電部分90A。As shown in FIG. 18C, the species concentration of the ferroelectric layer 90' may range from about 1E17/cm 3 to about 1E20/cm 3 . In some embodiments, ferroelectric layer 90 ′ has different concentrations of species (eg, fluorine, nitrogen, or the like), and the concentration of species may decrease in the direction toward wire 72 . For example, the ferroelectric layer 90' may have a three-part structure including a bottom ferroelectric portion 90B, a middle ferroelectric portion 90M, and a top ferroelectric portion 90T. Bottom ferroelectric portion 90B is in contact with wire 72, and middle ferroelectric portion 90M is located between bottom ferroelectric portion 90B and top ferroelectric portion 90T. The middle ferroelectric portion 90M and the top ferroelectric portion 90T are collectively referred to as the treated ferroelectric portion 90A.

在一些實施例中，頂部鐵電部分90T具有鐵電層90'的最大物質濃度。鐵電層90'的最大物質濃度在頂部鐵電部分90T的中心處。在一個實施例中，頂部鐵電部分90T的物質濃度可介於鐵電層90'的最大物質濃度的約50%至約100%範圍內；中間鐵電部分90M的物質濃度可介於鐵電層90'的最大物質濃度的約1%至約40%範圍內；而底部鐵電部分90B的物質濃度可小於鐵電層90'的最大物質濃度的1%。在一些實施例中，鐵電層90'的最大物質濃度可介於約1E17/cm3 至約1E20/cm3 範圍內。In some embodiments, the top ferroelectric portion 90T has the maximum species concentration of the ferroelectric layer 90'. The maximum species concentration of the ferroelectric layer 90' is at the center of the top ferroelectric portion 90T. In one embodiment, the species concentration of the top ferroelectric portion 90T may range from about 50% to about 100% of the maximum species concentration of the ferroelectric layer 90'; the species concentration of the middle ferroelectric portion 90M may be between ferroelectric The species concentration of the bottom ferroelectric portion 90B may be less than 1% of the maximum species concentration of the ferroelectric layer 90'. In some embodiments, the maximum species concentration of the ferroelectric layer 90' may range from about 1E17/cm 3 to about 1E20/cm 3 .

在一些實施例中，頂部鐵電部分90T具有厚度T3；中間鐵電部分90M具有厚度T2；且底部鐵電部分90B具有厚度T1。在一些實施例中，厚度T1、厚度T2以及厚度T3可介於大約5埃與大約10奈米之間、大約1奈米與大約50奈米之間或其他類似值的範圍內。此外，厚度T1與組合厚度（例如，厚度T3加上厚度T2）的厚度比介於約1:2至1:10範圍內。In some embodiments, top ferroelectric portion 90T has thickness T3; middle ferroelectric portion 90M has thickness T2; and bottom ferroelectric portion 90B has thickness T1. In some embodiments, thickness T1, thickness T2, and thickness T3 may range between about 5 angstroms and about 10 nanometers, between about 1 nanometer and about 50 nanometers, or other similar values. Furthermore, the thickness ratio of thickness T1 to the combined thickness (eg, thickness T3 plus thickness T2 ) is in the range of about 1:2 to 1:10.

如圖18D中所示出，在替代實施例中，經處理的鐵電部分90A佔據整個鐵電層90'。整個鐵電層90'包括物質（例如，氟、氮或類似物）。在一些實施例中，鐵電層90'具有均勻分佈濃度的物質。鐵電層90'的物質濃度可介於約1E17/cm3 至約1E20/cm3 範圍內。As shown in Figure 18D, in an alternative embodiment, the treated ferroelectric portion 90A occupies the entire ferroelectric layer 90'. The entire ferroelectric layer 90' includes a substance (eg, fluorine, nitrogen, or the like). In some embodiments, the ferroelectric layer 90' has a uniformly distributed concentration of species. The species concentration of the ferroelectric layer 90' may range from about 1E17/cm 3 to about 1E20/cm 3 .

如圖19C及圖19D中所示出以及在圖21的動作S106處，對鐵電層90'執行第二回火製程89。在一些實施例中，第二回火製程89包括尖峰回火製程。可使用以下製程參數或條件執行尖峰回火製程：維持在約380℃與約420℃之間的範圍內的峰值回火溫度、介於約1秒與約60秒之間的範圍內的回火時間（或持續時間）（在此期間維持峰值溫度），以及介於約50托與約760托之間的範圍內的回火壓力。並不任意選擇回火製程的上述這些製程參數，而是小心地調節這些製程參數以活化鐵電層90'中的物質。As shown in FIGS. 19C and 19D and at act S106 of FIG. 21 , a second tempering process 89 is performed on the ferroelectric layer 90 ′. In some embodiments, the second tempering process 89 includes a spike tempering process. The peak tempering process may be performed using the following process parameters or conditions: peak tempering temperature maintained in a range between about 380°C and about 420°C, tempering in a range between about 1 second and about 60 seconds The time (or duration) during which the peak temperature is maintained, and the tempering pressure in the range between about 50 Torr and about 760 Torr. These process parameters of the tempering process are not arbitrarily selected, but are carefully adjusted to activate the species in the ferroelectric layer 90'.

在圖20A、圖20B中且在圖21的動作S108處，通道層92在鐵電層90'上方共形地沈積在溝渠86中。通道層92包括適合於為記憶胞202（參看圖1A）提供通道區的材料。舉例而言，通道層92包括氧化物半導體（OS），諸如氧化鋅（ZnO）、氧化銦鎢（InWO）、氧化銦鎵鋅（InGaZnO，IGZO）、氧化銦鋅（InZnO）、氧化銦錫（ITO）、其組合或類似物。在一些實施例中，通道層92包括多晶矽（poly-Si）、非晶矽（a-Si）或類似物。可藉由CVD、PVD、ALD、PECVD或類似者沈積通道層92。通道層92可在鐵電層90上方沿著溝渠86的側壁及底部表面延伸。在一些實施例中，通道層92可進一步沈積在IMD 70上且沿著階梯區中的階梯結構中的每一階的側壁沈積。在圖21的動作S110處，在通道層92沈積之後，可在氧相關環境中執行第三回火步驟（例如，在約300℃至約450℃的溫度範圍下），以活化通道層92的電荷載子。In FIGS. 20A, 20B, and at act S108 of FIG. 21, channel layer 92 is conformally deposited in trench 86 over ferroelectric layer 90'. Channel layer 92 includes a material suitable for providing channel regions for memory cells 202 (see FIG. 1A ). For example, the channel layer 92 includes an oxide semiconductor (OS) such as zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO, IGZO), indium zinc oxide (InZnO), indium tin oxide ( ITO), combinations thereof, or the like. In some embodiments, the channel layer 92 includes polysilicon (poly-Si), amorphous silicon (a-Si), or the like. Channel layer 92 may be deposited by CVD, PVD, ALD, PECVD, or the like. Channel layer 92 may extend along sidewalls and bottom surfaces of trench 86 over ferroelectric layer 90 . In some embodiments, a channel layer 92 may be further deposited on the IMD 70 and along the sidewalls of each of the stepped structures in the stepped region. At act S110 of FIG. 21 , after the deposition of the channel layer 92 , a third annealing step may be performed in an oxygen-related environment (eg, at a temperature ranging from about 300° C. to about 450° C.) to activate the channel layer 92 charge carriers.

在圖20C中，在執行第三回火製程之後，物質中的一些擴散至通道層92。在一些實施例中，物質中的一些擴散至通道層92的與頂部鐵電部分90T接觸的底部通道部分92B，且通道層92的中間通道部分92M及頂部通道部分具有極少物質或不含物質。頂部通道部分92T具有厚度T6；中間通道部分92M具有厚度T5；且底部通道部分92B具有厚度T4。其他厚度範圍可為適用的。在一些實施例中，組合厚度T3與組合厚度（例如，厚度T3加上厚度T2及厚度T1）的厚度比介於約5%至約50%、約10%至約60%或其他類似值的範圍內。在一些實施例中，組合厚度T4與組合厚度（例如，厚度T6加上厚度T5及厚度T4）的厚度比介於約5%至50%、約10%至約60%或其他類似值的範圍內。In FIG. 20C, some of the species diffuses into the channel layer 92 after the third annealing process is performed. In some embodiments, some of the species diffuses to the bottom channel portion 92B of the channel layer 92 that contacts the top ferroelectric portion 90T, and the middle channel portion 92M and the top channel portion of the channel layer 92 have little or no species. Top channel portion 92T has a thickness T6; middle channel portion 92M has a thickness T5; and bottom channel portion 92B has a thickness T4. Other thickness ranges may be applicable. In some embodiments, the thickness ratio of the combined thickness T3 to the combined thickness (eg, thickness T3 plus thickness T2 and thickness T1 ) is between about 5% to about 50%, about 10% to about 60%, or other similar values within the range. In some embodiments, the thickness ratio of the combined thickness T4 to the combined thickness (eg, thickness T6 plus thickness T5 and thickness T4 ) ranges from about 5% to 50%, about 10% to about 60%, or other similar values Inside.

在圖20D中，繪示物質濃度及氧濃度與通道層92、鐵電層90'以及導線72的深度的關係圖。y軸表示物質濃度及氧濃度。x軸表示通道層92、鐵電層90'以及導線72的深度。曲線[012]表示通道層92的氧濃度分佈；曲線[011]表示鐵電層90'的氧濃度；而曲線[S1]表示物質濃度。In FIG. 20D , the relationship between the concentration of species and the concentration of oxygen and the depth of the channel layer 92 , the ferroelectric layer 90 ′ and the wire 72 is shown. The y-axis represents the substance concentration and the oxygen concentration. The x-axis represents the depth of channel layer 92 , ferroelectric layer 90 ′, and wire 72 . Curve [012] represents the oxygen concentration distribution of the channel layer 92; curve [011] represents the oxygen concentration of the ferroelectric layer 90'; and curve [S1] represents the species concentration.

在一些實施例中，曲線[012]表示通道層92的中間通道部分92M具有最大氧濃度。氧濃度自靠近於稍後形成的介電材料98A的頂部通道部分92T的一部分至中間通道部分92M的中心增大。氧濃度自中間通道部分92M的中心至底部通道部分92B與頂部鐵電部分90T之間的界面IF2降低。通道層92的頂部通道部分92T及底部通道部分92B的氧濃度低於通道層92的中間通道部分92M的氧濃度。In some embodiments, the curve [012] indicates that the middle channel portion 92M of the channel layer 92 has a maximum oxygen concentration. The oxygen concentration increases from a portion near the top channel portion 92T of the later-formed dielectric material 98A to the center of the middle channel portion 92M. The oxygen concentration decreases from the center of the middle channel portion 92M to the interface IF2 between the bottom channel portion 92B and the top ferroelectric portion 90T. The oxygen concentration of the top channel portion 92T and the bottom channel portion 92B of the channel layer 92 is lower than the oxygen concentration of the middle channel portion 92M of the channel layer 92 .

曲線[011]表示靠近底部鐵電部分90B的中間鐵電部分90M的一部分具有最大氧濃度。鐵電層90'的最大氧濃度高於通道層92的最大氧濃度。氧濃度自頂部鐵電部分90T與底部通道部分92B之間的界面IF2至靠近底部鐵電部分90B的中間鐵電部分90M的部分增加。氧濃度自靠近底部鐵電部分90B的中間鐵電部分90M的部分至底部鐵電部分90B與導線72之間的界面IF1減少。頂部鐵電部分90T的氧濃度低於中間鐵電部分90M及底部鐵電部分90B的氧濃度。Curve [011] indicates that a portion of the middle ferroelectric portion 90M near the bottom ferroelectric portion 90B has a maximum oxygen concentration. The maximum oxygen concentration of the ferroelectric layer 90 ′ is higher than the maximum oxygen concentration of the channel layer 92 . The oxygen concentration increases from the interface IF2 between the top ferroelectric portion 90T and the bottom channel portion 92B to the portion of the middle ferroelectric portion 90M near the bottom ferroelectric portion 90B. The oxygen concentration decreases from the portion of the middle ferroelectric portion 90M near the bottom ferroelectric portion 90B to the interface IF1 between the bottom ferroelectric portion 90B and the wire 72 . The oxygen concentration of the top ferroelectric portion 90T is lower than that of the middle ferroelectric portion 90M and the bottom ferroelectric portion 90B.

曲線[S1]表示鐵電層90'具有最大物質濃度。鐵電層90'的最大物質濃度介於通道層92的最大氧濃度與鐵電層90'的最大氧濃度之間。頂部鐵電部分90T具有最大物質濃度。中間鐵電部分90M的物質濃度亦低於頂部鐵電部分90T的物質濃度且大於底部鐵電部分90B的物質濃度。Curve [S1] indicates that the ferroelectric layer 90' has the maximum species concentration. The maximum species concentration of the ferroelectric layer 90' is between the maximum oxygen concentration of the channel layer 92 and the maximum oxygen concentration of the ferroelectric layer 90'. The top ferroelectric portion 90T has the largest species concentration. The species concentration of the middle ferroelectric portion 90M is also lower than that of the top ferroelectric portion 90T and greater than that of the bottom ferroelectric portion 90B.

底部通道部分92B的物質濃度低於頂部鐵電部分90T的物質濃度且大於中間通道部分92M及頂部通道部分92T。在一個實施例中，底部通道部分92B的物質濃度可介於鐵電層90'的最大物質濃度的約1%至約60%範圍內。中間通道部分92M及頂部通道部分92T可具有極少物質或不含物質，且因此，中間通道部分92M或頂部通道部分92T的物質濃度可小於鐵電層90'的最大物質濃度的1%或為零。鐵電層90'中的物質的分佈範圍與氧的分佈範圍的比大於通道層92（例如，氧化物半導體層）中的物質的分佈範圍與氧的分佈範圍的比。The species concentration of the bottom channel portion 92B is lower than that of the top ferroelectric portion 90T and greater than that of the middle channel portion 92M and the top channel portion 92T. In one embodiment, the species concentration of bottom channel portion 92B may range from about 1% to about 60% of the maximum species concentration of ferroelectric layer 90'. The middle channel portion 92M and the top channel portion 92T may have little or no species, and thus, the species concentration of the middle channel portion 92M or the top channel portion 92T may be less than 1% or zero of the maximum species concentration of the ferroelectric layer 90' . The ratio of the distribution range of the species to the oxygen distribution range in the ferroelectric layer 90 ′ is larger than the ratio of the distribution range of the species to the oxygen distribution range in the channel layer 92 (eg, oxide semiconductor layer).

頂部鐵電部分90T的物質濃度高於其氧濃度。底部通道部分92B與頂部鐵電部分90T之間的界面IF2的物質濃度亦高於其氧濃度。底部通道部分92B與頂部鐵電部分90T之間的界面IF2的物質濃度高於底部鐵電部分90B與導線72之間的界面IF1的物質濃度。The species concentration of the top ferroelectric portion 90T is higher than its oxygen concentration. The interface IF2 between the bottom channel portion 92B and the top ferroelectric portion 90T also has a higher species concentration than its oxygen concentration. The species concentration of the interface IF2 between the bottom channel portion 92B and the top ferroelectric portion 90T is higher than the species concentration of the interface IF1 between the bottom ferroelectric portion 90B and the wire 72 .

圖22至圖25B示出在溝渠86中形成記憶胞202（參看圖1A）的介電材料98以及圖案化通道層92。以部分三維圖示出圖25A，其為藉由圖25B中的虛線30所圍的部分的透視圖。在圖22、圖23、圖24以及圖25B中，提供沿著圖1A的線C-C'的橫截面圖。22-25B illustrate the formation of the dielectric material 98 of the memory cells 202 (see FIG. 1A ) in the trenches 86 and the patterned channel layer 92 . Figure 25A is shown in a partial three-dimensional view, which is a perspective view of the portion enclosed by the dashed line 30 in Figure 25B. In FIGS. 22, 23, 24, and 25B, cross-sectional views along line CC' of FIG. 1A are provided.

在圖22中，將介電材料98A沈積在溝渠86中在通道層92上方。在一些實施例中，介電材料98A包括可藉由CVD、PVD、ALD、PECVD或類似者沈積的氧化矽、氮化矽、氮氧化矽或類似物。介電材料98A可在通道層92上方沿著溝渠86的側壁及底部表面延伸。在一些實施例中，介電材料98A為視情況選用的且可省略。In FIG. 22 , dielectric material 98A is deposited in trench 86 over channel layer 92 . In some embodiments, the dielectric material 98A includes silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. Dielectric material 98A may extend along sidewalls and bottom surfaces of trenches 86 over channel layer 92 . In some embodiments, dielectric material 98A is optional and may be omitted.

在圖23中，移除溝渠86中的介電材料98A及通道層92的底部部分。移除製程包括可接受的蝕刻製程，諸如乾式蝕刻（例如，RIE、NBE、類似蝕刻）、濕式蝕刻、類似蝕刻或其組合。蝕刻可為非等向性的。在一些實施例中，自多層堆疊58移除介電材料98A及通道層92的頂部部分。在一些實施例中，移除製程包括微影及蝕刻的組合。In FIG. 23, the dielectric material 98A in trench 86 and the bottom portion of channel layer 92 are removed. Removal processes include acceptable etch processes, such as dry etch (eg, RIE, NBE, similar etch), wet etch, similar etch, or combinations thereof. Etching can be anisotropic. In some embodiments, dielectric material 98A and a top portion of channel layer 92 are removed from multilayer stack 58 . In some embodiments, the removal process includes a combination of lithography and etching.

相應地，剩餘的介電材料98A及通道層92可在溝渠86的底部表面上暴露鐵電層90'的部分。因此，溝渠86的相對側壁上的通道層92的部分可彼此分隔開，此可提升記憶陣列200的記憶胞202（參看圖1A）之間的隔離。Accordingly, remaining dielectric material 98A and channel layer 92 may expose portions of ferroelectric layer 90 ′ on the bottom surface of trench 86 . Accordingly, portions of channel layer 92 on opposite sidewalls of trenches 86 may be separated from each other, which may improve isolation between memory cells 202 (see FIG. 1A ) of memory array 200 .

在圖24中，沈積介電材料98B以完全填充溝渠86。介電材料98B可由一或多種材料形成且藉由與介電材料98A的製程相同或類似的製程形成。在一些實施例中，介電材料98B及介電材料98A包括不同材料。In FIG. 24 , dielectric material 98B is deposited to completely fill trench 86 . Dielectric material 98B can be formed from one or more materials and is formed by the same or similar process as that of dielectric material 98A. In some embodiments, dielectric material 98B and dielectric material 98A comprise different materials.

在圖25A及圖25B中，對介電材料98A/98B、通道層92以及鐵電層90'進行移除製程，以移除多層堆疊58上方的多餘材料。在一些實施例中，可利用平坦化製程，諸如CMP、回蝕製程、其組合或類似者。平坦化製程暴露多層堆疊58，使得在平坦化製程完成之後，多層堆疊58（例如，介電層52E）、鐵電層90'、通道層92、介電材料98A/98B（統稱為介電材料98）以及IMD 70的頂面齊平。In FIGS. 25A and 25B , a removal process is performed on the dielectric material 98A/98B, the channel layer 92 and the ferroelectric layer 90 ′ to remove excess material above the multilayer stack 58 . In some embodiments, planarization processes such as CMP, etch-back processes, combinations thereof, or the like may be utilized. The planarization process exposes the multi-layer stack 58 such that after the planarization process is complete, the multi-layer stack 58 (eg, dielectric layer 52E), ferroelectric layer 90', channel layer 92, dielectric material 98A/98B (collectively referred to as dielectric material) 98) and the top surface of the IMD 70 is flush.

圖26A至圖29B示出製造記憶陣列200中的導電柱106及導電柱108（例如，源極/汲極柱）的中間步驟。導電柱106及導電柱108可沿著垂直於導線72的方向延伸，使得可針對讀取操作及寫入操作選擇記憶陣列200的個別胞。以部分三維圖示出圖26A、圖27A、圖28A以及圖29A，其分別為藉由圖26B、圖27B、圖28B以及圖29B中的虛線30所圍的部分的透視圖。在圖26B及圖27B中，提供沿著圖1A的線C-C'的橫截面圖。在圖28B及圖29B中，提供沿著圖1A的線D-D'的橫截面圖。FIGS. 26A-29B illustrate intermediate steps in fabricating conductive pillars 106 and 108 (eg, source/drain pillars) in memory array 200 . Conductive pillars 106 and 108 may extend in a direction perpendicular to wires 72 such that individual cells of memory array 200 may be selected for read and write operations. Figures 26A, 27A, 28A, and 29A are shown in partial three-dimensional views, which are perspective views of the portion enclosed by dashed line 30 in Figures 26B, 27B, 28B, and 29B, respectively. In FIGS. 26B and 27B, a cross-sectional view along line CC' of FIG. 1A is provided. In FIGS. 28B and 29B, a cross-sectional view along line DD' of FIG. 1A is provided.

在圖26A及圖26B中，在一些實施例中，經由通道層92及介電材料98圖案化溝渠100。在替代實施例中，經由通道層92、介電材料98以及鐵電層90'（未繪示）圖案化溝渠100。可經由例如微影及蝕刻的組合執行對溝渠100的圖案化。溝渠100可安置在鐵電層90'的相對側壁之間，且溝渠100可實體上分隔開記憶陣列200（參看圖1A）中的記憶胞的相鄰堆疊。In FIGS. 26A and 26B , trench 100 is patterned through channel layer 92 and dielectric material 98 in some embodiments. In an alternative embodiment, trench 100 is patterned through channel layer 92, dielectric material 98, and ferroelectric layer 90' (not shown). Patterning of trenches 100 may be performed, for example, through a combination of lithography and etching. The trenches 100 may be disposed between opposing sidewalls of the ferroelectric layer 90', and the trenches 100 may physically separate adjacent stacks of memory cells in the memory array 200 (see FIG. 1A).

在圖27A及圖27B中，在溝渠100中形成隔離柱102。在一些實施例中，隔離層沈積在多層堆疊58上方，並填充在溝渠100之中。隔離層可包括例如可藉由CVD、PVD、ALD、PECVD或類似者沈積的氧化矽、氮化矽、氮氧化矽或類似物。隔離層可在通道層92上方沿著溝渠100的側壁及底部表面延伸。在沈積之後，可執行平坦化製程（例如，CMP、回蝕或類似者）以移除隔離層的多餘部分。在所得結構中，多層堆疊58（例如介電層52E）、鐵電層90'、通道層92以及隔離柱102的頂面可為實質上齊平的（例如，在製程變化內）。在一些實施例中，可選擇介電材料98及隔離柱102的材料，使得其可相對於彼此選擇性地蝕刻。舉例而言，在一些實施例中，介電材料98包括氧化物且隔離柱102包括氮化物。在一些實施例中，介電材料98包括氮化物且隔離柱102包括氧化物。也可以採用其他材料。In FIGS. 27A and 27B , isolation pillars 102 are formed in the trenches 100 . In some embodiments, an isolation layer is deposited over multilayer stack 58 and fills trench 100 . The isolation layer may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. An isolation layer may extend along the sidewalls and bottom surfaces of trench 100 over channel layer 92 . After deposition, a planarization process (eg, CMP, etch-back, or the like) may be performed to remove excess portions of the isolation layer. In the resulting structure, the top surfaces of the multilayer stack 58 (eg, dielectric layer 52E), ferroelectric layer 90', channel layer 92, and isolation pillars 102 may be substantially flush (eg, within process variations). In some embodiments, the materials of the dielectric material 98 and the isolation pillars 102 can be selected such that they can be selectively etched with respect to each other. For example, in some embodiments, dielectric material 98 includes oxide and isolation pillars 102 include nitride. In some embodiments, dielectric material 98 includes nitride and isolation pillars 102 include oxide. Other materials may also be used.

在圖28A及圖28B中，形成溝渠104，以用於後續界定導電柱106及導電柱108。舉例而言，藉由利用微影及蝕刻的組合圖案化介電材料98來形成溝渠104。在一些實施例中，如圖28A中所繪示，在多層堆疊58、介電材料98、隔離柱102、通道層92以及鐵電部分90'上方形成光阻118。在一些實施例中，藉由可接受的微影技術圖案化光阻118以界定開口120。開口120中的每一者可暴露對應的隔離柱102以及介電材料98的在隔離柱102旁邊的兩個分隔開的區。以此方式，開口120中的每一者可界定由隔離柱102分隔開的導電柱106及相鄰導電柱108的圖案。In FIGS. 28A and 28B , trenches 104 are formed for subsequently defining conductive pillars 106 and 108 . For example, trenches 104 are formed by patterning dielectric material 98 using a combination of lithography and etching. In some embodiments, photoresist 118 is formed over multilayer stack 58, dielectric material 98, isolation pillars 102, channel layer 92, and ferroelectric portion 90', as depicted in FIG. 28A. In some embodiments, photoresist 118 is patterned by acceptable lithography techniques to define openings 120 . Each of the openings 120 may expose the corresponding isolation pillar 102 and two spaced-apart regions of the dielectric material 98 next to the isolation pillar 102 . In this manner, each of the openings 120 may define a pattern of conductive pillars 106 and adjacent conductive pillars 108 separated by isolation pillars 102 .

隨後，被開口120暴露的介電材料98的部分可藉由諸如乾式蝕刻（例如，RIE、NBE、類似蝕刻）、濕式蝕刻、類似蝕刻或其組合的可接受的蝕刻製程移除。蝕刻可為非等向性的。蝕刻製程可使用蝕刻介電材料98而不顯著地蝕刻隔離柱102的蝕刻劑。因此，即使開口120暴露隔離柱102，仍不可顯著地移除隔離柱102。溝渠104的圖案可對應於導電柱106及導電柱108（參看圖29A及圖29B）。舉例而言，在圖案化溝渠104之後，可藉由灰化移除光阻118。Subsequently, the portion of dielectric material 98 exposed by opening 120 may be removed by an acceptable etching process such as dry etching (eg, RIE, NBE, similar etching), wet etching, similar etching, or a combination thereof. Etching can be anisotropic. The etching process may use an etchant that etches the dielectric material 98 without significantly etching the isolation pillars 102 . Thus, even though the openings 120 expose the isolation pillars 102, the isolation pillars 102 may not be significantly removed. The pattern of trenches 104 may correspond to conductive pillars 106 and 108 (see FIGS. 29A and 29B ). For example, after patterning trench 104, photoresist 118 may be removed by ashing.

在圖29A及圖29B中，將導電材料填充於溝渠104之中以形成導電柱106及導電柱108。導電材料可包括銅、鈦、氮化鈦、鉭、氮化鉭、鎢、釕、鋁、其組合或類似物，其可使用例如CVD、ALD、PVD、PECVD或類似者形成。在沈積導電材料之後，可執行平坦化（例如，CMP、回蝕或類似者）以移除導電材料的多餘部分，藉此形成導電柱106及導電柱108。在所得結構中，多層堆疊58（例如，介電層52E）、鐵電層90'、通道層92、導電柱106以及導電柱108的頂面可為實質上齊平的（例如，在製程變化內）。在一些實施例中，導電柱106對應於且電連接至記憶陣列中的位元線，且導電柱108對應於且電連接至記憶陣列200中的源極線。In FIGS. 29A and 29B , conductive material is filled in the trenches 104 to form conductive pillars 106 and 108 . The conductive material may include copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, which may be formed using, for example, CVD, ALD, PVD, PECVD, or the like. After depositing the conductive material, planarization (eg, CMP, etch-back, or the like) may be performed to remove excess portions of the conductive material, thereby forming conductive pillars 106 and 108 . In the resulting structure, the top surfaces of the multilayer stack 58 (eg, dielectric layer 52E), ferroelectric layer 90', channel layer 92, conductive pillars 106, and conductive pillars 108 may be substantially flush (eg, during process variations Inside). In some embodiments, conductive pillars 106 correspond to and are electrically connected to bit lines in the memory array, and conductive pillars 108 correspond to and are electrically connected to source lines in the memory array 200 .

因此，堆疊的記憶胞202可形成在記憶陣列200中，如圖29A中所繪示。每一記憶胞202包括閘電極（例如，對應導線72的一部分）、閘介電質（例如，對應鐵電層90'的一部分）、通道區（例如，對應通道層92的一部分）以及源極/汲極柱（例如，對應導電柱106及導電柱108的部分）。隔離柱102隔離在同一行中且在同一垂直位準處的相鄰記憶胞202。記憶胞202可安置在垂直堆疊的列及行的陣列中。Accordingly, stacked memory cells 202 can be formed in memory array 200, as shown in FIG. 29A. Each memory cell 202 includes a gate electrode (eg, corresponding to a portion of wire 72 ), a gate dielectric (eg, corresponding to a portion of ferroelectric layer 90 ′), a channel region (eg, corresponding to a portion of channel layer 92 ), and a source electrode /Drain pillars (eg, corresponding to portions of conductive pillars 106 and 108). The isolation pillars 102 isolate adjacent memory cells 202 in the same row and at the same vertical level. The memory cells 202 may be arranged in an array of vertically stacked columns and rows.

在圖30A、圖30B、圖30C、圖30D以及圖30E中，IMD 74形成在多層堆疊58（例如，介電層52E）、鐵電層90'、通道層92、導電柱106以及導電柱108及IMD 70的頂面上。分別在導線72、導電柱106以及導電柱108上製得導電接觸窗110、導電接觸窗112以及導電接觸窗114。圖30A示出記憶陣列200的透視圖，其亦為藉由圖30B中的虛線30所圍的部分的透視圖；圖30B示出沿著圖1A的線D-D'的元件的橫截面圖；圖30C示出記憶陣列200的自上而下視圖；且圖30D示出沿著圖30A的線E-E'的橫截面圖；且圖30E示出沿著圖1A的線B-B'的元件的橫截面圖。In FIGS. 30A , 30B, 30C, 30D, and 30E, IMD 74 is formed on multilayer stack 58 (eg, dielectric layer 52E), ferroelectric layer 90 ′, channel layer 92 , conductive pillars 106 , and conductive pillars 108 and the top surface of the IMD 70. Conductive contact windows 110 , conductive contact windows 112 and conductive contact windows 114 are formed on the wires 72 , the conductive posts 106 and the conductive posts 108 , respectively. Figure 30A shows a perspective view of memory array 200, which is also a perspective view of the portion enclosed by dashed line 30 in Figure 30B; Figure 30B shows a cross-sectional view of elements along line DD' of Figure 1A 30C shows a top-down view of the memory array 200; and FIG. 30D shows a cross-sectional view along line EE' of FIG. 30A; and FIG. 30E shows a cross-sectional view along line BB' of FIG. 1A A cross-sectional view of the element.

IMD 74可由介電材料形成，且可藉由任何適合方法沈積，所述方法諸如CVD、PECVD、可流動CVD（flowable CVD；FCVD）或類似者。介電材料可包括磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、硼摻雜磷矽酸鹽玻璃（BPSG）、未摻雜的矽酸鹽玻璃（USG）、低k介電材料或類似物。在一些實施例中，IMD 74可包括氧化物（例如，氧化矽或類似物）、氮化物（例如，氮化矽或類似物）、其組合或類似物。可使用由任何可接受的製程形成的其他介電材料。之後，對IMD 74應用移除製程以移除多層堆疊58及IMD 70上方的多餘介電材料。在一些實施例中，移除製程可為平坦化製程，諸如化學機械研磨（CMP）、回蝕製程、其組合或類似者。The IMD 74 may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, PECVD, flowable CVD (FCVD), or the like. Dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), low-k dielectric electrical material or the like. In some embodiments, IMD 74 may include oxides (eg, silicon oxide or the like), nitrides (eg, silicon nitride or the like), combinations thereof, or the like. Other dielectric materials formed by any acceptable process can be used. Afterwards, a removal process is applied to IMD 74 to remove excess dielectric material over multilayer stack 58 and IMD 70 . In some embodiments, the removal process may be a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like.

在一些實施例中，導線72的階梯形狀可在導線72中的每一者上提供用於使導電接觸窗110落在其上的表面。在一些實施例中，形成導電接觸窗110可包括例如使用微影及蝕刻的組合在IMD 74及IMD 70中圖案化開口以暴露導線72的部分。在開口中形成諸如擴散阻障層、黏著層或類似物的襯墊（未繪示）及導電材料。襯墊可包括鈦、氮化鈦、鉭、氮化鉭或類似物。導電材料可包括銅、銅合金、銀、金、鎢、鈷、鋁、鎳或類似物。可執行平坦化製程（諸如CMP）以自IMD 74的表面移除多餘材料。剩餘的襯墊及導電材料在開口中形成導電接觸窗110。In some embodiments, the stepped shape of the wires 72 may provide a surface on each of the wires 72 for the conductive contacts 110 to land on. In some embodiments, forming conductive contacts 110 may include patterning openings in IMD 74 and IMD 70 to expose portions of wires 72 , eg, using a combination of lithography and etching. A liner (not shown) such as a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may include copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of IMD 74 . The remaining pads and conductive material form conductive contacts 110 in the openings.

亦如圖30A的透視圖所示出，亦可分別在導電柱106及導電柱108上製得導電接觸窗112及導電接觸窗114。導電接觸窗112、導電接觸窗114以及導電接觸窗110可分別電連接至導線116A、導線116B以及導線116C，其將記憶陣列連接至半導體晶粒中的下伏/上覆電路（例如，控制電路）及/或信號、功率以及接地線。舉例而言，如圖30D中所繪示，導電接觸窗110可延伸穿過IMD 74及IMD 70以將導線116C電連接至導線72。可經由IMD 74形成其他導電接觸窗或通孔以將導線116A及導線116B電連接至基底上的下伏主動元件。在替代實施例中，除了內連線結構320以外或代替內連線結構320，可藉由在記憶陣列200上方形成的內連線結構來提供至記憶陣列及自記憶陣列的佈線及/或功率線。相應地，可完成記憶陣列200。As also shown in the perspective view of FIG. 30A , conductive contacts 112 and 114 may also be formed on conductive posts 106 and 108 , respectively. Conductive contacts 112, 114, and 110 may be electrically connected to wires 116A, 116B, and 116C, respectively, which connect the memory array to underlying/overlying circuits (eg, control circuits) in the semiconductor die ) and/or signal, power and ground wires. For example, as shown in FIG. 30D , conductive contact 110 may extend through IMD 74 and IMD 70 to electrically connect wire 116C to wire 72 . Other conductive contacts or vias may be formed through IMD 74 to electrically connect wires 116A and 116B to underlying active elements on the substrate. In alternative embodiments, routing and/or power to and from the memory array 200 may be provided by interconnect structures formed over the memory array 200 in addition to or instead of the interconnect structure 320 String. Accordingly, the memory array 200 can be completed.

雖然圖1A至圖30B的實施例示出導電柱106及導電柱108的特定圖案，但其他組態亦為可能的。舉例而言，在這些實施例中，導電柱106及導電柱108具有交錯的圖案。然而，在其他實施例中，陣列的同一列中的導電柱106及導電柱108彼此對準，如圖32的鐵電記憶體200A中所繪示。Although the embodiments of FIGS. 1A-30B show specific patterns of conductive pillars 106 and 108, other configurations are possible. For example, in these embodiments, conductive pillars 106 and 108 have a staggered pattern. However, in other embodiments, the conductive pillars 106 and the conductive pillars 108 in the same column of the array are aligned with each other, as shown in the ferroelectric memory 200A of FIG. 32 .

圖1A至圖30B的實施例示出為在特定時機下執行的處理88，其他適合時機亦為可能的。舉例而言，在這些實施例中，在通道層92形成之前執行處理88。然而，在其他實施例中，處理88以在通道層192形成之後執行的處理188替換，如圖32A、圖32B、圖33A、圖33B、圖34A、圖34B、圖34C、圖34D、圖35以及圖36的記憶陣列200'中所繪示。The embodiment of FIGS. 1A-30B is shown as processing 88 performed at a particular occasion, other suitable occasions are possible. For example, in these embodiments, process 88 is performed before channel layer 92 is formed. However, in other embodiments, process 88 is replaced with process 188 performed after channel layer 192 is formed, as shown in FIGS. 32A, 32B, 33A, 33B, 34A, 34B, 34C, 34D, 35 and as shown in the memory array 200' of FIG. 36 .

圖32A至圖36示出在溝渠86中形成鐵電層190'及通道層192'。以部分三維圖示出圖32A、圖33A、圖34A以及圖36。圖32A、圖33A以及圖34A亦分別為藉由圖32B、圖33B以及圖34B中的虛線30所圍的部分的透視圖。在圖32B、圖33B以及圖34B中，提供沿著圖36的線C-C'的橫截面圖。圖34C示出圖34B的區R2的局部放大圖。圖34D示出物質濃度及氧濃度與通道層192'、鐵電層190'以及導線72的深度的圖表。圖35示出根據一些實施例的形成鐵電層190'及通道層192'的方法。FIGS. 32A-36 illustrate the formation of a ferroelectric layer 190 ′ and a channel layer 192 ′ in trench 86 . Figures 32A, 33A, 34A, and 36 are shown in partial three-dimensional views. 32A, 33A, and 34A are also perspective views of the portion enclosed by the dotted line 30 in FIGS. 32B, 33B, and 34B, respectively. In FIGS. 32B, 33B, and 34B, cross-sectional views along line CC' of FIG. 36 are provided. FIG. 34C shows a partial enlarged view of the region R2 of FIG. 34B. FIG. 34D shows a graph of species concentration and oxygen concentration versus depth of channel layer 192 ′, ferroelectric layer 190 ′, and wire 72 . 35 illustrates a method of forming a ferroelectric layer 190' and a channel layer 192' according to some embodiments.

在圖32A、圖32B中且在圖35的動作S200處，在圖案化塊狀多層堆疊58以形成穿過其的溝渠86且用導電材料取代犧牲層53以界定導線72之後，鐵電層190可沿著導線72的側壁及介電層52E的頂面且沿著溝渠86的底部表面共形地沈積在溝渠86中。在一些實施例中，鐵電層190可進一步沈積在IMD 70上且沿著階梯區中的階梯結構中的每一階的側壁沈積。鐵電層190可包括能夠藉由在鐵電層190上施加適當電壓差而在兩個不同極化方向之間切換的材料。鐵電層190可與圖17A的鐵電層90相同或類似。在圖35的動作S202處，對鐵電層190執行第一回火製程，以實現鐵電層190的所要晶格結構。在這些實施例中，第一回火製程可與圖21的動作S102處的第三回火製程相同或類似。In FIGS. 32A, 32B, and at act S200 of FIG. 35, after patterning bulk multilayer stack 58 to form trenches 86 therethrough and replacing sacrificial layer 53 with a conductive material to define wires 72, ferroelectric layer 190 The trenches 86 may be deposited conformally along the sidewalls of the wires 72 and the top surface of the dielectric layer 52E and along the bottom surfaces of the trenches 86 . In some embodiments, a ferroelectric layer 190 may be further deposited on the IMD 70 and along the sidewalls of each of the stepped structures in the stepped region. The ferroelectric layer 190 may comprise a material that can be switched between two different polarization directions by applying an appropriate voltage difference across the ferroelectric layer 190 . The ferroelectric layer 190 may be the same as or similar to the ferroelectric layer 90 of Figure 17A. At act S202 of FIG. 35 , a first tempering process is performed on the ferroelectric layer 190 to achieve a desired lattice structure of the ferroelectric layer 190 . In these embodiments, the first tempering process may be the same as or similar to the third tempering process at act S102 of FIG. 21 .

在圖32A、圖32B中且在圖35的動作S204處，將通道層192共形地沈積在溝渠86中的鐵電層190上方。通道層192包括適合於為記憶胞202'（參看圖36）提供通道區的材料。通道層192可與圖20A的通道層92相同或類似。在圖35的動作S206處，對通道層192執行第二回火製程以活化通道層192的電荷載子。在這些實施例中，第二回火製程可與圖21的動作S110處的第三回火製程相同或類似。In FIGS. 32A , 32B and at act S204 of FIG. 35 , channel layer 192 is conformally deposited over ferroelectric layer 190 in trench 86 . Channel layer 192 includes a material suitable for providing channel regions for memory cells 202' (see Figure 36). Channel layer 192 may be the same as or similar to channel layer 92 of Figure 20A. At act S206 of FIG. 35 , a second annealing process is performed on the channel layer 192 to activate the charge carriers of the channel layer 192 . In these embodiments, the second tempering process may be the same as or similar to the third tempering process at act S110 of FIG. 21 .

在圖33A、圖33B中且在圖35的動作S208處，在鐵電層190及通道層192形成之後，對通道層192及鐵電層190執行處理188以形成通道層192'及鐵電層190'，從而提升元件的耐久效能。在一些實施例中，處理188藉由能量源將物質引入於通道層192及鐵電層190中。處理188的能量源可藉由包括熱擴散、電子束、紫外線（UV）或其組合的離子植入製程、電漿製程或其他適合製程提供。In FIGS. 33A, 33B, and at act S208 of FIG. 35, after ferroelectric layer 190 and channel layer 192 are formed, process 188 is performed on channel layer 192 and ferroelectric layer 190 to form channel layer 192' and the ferroelectric layer 190', thereby increasing the durability of the element. In some embodiments, process 188 introduces species into channel layer 192 and ferroelectric layer 190 via an energy source. The energy source for processing 188 may be provided by an ion implantation process, plasma process, or other suitable process including thermal diffusion, electron beam, ultraviolet (UV), or a combination thereof.

處理188可為氮化處理製程，或鹵素處理製程。在一些實施例中，處理188引入價數為5（例如氮（N））或價數為7（例如氟（F））的物質，以便消除或阻止鐵電層190與通道層192之間的界面IF4中的陷阱或缺陷，且/或佔據界面IF4、通道層192及/或鐵電層190中的氧空缺且充當鈍化物以抑制氧、氫以及空缺的相互擴散，使得可提升鐵電層190'的固有疲勞效能及耐久性。在一些實施例中，通道層192'亦可稱為含有物質（諸如氮或鹵素）的通道層，且鐵電層190'亦可稱為含有物質（諸如氮或鹵素）的鐵電層。在替代實施例中，通道層192'亦可稱為鈍化物質（諸如氮或鹵素）摻雜的通道層，且鐵電層190'亦可稱為鈍化物質（諸如氮或鹵素）摻雜的鐵電層。Treatment 188 may be a nitridation treatment process, or a halogen treatment process. In some embodiments, the process 188 introduces a species with a valence of 5 (eg, nitrogen (N)) or a valence of 7 (eg, fluorine (F)) in order to eliminate or prevent the interaction between the ferroelectric layer 190 and the channel layer 192 . Traps or defects in interface IF4 and/or occupy oxygen vacancies in interface IF4, channel layer 192 and/or ferroelectric layer 190 and act as passivators to inhibit interdiffusion of oxygen, hydrogen and vacancies so that the ferroelectric layer can be lifted 190' of inherent fatigue performance and durability. In some embodiments, channel layer 192' may also be referred to as a channel layer containing species such as nitrogen or halogen, and ferroelectric layer 190' may also be referred to as a ferroelectric layer containing species such as nitrogen or halogen. In alternative embodiments, channel layer 192' may also be referred to as a passivation species (such as nitrogen or halogen) doped channel layer, and ferroelectric layer 190' may also be referred to as passivation species (such as nitrogen or halogen) doped iron electrical layer.

因此，通道層192'及鐵電層190'具有價數為5、7或其組合的物質。在一些實施例中，離子植入製程或電漿製程在相對較低能量下執行，以防止損壞通道層192及鐵電層190且提升中和效率。舉例而言，離子植入製程在約10千電子伏特至50千電子伏特的能量下以約1原子/平方公分至1000原子/平方公分的劑量執行。舉例而言，電漿製程在電漿腔室中以約10 sccm至約1000 sccm的氣體（例如，N2 、NH3 、CF4 或CFH3 ）流動速率、15瓦特至500瓦特的功率以及約1托至約760托的壓力在小於250℃至400℃的溫度下執行約1秒至約30秒的時段。在其他實施例中，電漿製程在電漿腔室中以約1000 sccm至約10000 sccm的氣體（例如，N2 、NH3 、CF4 或CFH3 ）流動速率、10瓦特至1000瓦特的功率以及約1托至約1000托的壓力在小於500℃的溫度下執行約1秒至約360秒的時段。Therefore, the channel layer 192' and the ferroelectric layer 190' have substances with valences of 5, 7, or a combination thereof. In some embodiments, the ion implantation process or plasma process is performed at relatively low energy to prevent damage to the channel layer 192 and the ferroelectric layer 190 and to improve neutralization efficiency. For example, the ion implantation process is performed at an energy of about 10 keV to 50 keV at a dose of about 1 atom/cm2 to 1000 atoms/cm2. For example, a plasma process in the plasma chamber to about 10 sccm to about 1000 sccm of a gas (e.g., N 2, NH 3, CF 4 , or CFH 3) flow rate of 15 to 500 watts of power and about A pressure of 1 Torr to about 760 Torr is performed at a temperature of less than 250°C to 400°C for a period of about 1 second to about 30 seconds. In other embodiments, the plasma process is performed in the plasma chamber at a gas (eg, N 2 , NH 3 , CF 4 or CFH 3 ) flow rate of about 1000 sccm to about 10,000 sccm, a power of 10 watts to 1000 watts And a pressure of about 1 Torr to about 1000 Torr is performed at a temperature of less than 500° C. for a period of about 1 second to about 360 seconds.

在圖35的動作S210處，對通道層192'及鐵電層190'執行第三回火製程189。在一些實施例中，第三回火製程189包括尖峰回火製程。尖峰回火製程可使用以下製程參數或條件執行：維持在約380℃與約420℃之間的範圍內的峰值回火溫度、介於約1秒與約60秒之間的範圍內的回火時間（或持續時間）（在此期間維持峰值溫度），以及介於約50托與約760托之間的範圍內的回火壓力。並不任意選擇回火製程的上述這些製程參數，而是小心地調節這些製程參數以活化通道層192'及鐵電層190'中的物質。因此，舉例而言，通道層192'的物質濃度可介於約1E17/cm3 至約1E20/cm3 範圍內，且鐵電層190'的物質濃度可介於約1E17/cm3 至約1E20/cm3 範圍內。At act S210 of FIG. 35 , a third tempering process 189 is performed on the channel layer 192 ′ and the ferroelectric layer 190 ′. In some embodiments, the third tempering process 189 includes a peak tempering process. The peak temper process may be performed using the following process parameters or conditions: a peak temper temperature maintained in a range between about 380°C and about 420°C, a temper in a range between about 1 second and about 60 seconds The time (or duration) during which the peak temperature is maintained, and the tempering pressure in the range between about 50 Torr and about 760 Torr. These process parameters of the tempering process are not arbitrarily selected, but are carefully adjusted to activate the species in the channel layer 192' and the ferroelectric layer 190'. Thus, for example, the channel layer 192 'substance concentration may range from about 1E17 / cm 3 to about 1E20 / cm 3, and the ferroelectric layer 190' substance concentration may be between about 1E17 / cm 3 to about 1E20 /cm 3 range.

如圖34C及圖34D中所示出，在一些實施例中，鐵電層190'及通道層192'具有不同濃度的物質（例如，氟、氮或類似物）。舉例而言，鐵電層190'可具有三部分結構，其包括具有厚度T11的底部鐵電部分190B、具有厚度T12的中間鐵電部分190M以及具有厚度T13的頂部鐵電部分190T。底部鐵電部分190B與導線72接觸，且中間鐵電部分190M位於底部鐵電部分190B與頂部鐵電部分190T之間。通道層192'可具有三部分結構，其包括具有厚度T14的底部通道部分192B、具有厚度T15的中間通道部分192M以及具有厚度T16的頂部通道部分192T。底部通道部分192B與導線72接觸，且中間通道部分192M位於底部通道部分192B與頂部通道部分192T之間。通道層192'及鐵電層190'的這些部分具有不同物質濃度及氧濃度。As shown in Figures 34C and 34D, in some embodiments, the ferroelectric layer 190' and the channel layer 192' have different concentrations of species (eg, fluorine, nitrogen, or the like). For example, the ferroelectric layer 190' may have a three-part structure including a bottom ferroelectric portion 190B having a thickness T11, a middle ferroelectric portion 190M having a thickness T12, and a top ferroelectric portion 190T having a thickness T13. Bottom ferroelectric portion 190B is in contact with wire 72, and middle ferroelectric portion 190M is located between bottom ferroelectric portion 190B and top ferroelectric portion 190T. The channel layer 192' may have a three-part structure including a bottom channel portion 192B having a thickness T14, a middle channel portion 192M having a thickness T15, and a top channel portion 192T having a thickness T16. Bottom channel portion 192B is in contact with wire 72, and middle channel portion 192M is located between bottom channel portion 192B and top channel portion 192T. These portions of the channel layer 192' and the ferroelectric layer 190' have different species concentrations and oxygen concentrations.

在圖34D中，繪示物質濃度與通道層192'、鐵電層190'以及導線72的位置的關係圖。y軸表示物質濃度及氧濃度。x軸表示通道層192'、鐵電層190'以及導線72的深度。曲線[022]表示通道層192'的氧濃度，曲線[021]表示鐵電層190'的氧濃度，且曲線[S2]表示物質濃度。In FIG. 34D , the relationship between the species concentration and the position of the channel layer 192 ′, the ferroelectric layer 190 ′ and the wire 72 is shown. The y-axis represents the substance concentration and the oxygen concentration. The x-axis represents the depth of channel layer 192 ′, ferroelectric layer 190 ′, and wire 72 . Curve [022] represents the oxygen concentration of the channel layer 192', curve [021] represents the oxygen concentration of the ferroelectric layer 190', and curve [S2] represents the species concentration.

在一些實施例中，曲線[022]表示通道層192'的中間通道部分192M具有最大氧濃度，且通道層192'的頂部通道部分192T及底部通道部分192B的氧濃度低於通道層192'的中間通道部分192M的氧濃度。In some embodiments, the curve [022] indicates that the middle channel portion 192M of the channel layer 192' has a maximum oxygen concentration, and the top channel portion 192T and the bottom channel portion 192B of the channel layer 192' have a lower oxygen concentration than the channel layer 192' Oxygen concentration in middle channel section 192M.

曲線[021]表示靠近底部鐵電部分190B的中間鐵電部分190M的一部分具有最大氧濃度。鐵電層190'的最大氧濃度高於通道層192'的最大氧濃度。頂部鐵電部分190T的氧濃度低於底部鐵電部分190B及中間鐵電部分190M的氧濃度。Curve [021] indicates that a portion of the middle ferroelectric portion 190M near the bottom ferroelectric portion 190B has a maximum oxygen concentration. The maximum oxygen concentration of the ferroelectric layer 190' is higher than the maximum oxygen concentration of the channel layer 192'. The oxygen concentration of the top ferroelectric portion 190T is lower than that of the bottom ferroelectric portion 190B and the middle ferroelectric portion 190M.

曲線[S2]表示頂部通道部分192T、中間通道部分192M以及底部通道部分192B、頂部鐵電部分190T、中間鐵電部分190M以及底部鐵電部分190B具有物質。通道層192'具有最大物質濃度。通道層192'（例如，氧化物半導體層）中的物質的分佈範圍與氧的分佈範圍的比大於鐵電層190'中的物質的分佈範圍與氧的分佈範圍的比。Curve [S2] indicates that the top channel portion 192T, the middle channel portion 192M, and the bottom channel portion 192B, the top ferroelectric portion 190T, the middle ferroelectric portion 190M, and the bottom ferroelectric portion 190B have substances. The channel layer 192' has a maximum species concentration. The ratio of the distribution range of the species to the oxygen distribution range in the channel layer 192 ′ (eg, oxide semiconductor layer) is greater than the ratio of the distribution range of the species to the oxygen distribution range in the ferroelectric layer 190 ′.

最大物質濃度介於通道層192'的最大氧濃度與鐵電層190'的最大氧濃度之間。底部通道部分192B具有最大物質濃度。物質濃度自通道層192'的頂部通道部分192T至底部通道部分192B增加。物質濃度自通道層192'的底部通道部分192B至鐵電層190'的底部鐵電部分190B減少。底部通道部分192B與頂部鐵電部分190T之間的界面IF4的物質濃度高於底部鐵電部分190B與導線72之間的界面IF3的物質濃度。The maximum species concentration is between the maximum oxygen concentration of the channel layer 192' and the maximum oxygen concentration of the ferroelectric layer 190'. Bottom channel portion 192B has a maximum species concentration. The species concentration increases from the top channel portion 192T to the bottom channel portion 192B of the channel layer 192'. The species concentration decreases from the bottom channel portion 192B of the channel layer 192' to the bottom ferroelectric portion 190B of the ferroelectric layer 190'. The species concentration of the interface IF4 between the bottom channel portion 192B and the top ferroelectric portion 190T is higher than the species concentration of the interface IF3 between the bottom ferroelectric portion 190B and the wire 72 .

底部通道部分192B與頂部鐵電部分190T之間的界面IF4的物質濃度高於其氧濃度。底部通道部分192B的物質濃度高於其氧濃度。頂部鐵電部分190T的物質濃度高於其氧濃度。The interface IF4 between the bottom channel portion 192B and the top ferroelectric portion 190T has a species concentration higher than its oxygen concentration. The bottom channel portion 192B has a species concentration higher than its oxygen concentration. The species concentration of the top ferroelectric portion 190T is higher than its oxygen concentration.

在通道層192'形成之後，根據前述方法圖案化通道層192'且執行後續製程，以便形成如圖36中所繪示的包括多個記憶胞202'的記憶陣列200'。After the channel layer 192' is formed, the channel layer 192' is patterned according to the aforementioned methods and subsequent processes are performed to form a memory array 200' including a plurality of memory cells 202' as shown in FIG. 36 .

圖36示出根據一些實施例的鐵電記憶元件的簡化透視圖。記憶陣列200'與記憶陣列200類似，且記憶胞202'與圖1A的記憶胞202類似，但氧化物半導體層192'比通道層92（例如，氧化物半導體層）具有更寬的物質的分佈範圍。36 shows a simplified perspective view of a ferroelectric memory element in accordance with some embodiments. Memory array 200' is similar to memory array 200, and memory cell 202' is similar to memory cell 202 of FIG. 1A, but oxide semiconductor layer 192' has a wider distribution of species than channel layer 92 (eg, oxide semiconductor layer) Scope.

圖37示出根據一些實施例的形成鐵電記憶元件的方法。雖然方法經示出及/或描述為一系列動作或事件，但應瞭解，方法不限於所示出的次序或動作。因此，在一些實施例中，所述動作可以與所示出的不同的次序進行且/或可同時進行。此外，在一些實施例中，所示出的動作或事件可細分為多個動作或事件，其可在不同時間進行或與其他動作或子動作同時進行。在一些實施例中，可省略一些所示出的動作或事件，且可包括其他未示出的動作或事件。37 illustrates a method of forming a ferroelectric memory element in accordance with some embodiments. Although the methodology is shown and/or described as a series of acts or events, it should be understood that the methodology is not limited to the order or acts shown. Thus, in some embodiments, the actions may be performed in a different order than shown and/or may be performed concurrently. Furthermore, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at different times or concurrently with other actions or sub-actions. In some embodiments, some actions or events shown may be omitted, and other actions or events not shown may be included.

在動作S300處，形成延伸穿過導線的溝渠。圖16A至圖16B示出對應於動作S300的一些實施例的不同視圖。At act S300, trenches are formed extending through the wires. 16A-16B illustrate different views corresponding to some embodiments of act S300.

在動作S302處，沿著溝渠的側壁及底部表面沈積鐵電層。圖17A至圖17B以及圖32A及圖32B示出對應於動作S302的一些實施例的不同視圖。At act S302, a ferroelectric layer is deposited along sidewalls and bottom surfaces of the trenches. Figures 17A-17B and Figures 32A and 32B illustrate different views corresponding to some embodiments of act S302.

在動作S304處，在鐵電層上方沈積氧化物半導體層。氧化物半導體層沿著溝渠的側壁及底部表面延伸。圖20A至圖20B以及圖32A及圖32B示出對應於動作S304的一些實施例的不同視圖。At act S304, an oxide semiconductor layer is deposited over the ferroelectric layer. The oxide semiconductor layer extends along the sidewall and bottom surface of the trench. Figures 20A-20B and Figures 32A and 32B illustrate different views corresponding to some embodiments of act S304.

在動作S306處，執行處理以將價數為5、價數為7或其組合的物質引入於鐵電層中。圖18A、圖18B、圖33A以及圖33B示出對應於動作S306的一些實施例的不同視圖。處理製程為例如離子植入製程、電漿製程或其組合。在一些實施例中，在鐵電層與氧化物半導體層沈積之間執行處理。在替代實施例中，在氧化物半導體層沈積之後執行處理。At act S306, a process is performed to introduce a species with a valence of 5, a valence of 7, or a combination thereof into the ferroelectric layer. 18A, 18B, 33A, and 33B illustrate different views corresponding to some embodiments of act S306. The processing process is, for example, an ion implantation process, a plasma process, or a combination thereof. In some embodiments, processing is performed between the deposition of the ferroelectric layer and the oxide semiconductor layer. In an alternative embodiment, the processing is performed after the deposition of the oxide semiconductor layer.

在動作S308處，在處理執行之後執行回火製程。圖19A、圖19B、圖34A以及圖34B示出對應於動作S308的一些實施例的不同視圖。At act S308, a tempering process is performed after the processing is performed. 19A, 19B, 34A, and 34B illustrate different views corresponding to some embodiments of act S308.

雖然圖1A至圖30B以及圖32A至圖36的實施例示出階梯結構在溝渠86形成之前形成，但其他時機亦為可能的。舉例而言，階梯結構在導電柱106及導電柱108形成之後且在IMD 74形成之前形成。Although the embodiments of FIGS. 1A-30B and 32A-36 show that the stepped structures are formed before trenches 86 are formed, other timings are possible. For example, the stepped structure is formed after conductive pillars 106 and 108 are formed and before IMD 74 is formed.

各種實施例提供具有垂直堆疊的記憶胞的3D記憶陣列。記憶胞各自包括具有FE閘極介電材料及氧化物半導體通道區的TFT。在一些實施例中，鐵電層90'/190'及/或氧化物半導體層92/192'可含有價數為5、價數為7或其組合的物質。舉例而言，價數為5的物質是氮，且價數為7的物質是氟。包括物質可允許鐵電層90'消除或阻止鐵電層90'/190'與通道層92/192'之間的界面IF2中的陷阱或缺陷，且/或佔據界面IF2、鐵電層90'/190'以及通道層92/192'中的氧空缺且充當鈍化物以抑制氧、氫以及空缺的相互擴散，使得可改良鐵電層90'/190'的固有疲勞效能及耐久性。相應地，各種實施例提升所得元件的可靠度及製造簡易性。Various embodiments provide 3D memory arrays with vertically stacked memory cells. The memory cells each include a TFT having an FE gate dielectric material and an oxide semiconductor channel region. In some embodiments, the ferroelectric layer 90'/190' and/or the oxide semiconductor layer 92/192' may contain species having a valence of 5, a valence of 7, or a combination thereof. For example, a species with a valence of 5 is nitrogen, and a species with a valence of 7 is fluorine. Inclusion of a substance may allow ferroelectric layer 90' to eliminate or prevent traps or defects in interface IF2 between ferroelectric layer 90'/190' and channel layer 92/192' and/or occupy interface IF2, ferroelectric layer 90' Oxygen vacancies in the /190' and channel layers 92/192' and act as passivators to inhibit the interdiffusion of oxygen, hydrogen and vacancies so that the inherent fatigue performance and durability of the ferroelectric layers 90'/190' can be improved. Accordingly, various embodiments improve the reliability and ease of manufacture of the resulting device.

根據本揭露的一些實施例，一種記憶胞包括半導體基底上方的電晶體，所述電晶體包括：鐵電層，沿著字元線的側壁配置，所述鐵電層包括價數為5、價數為7或其組合的物質；以及氧化物半導體層，電耦接至源極線及位元線，其中所述FE層安置在氧化物半導體層與字元線之間。According to some embodiments of the present disclosure, a memory cell includes a transistor above a semiconductor substrate, the transistor includes: a ferroelectric layer disposed along a sidewall of a word line, the ferroelectric layer includes a valence of 5 and a valence of 5. a substance having the number 7 or a combination thereof; and an oxide semiconductor layer electrically coupled to the source line and the bit line, wherein the FE layer is disposed between the oxide semiconductor layer and the word line.

根據本揭露的替代實施例，一種元件包括：半導體基底；第一記憶胞，位於半導體基底上方，所述第一記憶胞包括第一電晶體，其中所述第一電晶體包括：鐵電層的第一部分，所述鐵電層的第一部分位於第一字元線的側壁上，且所述鐵電層包括價數為5、價數為7或其組合的物質；以及第一通道區，位於鐵電層的側壁上，所述第一通道區包括氧化物半導體層，其中第一通道區與鐵電層的第一部分之間的第一界面具有價數為5、價數為7或其組合的物質；以及，第二記憶胞，位於第一記憶胞上方。According to an alternative embodiment of the present disclosure, an element includes: a semiconductor substrate; a first memory cell overlying the semiconductor substrate, the first memory cell including a first transistor, wherein the first transistor includes: a ferroelectric layer of a first part, the first part of the ferroelectric layer is located on the sidewall of the first word line, and the ferroelectric layer includes a valence of 5, a valence of 7 or a combination of substances; and a first channel region, located in On the sidewall of the ferroelectric layer, the first channel region includes an oxide semiconductor layer, wherein the first interface between the first channel region and the first portion of the ferroelectric layer has a valence of 5, a valence of 7, or a combination thereof and, a second memory cell located above the first memory cell.

根據本揭露的另外替代實施例，一種方法包括：形成延伸穿過導線的溝渠；沿著溝渠的側壁及底部表面沈積鐵電層；在鐵電層上方沈積氧化物半導體層，所述氧化物半導體層沿著溝渠的側壁及底部表面延伸；以及執行處理以將價數為5、價數為7或其組合的物質引入於鐵電層中。According to a further alternative embodiment of the present disclosure, a method includes: forming a trench extending through a wire; depositing a ferroelectric layer along sidewalls and bottom surfaces of the trench; depositing an oxide semiconductor layer over the ferroelectric layer, the oxide semiconductor A layer extends along the sidewall and bottom surface of the trench; and processing is performed to introduce a valence 5, a valence 7, or a combination thereof into the ferroelectric layer.

前述內容概述若干實施例的特徵，使得本領域的技術人員可更好地理解本揭露的態樣。本領域的技術人員應理解，其可易於使用本揭露做為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他方法及結構的基礎。本領域的技術人員亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且本領域的技術人員可在不脫離本揭露的精神及範疇的情況下在本文中作出各種改變、替代以及更改。The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other methods and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art can make various changes herein without departing from the spirit and scope of the present disclosure , substitutions, and changes.

30:虛線 50:基底 52、52A~52E、324:介電層 53、53A~53D:犧牲層 56、118:光阻 58:多層堆疊 60、62、64、66、R1、R2:區 61、120:開口 70、74:金屬間介電質 71、75:阻障層 72、72A~72D、116A、116B、116C:導線 73:金屬層 80:硬罩幕圖案 82:光阻圖案 86、100、104:溝渠 88、188:處理 89:第二回火製程 90、90'、190、190':鐵電層 90A:經處理的鐵電部分 90B、190B:底部鐵電部分 90M、190M:中間鐵電部分 90T、190T:頂部鐵電部分 92、192、192':通道層 92B、192B:底部通道部分 92M、192M:中間通道部分 92T、192T:頂部通道部分 98、98A、98B:介電材料 102:隔離柱 106、108:導電柱 110、112、114:導電接觸窗 189:第三回火製程 200、200':記憶陣列 200A:鐵電記憶體 202、202':記憶胞 206:箭頭 302:閘介電層 304:閘電極 306:源極/汲極區 308:閘極間隔件 310、312:ILD 314:源極/汲極接觸窗 316:閘極接觸窗 320:內連線結構 322:導電特徵 B-B'、C-C'、D-D'、E-E':線 IF1、IF2、IF3、IF4:界面 S100、S102、S104、S106、S108、S110、S200、S202、S204、S206、S208、S210、S300、S302、S304、S306、S308:動作 T1、T2、T3、T4、T5、T6、T11、T12、T13、T14、T15、T16:厚度 [011]、[012]、[021]、[022]、[S1]、[S2]:曲線30: Dotted line 50: base 52, 52A~52E, 324: Dielectric layer 53, 53A~53D: sacrificial layer 56, 118: photoresist 58: Multilayer Stacking 60, 62, 64, 66, R1, R2: District 61, 120: Opening 70, 74: Intermetal dielectric 71, 75: Barrier layer 72, 72A~72D, 116A, 116B, 116C: Wire 73: Metal layer 80: Hard mask pattern 82: Photoresist Pattern 86, 100, 104: Ditch 88, 188: Processing 89: Second tempering process 90, 90', 190, 190': Ferroelectric layer 90A: Treated ferroelectric part 90B, 190B: Bottom ferroelectric part 90M, 190M: Middle ferroelectric part 90T, 190T: top ferroelectric part 92, 192, 192': channel layer 92B, 192B: Bottom channel section 92M, 192M: middle channel part 92T, 192T: Top channel section 98, 98A, 98B: Dielectric materials 102: Isolation column 106, 108: Conductive column 110, 112, 114: Conductive contact windows 189: The third tempering process 200, 200': memory array 200A: Ferroelectric memory 202, 202': memory cells 206: Arrow 302: Gate Dielectric Layer 304: Gate electrode 306: source/drain region 308: Gate spacer 310, 312: ILD 314: source/drain contact window 316: gate contact window 320: Interconnect structure 322: Conductive Features B-B', C-C', D-D', E-E': line IF1, IF2, IF3, IF4: Interface S100, S102, S104, S106, S108, S110, S200, S202, S204, S206, S208, S210, S300, S302, S304, S306, S308: Actions T1, T2, T3, T4, T5, T6, T11, T12, T13, T14, T15, T16: Thickness [011], [012], [021], [022], [S1], [S2]: Curves

當結合隨附圖式閱讀時，根據以下詳細描述最佳地理解本揭露的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，出於論述清楚起見，可任意地增加或減小各種特徵之尺寸。 圖1A、圖1B以及圖1C示出根據一些實施例的鐵電記憶元件的簡化透視圖、電路圖以及自上而下視圖。 圖2、圖3、圖4、圖5、圖6、圖7、圖8、圖9、圖10、圖11、圖12、圖13、圖14、圖15A、圖15B、圖16A、圖16B、圖17A、圖17B、圖18A、圖18B、圖18C、圖18D、圖19A、圖19B、圖20A、圖20B、圖20C、圖22、圖23、圖24、圖25A、圖25B、圖26A、圖26B、圖27A、圖27B、圖28A、圖28B、圖29A、圖29B、圖30A、圖30B、圖30C、圖30D以及圖30E示出根據一些實施例的製造鐵電記憶元件的各種視圖。 圖20D示出根據一些實施例的物質濃度及氧濃度與通道層、鐵電層以及導線的深度的圖表。 圖21示出根據一些實施例的形成鐵電記憶元件的鐵電層及通道層的方法。 圖31示出根據替代實施例的鐵電記憶元件的簡化透視圖。 圖32A、圖32B、圖33A、圖33B、圖34A、圖34B、圖34C以及圖36示出根據另外替代實施例的製造鐵電記憶元件中的中間階段的各種視圖。 圖34D示出根據一些實施例的物質濃度及氧濃度與通道層、鐵電層以及導線的深度的關係圖。 圖35示出根據一些實施例的形成鐵電記憶元件的鐵電層及通道層的方法。 圖37示出根據一些實施例的形成鐵電記憶元件的方法。Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. 1A, 1B, and 1C show simplified perspective, circuit, and top-down views of a ferroelectric memory element in accordance with some embodiments. Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, Figure 14, Figure 15A, Figure 15B, Figure 16A, Figure 16B , Figure 17A, Figure 17B, Figure 18A, Figure 18B, Figure 18C, Figure 18D, Figure 19A, Figure 19B, Figure 20A, Figure 20B, Figure 20C, Figure 22, Figure 23, Figure 24, Figure 25A, Figure 25B, Figure 2 26A, 26B, 27A, 27B, 28A, 28B, 29A, 29B, 30A, 30B, 30C, 30D, and 30E illustrate the fabrication of ferroelectric memory elements according to some embodiments. Various views. 20D shows a graph of species concentration and oxygen concentration versus depth of channel layers, ferroelectric layers, and wires, according to some embodiments. 21 illustrates a method of forming a ferroelectric layer and a channel layer of a ferroelectric memory element in accordance with some embodiments. 31 shows a simplified perspective view of a ferroelectric memory element according to an alternative embodiment. 32A, 32B, 33A, 33B, 34A, 34B, 34C, and 36 show various views of intermediate stages in the fabrication of ferroelectric memory elements according to further alternative embodiments. 34D shows a graph of species concentration and oxygen concentration versus depth of channel layers, ferroelectric layers, and wires, according to some embodiments. 35 illustrates a method of forming a ferroelectric layer and a channel layer of a ferroelectric memory element in accordance with some embodiments. 37 illustrates a method of forming a ferroelectric memory element in accordance with some embodiments.

S200、S202、S204、S206、S208、s210:動作S200, S202, S204, S206, S208, s210: Actions

Claims (20)

一種記憶胞，包括： 電晶體，位於半導體基底上方，所述電晶體包括： 鐵電層，沿著字元線的側壁配置，所述鐵電層包括價數為5、價數為7或其組合的物質；以及 氧化物半導體層，電耦接至源極線及位元線，其中所述鐵電層安置在所述氧化物半導體層與所述字元線之間。A memory cell comprising: A transistor located over a semiconductor substrate, the transistor comprising: a ferroelectric layer disposed along the sidewalls of the word lines, the ferroelectric layer comprising a substance having a valence of 5, a valence of 7, or a combination thereof; and an oxide semiconductor layer electrically coupled to the source line and the bit line, wherein the ferroelectric layer is disposed between the oxide semiconductor layer and the word line. 如請求項1所述的記憶胞，其中價數為5的所述物質是氮，且價數為7的所述物質是氟。The memory cell of claim 1, wherein the substance having a valence of 5 is nitrogen, and the substance having a valence of 7 is fluorine. 如請求項1所述的記憶胞，其中所述鐵電層與所述氧化物半導體層接觸。The memory cell of claim 1, wherein the ferroelectric layer is in contact with the oxide semiconductor layer. 如請求項1所述的記憶胞，其中所述鐵電層與所述氧化物半導體層之間的第一界面具有第一物質濃度，所述第一物質濃度高於所述鐵電層與所述字元線之間的第二界面的第二物質濃度。The memory cell of claim 1, wherein the first interface between the ferroelectric layer and the oxide semiconductor layer has a first substance concentration higher than that between the ferroelectric layer and the oxide semiconductor layer. and the concentration of the second substance at the second interface between the word lines. 如請求項4所述的記憶胞，其中所述鐵電層在所述第一界面與所述第二界面之間具有最大物質濃度。The memory cell of claim 4, wherein the ferroelectric layer has a maximum species concentration between the first interface and the second interface. 如請求項4所述的記憶胞，其中所述氧化物半導體層的靠近所述第一界面的一部分具有物質濃度。The memory cell according to claim 4, wherein a portion of the oxide semiconductor layer close to the first interface has a substance concentration. 一種記憶元件，包括： 半導體基底； 第一記憶胞，位於所述半導體基底上方，所述第一記憶胞包括第一電晶體，其中所述第一電晶體包括： 鐵電層的第一部分，所述鐵電層的所述第一部分位於第一字元線的側壁上，且所述鐵電層包括價數為5、價數為7或其組合的物質；以及 第一通道區，位於所述鐵電層的側壁上，所述第一通道區包括氧化物半導體層，其中所述第一通道區與所述鐵電層的所述第一部分之間的第一界面具有價數為5、價數為7或其組合的物質，以及 第二記憶胞，位於所述第一記憶胞上方。A memory element comprising: semiconductor substrate; a first memory cell, located above the semiconductor substrate, the first memory cell includes a first transistor, wherein the first transistor includes: a first portion of a ferroelectric layer located on a sidewall of a first word line, and the ferroelectric layer includes a 5 valence, 7 valence, or a combination thereof; and a first channel region on the sidewall of the ferroelectric layer, the first channel region comprising an oxide semiconductor layer, wherein a first channel region between the first channel region and the first portion of the ferroelectric layer the interface has a species with a valence of 5, a valence of 7, or a combination thereof, and The second memory cell is located above the first memory cell. 如請求項7所述的記憶元件，其中所述第一界面的物質濃度高於其氧濃度。The memory element of claim 7, wherein the first interface has a species concentration higher than its oxygen concentration. 如請求項7所述的記憶元件，其中所述鐵電層持續延伸超過所述第一字元線且超過第二字元線，所述第二字元線藉由介電層與所述第一字元線垂直分隔開。The memory device of claim 7, wherein the ferroelectric layer continues to extend beyond the first word line and beyond the second word line, the second word line being connected to the first word line through a dielectric layer A character line is separated vertically. 如請求項7所述的記憶元件，更包括： 第三記憶胞，包括： 所述鐵電層的第三部分，位於所述第一字元線的第二側壁上，所述第二側壁與所述第一字元線的所述側壁相對；以及 第二通道區，藉由所述鐵電層的所述第三部分與所述第一字元線的所述第二側壁分隔開。The memory element as claimed in claim 7, further comprising: Third memory cells, including: a third portion of the ferroelectric layer on a second side wall of the first word line, the second side wall being opposite the side wall of the first word line; and A second channel region is separated from the second sidewall of the first word line by the third portion of the ferroelectric layer. 如請求項7所述的記憶元件，其中所述物質還佔據所述鐵電層、所述氧化物半導體層或其組合中的氧空缺。The memory element of claim 7, wherein the species also occupies oxygen vacancies in the ferroelectric layer, the oxide semiconductor layer, or a combination thereof. 如請求項7所述的記憶元件，其中所述鐵電層中的所述物質的分佈範圍與氧的分佈範圍的比大於所述氧化物半導體層中的所述物質的分佈範圍與氧的分佈範圍的比。The memory element according to claim 7, wherein the ratio of the distribution range of the substance to the distribution range of oxygen in the ferroelectric layer is larger than the distribution range of the substance and the distribution of oxygen in the oxide semiconductor layer range ratio. 如請求項7所述的記憶元件，其中所述氧化物半導體層中的所述物質的分佈範圍與氧的分佈範圍的比大於所述鐵電層中的所述物質的分佈範圍與氧的分佈範圍的比。The memory element according to claim 7, wherein the ratio of the distribution range of the substance to the distribution range of oxygen in the oxide semiconductor layer is larger than the distribution range of the substance and the distribution of oxygen in the ferroelectric layer range ratio. 如請求項7所述的記憶元件，其中所述第二記憶胞包括第二電晶體，所述第二電晶體包括： 所述鐵電層的第二部分，所述鐵電層的所述第二部分經由所述第一字元線電耦接至第二字元線，且所述第二字元線及所述第一字元線藉由介電層分隔開；以及 第二通道區。The memory element of claim 7, wherein the second memory cell comprises a second transistor comprising: a second portion of the ferroelectric layer that is electrically coupled to a second word line through the first word line, and the second word line and the the first word lines are separated by a dielectric layer; and Second channel area. 一種記憶元件的製造方法，包括： 形成延伸穿過導線的溝渠； 沿著所述溝渠的側壁及底部表面沈積鐵電層； 在所述鐵電層上方沈積氧化物半導體層，所述氧化物半導體層沿著所述溝渠的所述側壁及所述底部表面延伸；以及 執行處理以將價數為5、價數為7或其組合的物質引入於所述鐵電層中。A manufacturing method of a memory element, comprising: forming trenches extending through the wires; depositing a ferroelectric layer along sidewalls and bottom surfaces of the trench; depositing an oxide semiconductor layer over the ferroelectric layer, the oxide semiconductor layer extending along the sidewalls and the bottom surface of the trench; and The treatment is performed to introduce into the ferroelectric layer a species having a valence of 5, a valence of 7, or a combination thereof. 如請求項15所述的記憶元件的製造方法，其中價數為5的所述物質是氮，且價數為7的所述物質是氧。The method for manufacturing a memory element according to claim 15, wherein the substance having a valence of 5 is nitrogen, and the substance having a valence of 7 is oxygen. 如請求項15所述的記憶元件的製造方法，其中所述處理製程包括離子植入製程、電漿製程或其組合。The method for manufacturing a memory device as claimed in claim 15, wherein the processing process includes an ion implantation process, a plasma process or a combination thereof. 如請求項15所述的記憶元件的製造方法，其中所述處理在沈積所述鐵電層與沈積所述氧化物半導體層之間執行。The method of manufacturing a memory element according to claim 15, wherein the processing is performed between depositing the ferroelectric layer and depositing the oxide semiconductor layer. 如請求項15所述的記憶元件的製造方法，其中所述處理在沈積所述氧化物半導體層之後執行。The method of manufacturing a memory element according to claim 15, wherein the processing is performed after depositing the oxide semiconductor layer. 如請求項15所述的記憶元件的製造方法，更包括在執行所述處理之後執行回火製程。The method for manufacturing a memory element as claimed in claim 15, further comprising performing a tempering process after performing the processing.
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