TW202144905A

TW202144905A - Vernier mark for semiconductor manufacturing process and lithographic process inspection method using the same

Info

Publication number: TW202144905A
Application number: TW109116487A
Authority: TW
Inventors: 陳熙之; 李世平
Original assignee: 力晶積成電子製造股份有限公司
Priority date: 2020-05-19
Filing date: 2020-05-19
Publication date: 2021-12-01
Also published as: TWI743792B

Abstract

A vernier mark for semiconductor manufacturing process includes at least one vernier structure and a plurality of identification symbols formed on or in a semiconductor substrate. The vernier structure includes a plurality of first linear layers extending in X direction and a plurality of second linear layers extending in Y direction, and the first linear layers are intersected with the second linear layers. The length of the center line in the first linear layers is greater than the length of the remaining first linear layers, and the length of the center line in the second linear layer is greater than the length of the remaining second linear layers. The identification symbols are formed on at least one end of each first linear layers and at least one end of each second linear layers to distinguish different first linear layers and different second linear layers in the vernier structure.

Description

半導體製程用游標尺及使用其進行的微影製程檢測方法Vernier ruler for semiconductor process and lithography process inspection method using the same

本發明是有關於一種微影製程檢測技術，且特別是有關於一種半導體製程用游標尺及使用其進行的微影製程檢測方法。The present invention relates to a lithography process inspection technology, and more particularly, to a vernier for semiconductor process and a lithography process inspection method using the same.

隨著半導體製程技術的快速發展，為了增進元件的速度與效能，整個電路元件的尺寸必須不斷縮小，且元件的積集度也必須持續不斷地提升。一般來說，在半導體均趨向縮小電路元件的設計發展下，微影製程在整個製程中佔有舉足輕重的地位。With the rapid development of semiconductor process technology, in order to improve the speed and performance of the device, the size of the entire circuit device must be continuously reduced, and the integration of the device must also be continuously improved. Generally speaking, as semiconductors tend to shrink circuit components, the lithography process plays an important role in the entire process.

為了確保產品良率，會在微影製程中加入至少三個檢測站點，使用不同儀器與人工進行各種檢測，例如使用光學顯微鏡（OM）進行X方向與Y方向的重疊檢測（Overlap Check）、使用掃描式電子顯微鏡儀器（SEM tool）檢查臨界尺寸（CD）以及針對晶片進行目檢（Visual Check）。In order to ensure the product yield, at least three inspection stations will be added to the lithography process, and various inspections will be performed using different instruments and manual labor, such as the use of optical microscopes (OM) for X-direction and Y-direction overlap inspection (Overlap Check), The critical dimension (CD) was checked using a scanning electron microscope (SEM tool) and the wafer was visually inspected (Visual Check).

然而，隨著半導體元件發展到數十奈米以下製程，作為微影製程檢測用的既有對準標記已經與真實元件尺寸相差數百或數千倍，導致無法準確檢測出重疊（OL）偏移量之類的數值，而影響產品良率。此外，隨著半導體元件尺寸縮小，也會使CD檢測時間大幅增加，而影響採樣率（Sampling rate）。However, with the development of semiconductor components to processes below tens of nanometers, the existing alignment marks used for lithography process detection have been hundreds or thousands of times different from the real component size, resulting in the inability to accurately detect the overlap (OL) offset. Shifts and other values affect the product yield. In addition, as the size of semiconductor components shrinks, the CD detection time will also increase significantly, which will affect the sampling rate (Sampling rate).

本發明提供一種半導體製程用游標尺，能配合半導體元件小型化的發展，改進微影製程檢測的精確度。The invention provides a vernier for semiconductor manufacturing process, which can cooperate with the development of miniaturization of semiconductor components and improve the detection accuracy of lithography manufacturing process.

本發明另提供一種微影製程檢測方法，可同時檢測出OL偏移量與CD，並藉此縮短檢測時間，進而增加採樣率。The present invention further provides a lithography process detection method, which can simultaneously detect the OL offset and the CD, thereby shortening the detection time and increasing the sampling rate.

本發明的一種半導體製程用游標尺，包括形成於半導體基板上或半導體基板內的至少一游標尺結構與多個識別符號。所述游標尺結構包括在X方向延伸的數條第一線型層與在Y方向延伸的數條第二線型層，第一線型層與第二線型層交叉設置。第一線型層中的中線長度大於其餘第一線型層的長度，且第二線型層中的中線長度大於其餘第二線型層的長度。識別符號則形成於每條第一線型層的至少一端與每條第二線型層的至少一端，以區別游標尺結構中的不同條第一線型層與不同條第二線型層。A vernier scale for a semiconductor process of the present invention includes at least one vernier scale structure and a plurality of identification symbols formed on or in the semiconductor substrate. The vernier structure includes several first linear layers extending in the X direction and several second linear layers extending in the Y direction, and the first linear layers and the second linear layers are arranged to intersect. The length of the center line in the first line type layer is greater than the length of the remaining first line type layers, and the length of the center line in the second line type layer is greater than the length of the remaining second line type layers. Identification symbols are formed on at least one end of each first line type layer and at least one end of each second line type layer to distinguish different first line type layers and different second line type layers in the vernier structure.

在本發明的一實施例中，上述游標尺結構形成於半導體基板內，且所述第一線型層與所述第二線型層為淺溝渠隔離結構。In an embodiment of the present invention, the vernier structure is formed in a semiconductor substrate, and the first linear layer and the second linear layer are shallow trench isolation structures.

在本發明的一實施例中，上述游標尺結構形成於半導體基板上，且所述第一線型層與所述第二線型層為多晶矽線。In an embodiment of the present invention, the vernier structure is formed on a semiconductor substrate, and the first line type layer and the second line type layer are polysilicon lines.

在本發明的一實施例中，上述識別符號包括***數字或羅馬數字。In an embodiment of the present invention, the above-mentioned identification symbols include Arabic numerals or Roman numerals.

在本發明的一實施例中，上述識別符號的形狀包括長方形、正方形、菱形、圓形、三角形、多邊形、十字形或星形。In an embodiment of the present invention, the shape of the identification symbol includes a rectangle, a square, a diamond, a circle, a triangle, a polygon, a cross or a star.

在本發明的一實施例中，每條第一線型層的線寬及第一線型層之間的間距相同，且每條第二線型層的線寬及第二線型層之間的間距相同。In an embodiment of the present invention, the line width of each first line type layer and the spacing between the first line type layers are the same, and the line width of each second line type layer and the spacing between the second line type layers are the same same.

在本發明的一實施例中，每條第一線型層的線寬與每條第二線型層的線寬相同，且第一線型層之間的間距第二線型層之間的間距相同。In an embodiment of the present invention, the line width of each first line type layer is the same as the line width of each second line type layer, and the distance between the first line type layers and the distance between the second line type layers is the same .

在本發明的一實施例中，上述游標尺結構設置於所述半導體基板的切割道。In an embodiment of the present invention, the vernier structure is disposed on a dicing line of the semiconductor substrate.

在本發明的另一實施例中，上述游標尺結構設置於所述半導體基板的晶片區之焊墊（bonding pad）的正下方。In another embodiment of the present invention, the vernier structure is disposed directly below the bonding pad in the chip area of the semiconductor substrate.

本發明的一種微影製程檢測方法，包括提供如上所述的半導體製程用游標尺，其包括半導體基板、至少一游標尺結構以及數個識別符號。進行一微影製程，以同時在半導體基板上形成至少一元件圖案並在上述游標尺結構上形成一對照圖案，所述對照圖案具有X方向上的第一對邊與Y方向上的第二對邊。取得所述第一對邊在X方向上到游標尺結構的兩邊的第一最短距離X1以及X2，同時取得所述第二對邊在Y方向上到游標尺結構的另兩邊的第二最短距離Y1以及Y2。以第一最短距離X1與X2的差值（X1-X2）以及第二最短距離Y1與Y2的差值（Y1-Y2）作為重疊（Overlap，OL）偏移值（shift value），判定是否超出OL偏移容許量。根據游標尺結構在X方向的長度X_V 減掉所述第一最短距離X1與X2的總和（= X_V -(X1+X2)），取得對照圖案在X方向的臨界尺寸（CD）偏移值，以判定是否超出X方向的CD偏移容許量。根據游標尺結構在Y方向的長度Y_V 減掉所述第二最短距離Y1與Y2的總和（= Y_V - (Y1+Y2) ），取得對照圖案在Y方向的臨界尺寸（CD）偏移值，以判定是否超出Y方向的CD偏移容許量。A lithography process detection method of the present invention includes providing the above-mentioned vernier for semiconductor process, which includes a semiconductor substrate, at least one vernier structure and several identification symbols. A lithography process is performed to simultaneously form at least one element pattern on the semiconductor substrate and form a contrast pattern on the vernier structure, the contrast pattern has a first pair of sides in the X direction and a second pair in the Y direction side. Obtain the first shortest distance X1 and X2 from the first pair of sides to the two sides of the vernier structure in the X direction, and simultaneously obtain the second shortest distance from the second pair of sides to the other two sides of the vernier structure in the Y direction Y1 and Y2. Take the difference (X1-X2) between the first shortest distance X1 and X2 and the difference (Y1-Y2) between the second shortest distance Y1 and Y2 as the overlap (Overlap, OL) offset value (shift value) to determine whether it exceeds the OL offset tolerance. _{According to the length X V of the} vernier structure in the X direction minus the sum of the first shortest distances X1 and X2 (= X _V -(X1+X2)), the critical dimension (CD) offset of the control pattern in the X direction is obtained. value to determine whether the allowable amount of CD shift in the X direction is exceeded. The critical dimension (CD) offset of the contrast pattern in the Y direction is obtained by subtracting the sum of the second shortest distances Y1 and Y2 from _{the length Y V of the} vernier structure in the Y direction _{(= Y V - (Y1+Y2) )} value to determine whether the CD shift tolerance in the Y direction is exceeded.

在本發明的另一實施例中，若是超出上述OL偏移容許量，還可包括執行重疊檢測（Overlap Check）或執行重工（rework）。In another embodiment of the present invention, if the above-mentioned OL offset tolerance is exceeded, it may further include performing an overlap check (Overlap Check) or performing a rework (rework).

在本發明的另一實施例中，若是超出上述X方向的CD偏移容許量，還可包括執行SEM檢測（SEM Check）或執行重工。In another embodiment of the present invention, if the above-mentioned allowable amount of CD offset in the X direction is exceeded, it may further include performing SEM Check or performing rework.

在本發明的另一實施例中，若是超出上述Y方向的CD偏移容許量，還可包括執行SEM檢測或執行重工。In another embodiment of the present invention, if the above-mentioned CD offset tolerance in the Y direction is exceeded, SEM inspection or rework may also be performed.

在本發明的另一實施例中，取得上述第一最短距離X1與X2以及取得上述第二最短距離Y1與Y2的方法包括：使用光學顯微鏡（OM）觀測第一和第二對邊相對於游標尺結構的位置，以根據上述識別符號判定第一最短距離X1與X2以及第二最短距離Y1與Y2。In another embodiment of the present invention, the methods for obtaining the first shortest distances X1 and X2 and obtaining the second shortest distances Y1 and Y2 include: using an optical microscope (OM) to observe the first and second opposite sides relative to a cursor The position of the ruler structure is used to determine the first shortest distances X1 and X2 and the second shortest distances Y1 and Y2 according to the above identification symbols.

在本發明的另一實施例中，取得上述第一最短距離X1與X2以及取得上述第二最短距離Y1與Y2的方法包括：利用掃描式電子顯微鏡（SEM）進行拍攝得到影像，並觀測所述影像，以取得第一和第二對邊相對於游標尺結構的位置，並根據上述識別符號判定第一最短距離X1與X2以及第二最短距離Y1與Y2。In another embodiment of the present invention, the methods for obtaining the first shortest distances X1 and X2 and obtaining the second shortest distances Y1 and Y2 include: capturing images with a scanning electron microscope (SEM), and observing the image to obtain the positions of the first and second opposite sides relative to the vernier structure, and determine the first shortest distances X1 and X2 and the second shortest distances Y1 and Y2 according to the above identification symbols.

在本發明的另一實施例中，取得上述第一最短距離X1與X2以及取得上述第二最短距離Y1與Y2以及判定是否超出OL偏移容許量的方法包括：使用SEM儀器（SEM tool）取得上述第一最短距離X1與X2以及上述第二最短距離Y1與Y2，並將上述檢測的結果回饋給進行上述微影製程的機台。In another embodiment of the present invention, the methods for obtaining the first shortest distances X1 and X2, obtaining the second shortest distances Y1 and Y2, and determining whether the OL offset tolerance is exceeded include: using a SEM tool to obtain The above-mentioned first shortest distances X1 and X2 and the above-mentioned second shortest distances Y1 and Y2 are fed back to the machine for performing the above-mentioned lithography process.

在本發明的另一實施例中，上述微影製程的機台收到所述檢測的結果後，還可包括調整所述微影製程。In another embodiment of the present invention, after receiving the detection result, the machine of the lithography process may further include adjusting the lithography process.

在本發明的另一實施例中，上述微影製程包括用於蝕刻的微影製程或用於植入的微影製程。In another embodiment of the present invention, the above-mentioned lithography process includes a lithography process for etching or a lithography process for implantation.

在本發明的另一實施例中，上述對照圖案包括圖案化光阻、圖案化介電層或圖案化金屬層。In another embodiment of the present invention, the above-mentioned control pattern includes a patterned photoresist, a patterned dielectric layer or a patterned metal layer.

在本發明的另一實施例中，進行上述微影製程之前還可先在半導體基板上形成一介電層覆蓋上述游標尺結構，使對照圖案與游標尺結構通過上述介電層相隔開。In another embodiment of the present invention, a dielectric layer may be formed on the semiconductor substrate to cover the vernier structure before the lithography process, so that the contrast pattern and the vernier structure are separated by the dielectric layer.

在本發明的另一實施例中，上述對照圖案的尺寸是上述元件圖案的尺寸的10倍以下。In another embodiment of the present invention, the size of the control pattern is less than 10 times the size of the element pattern.

基於上述，本發明藉由設置在切割道或焊墊下方的游標尺，能通過一道檢測步驟同時取得X方向與Y方向的OL偏移量與CD值，因此能縮減微影製程檢測的時間，甚至直接省略原有三個檢測站點中的OL檢測站點，提升採樣率。此外，由於游標尺的大小接近實際元件尺寸，所以能取得較精確的檢測結果。Based on the above, the present invention can obtain the OL offset and CD value in the X direction and the Y direction at the same time through one detection step by means of the vernier set under the scribe line or the bonding pad, so that the detection time of the lithography process can be shortened. Even the OL detection site in the original three detection sites is directly omitted to improve the sampling rate. In addition, since the size of the vernier scale is close to the actual component size, more accurate detection results can be obtained.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

下文列舉一些實施例並配合所附圖式來進行詳細地說明，但所提供的實施例並非用以限制本發明所涵蓋的範圍。此外，圖式僅以說明為目的，並未依照原尺寸作圖。為了方便理解，下述說明中相同的元件將以相同之符號標示來說明。另外，關於文中所使用「包含」、「包括」、「具有」等等用語，均為開放性的用語；也就是指包含但不限於。而且，文中所提到的方向性用語，例如：「上」、「下」等，僅是用以參考圖式的方向。因此，使用的方向性用語是用來說明，而並非用來限制本發明。Some embodiments are listed below and described in detail with the accompanying drawings, but the provided embodiments are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn in full scale. In order to facilitate understanding, the same elements in the following description will be denoted by the same symbols. In addition, the terms such as "comprising", "including", "having", etc. used in the text are all open-ended terms; that is, including but not limited to. Moreover, the directional terms mentioned in the text, such as "up", "down", etc., are only used to refer to the direction of the drawings. Accordingly, the directional terms used are intended to illustrate rather than limit the present invention.

圖1A是依照本發明的第一實施例的一種半導體製程用游標尺的上視示意圖。圖1B是圖1A的I-I線段的一種半導體製程用游標尺的剖面示意圖。1A is a schematic top view of a vernier for a semiconductor process according to a first embodiment of the present invention. FIG. 1B is a schematic cross-sectional view of a vernier for a semiconductor process along the I-I line segment of FIG. 1A .

請參照圖1A與圖1B，第一實施例的半導體製程用游標尺包括形成於半導體基板100內的至少一游標尺結構102與多個識別符號104。所述游標尺結構102包括在X方向延伸的數條第一線型層106與在Y方向延伸的數條第二線型層108，第一線型層106與第二線型層108交叉設置，其中每條第一線型層106的線寬w1例如與第一線型層106之間的間距s1相同，且每條第二線型層108的線寬w2例如與第二線型層108之間的間距s2相同。在一實施例中，第一線型層106與第二線型層108例如是淺溝渠隔離結構（STI）。識別符號104則形成於每條第一線型層106的至少一端與每條第二線型層108的至少一端，以區別游標尺結構102中的不同條第一線型層106與不同條第二線型層108。在本實施例中，識別符號104是***數字（0、1、2...），但本發明並不限於此，識別符號104也可以是羅馬數字（I、II、III...）。在元件尺寸愈來愈小的情況下，識別符號104也可改以不同行形狀的符號取代，例如長方形、正方形、菱形、圓形、三角形、多邊形、十字形或星形。Referring to FIGS. 1A and 1B , the vernier scale for a semiconductor process according to the first embodiment includes at least one vernier scale structure 102 and a plurality of identification symbols 104 formed in the semiconductor substrate 100 . The vernier structure 102 includes several first linear layers 106 extending in the X direction and several second linear layers 108 extending in the Y direction. The first linear layers 106 and the second linear layers 108 are arranged to intersect, wherein The line width w1 of each first line type layer 106 is, for example, the same as the distance s1 between the first line type layers 106 , and the line width w2 of each second line type layer 108 is, for example, the distance between the second line type layers 108 s2 is the same. In one embodiment, the first linear layer 106 and the second linear layer 108 are, for example, shallow trench isolation (STI). The identification symbols 104 are formed on at least one end of each of the first line-type layers 106 and at least one end of each of the second line-type layers 108 to distinguish different first line-type layers 106 and different second line-type layers in the vernier structure 102 Line layer 108 . In this embodiment, the identification symbols 104 are Arabic numerals (0, 1, 2...), but the present invention is not limited thereto, and the identification symbols 104 may also be Roman numerals (I, II, III...). In the case of smaller and smaller component sizes, the identification symbols 104 can also be replaced with symbols of different row shapes, such as rectangles, squares, diamonds, circles, triangles, polygons, crosses or stars.

在圖1A中顯示5條第一線型層106與5條第二線型層108，然而本發明並不限於此，根據曝光機台所使用的光源波長，可形成更細的線型層以及更多條的線型層。舉例來說，I-line光源(波長365nm)可製作的最小線寬是350nm；KrF光源(波長248nm)可製作的最小線寬是150nm、ArF光源(波長193nm)可製作的最小線寬是65nm、ArF光源浸潤式微影可製作的最小線寬是19nm，所以若是要針對I-line微影製程進行檢測，則游標尺結構102可利用ArF微影製程形成5條線寬w1為65nm的第一線型層106和5條線寬w2為65nm的第二線型層108，且第一線型層106之間的間距s1也是65nm、第二線型層108之間的間距s2也是65nm。當原本應該形成在游標尺結構102正中央的圖案（以虛線表示長寬各350nm的正方形）偏移形成到左下角的圖案110，即可從游標尺結構102直接取得X方向偏移量∆X與Y方向偏移量∆Y。一旦X方向偏移量∆X與Y方向偏移量∆Y中有任一項超出可容許的偏移量，則需進行微影製程的校正或重工（rework）。依此類推，若是要針對KrF微影製程進行檢測，則游標尺結構102可利用ArF光源浸潤式微影形成15條線寬w1約20nm的第一線型層（未繪示）和15條線寬w2約20nm的第二線型層（未繪示），且第一線型層之間的間距s1、第二線型層之間的間距s2也約20nm。In FIG. 1A , five first linear layers 106 and five second linear layers 108 are shown, however, the present invention is not limited to this. According to the wavelength of the light source used by the exposure machine, thinner linear layers and more linear layers can be formed. linetype layer. For example, the minimum line width that can be produced by I-line light source (wavelength 365nm) is 350nm; the minimum line width that can be produced by KrF light source (wavelength 248nm) is 150nm, and the minimum line width that can be produced by ArF light source (wavelength 193nm) is 65nm , The minimum line width that can be produced by ArF light source immersion lithography is 19nm, so if it is to be tested for the I-line lithography process, the vernier structure 102 can use the ArF lithography process to form 5 first lines with a line width w1 of 65nm The line-type layer 106 and five second line-type layers 108 with a line width w2 of 65 nm, the spacing s1 between the first line-type layers 106 is also 65 nm, and the spacing s2 between the second line-type layers 108 is also 65 nm. When the pattern originally formed in the center of the vernier structure 102 (a square with a length and width of 350 nm is represented by a dotted line) is shifted to the pattern 110 formed in the lower left corner, the X-direction offset ΔX can be directly obtained from the vernier structure 102 Offset ∆Y from the Y direction. Once any of the X-direction offset ΔX and the Y-direction offset ΔY exceeds the allowable offset, correction or rework of the lithography process is required. By analogy, if testing is required for the KrF lithography process, the vernier structure 102 can use ArF light source immersion lithography to form 15 first line layers (not shown) with a line width w1 of about 20 nm and 15 line widths. The second linear layer (not shown) with w2 of about 20 nm, and the spacing s1 between the first linear layers and the spacing s2 between the second linear layers are also about 20 nm.

此外，如果針對線寬較大的（如I-line）微影製程進行檢測，如圖2所示，游標尺結構200可以是利用如ArF光源浸潤式微影形成線寬w1較小的第一線型層202和線寬w2較小的第二線型層204，不但可從游標尺結構200參照識別符號206直接取得X方向偏移量∆X與Y方向偏移量∆Y，也因為游標尺結構200的第一線型層202和第二線型層204很細且密，還可用來取得X方向與Y方向的臨界尺寸（CD）。In addition, if testing is performed on a lithography process with a larger line width (eg, I-line), as shown in FIG. 2 , the vernier structure 200 can be formed by using ArF light source immersion lithography to form a first line with a smaller line width w1 The shape layer 202 and the second line shape layer 204 with a smaller line width w2 can not only directly obtain the X-direction offset ΔX and the Y-direction offset ΔY from the vernier structure 200 with reference to the identification symbol 206, but also because of the vernier structure The first line type layer 202 and the second line type layer 204 of 200 are very thin and dense, and can also be used to obtain critical dimensions (CD) in the X direction and the Y direction.

請再度參照圖1A和圖2，由於游標尺結構102/200中的第一線型層106/202和第二線型層108/204距離接近，為了清楚分辨識別符號104/206所對應的是哪一條線，第一線型層106/202中的中線CL長度會大於其餘第一線型層106/202的長度，且第二線型層108/204中的中線CL長度也會大於其餘第二線型層108/204的長度。雖然以上說明都是以每條第一線型層106/202的線寬w1與每條第二線型層108/204的線寬w2相同，且第一線型層106/202之間的間距s1與第二線型層108/204之間的間距s2相同為例，但本發明並不限於此。Please refer to FIG. 1A and FIG. 2 again, since the distance between the first line type layer 106/202 and the second line type layer 108/204 in the vernier scale structure 102/200 is close, in order to clearly distinguish which identification symbol 104/206 corresponds to For one line, the length of the center line CL in the first line type layer 106/202 will be greater than the length of the remaining first line type layers 106/202, and the length of the center line CL in the second line type layer 108/204 will also be greater than the length of the remaining first line type layers 108/204. The length of the bilinear layer 108/204. Although the above description is based on the line width w1 of each first line type layer 106/202 and the line width w2 of each second line type layer 108/204 being the same, and the spacing s1 between the first line type layers 106/202 The same as the spacing s2 between the second linear layers 108 / 204 is taken as an example, but the present invention is not limited thereto.

整體而言，本實施例的半導體製程用游標尺的長寬約在1微米左右，因此與既有的對準標記（長寬）動輒數十微米相比，面積大概縮減數百倍，所以本實施例的游標尺結構102/200（連同識別符號104/206）不但可設置於半導體基板100的切割道，還能設置於半導體基板100的晶片區之焊墊（bonding pad）的正下方。因為焊墊下方通常不會有線路，且焊墊的面積大，所以能將尺寸小的游標尺結構102/200設計在焊墊正下方的半導體基板100內。On the whole, the length and width of the vernier used for the semiconductor process of this embodiment is about 1 micrometer. Therefore, compared with the existing alignment marks (length and width) that are often tens of micrometers, the area is reduced by hundreds of times. The vernier structure 102 / 200 of the embodiment (together with the identification symbols 104 / 206 ) can be disposed not only on the scribe lines of the semiconductor substrate 100 , but also directly under the bonding pads in the wafer area of the semiconductor substrate 100 . Because there are usually no lines under the pads, and the pads have a large area, the vernier structure 102/200 with a small size can be designed in the semiconductor substrate 100 directly under the pads.

圖1C是圖1A的I-I線段的另一種半導體製程用游標尺的剖面示意圖，使用與圖1B相同的元件符號來代表相同或相似的構件，且所省略的部分技術說明，如各層或區域的位置、尺寸等均可參照圖1B的內容，因此於下文不再贅述。1C is a schematic cross-sectional view of another vernier for semiconductor manufacturing along the line II of FIG. 1A , the same component symbols as those in FIG. 1B are used to represent the same or similar components, and some technical descriptions are omitted, such as the positions of various layers or regions , dimensions, etc., can refer to the content of FIG. 1B , and therefore will not be repeated below.

在圖1C中，半導體製程用游標尺是由形成於半導體基板100上的游標尺結構102與識別符號104構成，且第一線型層(未繪示)與第二線型層108是多晶矽線。也就是說，第一線型層(未繪示)與第二線型層108可與元件區的多晶矽閘極一起製作，所以線寬w2可以很小。In FIG. 1C , the vernier for semiconductor process is composed of a vernier structure 102 and an identification symbol 104 formed on a semiconductor substrate 100 , and the first line type layer (not shown) and the second line type layer 108 are polysilicon lines. That is to say, the first linear layer (not shown) and the second linear layer 108 can be fabricated together with the polysilicon gate of the device region, so the line width w2 can be very small.

圖3是依照本發明的第二實施例的一種微影製程檢測步驟圖。FIG. 3 is a diagram showing the inspection steps of a lithography process according to the second embodiment of the present invention.

請參照圖3，第二實施例的微影製程檢測方法需先提供上一實施例的半導體製程用游標尺（步驟S300），其包括圖1A至圖2所示的半導體基板、游標尺結構以及識別符號，且有關半導體製程用游標尺的各構件技術說明，如線型層的位置、尺寸等、識別符號的樣式，均可參照第一實施例的內容，因此於下文不再贅述。Referring to FIG. 3 , the lithography process detection method of the second embodiment needs to first provide the vernier scale for the semiconductor process of the previous embodiment (step S300 ), which includes the semiconductor substrate shown in FIGS. 1A to 2 , the vernier scale structure and The identification symbols, and the technical descriptions of the components of the vernier for semiconductor manufacturing, such as the position and size of the line layer, and the style of the identification symbols, can all refer to the content of the first embodiment, so they will not be repeated below.

然後，進行一微影製程（步驟S302），以同時在半導體基板上形成至少一元件圖案並在游標尺結構（如圖1A的102）上形成一對照圖案（如圖1A的110），由於上述微影製程可為用於蝕刻的微影製程或用於植入的微影製程，所以對照圖案可以是顯影後的圖案化光阻、蝕刻後的圖案化介電層或蝕刻後的圖案化金屬層。至於元件圖案則是實際形成在元件區的摻雜區或者線路的圖案。因此，對照圖案的尺寸可以是上述元件圖案的尺寸的10倍以下。舉例來說，如果游標尺結構是直接形成在半導體基板內的STI，則可在半導體基板表面塗佈光阻，再進行步驟S302，使上述光阻成為圖案化光阻（即對照圖案）；如果游標尺結構是直接形成在半導體基板內的STI，也可在步驟S302之前，先在半導體基板上形成一介電層覆蓋STI，再於介電層表面塗佈光阻，然後進行步驟S302，使光阻成為圖案化光阻（即對照圖案）。同樣地，如果游標尺結構是形成在半導體基板上的多晶矽線，則可在步驟S302之前，先在半導體基板上形成一介電層覆蓋多晶矽線再塗佈光阻，然後進行步驟S302，使上述光阻成為圖案化光阻（即對照圖案）。此外，形成圖案化光阻之後，也可先進行蝕刻製程，將上述介電層蝕刻成為圖案化介電層（即對照圖案）。若是將上述介電層置換成金屬層也可施行，故不再贅述。Then, a lithography process (step S302 ) is performed to form at least one element pattern on the semiconductor substrate and a control pattern (110 in FIG. 1A ) on the vernier structure (102 in FIG. 1A ) at the same time. The lithography process can be a lithography process for etching or a lithography process for implantation, so the control pattern can be a patterned photoresist after development, a patterned dielectric layer after etching, or a patterned metal layer after etching Floor. As for the element pattern, it is the pattern of the doped regions or lines actually formed in the element region. Therefore, the size of the control pattern may be 10 times or less the size of the above-described element pattern. For example, if the vernier structure is an STI directly formed in the semiconductor substrate, a photoresist can be coated on the surface of the semiconductor substrate, and then step S302 is performed to make the photoresist a patterned photoresist (ie, a control pattern); if The vernier structure is the STI directly formed in the semiconductor substrate. Before step S302, a dielectric layer can be formed on the semiconductor substrate to cover the STI, and then a photoresist is coated on the surface of the dielectric layer, and then step S302 is performed to make The photoresist becomes the patterned photoresist (ie, the control pattern). Similarly, if the vernier structure is a polysilicon line formed on a semiconductor substrate, before step S302, a dielectric layer can be formed on the semiconductor substrate to cover the polysilicon line, and then a photoresist can be coated, and then step S302 is performed to make the above The photoresist becomes the patterned photoresist (ie, the control pattern). In addition, after the patterned photoresist is formed, an etching process can also be performed first to etch the above-mentioned dielectric layer into a patterned dielectric layer (ie, a control pattern). If the above-mentioned dielectric layer is replaced with a metal layer, it can also be implemented, so it will not be repeated.

所述對照圖案一般為方形或矩形，所以具有X方向上的第一對邊與Y方向上的第二對邊。然後，取得所述第一對邊在X方向上到游標尺結構的兩邊的第一最短距離X1以及X2，同時取得所述第二對邊在Y方向上到游標尺結構的另兩邊的第二最短距離Y1以及Y2（步驟S304）。在一實施例中，取得X1與X2以及Y1與Y2的方法包括：使用光學顯微鏡（OM）觀測所述對照圖案的第一對邊和第二對邊相對於游標尺結構的位置，以根據識別符號判定第一最短距離X1與X2以及第二最短距離Y1與Y2。在另一實施例中，取得X1與X2以及Y1與Y2的方法包括：利用掃描式電子顯微鏡（SEM）進行拍攝得到影像，並觀測所述影像，以取得所述對照圖案的第一對邊和第二對邊相對於游標尺結構的位置，並根據識別符號判定第一最短距離X1與X2以及第二最短距離Y1與Y2。The contrast pattern is generally square or rectangular, so it has a first pair of sides in the X direction and a second pair of sides in the Y direction. Then, obtain the first shortest distances X1 and X2 from the first pair of sides to the two sides of the vernier scale structure in the X direction, and simultaneously obtain the second pair of sides in the Y direction to the other two sides of the vernier scale structure. The shortest distances Y1 and Y2 (step S304 ). In one embodiment, the method of obtaining X1 and X2 and Y1 and Y2 includes: using an optical microscope (OM) to observe the position of the first pair of sides and the second pair of sides of the contrast pattern relative to the vernier structure to identify The sign determines the first shortest distances X1 and X2 and the second shortest distances Y1 and Y2. In another embodiment, the method for obtaining X1 and X2 and Y1 and Y2 includes: using a scanning electron microscope (SEM) to capture an image, and observing the image to obtain the first pair of sides and The positions of the second pair of sides relative to the vernier structure are determined according to the identification symbols of the first shortest distances X1 and X2 and the second shortest distances Y1 and Y2.

接著，以第一最短距離X1與X2的差值（X1-X2）以及第二最短距離Y1與Y2的差值（Y1-Y2）作為重疊（Overlap，OL）偏移值（shift value），判定是否超出OL偏移容許量（步驟S306）。在一實施例中，步驟S304若是使用SEM儀器（SEM tool）直接取得X1、X2、Y1、Y2，即可判定是否超出OL偏移容許量（步驟S306）並將檢測的結果回饋給進行步驟S302的微影製程的機台。在進行步驟S302的微影製程的機台收到上述檢測的結果後，還可調整步驟S302的微影製程，以降低OL偏移值。而且，根據上述差值是正值或負值還能判斷方向性的偏移，例如差值（X1-X2）若是負值代表往右偏移，依此類推。Next, the difference (X1-X2) between the first shortest distance X1 and X2 and the difference (Y1-Y2) between the second shortest distance Y1 and Y2 are used as the overlap (Overlap, OL) offset value (shift value) to determine Whether the OL shift tolerance is exceeded (step S306 ). In one embodiment, in step S304, if X1, X2, Y1, and Y2 are directly obtained by using a SEM tool (SEM tool), it can be determined whether the OL offset tolerance is exceeded (step S306), and the detection result is fed back to perform step S302 lithography process machine. After the machine performing the lithography process in step S302 receives the above detection result, the lithography process in step S302 can also be adjusted to reduce the OL offset value. Moreover, according to whether the above difference is positive or negative, the directional offset can also be determined. For example, if the difference (X1-X2) is negative, it means a right offset, and so on.

同時，根據游標尺結構在X方向的長度X_V 減掉所述第一最短距離X1與X2的總和（= X_V -(X1+X2)），取得對照圖案在X方向的臨界尺寸（CD）偏移值，以判定是否超出X方向的CD偏移容許量（步驟S308）。根據游標尺結構在Y方向的長度Y_V 減掉所述第二最短距離Y1與Y2的總和（= Y_V - (Y1+Y2) ），取得對照圖案在Y方向的臨界尺寸（CD）偏移值，以判定是否超出Y方向的CD偏移容許量（步驟S310）。At the same time, subtract the sum of the first shortest distances X1 and X2 from _{the length X V of the} vernier structure in the X direction _{(= X V} -(X1+X2)) to obtain the critical dimension (CD) of the control pattern in the X direction The offset value is determined to determine whether or not the allowable amount of CD offset in the X direction is exceeded (step S308 ). The critical dimension (CD) offset of the contrast pattern in the Y direction is obtained by subtracting the sum of the second shortest distances Y1 and Y2 from _{the length Y V of the} vernier structure in the Y direction _{(= Y V - (Y1+Y2) )} value to determine whether the CD shift tolerance in the Y direction is exceeded (step S310 ).

若是步驟S306、S308、S310的判定結果是「否」，則完成檢測。If the determination results of steps S306, S308, and S310 are "No", the detection is completed.

若是超出OL偏移容許量，則可選擇執行重疊檢測（Overlap Check）（步驟S312）或執行重工（步驟S314）。If the OL offset tolerance is exceeded, it can be selected to perform Overlap Check (step S312 ) or to perform rework (step S314 ).

若是超出X方向的CD偏移容許量，還可包括執行SEM檢測（SEM Check）（步驟S316）或執行重工（步驟S314）。If the allowable amount of CD offset in the X direction is exceeded, it may further include performing SEM Check (step S316 ) or performing rework (step S314 ).

若是超出Y方向的CD偏移容許量，則可選擇執行SEM檢測（步驟S316）或執行重工（步驟S314）。If the allowable amount of CD shift in the Y direction is exceeded, SEM inspection (step S316 ) or rework (step S314 ) can be selected.

當微影製程原本具有三個檢測站點，例如使用OM進行X方向與Y方向的重疊檢測站、使用SEM tool的CD檢測站以及目檢（Visual Check）站，利用本實施例的檢測方法可以達到以下效果。When the lithography process originally has three inspection stations, such as the X-direction and Y-direction overlap inspection station using OM, the CD inspection station using SEM tool, and the Visual Check station, the inspection method of this embodiment can be used to achieve the following effects.

首先，如果利用OM進行目檢並同時取得X1、X2、Y1、Y2，即可判定OL偏移的程度，因而省略上述重疊檢測站。或者，利用SEM tool進行CD檢測並同時取得X1、X2、Y1、Y2的話，也可在取得CD值的時候判定OL偏移的程度，並省略上述重疊檢測站。另一方面，如果利用OM進行目檢並經由本發明的方式同時量測X方向與Y方向的CD值，還能提升CD採樣率。First, if X1, X2, Y1, and Y2 are simultaneously obtained by visual inspection using OM, the degree of OL shift can be determined, and thus the above-mentioned overlapping detection station is omitted. Alternatively, if X1, X2, Y1, and Y2 are simultaneously acquired by CD detection using the SEM tool, the degree of OL shift can be determined when acquiring the CD value, and the above-described overlapping detection station can be omitted. On the other hand, if the OM is used for visual inspection and the CD values in the X direction and the Y direction are simultaneously measured by the method of the present invention, the CD sampling rate can be improved.

綜上所述，本發明藉由設置在切割道或焊墊下方的游標尺，能通過一道檢測步驟同時取得X方向與Y方向的OL偏移量與CD值，因此能縮減微影製程檢測的時間，甚至直接省略原有三個檢測站點中的OL檢測站點，提升採樣率。此外，由於游標尺的大小接近實際元件尺寸，所以能取得較精確的檢測結果。游標尺可形成於半導體基板上或半導體基板內，因此除了針對元件（cell）的微影製程（蝕刻或植入）進行檢測，還能對其上的線路（如M1、M2…）的微影製程（蝕刻）進行檢測。To sum up, the present invention can obtain the OL offset and CD value in the X direction and the Y direction at the same time through a single detection step by means of the vernier set under the scribe line or the solder pad, so that the detection time of the lithography process can be reduced. Time, or even directly omit the OL detection site in the original three detection sites to improve the sampling rate. In addition, since the size of the vernier scale is close to the actual component size, more accurate detection results can be obtained. The vernier scale can be formed on or in the semiconductor substrate, so in addition to testing the lithography process (etching or implanting) of the component (cell), it can also perform lithography on the lines (such as M1, M2...) Process (etching) for inspection.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

100:半導體基板 102、200:游標尺結構 104、206:識別符號 106、202:第一線型層 108、204:第二線型層 110:對照圖案 CL:中線 s1、s2:間距 S300、S302、S304、S306、S308、S310、S312、S314、S316:步驟 X1、X2:第一最短距離 X_V 、Y_V :長度 Y1、Y2:第二最短距離 ∆X:X方向偏移量 ∆Y:Y方向偏移量 w1、w2:線寬100: Semiconductor substrate 102, 200: Vernier structure 104, 206: Identification symbols 106, 202: First line layer 108, 204: Second line layer 110: Control pattern CL: Center line s1, s2: Spacing S300, S302 , S304, S306, S308, S310, S312, S314, S316: Step X1, X2: First shortest distance X _V , Y _V : Length Y1, Y2: Second shortest distance ∆X: Offset in X direction ∆Y: Y direction offset w1, w2: line width

圖1A是依照本發明的第一實施例的一種半導體製程用游標尺的上視示意圖。圖1B是圖1A的I-I線段的一種半導體製程用游標尺的剖面示意圖。圖1C是圖1A的I-I線段的另一種半導體製程用游標尺的剖面示意圖。圖2是第一實施例的另一種半導體製程用游標尺的上視示意圖。圖3是依照本發明的第二實施例的一種微影製程檢測步驟圖。1A is a schematic top view of a vernier for a semiconductor process according to a first embodiment of the present invention. FIG. 1B is a schematic cross-sectional view of a vernier for a semiconductor process along the I-I line segment of FIG. 1A . FIG. 1C is a schematic cross-sectional view of another vernier for semiconductor manufacturing along the I-I line segment of FIG. 1A . 2 is a schematic top view of another vernier for a semiconductor process according to the first embodiment. FIG. 3 is a diagram showing the inspection steps of a lithography process according to the second embodiment of the present invention.

102:游標尺結構102: Vernier ruler structure

104:識別符號104: Identification symbols

106:第一線型層106: The first line type layer

108:第二線型層108: Second line type layer

110:對照圖案110: Control pattern

CL:中線CL: center line

s1、s2:間距s1, s2: Spacing

X1、X2:第一最短距離X1, X2: the first shortest distance

X_V 、Y_V :長度X _V , Y _V : length

Y1、Y2:第二最短距離Y1, Y2: The second shortest distance

△X:X方向偏移量△X: Offset in X direction

△Y:Y方向偏移量△Y: Offset in Y direction

w1、w2:線寬w1, w2: line width

Claims

一種半導體製程用游標尺，包括：一半導體基板；以及至少一游標尺結構，形成於所述半導體基板上或所述半導體基板內，其中所述游標尺結構包括在X方向延伸的多數條第一線型層與在Y方向延伸的多數條第二線型層，所述多數條第一線型層與所述多數條第二線型層交叉設置，所述多數條第一線型層中的中線長度大於其餘所述第一線型層的長度，且所述多數條第二線型層中的中線長度大於其餘所述第二線型層的長度；以及多數個識別符號，形成於每條所述第一線型層的至少一端與每條所述第二線型層的至少一端，以區別所述游標尺結構中的不同條所述第一線型層與不同條所述第二線型層。A vernier ruler for semiconductor process, comprising: a semiconductor substrate; and At least one vernier structure is formed on the semiconductor substrate or in the semiconductor substrate, wherein the vernier structure includes a plurality of first line-type layers extending in the X direction and a plurality of second line-type layers extending in the Y direction layer, the plurality of first line type layers and the plurality of second line type layers are crossed, the length of the center line in the plurality of first line type layers is greater than the length of the rest of the first line type layers, and The median length of the plurality of second line type layers is greater than the length of the rest of the second line type layers; and A plurality of identification symbols are formed on at least one end of each of the first line-type layers and at least one end of each of the second line-type layers to distinguish different first line-type layers in the vernier structure with different strips of the second linear layer.

如請求項1所述的半導體製程用游標尺，其中所述游標尺結構形成於所述半導體基板內，且所述第一線型層與所述第二線型層為淺溝渠隔離結構（STI）。The vernier for a semiconductor process according to claim 1, wherein the vernier structure is formed in the semiconductor substrate, and the first line type layer and the second line type layer are shallow trench isolation structures (STI) .

如請求項1所述的半導體製程用游標尺，其中所述游標尺結構形成於所述半導體基板上，且所述第一線型層與所述第二線型層為多晶矽線。The vernier for a semiconductor process according to claim 1, wherein the vernier structure is formed on the semiconductor substrate, and the first line type layer and the second line type layer are polysilicon lines.

如請求項1所述的半導體製程用游標尺，其中所述識別符號包括***數字或羅馬數字。The vernier ruler for a semiconductor process according to claim 1, wherein the identification symbols include Arabic numerals or Roman numerals.

如請求項1所述的半導體製程用游標尺，其中所述識別符號的形狀包括長方形、正方形、菱形、圓形、三角形、多邊形、十字形或星形。The vernier ruler for a semiconductor process according to claim 1, wherein the shape of the identification symbol includes a rectangle, a square, a diamond, a circle, a triangle, a polygon, a cross or a star.

如請求項1所述的半導體製程用游標尺，其中每條所述第一線型層的線寬及所述多數條第一線型層之間的間距相同，且每條所述第二線型層的線寬及所述多數條第二線型層之間的間距相同。The vernier for a semiconductor process according to claim 1, wherein the line width of each of the first line-type layers and the spacing between the plurality of first line-type layers are the same, and each of the second line-type layers is the same The line width of the layers and the spacing between the plurality of second line type layers are the same.

如請求項1所述的半導體製程用游標尺，其中每條所述第一線型層的線寬與每條所述第二線型層的線寬相同，且所述多數條第一線型層之間的間距與所述多數條第二線型層之間的間距相同。The vernier for a semiconductor process according to claim 1, wherein the line width of each of the first line type layers is the same as the line width of each of the second line type layers, and the plurality of first line type layers The spacing therebetween is the same as the spacing between the plurality of second line type layers.

如請求項1所述的半導體製程用游標尺，其中所述游標尺結構設置於所述半導體基板的切割道。The vernier for a semiconductor process according to claim 1, wherein the vernier structure is disposed on a dicing line of the semiconductor substrate.

如請求項1所述的半導體製程用游標尺，其中所述游標尺結構設置於所述半導體基板的晶片區之焊墊（bonding pad）的正下方。The vernier scale for a semiconductor process as claimed in claim 1, wherein the vernier scale structure is disposed just below the bonding pads in the chip area of the semiconductor substrate.

一種微影製程檢測方法，包括：提供如請求項1~9中任一項所述的半導體製程用游標尺，其包括一半導體基板、至少一游標尺結構以及多數個識別符號；進行一微影製程，以同時在所述半導體基板上形成至少一元件圖案並在所述游標尺結構上形成一對照圖案，所述對照圖案具有X方向上的第一對邊與Y方向上的第二對邊；取得所述第一對邊在X方向上到所述游標尺結構的兩邊的第一最短距離X1以及X2以及所述第二對邊在Y方向上到所述游標尺結構的另兩邊的第二最短距離Y1以及Y2；以所述第一最短距離X1與X2的差值以及所述第二最短距離Y1與Y2的差值作為重疊（Overlap，OL）偏移值（shift value），判定是否超出OL偏移容許量；根據所述游標尺結構在X方向的長度X_V 減掉所述第一最短距離X1與X2的總和(X1+X2)，取得所述對照圖案在X方向的臨界尺寸（CD）偏移值，以判定是否超出X方向的CD偏移容許量；以及根據所述游標尺結構在Y方向的長度Y_V 減掉所述第二最短距離Y1與Y2的總和(Y1+Y2)，取得所述對照圖案在Y方向的臨界尺寸（CD）偏移值，以判定是否超出Y方向的CD偏移容許量。A lithography process detection method, comprising: providing a vernier for a semiconductor process according to any one of claims 1 to 9, which includes a semiconductor substrate, at least one vernier structure and a plurality of identification symbols; performing a lithography a process for simultaneously forming at least one element pattern on the semiconductor substrate and forming a contrast pattern on the vernier structure, the contrast pattern having a first opposite side in the X direction and a second opposite side in the Y direction ; Obtain the first shortest distances X1 and X2 from the first pair of sides to the two sides of the vernier scale structure in the X direction and the second pair of sides to the other two sides of the vernier scale structure in the Y direction. Two shortest distances Y1 and Y2; Take the difference between the first shortest distance X1 and X2 and the difference between the second shortest distance Y1 and Y2 as the overlap (Overlap, OL) offset value (shift value) to determine whether Exceeding the OL offset tolerance; According to the length X _{V of the} vernier structure in the X direction, subtract the sum (X1+X2) of the first shortest distance X1 and X2 to obtain the critical dimension of the control pattern in the X direction (CD) offset value to determine whether the CD offset tolerance in the X direction is exceeded; and subtract the sum of the second shortest distance Y1 and Y2 from _{the length Y V of the vernier structure in the Y direction (Y1+} Y2), obtain the critical dimension (CD) offset value of the control pattern in the Y direction, to determine whether the CD offset tolerance in the Y direction is exceeded.

如請求項10所述的微影製程檢測方法，其中若是超出所述OL偏移容許量，更包括：執行重疊檢測（Overlap Check）或執行重工（rework）。The lithography process detection method according to claim 10, wherein if the OL offset tolerance is exceeded, the method further comprises: performing an overlap check (Overlap Check) or performing a rework (rework).

如請求項10所述的微影製程檢測方法，其中若是超出所述X方向的CD偏移容許量，更包括：執行SEM檢測（SEM Check）或執行重工。The lithography process inspection method according to claim 10, wherein if the allowable amount of CD offset in the X direction is exceeded, the method further comprises: performing SEM Check or performing rework.

如請求項10所述的微影製程檢測方法，其中若是超出所述Y方向的CD偏移容許量，更包括：執行SEM檢測或執行重工。The lithography process inspection method according to claim 10, wherein if the CD offset tolerance in the Y direction is exceeded, the method further comprises: performing SEM inspection or performing rework.

如請求項10所述的微影製程檢測方法，其中取得所述第一最短距離X1與X2以及取得所述第二最短距離Y1與Y2的方法包括：使用光學顯微鏡（OM）觀測所述第一對邊和所述第二對邊相對於所述游標尺結構的位置，以根據所述識別符號判定所述第一最短距離X1與X2以及所述第二最短距離Y1與Y2。The lithography process detection method according to claim 10, wherein the methods for obtaining the first shortest distances X1 and X2 and obtaining the second shortest distances Y1 and Y2 include: observing the first shortest distances with an optical microscope (OM). The positions of the opposite side and the second opposite side relative to the vernier structure are used to determine the first shortest distances X1 and X2 and the second shortest distances Y1 and Y2 according to the identification symbols.

如請求項10所述的微影製程檢測方法，其中取得所述第一最短距離X1與X2以及取得所述第二最短距離Y1與Y2的方法包括：利用掃描式電子顯微鏡（SEM）進行拍攝得到影像，並觀測所述影像，以取得所述第一對邊和所述第二對邊相對於所述游標尺結構的位置，並根據所述識別符號判定所述第一最短距離X1與X2以及所述第二最短距離Y1與Y2。The lithography process detection method according to claim 10, wherein the methods for obtaining the first shortest distances X1 and X2 and obtaining the second shortest distances Y1 and Y2 include: photographing with a scanning electron microscope (SEM) to obtain image, and observe the image to obtain the positions of the first opposite side and the second opposite side relative to the vernier structure, and determine the first shortest distances X1 and X2 and The second shortest distances Y1 and Y2.

如請求項10所述的微影製程檢測方法，其中取得所述第一最短距離X1與X2、取得所述第二最短距離Y1與Y2以及判定是否超出所述OL偏移容許量的方法包括：使用SEM儀器（SEM tool）取得所述第一最短距離X1與X2以及所述第二最短距離Y1與Y2，並將檢測的結果回饋給進行所述微影製程的機台。The lithography process detection method according to claim 10, wherein the methods for obtaining the first shortest distances X1 and X2, obtaining the second shortest distances Y1 and Y2, and determining whether the OL offset tolerance is exceeded include: The first shortest distances X1 and X2 and the second shortest distances Y1 and Y2 are obtained by using a SEM tool, and the detection results are fed back to the machine performing the lithography process.

如請求項16所述的微影製程檢測方法，其中所述微影製程的機台收到所述檢測的結果後，更包括：調整所述微影製程。The lithography process detection method according to claim 16, wherein after receiving the detection result, the lithography process machine further comprises: adjusting the lithography process.

如請求項10所述的微影製程檢測方法，其中所述微影製程包括用於蝕刻的微影製程或用於植入的微影製程。The lithography process detection method of claim 10, wherein the lithography process includes a lithography process for etching or a lithography process for implantation.

如請求項10所述的微影製程檢測方法，其中所述對照圖案包括圖案化光阻、圖案化介電層或圖案化金屬層。The lithography process inspection method according to claim 10, wherein the control pattern comprises a patterned photoresist, a patterned dielectric layer or a patterned metal layer.

如請求項10所述的微影製程檢測方法，其中進行所述微影製程之前，更包括在所述半導體基板上形成一介電層覆蓋所述游標尺結構，使所述對照圖案與所述游標尺結構通過所述介電層相隔開。The lithography process detection method according to claim 10, wherein before the lithography process is performed, further comprising forming a dielectric layer on the semiconductor substrate to cover the vernier structure, so that the comparison pattern and the vernier structure are formed. The vernier structures are separated by the dielectric layer.

如請求項10所述的微影製程檢測方法，其中所述對照圖案的尺寸是所述元件圖案的尺寸的10倍以下。The lithography process detection method according to claim 10, wherein the size of the control pattern is less than 10 times the size of the element pattern.