TW202137294A

TW202137294A - Fully reflective phase-edge mask for euv lithography

Info

Publication number: TW202137294A
Application number: TW110100277A
Authority: TW
Inventors: 鄭文豪
Original assignee: 台灣積體電路製造股份有限公司
Priority date: 2020-03-30
Filing date: 2021-01-05
Publication date: 2021-10-01
Also published as: CN113050360A; TWI811609B

Abstract

A EUV lithography mask includes a substrate of a low thermal expansion material, a first reflective multilayer over the substrate, and a patterned reflective multilayer over the first reflective multilayer. The patterned reflective multilayer includes trenches through the patterned reflective multilayer. Each of the first reflective multilayer and the patterned reflective multilayer includes a stack of film pairs.

Description

用於極紫外光微影的全反射式相位邊緣光罩Total reflection type phase edge mask for extreme ultraviolet light lithography

本發明實施係有關用於極紫外光微影的全反射式相位邊緣光罩。The implementation of the present invention relates to a total reflection type phase edge mask for extreme ultraviolet light lithography.

半導體積體電路(IC)產業已經歷快速增長。在IC演進之過程中，功能密度(即，每晶片面積之互連裝置之數目)一般已增大，而幾何大小(即，可使用一製程產生之最小組件(或線))已減小。此按比例縮小程序一般藉由提高生產效率及降低相關聯成本來提供益處。此按比例縮小亦增加處理及製造IC之複雜性，且為實現此等進步，需要IC製造之類似發展。The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the process of IC evolution, the functional density (ie, the number of interconnected devices per chip area) has generally increased, and the geometric size (ie, the smallest component (or line) that can be produced using a process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing ICs, and to achieve these advancements, similar developments in IC manufacturing are required.

例如，已利用極紫外光(EUV)微影來支援更小裝置之臨界尺寸(CD)要求。EUV微影採用掃描儀以使用EUV區域中具有約1 nm至約100 nm之一波長之輻射。除EUV掃描儀使用反射而非折射光學器件(例如反射鏡而非透鏡)之外，類似於一些光學掃描儀，一些EUV掃描儀提供4x縮小投影印刷。用於EUV微影中之光罩提出新挑戰。例如，一些EUV光罩在一反射多層(ML)上方使用一圖案化吸收劑，其中吸收劑吸收EUV光且ML反射EUV光以藉此產生一圖案化EUV輻射用於EUV微影。歸因於對蝕刻選擇性、側壁輪廓、線性度等等之嚴格要求，圖案化吸收劑可能較困難。此外，吸收劑在曝露期間引起一些EUV能量損失，其降低EUV晶圓每小時(WPH, wafer per hour)通量。此外，吸收EUV光加熱EUV光罩。為此，一些EUV光罩有時必須離線用於冷卻，其進一步降低EUV WPH通量。因此，儘管既有微影方法一般已足夠，但其非所有方面都令人滿意。For example, extreme ultraviolet (EUV) lithography has been used to support the critical dimension (CD) requirements of smaller devices. EUV lithography uses a scanner to use radiation with a wavelength of about 1 nm to about 100 nm in the EUV region. Except that EUV scanners use reflective rather than refractive optics (such as mirrors instead of lenses), similar to some optical scanners, some EUV scanners provide 4x reduced projection printing. The mask used in EUV lithography presents new challenges. For example, some EUV masks use a patterned absorber over a reflective multilayer (ML), where the absorber absorbs EUV light and the ML reflects EUV light to thereby generate a patterned EUV radiation for EUV lithography. Due to strict requirements on etch selectivity, sidewall profile, linearity, etc., patterning the absorber may be difficult. In addition, the absorber causes some EUV energy loss during exposure, which reduces EUV wafer per hour (WPH, wafer per hour) flux. In addition, the EUV mask is heated by absorbing EUV light. For this reason, some EUV masks must sometimes be used offline for cooling, which further reduces EUV WPH flux. Therefore, although existing lithography methods are generally sufficient, they are not satisfactory in all aspects.

根據本發明之一實施例，一種EUV微影光罩包括：一低熱膨脹材料之一基板；一第一反射多層，其在該基板上方；及一圖案化反射多層，其在該第一反射多層上方，其中該圖案化反射多層包含穿過該圖案化反射多層之溝槽，且該第一反射多層及該圖案化反射多層之各者包含一膜對堆疊。According to an embodiment of the present invention, an EUV lithography photomask includes: a substrate with a low thermal expansion material; a first reflective multilayer on the substrate; and a patterned reflective multilayer on the first reflective multilayer Above, the patterned reflective multilayer includes a trench passing through the patterned reflective multilayer, and each of the first reflective multilayer and the patterned reflective multilayer includes a film pair stack.

根據本發明之一實施例，一種製造一EUV微影光罩之方法包括：接收一結構，該結構具有一低熱膨脹材料之一基板、該基板上方之一第一反射多層、該第一反射多層上方之一蝕刻停止層、該蝕刻停止層上方之一第二反射多層及該第二反射多層上方之一覆蓋層；在該覆蓋層上方形成一圖案化光阻劑；透過該圖案化光阻劑蝕刻該覆蓋層及該第二反射多層，直至曝露該蝕刻停止層；及移除該圖案化光阻劑。According to an embodiment of the present invention, a method of manufacturing an EUV lithography photomask includes: receiving a structure having a substrate with a low thermal expansion material, a first reflective multilayer above the substrate, and the first reflective multilayer An upper etch stop layer, a second reflective multilayer above the etch stop layer, and a cover layer above the second reflective multilayer; a patterned photoresist is formed on the cover layer; the patterned photoresist is transmitted through Etching the covering layer and the second reflective multilayer until the etching stop layer is exposed; and removing the patterned photoresist.

根據本發明之一實施例，一種製造一EUV微影光罩之方法包括：接收一結構，該結構具有一低熱膨脹材料之一基板及該基板上方之一反射多層；在該反射多層上方形成一圖案化光阻劑；透過該圖案化光阻劑蝕刻該反射多層以形成未完全蝕刻穿過該反射多層之一第一深度之溝槽；及移除該圖案化光阻劑。According to an embodiment of the present invention, a method of manufacturing an EUV lithography photomask includes: receiving a structure having a substrate with a low thermal expansion material and a reflective multilayer on the substrate; and forming a reflective multilayer on the reflective multilayer. Patterning photoresist; etching the reflective multilayer through the patterned photoresist to form a trench that is not completely etched through a first depth of the reflective multilayer; and removing the patterned photoresist.

以下揭露提供用於實施所提供標的之不同特徵之諸多不同實施例或實例。下文將描述組件及配置之特定實例以簡化本揭露。當然，此等僅為實例且不意在限制。例如，在以下描述中，使一第一構件形成於一第二構件上方或一第二構件上可包含其中形成直接接觸之該第一構件及該第二構件之實施例，且亦可包含其中額外構件可形成於該第一構件與該第二構件之間使得該第一構件及該第二構件可不直接接觸之實施例。另外，本揭露可在各種實例中重複元件符號及/或字母。此重複係為了簡單及清楚且其本身不指示所討論之各種實施例及/或組態之間的一關係。The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first member on a second member or on a second member may include an embodiment in which the first member and the second member are in direct contact, and may also include An embodiment in which an additional member may be formed between the first member and the second member so that the first member and the second member may not directly contact. In addition, the present disclosure may repeat element symbols and/or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

此外，為便於描述，諸如「下面」、「下方」、「下」、「上方」、「上」及其類似者之空間相對術語在本文中可用於描述一元件或構件與另一(些)元件或構件之關係，如圖中所繪示。空間相對術語除涵蓋圖中所描繪之定向之外，亦意欲涵蓋裝置在使用或操作中之不同定向。可依其他方式定向設備(旋轉90度或依其他定向)且亦可因此解譯本文中所使用之空間相對描述詞。此外，當用「約」、「大致」及其類似者描述一數目或一數目範圍時，除非另有說明，否則術語涵蓋某些變動(諸如+/-10%)內之數目或根據熟習技術者鑑於本文中所揭露之特定技術之知識所描述之其他數目。例如，術語「約5 nm」涵蓋自4.5 nm至5.5 nm、4.0 nm至5 nm等等之尺寸範圍。In addition, for ease of description, spatially relative terms such as "below", "below", "below", "above", "upper" and the like can be used herein to describe one element or component and another(s) The relationship between elements or components is shown in the figure. In addition to the orientation depicted in the figures, the spatial relative terms are also intended to cover the different orientations of the device in use or operation. The device can be oriented in other ways (rotated by 90 degrees or in other orientations) and the spatial relative descriptors used in this article can also be interpreted accordingly. In addition, when "about", "approximately" and the like are used to describe a number or a range of numbers, unless otherwise specified, the term covers the number within certain variations (such as +/-10%) or is based on familiar techniques In view of the other numbers described in the knowledge of the specific technology disclosed in this article. For example, the term "about 5 nm" covers the size range from 4.5 nm to 5.5 nm, 4.0 nm to 5 nm, and so on.

本申請案係關於一種半導體製程及其結構，且更特定言之，本申請案係關於一種新穎EUV (極紫外光)光罩。如上文所討論，一些EUV光罩在一反射多層(ML)上方使用一圖案化吸收劑。此類型之EUV光罩指稱二元EUV光罩。存在與圖案化吸收劑有關之問題。例如，一般難以精確蝕刻一吸收劑以產生理想光罩圖案。而且，一吸收劑給EUV光罩帶來額外EUV能量損失及額外熱，該兩者降低EUV WPH通量。本揭露之一般目的包含製造無圖案化吸收劑之一新型EUV光罩。代替地，圖案化一反射多層(ML)以產生用於電路之圖案(或ML圖案)，諸如1維線/空間圖案、2維孔圖案或其他圖案。ML圖案可進一步由一薄覆蓋層覆蓋保護。使用此新型EUV光罩，成像對比度由相位邊緣(ML圖案之邊緣)調變。因此，此新型EUV光罩指稱全反射式相位邊緣光罩或FR-PEM。實驗及模擬表明，在由對比度、ILS (影像對數斜率, Image Log Slope)、NILS (正規化ILS)及/或DoF (聚焦深度, Depth of Focus)量測之成像效能等效之情況下，FR-PEM實現比二元EUV光罩高得多之WPH通量。FR-PEM亦可產生與二元EUV光罩相同或比其更好之成像效能。因此，FR-PEM能夠同時最佳化較高WPH通量及EUV微影成像效能。參考附圖來描述本發明之方法及裝置之細節。This application is related to a semiconductor manufacturing process and its structure, and more specifically, this application is related to a novel EUV (Extreme Ultraviolet) photomask. As discussed above, some EUV masks use a patterned absorber over a reflective multilayer (ML). This type of EUV mask refers to binary EUV mask. There are problems related to patterned absorbents. For example, it is generally difficult to precisely etch an absorbent to produce an ideal mask pattern. Moreover, an absorbent brings extra EUV energy loss and extra heat to the EUV mask, both of which reduce EUV WPH flux. The general purpose of the present disclosure includes manufacturing a new type of EUV mask without patterned absorber. Instead, a reflective multilayer (ML) is patterned to produce a pattern (or ML pattern) for the circuit, such as a 1-dimensional line/space pattern, a 2-dimensional hole pattern, or other patterns. The ML pattern can be further covered and protected by a thin cover layer. Using this new EUV mask, the imaging contrast is adjusted by the phase edge (the edge of the ML pattern). Therefore, this new type of EUV mask is referred to as a total reflection phase edge mask or FR-PEM. Experiments and simulations show that when the imaging performance measured by contrast, ILS (Image Log Slope), NILS (normalized ILS) and/or DoF (Depth of Focus) is equivalent, FR -PEM achieves much higher WPH flux than binary EUV mask. FR-PEM can also produce the same or better imaging performance as the binary EUV mask. Therefore, FR-PEM can optimize both higher WPH flux and EUV lithography imaging performance at the same time. The details of the method and device of the present invention are described with reference to the drawings.

圖1A展示利用根據本發明之一或多個實施例之一FR-PEM用於EUV微影之一EUV微影系統100。系統100包含產生一輻射束104之一輻射源102、聚光光學器件106、一光罩台110上之一光罩108、投影光學器件112及一基板台114上之一基板116。其他組態及物品之包含或省略可為可行的。在本揭露中，系統100可為一步進器或一掃描儀。FIG. 1A shows an EUV lithography system 100 using an FR-PEM according to one or more embodiments of the present invention for EUV lithography. The system 100 includes a radiation source 102 that generates a radiation beam 104, a condensing optics 106, a mask 108 on a mask stage 110, a projection optics 112, and a substrate 116 on a substrate stage 114. The inclusion or omission of other configurations and items may be feasible. In this disclosure, the system 100 can be a stepper or a scanner.

輻射源102提供具有EUV範圍(諸如約1 nm至約100 nm)內之一波長之輻射束104。在一實施例中，輻射束104具有約13.5 nm之一波長。聚光光學器件106包含一多層塗覆收集器及複數個掠射鏡。聚光光學器件106經組態以收集及塑形輻射束104且將輻射束104之一狹縫提供至光罩108。光罩108 (亦指稱一光罩(photomask)或一倍縮光罩)包含一或多個目標IC裝置之圖案。光罩108將一圖案化空中影像提供至輻射束104。在本實施例中，光罩108係一反射光罩，尤其為一全反射式相位邊緣光罩或FR-PEM，如下文將進一步詳細描述。因此，其亦指稱FR-PEM 108。光罩108可併入諸如光學鄰近校正(OPC)之其他解析度提高技術。光罩台110 (諸如)藉由真空將光罩108固定於其上，且在EUV微影系統100中之對準、聚焦、調平及曝露操作期間提供光罩108之準確定位及移動。The radiation source 102 provides a radiation beam 104 having a wavelength in the EUV range (such as about 1 nm to about 100 nm). In one embodiment, the radiation beam 104 has a wavelength of about 13.5 nm. The condensing optical device 106 includes a multilayer coating collector and a plurality of grazing mirrors. The condensing optics 106 are configured to collect and shape the radiation beam 104 and provide a slit of the radiation beam 104 to the mask 108. The photomask 108 (also referred to as a photomask or a double-reduction photomask) contains the pattern of one or more target IC devices. The mask 108 provides a patterned aerial image to the radiation beam 104. In this embodiment, the photomask 108 is a reflective photomask, especially a total reflection type phase edge photomask or FR-PEM, which will be described in further detail below. Therefore, it is also referred to as FR-PEM 108. The mask 108 may incorporate other resolution enhancement technologies such as optical proximity correction (OPC). The mask stage 110, such as by vacuum, fixes the mask 108 thereon, and provides accurate positioning and movement of the mask 108 during the alignment, focusing, leveling, and exposure operations in the EUV lithography system 100.

投影光學器件112包含一或多個透鏡及複數個反射鏡。透鏡可具有小於1之一放大率以藉此減小光罩108至基板116之圖案化空中影像。基板116包含具有對輻射束104敏感之一光阻層之一半導體晶圓(或一晶圓)。基板116由基板台114固定，基板台114在EUV微影系統100中之對準、聚焦、調平及曝露操作期間提供基板116之準確定位及移動，使得光罩108之圖案化空中影像依一重複方式曝露至基板116上(但其他微影方法係可行的)。The projection optics 112 includes one or more lenses and a plurality of mirrors. The lens may have a magnification of less than 1 to thereby reduce the patterned aerial image from the mask 108 to the substrate 116. The substrate 116 includes a semiconductor wafer (or a wafer) having a photoresist layer that is sensitive to the radiation beam 104. The substrate 116 is fixed by the substrate stage 114. The substrate stage 114 provides accurate positioning and movement of the substrate 116 during the alignment, focusing, leveling, and exposure operations of the EUV lithography system 100, so that the patterned aerial image of the photomask 108 is aligned. Exposure to the substrate 116 is repeated in a repeated manner (but other lithography methods are possible).

輻射源102可包含經組態以在空間頻率上匹配FR-PEM 108中之圖案之源光瞳。例如，輻射源102可包含雙極照明以使一FR-PEM 108與1維線/空間圖案匹配。圖1B中展示一雙極照明源102之一實例。圖1B中亦展示具有交替配置之線圖案108a及空間108b之一FR-PEM 108之一俯視圖。舉另一實例而言，輻射源102可包含四極照明以使一FR-PEM 108與2維孔陣列圖案匹配。圖1C中展示四極照明源102之一實例。圖1C中亦展示具有由列及行中之空間108d分離之一島108c陣列之一FR-PEM 108之一俯視圖。應注意，鑑於一微影投影系統中之縮小因數(例如，自一光罩特徵至一光阻特徵縮小4倍)，圖1B及圖1C中所展示之FR-PEM 108之俯視圖可大致相同於已形成於或將形成於基板116上之一光阻層中之一目標圖案之一俯視圖。舉又一實例而言，輻射源102可包含六極照明，圖1D中展示其之一實例。已展示具有一頻率匹配源光瞳以增大光罩108上之ML圖案之蝕刻深度變動之錯誤容限。在一些實施例中，ML圖案(例如圖2、圖3及圖4中之ML圖案374)可高度變動+/-2 nm或+/-3 nm且仍分別達成晶圓影像CD (臨界尺寸)變動約0.3 nm及約0.5 nm。此CD變動對(例如)約12.5 nm之一CD目標而言一般係可接受的。The radiation source 102 may include a source pupil configured to match the pattern in the FR-PEM 108 in spatial frequency. For example, the radiation source 102 may include bipolar illumination to match an FR-PEM 108 to a 1-dimensional line/space pattern. An example of a bipolar illumination source 102 is shown in FIG. 1B. FIG. 1B also shows a top view of a FR-PEM 108 having alternately arranged line patterns 108a and spaces 108b. As another example, the radiation source 102 may include quadrupole illumination to match an FR-PEM 108 to a 2-dimensional hole array pattern. An example of the quadrupole illumination source 102 is shown in FIG. 1C. 1C also shows a top view of an FR-PEM 108 having an array of islands 108c separated by spaces 108d in columns and rows. It should be noted that in view of the reduction factor in a lithographic projection system (for example, a 4 times reduction from a mask feature to a photoresist feature), the top view of the FR-PEM 108 shown in FIG. 1B and FIG. 1C may be approximately the same as A top view of a target pattern in a photoresist layer that has been or will be formed on the substrate 116. As another example, the radiation source 102 may include hexapole illumination, an example of which is shown in FIG. 1D. It has been shown to have a frequency-matched source pupil to increase the error tolerance of the variation of the etching depth of the ML pattern on the mask 108. In some embodiments, the ML pattern (such as ML pattern 374 in FIG. 2, FIG. 3, and FIG. 4) can vary in height by +/- 2 nm or +/- 3 nm and still achieve wafer image CD (critical dimension) respectively The variation is about 0.3 nm and about 0.5 nm. This CD variation is generally acceptable for, for example, a CD target of about 12.5 nm.

在使基板116曝露於輻射束104之後，將其移動至一顯影劑，其中基於區域是否曝露於輻射束104來移除基板116之光阻層之區域以藉此將圖案自光罩108轉印至基板116。在一些實施例中，一顯影劑包含一水基顯影劑，諸如用於一正性顯影(PTD)之氫氧化四甲基銨(TMAH)。在其他實施例中，一顯影劑可包含用於一負性顯影(NTD)之一有機溶劑或有機溶劑之一混合物，諸如甲基a-戊基酮(MAK)或涉及MAK之一混合物。施加一顯影劑包含(例如)藉由一旋塗程序將一顯影劑噴塗於曝露光阻膜上。施加一顯影劑亦包含使用一曝露後烘烤(PEB)程序、一顯影後烘烤(PDB)程序或其等之一組合。顯影或圖案化光阻層用於進一步處理基板116以形成目標IC裝置。例如，可使用圖案化光阻層作為一蝕刻光罩來蝕刻基板116之一或多個層以形成電路特徵。After exposing the substrate 116 to the radiation beam 104, it is moved to a developer, wherein the area of the photoresist layer of the substrate 116 is removed based on whether the area is exposed to the radiation beam 104 to thereby transfer the pattern from the photomask 108 To substrate 116. In some embodiments, a developer includes a water-based developer, such as tetramethylammonium hydroxide (TMAH) for a positive developing (PTD). In other embodiments, a developer may include an organic solvent or a mixture of organic solvents for a negative development (NTD), such as methyl a-pentyl ketone (MAK) or a mixture involving MAK. Applying a developer includes, for example, spraying a developer on the exposed photoresist film by a spin coating process. Applying a developer also includes using a post-exposure bake (PEB) process, a post-development bake (PDB) process, or a combination thereof. The developed or patterned photoresist layer is used to further process the substrate 116 to form the target IC device. For example, the patterned photoresist layer can be used as an etching mask to etch one or more layers of the substrate 116 to form circuit features.

圖2提供沿圖1B之A-A線或圖1C之A-A線取得之光罩108之一橫截面圖。參考圖2，光罩108包含一材料層310、放置於材料層310上方之一反射多層(ML) 320及放置於反射ML 320上方之一圖案化ML 370。另外，在一些實施例中，為了靜電吸附，一導電層305可放置於材料層310下方。在一實施例中，導電層305包含氮化鉻(CrN)。在另一實施例中，導電層305包含約60 nm至約80 nm之硼化鉭(TaB)。光罩108中之其他組態及各種物品之包含或省略可為可行的。FIG. 2 provides a cross-sectional view of the mask 108 taken along the line A-A of FIG. 1B or the line A-A of FIG. 1C. 2, the photomask 108 includes a material layer 310, a reflective multilayer (ML) 320 placed above the material layer 310, and a patterned ML 370 placed above the reflective ML 320. In addition, in some embodiments, for electrostatic adsorption, a conductive layer 305 may be placed under the material layer 310. In one embodiment, the conductive layer 305 includes chromium nitride (CrN). In another embodiment, the conductive layer 305 includes about 60 nm to about 80 nm of tantalum boride (TaB). Other configurations in the mask 108 and the inclusion or omission of various items may be feasible.

材料層310包含用於使歸因於由增強EUV輻射引起之光罩加熱之影像失真最小化之一低熱膨脹材料(LTEM)。因此，材料層310亦指稱一LTEM層310或一LTEM基板310。LTEM層310可包含熔融二氧化矽、熔融石英、氟化鈣(CaF₂ )、碳化矽、氧化矽-氧化鈦合金及/或其他適合低熱膨脹材料。The material layer 310 includes a low thermal expansion material (LTEM) for minimizing image distortion due to the heating of the mask caused by enhanced EUV radiation. Therefore, the material layer 310 is also referred to as an LTM layer 310 or an LTM substrate 310. The LTEM layer 310 may include fused silica, fused silica, calcium fluoride (CaF ₂ ), silicon carbide, silicon oxide-titanium oxide alloy, and/or other suitable low thermal expansion materials.

反射多層(ML) 320放置於LTEM層310上方。ML 320包含複數個膜對，諸如鉬-矽(Mo/Si)膜對(例如各膜對中一矽層上方或下方之一鉬層)。替代地，ML 320可包含鉬-鈹(Mo/Be)膜對或具有大折射率差或小消光係數之任何兩個材料或兩材料組合。ML 320之各層之厚度取決於EUV輻射104之波長及一入射角。針對一指定入射角，ML 320之各層之厚度可經調整以達成對在ML 320之不同界面處反射之輻射之最大相長干涉。膜對之一典型數目係20至80，但任何數目個膜對係可行的。在一實施例中，ML 320包含40對Mo/Si層。各Mo/Si膜對具有約7 nm之一厚度，例如Mo約3 nm及Si約4 nm。在此情況中，達成約70%之一反射率。A reflective multilayer (ML) 320 is placed above the LEM layer 310. The ML 320 includes a plurality of film pairs, such as molybdenum-silicon (Mo/Si) film pairs (for example, a molybdenum layer above or below a silicon layer in each film pair). Alternatively, the ML 320 may include a molybdenum-beryllium (Mo/Be) film pair or any two materials or a combination of two materials with a large refractive index difference or a small extinction coefficient. The thickness of each layer of ML 320 depends on the wavelength of EUV radiation 104 and an incident angle. For a specified incident angle, the thickness of each layer of ML 320 can be adjusted to achieve the maximum constructive interference of radiation reflected at different interfaces of ML 320. A typical number of film pairs is 20 to 80, but any number of film pairs is possible. In one embodiment, ML 320 includes 40 pairs of Mo/Si layers. Each Mo/Si film pair has a thickness of about 7 nm, for example, about 3 nm for Mo and about 4 nm for Si. In this case, a reflectivity of about 70% is achieved.

圖案化ML 370放置於反射ML 320上方。圖案化ML 370亦包含複數個膜對，諸如鉬-矽(Mo/Si)膜對、鉬-鈹(Mo/Be)膜對或具有大折射率差及小消光係數之任何兩個材料或兩材料組合。在一實施例中，圖案化ML 370包含相同於ML 320之材料，但具有比ML 320少之膜對數目。在另一實施例中，圖案化ML 370包含不同於ML 320之材料。例如，圖案化ML 370可包含Mo/Si膜對，而ML 320包含Mo/Be膜對，或反之亦然。The patterned ML 370 is placed above the reflective ML 320. The patterned ML 370 also includes a plurality of film pairs, such as molybdenum-silicon (Mo/Si) film pairs, molybdenum-beryllium (Mo/Be) film pairs, or any two materials or two materials with a large refractive index difference and a small extinction coefficient. Material combination. In one embodiment, patterned ML 370 includes the same material as ML 320, but has a smaller number of film pairs than ML 320. In another embodiment, patterned ML 370 includes a different material than ML 320. For example, patterned ML 370 may include Mo/Si film pairs, while ML 320 includes Mo/Be film pairs, or vice versa.

如圖2中所展示，圖案化ML 370包含由溝槽372分離之脊374。脊374亦指稱ML圖案374。輻射束104由ML圖案374及ML 320兩者透過溝槽372反射。針對負性光罩及晶圓圖案化程序，脊374對應於圖1B中之線108a或圖1C中之島108c，且溝槽372對應於圖1B中之空間108b或圖1C中之間隔列/行108d。針對正性光罩及晶圓圖案化程序，溝槽372對應於圖1B中之線108a或圖1C中之島108c，且脊374對應於圖1B中之空間108b或圖1C中之間隔列/行108d。由ML圖案374反射之輻射束104及由ML 320反射之輻射束104具有不同相位。此相位差在一晶圓影像中產生對比度。特定言之，當跨ML圖案374之邊緣轉變時，相位差最大。此不同於具有一圖案化吸收劑之二元EUV光罩，其中圖案化吸收劑吸收而非反射輻射束104。本實施例之光罩108之一優點係其比二元EUV光罩吸收更少EUV能量且反射更多EUV能量。因此，使用光罩108比使用二元EUV光罩更多反射EUV能量朝向晶圓116 (圖1A)上之光阻層以增加WPH通量。而且，由於光罩108比二元EUV光罩吸收更少EUV能量，因此其比二元EUV光罩產生更少熱且可工作更長壽命。As shown in FIG. 2, patterned ML 370 includes ridges 374 separated by trenches 372. The ridge 374 is also referred to as the ML pattern 374. The radiation beam 104 is reflected by both the ML pattern 374 and the ML 320 through the groove 372. For the negative mask and wafer patterning process, the ridge 374 corresponds to the line 108a in FIG. 1B or the island 108c in FIG. 1C, and the groove 372 corresponds to the space 108b in FIG. 1B or the space 108b in FIG. . For the positive mask and wafer patterning process, the trench 372 corresponds to the line 108a in FIG. 1B or the island 108c in FIG. 1C, and the ridge 374 corresponds to the space 108b in FIG. 1B or the space 108b in FIG. . The radiation beam 104 reflected by the ML pattern 374 and the radiation beam 104 reflected by the ML 320 have different phases. This phase difference produces contrast in a wafer image. In particular, when transitioning across the edge of the ML pattern 374, the phase difference is the largest. This is different from a binary EUV mask with a patterned absorber, where the patterned absorber absorbs rather than reflects the radiation beam 104. One of the advantages of the photomask 108 of this embodiment is that it absorbs less EUV energy and reflects more EUV energy than a binary EUV photomask. Therefore, using the photomask 108 reflects more EUV energy toward the photoresist layer on the wafer 116 (FIG. 1A) than using a binary EUV photomask to increase the WPH flux. Moreover, since the photomask 108 absorbs less EUV energy than the binary EUV photomask, it generates less heat and can work longer than the binary EUV photomask.

在一些實施例中，溝槽372之寬度Wl取決於目標IC佈局設計且可在約20 nm至約120 nm之一範圍內，諸如自約40 nm至約90 nm。在一些實施例中，基於寬度W1調諧ML 370之厚度H1 (H1亦係ML圖案374之高度或溝槽372之深度)以達成(諸如)由成像對比度及/或ILS量測之特定成像品質。例如，當W1在50 nm至90 nm之範圍內時，可在約20 nm至約160 nm之一範圍內調諧H1，諸如自約60 nm至約 120nm。當H1超出上述(若干)範圍時，光罩108無法達成一可接受成像對比度及/或ILS。如上文所討論，H1可在溝槽327之間變動數奈米(諸如+/-2 nm或+/-3 nm)且仍達成可接受晶圓影像CD變動。此放寬溝槽蝕刻要求且係本發明之又一優點。In some embodiments, the width W1 of the trench 372 depends on the target IC layout design and may be in a range of about 20 nm to about 120 nm, such as from about 40 nm to about 90 nm. In some embodiments, the thickness H1 of the ML 370 (H1 is also the height of the ML pattern 374 or the depth of the groove 372) is tuned based on the width W1 to achieve a specific imaging quality measured by imaging contrast and/or ILS, for example. For example, when W1 is in the range of 50 nm to 90 nm, H1 can be tuned in a range of about 20 nm to about 160 nm, such as from about 60 nm to about 120 nm. When H1 exceeds the above range(s), the mask 108 cannot achieve an acceptable imaging contrast and/or ILS. As discussed above, H1 can vary several nanometers (such as +/- 2 nm or +/- 3 nm) between trenches 327 and still achieve acceptable wafer image CD variation. This relaxes the trench etching requirements and is another advantage of the present invention.

圖3繪示根據另一實施例之光罩108之一橫截面圖，除添加一覆蓋層330之外，其相同於圖2中之實施例。覆蓋層330亦指稱一保護層330。覆蓋層330放置於ML圖案374之頂面及側壁表面及ML 320曝露於溝槽372中之頂面上方。當光罩108處於一清潔程序中時，覆蓋層330可保護ML 320及ML圖案374免受氧化以藉此增強光罩108之清潔耐久性。覆蓋層330亦可增強光罩108對EUV輻射之耐久性。在一實施例中，覆蓋層330經沈積以在ML 320及ML圖案374之各個表面上具有一實質上均勻厚度。在一些實施例中，覆蓋層330之厚度在約1 nm至約5 nm之一範圍內，諸如約2 nm至約5 nm或約2 nm至約3 nm。若覆蓋層330薄於此範圍(例如，薄於1 nm)，則其一般無法對ML 320及ML圖案374提供足夠保護。若覆蓋層330厚於此範圍(例如，厚於5 nm)，則其對光學成像及WHP通量之負面影響將非常明顯。當覆蓋層330之厚度在以上所揭露之範圍內時，其對光學成像及WHP通量之影響係約-1%至約-2% (如由3D光學模擬所確認)，鑑於其提供之保護，此一般係可接受的。在本實施例中，覆蓋層330包含具有低k (消光係數)之一材料，諸如釕(Ru)、矽(Si)、碳化矽(SiC)、其等之一組合(例如一Si層上方之一Ru層)或其他適合材料。在各種實施例中，可使用ALD、CVD或其他適合方法來沈積覆蓋層330。FIG. 3 shows a cross-sectional view of the photomask 108 according to another embodiment, which is the same as the embodiment in FIG. 2 except that a covering layer 330 is added. The covering layer 330 is also referred to as a protective layer 330. The cover layer 330 is placed on the top surface and the sidewall surface of the ML pattern 374 and the ML 320 is exposed above the top surface in the trench 372. When the photomask 108 is in a cleaning process, the cover layer 330 can protect the ML 320 and the ML pattern 374 from oxidation, thereby enhancing the cleaning durability of the photomask 108. The cover layer 330 can also enhance the durability of the mask 108 to EUV radiation. In one embodiment, the capping layer 330 is deposited to have a substantially uniform thickness on each surface of the ML 320 and the ML pattern 374. In some embodiments, the thickness of the cover layer 330 is in a range of about 1 nm to about 5 nm, such as about 2 nm to about 5 nm or about 2 nm to about 3 nm. If the cover layer 330 is thinner than this range (for example, thinner than 1 nm), it generally cannot provide sufficient protection for the ML 320 and the ML pattern 374. If the cover layer 330 is thicker than this range (for example, thicker than 5 nm), its negative impact on optical imaging and WHP flux will be very obvious. When the thickness of the cover layer 330 is within the range disclosed above, its influence on optical imaging and WHP flux is about -1% to about -2% (as confirmed by 3D optical simulation), given the protection it provides , This is generally acceptable. In this embodiment, the cover layer 330 includes a material with a low k (extinction coefficient), such as ruthenium (Ru), silicon (Si), silicon carbide (SiC), a combination thereof (for example, a layer above a Si) One Ru layer) or other suitable materials. In various embodiments, the capping layer 330 may be deposited using ALD, CVD, or other suitable methods.

圖4繪示根據又一實施例之光罩108之一橫截面圖，其類似於圖2中之實施例且具有額外特徵。如所繪示，光罩108包含ML 320及圖案化ML 370。光罩108進一步包含一蝕刻停止層325及一覆蓋層330。蝕刻停止層325放置於ML 320與圖案化ML 370之間。特定言之，溝槽372曝露蝕刻停止層325且不曝露ML 320。覆蓋層330放置於ML圖案374之頂面上。在本實施例中，覆蓋層330不放置於ML圖案374之側壁表面上。蝕刻停止層325具有不同於ML 370之蝕刻特性且在ML 370之一圖案化或修復程序中充當一蝕刻停止層。在本實施例中，蝕刻停止層325包含具有低k (消光係數)之一材料，諸如釕(Ru)、矽(Si)、碳化矽(SiC)、其等之一組合或其他適合材料。在一實施例中，蝕刻停止層325可具有約1 nm至約8 nm之範圍內之一厚度，諸如約2 nm至約5 nm。在一實施例中，蝕刻停止層325包含一Si層上方之一Ru層。Ru層可具有約2 nm至約4 nm之一厚度，諸如3.5 nm。Si層可具有約2 nm至約4 nm之一厚度，諸如3.5 nm。層325之厚度經設計以達成其蝕刻停止功能，但對成像品質無太多負面影響。若層325薄於上述範圍(例如薄於1 nm)，則其一般無法提供預期蝕刻停止功能。若層325厚於上述範圍(例如厚於8nm)，則其對光學成像及WHP通量之負面影響將非常明顯。覆蓋層330可具有上文參考圖3所討論之一組成及厚度。當層325及330之厚度在上文所揭露之範圍內時，其對光學成像及WHP通量之影響係約-1%至約-2% (如由3D光學模擬所確認)，鑑於其提供之功能，此一般係可接受的。FIG. 4 shows a cross-sectional view of a photomask 108 according to another embodiment, which is similar to the embodiment in FIG. 2 and has additional features. As shown, the photomask 108 includes ML 320 and patterned ML 370. The photomask 108 further includes an etch stop layer 325 and a cover layer 330. The etch stop layer 325 is placed between the ML 320 and the patterned ML 370. In particular, the trench 372 exposes the etch stop layer 325 and does not expose the ML 320. The cover layer 330 is placed on the top surface of the ML pattern 374. In this embodiment, the cover layer 330 is not placed on the sidewall surface of the ML pattern 374. The etch stop layer 325 has different etching characteristics from the ML 370 and serves as an etch stop layer in one of the patterning or repair procedures of the ML 370. In this embodiment, the etch stop layer 325 includes a material with low k (extinction coefficient), such as ruthenium (Ru), silicon (Si), silicon carbide (SiC), a combination thereof, or other suitable materials. In an embodiment, the etch stop layer 325 may have a thickness in the range of about 1 nm to about 8 nm, such as about 2 nm to about 5 nm. In one embodiment, the etch stop layer 325 includes a Ru layer above a Si layer. The Ru layer may have a thickness from about 2 nm to about 4 nm, such as 3.5 nm. The Si layer may have a thickness from about 2 nm to about 4 nm, such as 3.5 nm. The thickness of the layer 325 is designed to achieve its etch stop function, but does not have much negative impact on the image quality. If the layer 325 is thinner than the above range (for example, thinner than 1 nm), it generally cannot provide the expected etch stop function. If the layer 325 is thicker than the above range (for example, thicker than 8 nm), its negative impact on optical imaging and WHP flux will be very obvious. The cover layer 330 may have a composition and thickness discussed above with reference to FIG. 3. When the thicknesses of layers 325 and 330 are within the range disclosed above, their impact on optical imaging and WHP flux is about -1% to about -2% (as confirmed by 3D optical simulation), in view of the fact that they provide This function is generally acceptable.

層305、310、320、370、325及330之各者可由包含以下各者之各種方法形成：物理汽相沈積(PVD)程序(諸如蒸鍍及DC磁控濺鍍)、一鍍覆程序(諸如無電極鍍覆或電鍍)、一化學汽相沈積(CVD)程序(諸如大氣壓CVD (APCVD)、低壓CVD (LPCVD)、電漿增強CVD (PECVD)或高密度電漿CVD (HDP CVD))、原子層沈積(ALD)、離子束沈積及/或其他方法。Each of the layers 305, 310, 320, 370, 325, and 330 can be formed by various methods including the following: physical vapor deposition (PVD) processes (such as evaporation and DC magnetron sputtering), a plating process ( (Such as electrodeless plating or electroplating), a chemical vapor deposition (CVD) process (such as atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD) or high density plasma CVD (HDP CVD)) , Atomic Layer Deposition (ALD), Ion Beam Deposition and/or other methods.

實驗及模擬表明，FR-PEM光罩108 (諸如圖2、圖3及圖4中所展示之實施例)實現比具有等效成像效能之二元光罩高得多之WPH通量。在一實驗中，一雙極照明源(諸如圖1B中之雙極照明源102)用於產生具有一節距25 nm (例如線寬12.5 nm及空間寬度12.5 nm)之一目標線/空間圖案。源光瞳根據2光束干涉之等焦條件最佳化：

在由成像對比度、ILS、NILS及DoF量測之成像品質等效之情況下，使用二元EUV光罩所需之一EUV能量劑量比使用FR-PEM 108所需之一EUV能量劑量多約2.569倍。換言之，使用FR-PEM 108使WPH通量比使用二元EUV光罩加速2.569倍。此外，FR-PEM 108提供比二元EUV光罩高之錯誤容限，如由掃描狹縫中心邊緣ΔCD減小約2倍及MEEF (光罩錯誤提高因數)減小約4倍至約5倍所證明。Experiments and simulations show that the FR-PEM mask 108 (such as the embodiments shown in FIG. 2, FIG. 3, and FIG. 4) achieves a much higher WPH flux than a binary mask with equivalent imaging performance. In an experiment, a bipolar illumination source (such as the bipolar illumination source 102 in FIG. 1B) was used to generate a target line/space pattern with a pitch of 25 nm (for example, a line width of 12.5 nm and a space width of 12.5 nm). The source pupil is optimized according to the isofocal condition of 2 beam interference:

When the imaging quality measured by imaging contrast, ILS, NILS and DoF is equivalent, the EUV energy dose required to use a binary EUV mask is about 2.569 more than the EUV energy dose required to use FR-PEM 108 Times. In other words, using FR-PEM 108 makes WPH flux faster than using a binary EUV mask by 2.569 times. In addition, FR-PEM 108 provides higher error tolerance than binary EUV masks, such as the reduction of ΔCD from the center edge of the scanning slit by about 2 times and the reduction of MEEF (mask error enhancement factor) by about 4 times to about 5 times. Proved.

在另一實驗中，四極照明源(諸如圖1C中之四極照明源102)用於產生具有一間距25 nm (例如島寬12.5 nm及空間寬度12.5 nm)之一目標2維孔/陣列圖案。源光瞳根據2光束干涉之等焦條件最佳化：

在由成像對比度、ILS、NILS及DoF量測之成像品質等效之情況下，使用二元EUV光罩所需之一EUV能量劑量比使用FR-PEM 108所需之一EUV能量劑量多約1.83倍。換言之，使用FR-PEM 108使WPH通量比使用二元EUV光罩加速1.83倍。類似於第一實驗，FR-PEM 108提供比二元EUV光罩高之錯誤容限，如由掃描狹縫中心邊緣ΔCD減小約2倍及MEEF減小約4倍至約5倍所證明。In another experiment, a quadrupole illumination source (such as the quadrupole illumination source 102 in FIG. 1C) was used to generate a target 2-dimensional hole/array pattern with a pitch of 25 nm (for example, an island width of 12.5 nm and a spatial width of 12.5 nm). The source pupil is optimized according to the isofocal condition of 2 beam interference:

When the imaging quality measured by imaging contrast, ILS, NILS and DoF is equivalent, the EUV energy dose required to use a binary EUV mask is about 1.83 more than the EUV energy dose required to use FR-PEM 108 Times. In other words, the use of FR-PEM 108 accelerates the WPH flux by 1.83 times compared to the use of a binary EUV mask. Similar to the first experiment, the FR-PEM 108 provides a higher error tolerance than the binary EUV mask, as evidenced by the reduction of the center edge of the scanning slit ΔCD by about 2 times and the reduction of MEEF by about 4 times to about 5 times.

在又一實驗中，六極照明源(諸如圖1D中之六極照明源102)用於產生具有節距25 nm、37 nm及50 nm之目標圖案。源光瞳根據等焦條件最佳化：

在由成像對比度、ILS、NILS及DoF量測之成像品質等效之情況下，使用二元EUV光罩所需之一EUV能量劑量比使用FR-PEM 108所需之一EUV能量劑量多約2.27倍。換言之，使用FR-PEM 108使WPH通量比與使用二元EUV光罩加速2.27倍。類似於前兩個實驗，FR-PEM 108一般提供比二元EUV光罩高之錯誤容限。In another experiment, a hexapole illumination source (such as the hexapole illumination source 102 in FIG. 1D) was used to generate target patterns with pitches of 25 nm, 37 nm, and 50 nm. The source pupil is optimized according to isofocal conditions:

When the imaging quality measured by imaging contrast, ILS, NILS and DoF is equivalent, the EUV energy dose required to use a binary EUV mask is about 2.27 more than the EUV energy dose required to use FR-PEM 108 Times. In other words, the use of FR-PEM 108 accelerates WPH flux by 2.27 times compared with the use of a binary EUV mask. Similar to the first two experiments, FR-PEM 108 generally provides higher error tolerance than binary EUV masks.

可調諧使用FR-PEM 108之一系統(諸如系統100)以同時最佳化成像品質及較高WPH通量兩者。例如，就上文所討論之雙極照明源及四極照明源而言，實驗已表明，使用FR-PEM 108具有比使用二元EUV光罩提高約1.3倍至約1.5倍之WPH通量及更佳成像品質。使用六極照明源已觀察到類似結果。One system of FR-PEM 108 (such as system 100) can be tuned to optimize both imaging quality and higher WPH throughput at the same time. For example, with regard to the bipolar illumination source and the quadrupole illumination source discussed above, experiments have shown that the use of FR-PEM 108 has a WPH flux that is about 1.3 times to about 1.5 times higher than that of a binary EUV mask. Good imaging quality. Similar results have been observed using a hexapole illumination source.

圖5繪示形成一FR-PEM光罩108，特定言之，圖2及圖3中所展示之光罩108之實施例，之一方法400。下文將結合圖6A至圖6E描述方法400。FIG. 5 shows a method 400 of forming an FR-PEM mask 108, in particular, the embodiment of the mask 108 shown in FIG. 2 and FIG. 3. The method 400 will be described below in conjunction with FIGS. 6A to 6E.

在操作402，方法400 (圖5)接收一結構300，如圖6A中所展示。結構300包含一LTEM基板310、放置於LTEM 310上方之一ML 320及放置於ML 320上方之一ML 370。結構300進一步包含放置於LTEM基板310下方之一導電層305。上文已參考圖2討論層305、310、320及370之組成。特定言之，在各種實施例中，ML 320及ML 370可包含相同材料或不同材料。In operation 402, the method 400 (FIG. 5) receives a structure 300, as shown in FIG. 6A. The structure 300 includes an LEM substrate 310, an ML 320 placed above the LEM 310, and an ML 370 placed above the ML 320. The structure 300 further includes a conductive layer 305 placed under the LEM substrate 310. The composition of layers 305, 310, 320, and 370 has been discussed above with reference to FIG. 2. In particular, in various embodiments, ML 320 and ML 370 may include the same material or different materials.

在操作404，方法400 (圖5)在ML 370上方形成一光阻圖案(或一圖案化光阻劑) 352，諸如圖6B中所展示。光阻圖案352提供曝露ML 370之開口354。在一實施例中，操作402包含光阻劑塗覆(例如旋塗塗覆)、軟烘烤、曝露、曝露後烘烤、光阻劑顯影、沖洗、乾燥(例如硬烘烤)、其他適合程序及/或其等之組合。曝露由電子束直接寫入、多電子束直接寫入或使用一光學寫入器完成。電子束寫入程序可以一光柵掃描模式或一向量掃描模式實施。電子束可為高斯(Gaussian)束或成形束。At operation 404, the method 400 (FIG. 5) forms a photoresist pattern (or a patterned photoresist) 352 over the ML 370, such as shown in FIG. 6B. The photoresist pattern 352 provides an opening 354 exposing the ML 370. In one embodiment, operation 402 includes photoresist coating (such as spin coating), soft baking, exposure, post-exposure baking, photoresist development, rinsing, drying (such as hard baking), and other suitable Programs and/or combinations thereof. Exposure is accomplished by direct writing with electron beams, direct writing with multiple electron beams, or using an optical writer. The electron beam writing process can be implemented in a raster scan mode or a vector scan mode. The electron beam can be a Gaussian beam or a shaped beam.

光阻圖案352可對應於一IC設計佈局中之層之一者。例如，一IC可包含靜態隨機存取記憶體(SRAM)及/或邏輯電路、被動組件(諸如電阻器、電容器及電感器)及主動組件(諸如p型FET (PFET)、n型FET (NFET)、FinFET、奈米線FET、奈米片FET、金屬氧化物半導體場效電晶體(MOSFET)、互補金屬氧化物半導體(CMOS)電晶體、雙極電晶體、高電壓電晶體、高頻電晶體、其他記憶體單元及其等之組合)。圖7A繪示包含具有6個電晶體之一SRAM單元(即，一6T SRAM)之一IC 200之一示意圖。一IC設計佈局包含針對IC (諸如IC 200)設計之各種幾何圖案。幾何圖案對應於組成IC之各種組件之金屬、氧化物或半導體層之圖案。例如，一IC設計佈局之一部分可包含用於主動區域、閘極電極、源極及汲極、一層間互連之金屬線或通路、用於接合墊之開口等等之幾何特徵。一IC設計佈局一般存在於具有幾何圖案資訊之一或多個資料檔(諸如一GDSII檔或DFII檔)中。一IC設計佈局包含多個圖案層，其中各層將圖案化至一光罩(諸如光罩108)上。圖7B中展示一實例IC佈局202，其包含用於閘極(垂直長條)、主動區域(水平長條)、接點(包含Vss、Vcc、BL、BLB、WL)及切割圖案CPO之幾何圖案。圖7B中之佈局202對應於圖7A中之IC設計200。圖7C展示圖7B中之閘極之幾何圖案212。圖7D展示解析度提高(例如)以解決光學鄰近效應(OPC)之後的閘極之幾何圖案。例如，閘極圖案現包含具有擴大端部分242之主圖案222及次解析度側條圖案232。在一實施例中，將圖案222、242及232轉印至光阻圖案352。The photoresist pattern 352 may correspond to one of the layers in an IC design layout. For example, an IC may include static random access memory (SRAM) and/or logic circuits, passive components (such as resistors, capacitors, and inductors), and active components (such as p-type FET (PFET), n-type FET (NFET) ), FinFET, Nanowire FET, Nanochip FET, Metal Oxide Semiconductor Field Effect Transistor (MOSFET), Complementary Metal Oxide Semiconductor (CMOS) Transistor, Bipolar Transistor, High Voltage Transistor, High Frequency Transistor Crystals, other memory cells and their combinations). FIG. 7A shows a schematic diagram of an IC 200 including an SRAM cell with 6 transistors (ie, a 6T SRAM). An IC design layout includes various geometric patterns designed for an IC (such as IC 200). The geometric patterns correspond to the patterns of the metal, oxide, or semiconductor layers that make up the various components of the IC. For example, a portion of an IC design layout may include geometric features for active areas, gate electrodes, source and drain electrodes, metal lines or vias for interconnection between layers, openings for bonding pads, and so on. An IC design layout generally exists in one or more data files (such as a GDSII file or DFII file) with geometric pattern information. An IC design layout includes multiple patterned layers, where each layer will be patterned onto a photomask (such as photomask 108). An example IC layout 202 is shown in FIG. 7B, which includes geometry for gate (vertical strip), active area (horizontal strip), contacts (including Vss, Vcc, BL, BLB, WL) and cutting pattern CPO pattern. The layout 202 in FIG. 7B corresponds to the IC design 200 in FIG. 7A. FIG. 7C shows the geometric pattern 212 of the gate in FIG. 7B. FIG. 7D shows the geometric pattern of the gate after the resolution is increased (for example) to solve the optical proximity effect (OPC). For example, the gate pattern now includes a main pattern 222 having an enlarged end portion 242 and a sub-resolution side strip pattern 232. In one embodiment, the patterns 222, 242, and 232 are transferred to the photoresist pattern 352.

在操作406，方法400 (圖5)使用一蝕刻程序蝕刻ML 370以藉此形成溝槽372，諸如圖6C中所展示。蝕刻程序可包含乾式(電漿)蝕刻、濕式蝕刻及/或其他蝕刻方法。在其中ML 370及ML 320包含不同材料之一實施例中，ML 320可用作一蝕刻停止層以判定何時停止蝕刻。在此實施例中，溝槽372之深度由ML 370之厚度判定。在其中ML 370及ML 320包含相同材料之另一實施例中，可使用一計時器基於一目標溝槽深度來判定何時停止蝕刻，如上文所討論。In operation 406, the method 400 (FIG. 5) uses an etching process to etch the ML 370 to thereby form the trench 372, such as shown in FIG. 6C. The etching process may include dry (plasma) etching, wet etching, and/or other etching methods. In an embodiment where ML 370 and ML 320 comprise different materials, ML 320 can be used as an etch stop layer to determine when to stop etching. In this embodiment, the depth of the trench 372 is determined by the thickness of the ML 370. In another embodiment where ML 370 and ML 320 comprise the same material, a timer can be used to determine when to stop etching based on a target trench depth, as discussed above.

在操作408，方法400 (圖5)(例如)藉由光阻劑剝離來移除光阻圖案352。圖6D中展示所得結構300，其變成上文參考圖2所討論之光罩108之一實施例。操作408可對結構300執行額外清潔程序。In operation 408, the method 400 (FIG. 5) (for example) removes the photoresist pattern 352 by photoresist stripping. The resulting structure 300 is shown in FIG. 6D, which becomes an embodiment of the photomask 108 discussed above with reference to FIG. 2. Operation 408 may perform additional cleaning procedures on the structure 300.

在操作410，方法400 (圖5)在ML 320及ML 370上方沈積覆蓋層330，諸如圖6E中所展示。上文已參考圖3討論覆蓋層330之組成及厚度。特定言之，在本實施例中，覆蓋層330沿各個表面沈積至一實質上均勻厚度。可使用ALD、CVD或其他適合方法來沈積覆蓋層330。此導致上文參考圖3所討論之光罩108之一實施例。在方法400之一些實施例中，操作410係選用的且可省略。At operation 410, the method 400 (FIG. 5) deposits a capping layer 330 over the ML 320 and ML 370, such as shown in FIG. 6E. The composition and thickness of the cover layer 330 have been discussed above with reference to FIG. 3. In particular, in this embodiment, the covering layer 330 is deposited to a substantially uniform thickness along each surface. The cap layer 330 may be deposited using ALD, CVD, or other suitable methods. This leads to an embodiment of the photomask 108 discussed above with reference to FIG. 3. In some embodiments of the method 400, operation 410 is optional and can be omitted.

圖8繪示形成一FR-PEM光罩108，特定言之，圖4中所展示之光罩108之實施例，之一方法450。下文將結合圖9A至圖9D描述方法450。FIG. 8 shows a method 450 of forming an FR-PEM mask 108. In particular, the embodiment of the mask 108 shown in FIG. 4 is a method 450. The method 450 will be described below in conjunction with FIGS. 9A to 9D.

在操作452，方法450 (圖8)接收一結構300，如圖9A中所展示。結構300包含一LTEM基板310、放置於LTEM 310上方之一ML 320、放置於ML 320上方之一蝕刻停止層325、放置於蝕刻停止層325上方之一ML 370及放置於ML 370上方之一覆蓋層330。結構300進一步包含放置於LTEM基板310下方之一導電層305。上文已參考圖4討論層305、310、320、325、370及330之組成。例如，在各種實施例中，ML 320及ML 370可包含相同材料或不同材料。In operation 452, the method 450 (FIG. 8) receives a structure 300, as shown in FIG. 9A. The structure 300 includes an LEM substrate 310, an ML 320 placed above the LEM 310, an etch stop layer 325 placed above the ML 320, an ML 370 placed above the etch stop layer 325, and an overlay placed above the ML 370.层330. The structure 300 further includes a conductive layer 305 placed under the LEM substrate 310. The composition of layers 305, 310, 320, 325, 370, and 330 has been discussed above with reference to FIG. 4. For example, in various embodiments, ML 320 and ML 370 may include the same material or different materials.

在操作454，方法450 (圖8)在覆蓋層330上方形成一光阻圖案(或一圖案化光阻劑)352，諸如圖9B中所展示。此操作可相同於或類似於上文所討論之操作404。In operation 454, the method 450 (FIG. 8) forms a photoresist pattern (or a patterned photoresist) 352 over the capping layer 330, such as shown in FIG. 9B. This operation may be the same as or similar to operation 404 discussed above.

在操作456，方法450 (圖8)使用一蝕刻程序蝕刻覆蓋層330及ML 370以藉此形成溝槽372，諸如圖9C中所展示。蝕刻程序可包含乾式(電漿)蝕刻、濕式蝕刻及/或其他蝕刻方法。在一實施例中，對覆蓋層330及ML 370之材料選擇性調諧蝕刻程序，而不(或極少)對蝕刻停止層325蝕刻。蝕刻停止層325用於判定何時停止蝕刻。可藉由使用蝕刻停止層325來達成對溝槽372之深度之準確控制。In operation 456, the method 450 (FIG. 8) uses an etching process to etch the capping layer 330 and the ML 370 to thereby form the trench 372, such as shown in FIG. 9C. The etching process may include dry (plasma) etching, wet etching, and/or other etching methods. In one embodiment, the etching process is selectively tuned for the materials of the capping layer 330 and the ML 370, and the etching stop layer 325 is not (or rarely) etched. The etching stop layer 325 is used to determine when to stop etching. The accurate control of the depth of the trench 372 can be achieved by using the etch stop layer 325.

在操作458，方法450 (圖8)(例如)藉由光阻劑剝離來移除光阻圖案352。圖9D中展示所得結構300，其變成上文參考圖4所討論之光罩108之一實施例。操作458可對結構300執行額外清潔程序。In operation 458, the method 450 (FIG. 8) (for example) removes the photoresist pattern 352 by photoresist stripping. The resulting structure 300 is shown in FIG. 9D, which becomes an embodiment of the photomask 108 discussed above with reference to FIG. 4. Operation 458 may perform additional cleaning procedures on structure 300.

圖10係根據本發明之各種態樣之使用光微影來曝露一半導體晶圓之一方法600之一流程圖。方法600可完全或部分由諸如系統100之一EUV微影系統實施。10 is a flowchart of a method 600 of exposing a semiconductor wafer using photolithography according to various aspects of the present invention. The method 600 may be implemented in whole or in part by an EUV lithography system such as the system 100.

方法600 (圖10)開始於操作604，其中接收或製造一FR-PEM光罩108。上文圖2、圖3及圖4中展示光罩108之一些實施例。可使用上文所討論之圖5及圖8中所展示之方法400或450之實施例來製造光罩108。光罩108可由利用光罩108製造積體電路裝置之相同製造商提供。替代地，光罩108可自可為一第三方之一供應商接收。The method 600 (FIG. 10) begins at operation 604, where an FR-PEM mask 108 is received or manufactured. Some embodiments of the photomask 108 are shown in FIGS. 2, 3, and 4 above. The photomask 108 can be manufactured using the embodiments of the method 400 or 450 shown in FIGS. 5 and 8 discussed above. The photomask 108 can be provided by the same manufacturer that uses the photomask 108 to manufacture the integrated circuit device. Alternatively, the photomask 108 may be received from a supplier that may be a third party.

方法600 (圖10)進行至操作606，其中接收或提供一晶圓，且晶圓包含一基板及形成於基板上方之一光阻層。參考圖11，繪示一晶圓500 (諸如一半導體晶圓)之一示意性橫截面側視圖。已為了清楚而簡化晶圓500以較佳理解本揭露之發明概念。可在晶圓500中添加額外特徵，且可在晶圓500之其他實施例中替換或消除下文將描述之一些特徵。The method 600 (FIG. 10) proceeds to operation 606, where a wafer is received or provided, and the wafer includes a substrate and a photoresist layer formed on the substrate. Referring to FIG. 11, a schematic cross-sectional side view of a wafer 500 (such as a semiconductor wafer) is shown. The wafer 500 has been simplified for clarity to better understand the inventive concept of this disclosure. Additional features can be added to the wafer 500, and some features described below can be replaced or eliminated in other embodiments of the wafer 500.

參考圖11，晶圓500包含一基板510。基板510可(例如)為一塊體基板或一絕緣體上半導體(SOI)基板。基板510可包括：一元素半導體，諸如一結晶結構中之矽或鍺；一化合物半導體，諸如矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；或其等之組合。可使用植氧分離(SIMOX)、晶圓接合及/或其他適合方法來製造一SOI基板。基板510可為一p型基板、一n型基板或其等之一組合。儘管本揭露提供一基板之各種實例，但除非明確主張，否則本揭露及申請專利範圍之範疇不應受限於特定實例。Referring to FIG. 11, the wafer 500 includes a substrate 510. The substrate 510 may be, for example, a bulk substrate or a semiconductor-on-insulator (SOI) substrate. The substrate 510 may include: an element semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or antimony Indium; or a combination thereof. A SOI substrate can be manufactured using SIMOX, wafer bonding, and/or other suitable methods. The substrate 510 may be a p-type substrate, an n-type substrate, or a combination thereof. Although the present disclosure provides various examples of a substrate, unless explicitly claimed, the scope of the present disclosure and the scope of the patent application should not be limited to specific examples.

仍參考圖11，基板510包含用於圖案化之一或多個層512。層可為(例如)介電層、非介電層、金屬層等等。一或多個層512可由化學汽相沈積(CVD)、物理汽相沈積(PVD)、原子層沈積(ALD)、高密度電漿CVD (HDPCVD)、鍍覆、其他適合方法及/或其等之組合形成。一光阻層514形成於層512上方。光阻層514包含對EUV處理敏感之一材料。光阻層514可由一旋塗程序或任何適合程序形成。可在塗覆光阻層514之後進一步實施其他步驟。例如，可對光阻層514施加一烘烤程序以自光阻層514部分驅除溶劑(用於旋塗程序中)。Still referring to FIG. 11, the substrate 510 includes one or more layers 512 for patterning. The layer can be, for example, a dielectric layer, a non-dielectric layer, a metal layer, and so on. The one or more layers 512 may be chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), plating, other suitable methods, and/or the like The combination of formation. A photoresist layer 514 is formed above the layer 512. The photoresist layer 514 includes a material that is sensitive to EUV processing. The photoresist layer 514 can be formed by a spin coating process or any suitable process. Other steps may be further performed after coating the photoresist layer 514. For example, a baking process can be applied to the photoresist layer 514 to partially remove the solvent from the photoresist layer 514 (used in the spin coating process).

方法600 (圖10)進行至操作608，其中將晶圓500定位於一台(諸如台114 (圖1))上以用FR-PEM EUV光罩108進行EUV曝露。在一實施例中，可在一EUV微影系統(諸如系統100 (圖1))中在EUV曝露程序期間移動及對準晶圓500或光罩108或其等兩者。在適當定位晶圓500及光罩108之後，方法600 (圖10)進行至操作610以用一定劑量之EUV輻射束104曝露晶圓500。如上文所討論，使用FR-PEM 108之一益處係可比使用二元EUV光罩減少EUV輻射束104之劑量以藉此提高晶圓每小時通量。The method 600 (FIG. 10) proceeds to operation 608, where the wafer 500 is positioned on a stage (such as stage 114 (FIG. 1)) for EUV exposure with the FR-PEM EUV mask 108. In one embodiment, the wafer 500 or the mask 108, or both, can be moved and aligned during the EUV exposure process in an EUV lithography system, such as system 100 (FIG. 1). After the wafer 500 and the photomask 108 are properly positioned, the method 600 (FIG. 10) proceeds to operation 610 to expose the wafer 500 with a certain dose of EUV radiation beam 104. As discussed above, one of the benefits of using FR-PEM 108 is that the dose of EUV radiation beam 104 can be reduced compared to using a binary EUV mask, thereby increasing the throughput per hour of the wafer.

在曝露光阻劑514之後，方法600 (圖10)進行至操作612以進行形成IC裝置中之進一步操作。例如，進一步操作可包含使光阻層514顯影及移除光阻層之曝露於EUV輻射束104之部分(或未曝露，取決於光阻層514之類型)、使用圖案化光阻層514作為一蝕刻光罩來蝕刻一或多個層512、在基板510中形成電路結構等等。After exposing the photoresist 514, the method 600 (FIG. 10) proceeds to operation 612 for further operations in forming an IC device. For example, further operations may include developing the photoresist layer 514 and removing the part of the photoresist layer exposed to the EUV radiation beam 104 (or unexposed, depending on the type of the photoresist layer 514), and using the patterned photoresist layer 514 as An etching mask is used to etch one or more layers 512, form circuit structures in the substrate 510, and so on.

儘管不旨在限制，但本發明之一或多個實施例為一半導體裝置及其形成提供諸多益處。例如，本發明之實施例提供用於EUV微影中之一新穎EUV光罩(一全反射式相位邊緣光罩(或FR-PEM))。一FR-PEM提供比具有等效或更佳成像品質之二元EUV光罩更佳之晶圓每小時(WPH)通量。此能夠同時最佳化WPH通量及EUV微影成像效能。本發明之實施例亦提供製造一FR-PEM之方法及使用一FR-PEM用於半導體製造之系統及方法。Although not intended to be limiting, one or more embodiments of the present invention provide many benefits for a semiconductor device and its formation. For example, the embodiment of the present invention provides a novel EUV mask (a total reflection phase edge mask (or FR-PEM)) used in EUV lithography. An FR-PEM provides better wafer per hour (WPH) throughput than a binary EUV mask with equivalent or better imaging quality. This can optimize WPH flux and EUV lithography imaging performance at the same time. The embodiments of the present invention also provide a method for manufacturing an FR-PEM and a system and method for semiconductor manufacturing using an FR-PEM.

在一實例態樣中，本揭露係針對一種EUV微影光罩，其包含：一低熱膨脹材料之一基板；一第一反射多層，其在該基板上方；及一圖案化反射多層，其在該第一反射多層上方。該圖案化反射多層包含穿過該圖案化反射多層之溝槽，且該第一反射多層及該圖案化反射多層之各者包含一膜對堆疊。In an example aspect, the present disclosure is directed to an EUV lithography photomask, which includes: a substrate with a low thermal expansion material; a first reflective multilayer on top of the substrate; and a patterned reflective multilayer on Above the first reflective multilayer. The patterned reflective multilayer includes a trench passing through the patterned reflective multilayer, and each of the first reflective multilayer and the patterned reflective multilayer includes a film pair stack.

在一實施例中，該EUV微影光罩進一步包含放置於該第一反射多層與該圖案化反射多層之間的一蝕刻停止層。在另一實施例中，該EUV微影光罩進一步包含放置於該圖案化反射多層之頂面上之一覆蓋層。在又一實施例中，該EUV微影光罩進一步包含放置於該圖案化反射多層之頂面及側壁表面上及由該等溝槽曝露之該第一反射多層之頂面上之一覆蓋層。In one embodiment, the EUV lithography mask further includes an etch stop layer placed between the first reflective multilayer and the patterned reflective multilayer. In another embodiment, the EUV lithography mask further includes a cover layer placed on the top surface of the patterned reflective multilayer. In another embodiment, the EUV lithography mask further includes a cover layer placed on the top surface and sidewall surfaces of the patterned reflective multilayer and the top surface of the first reflective multilayer exposed by the grooves .

在該EUV微影光罩之一些實施例中，該膜對堆疊包含鉬及矽膜對。在一些實施例中，該圖案化反射多層包含與該等溝槽交替之線圖案。在一些實施例中，該等溝槽之一第一子集沿一第一方向定向且該等溝槽之一第二子集沿大體上垂直於該第一方向之一第二方向定向。在一些實施例中，該EUV微影光罩進一步包含放置於該基板下方之一導電層。In some embodiments of the EUV lithography mask, the film pair stack includes a molybdenum and silicon film pair. In some embodiments, the patterned reflective multilayer includes line patterns alternating with the grooves. In some embodiments, a first subset of the trenches is oriented along a first direction and a second subset of the trenches is oriented along a second direction substantially perpendicular to the first direction. In some embodiments, the EUV lithography mask further includes a conductive layer placed under the substrate.

在另一實例態樣中，本揭露係針對一種製造一EUV微影光罩之方法。該方法包含：接收一結構，該結構具有一低熱膨脹材料之一基板、該基板上方之一第一反射多層、該第一反射多層上方之一蝕刻停止層、該蝕刻停止層上方之一第二反射多層及該第二反射多層上方之一覆蓋層。該方法進一步包含：在該覆蓋層上方形成一圖案化光阻劑；透過該圖案化光阻劑蝕刻該覆蓋層及該第二反射多層，直至曝露該蝕刻停止層；及移除該圖案化光阻劑。In another example aspect, the present disclosure is directed to a method of manufacturing an EUV lithography mask. The method includes: receiving a structure having a substrate with a low thermal expansion material, a first reflective multilayer above the substrate, an etch stop layer above the first reflective multilayer, and a second etch stop layer above the etch stop layer. The reflective multilayer and a covering layer above the second reflective multilayer. The method further includes: forming a patterned photoresist on the cover layer; etching the cover layer and the second reflective multilayer through the patterned photoresist until the etching stop layer is exposed; and removing the patterned light Resist.

在該方法之一些實施例中，該第二反射多層具有自約60 nm至約120 nm之一範圍內之一厚度。在一些實施例中，該第一反射多層及該第二反射多層之各者包含交替鉬及矽對之一堆疊。在一些實施例中，該覆蓋層包含Ru、Si、SiC或其等之一組合。在一實施例中，該蝕刻停止層包含Ru、Si、SiC或其等之一組合。在另一實施例中，該結構進一步包含放置於該基板下方之一導電層。In some embodiments of the method, the second reflective multilayer has a thickness in a range from about 60 nm to about 120 nm. In some embodiments, each of the first reflective multilayer and the second reflective multilayer includes a stack of alternating molybdenum and silicon pairs. In some embodiments, the capping layer includes Ru, Si, SiC, or a combination thereof. In one embodiment, the etch stop layer includes Ru, Si, SiC, or a combination thereof. In another embodiment, the structure further includes a conductive layer placed under the substrate.

在又一實例態樣中，本揭露係針對一種製造一EUV微影光罩之方法。該方法包含：接收一結構，該結構具有一低熱膨脹材料之一基板及該基板上方之一反射多層；在該反射多層上方形成一圖案化光阻劑；透過該圖案化光阻劑蝕刻該反射多層以形成未完全蝕刻穿過該反射多層之一第一深度之溝槽；及移除該圖案化光阻劑。In yet another example aspect, the present disclosure is directed to a method of manufacturing an EUV lithography mask. The method includes: receiving a structure having a substrate with a low thermal expansion material and a reflective multilayer above the substrate; forming a patterned photoresist on the reflective multilayer; and etching the reflection through the patterned photoresist Multiple layers are formed to form a trench that is not completely etched through a first depth of the reflective multilayer; and the patterned photoresist is removed.

在該方法之一實施例中，該第一深度在60 nm至120 nm之一範圍內。在另一實施例中，該反射多層包含交替鉬及矽對之一堆疊。In an embodiment of the method, the first depth is in a range of 60 nm to 120 nm. In another embodiment, the reflective multilayer includes a stack of alternating molybdenum and silicon pairs.

在一實施例中，該方法進一步包含在該反射多層之頂面及該等溝槽之側壁及底面上方沈積一覆蓋層。在另一實施例中，該覆蓋層在該反射多層之該等頂面及該等溝槽之該側壁及該等底面上方具有約2 nm至約5 nm之一厚度。在該方法之一些實施例中，該覆蓋層包含Ru、Si、SiC或其等之一組合。In one embodiment, the method further includes depositing a capping layer on the top surface of the reflective multilayer and the sidewalls and bottom surfaces of the trenches. In another embodiment, the cover layer has a thickness of about 2 nm to about 5 nm above the top surfaces of the reflective multilayer and the side walls and the bottom surfaces of the trenches. In some embodiments of the method, the cover layer includes Ru, Si, SiC, or a combination thereof.

上文已概述若干實施例之特徵，使得一般技術者可較佳理解本發明之態樣。一般技術者應瞭解，其可易於將本揭露用作用於設計或修改用於實施相同目的及/或達成本文中所引入之實施例之相同優點之其他程序及結構之一基礎。一般技術者亦應意識到，此等等效建構不應背離本發明之精神及範疇，且其可在不背離本發明之精神及範疇之情況下對本文作出各種改變、取代及更改。The features of several embodiments have been summarized above, so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other programs and structures for implementing the same purpose and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that these equivalent constructions should not depart from the spirit and scope of the present invention, and they can make various changes, substitutions and alterations to this text without departing from the spirit and scope of the present invention.

100:極紫外光(EUV)微影系統 102:輻射源 104:輻射束/EUV輻射 106:聚光光學器件 108:光罩/全反射式相位邊緣光罩(FR-PEM) 108a:線/線圖案 108b:空間 108c:島 108d:間隔列/行/空間 110:光罩台 112:投影光學器件 114:基板台 116:基板/晶圓 200:積體電路(IC)/IC設計 202:IC佈局 212:幾何圖案 222:主圖案 232:次解析度側條圖案 242:擴大端部分 300:結構 305:導電層 310:材料層/低熱膨脹材料(LTEM)層/LTEM基板 320:反射多層(ML) 325:蝕刻停止層 330:覆蓋層/保護層 352:光阻圖案 354:開口 370:圖案化ML 372:溝槽 374:脊/ML圖案 400:方法 402:操作 404:操作 406:操作 408:操作 410:操作 450:方法 452:操作 454:操作 456:操作 458:操作 500:晶圓 510:基板 512:層 514:光阻層/光阻劑 600:方法 604:操作 606:操作 608:操作 610:操作 612:操作 H1:厚度 W1:寬度100: extreme ultraviolet (EUV) lithography system 102: Radiation source 104: Radiation beam/EUV radiation 106: Condenser optics 108: Mask / Total reflection phase edge mask (FR-PEM) 108a: line/line pattern 108b: Space 108c: Island 108d: Interval column/row/space 110: Mask table 112: projection optics 114: substrate table 116: substrate/wafer 200: Integrated Circuit (IC)/IC Design 202: IC layout 212: Geometric pattern 222: Main pattern 232: Sub-resolution side strip pattern 242: Enlarged end part 300: structure 305: conductive layer 310: Material layer/Low thermal expansion material (LTEM) layer/LTEM substrate 320: reflective multilayer (ML) 325: Etch Stop Layer 330: cover layer/protective layer 352: photoresist pattern 354: open 370: Patterned ML 372: Groove 374: Ridge/ML pattern 400: method 402: Operation 404: Operation 406: Operation 408: Operation 410: Operation 450: method 452: Operation 454: operation 456: operation 458: Operation 500: Wafer 510: substrate 512: layer 514: photoresist layer/photoresist 600: method 604: Operation 606: Operation 608: Operation 610: Operation 612: Operation H1: Thickness W1: width

自結合附圖閱讀之以下詳細描述最佳理解本揭露。應注意，根據行業標準做法，各種構件未按比例繪製且僅用於說明。實際上，為使討論清楚，可任意增大或減小各種構件之尺寸。The present disclosure is best understood from the following detailed description read in conjunction with the accompanying drawings. It should be noted that according to industry standard practices, various components are not drawn to scale and are only for illustration. In fact, in order to make the discussion clear, the size of various components can be increased or decreased arbitrarily.

圖1A係根據本發明之一或多個實施例之使用一EUV光罩之一極紫外(EUV)微影曝露系統之一圖式。圖1B、圖1C及圖1D繪示根據一些實施例之用於圖1A之系統中之光源及目標圖案。FIG. 1A is a diagram of an extreme ultraviolet (EUV) lithography exposure system using an EUV mask according to one or more embodiments of the present invention. 1B, 1C, and 1D illustrate light source and target patterns used in the system of FIG. 1A according to some embodiments.

圖2、圖3及圖4繪示根據本發明之各種態樣之一EUV光罩之實施例之橫截面圖。Figures 2, 3, and 4 show cross-sectional views of an embodiment of an EUV mask according to various aspects of the present invention.

圖5繪示根據本發明之一實施例之製造一EUV光罩之一方法之一流程圖。FIG. 5 shows a flowchart of a method of manufacturing an EUV mask according to an embodiment of the present invention.

圖6A、圖6B、圖6C、圖6D及圖6E繪示根據圖5中之方法之各個製造步驟中之一EUV光罩之一實施例之橫截面圖。6A, FIG. 6B, FIG. 6C, FIG. 6D, and FIG. 6E are cross-sectional views of an embodiment of the EUV mask in one of the manufacturing steps of the method in FIG. 5.

圖7A、圖7B、圖7C及圖7D繪示根據本發明之一實施例之實施至一EUV光罩上之一電路設計。7A, 7B, 7C, and 7D illustrate a circuit design implemented on an EUV mask according to an embodiment of the present invention.

圖8繪示根據本發明之另一實施例之製造一EUV光罩之一方法之一流程圖。FIG. 8 shows a flowchart of a method of manufacturing an EUV mask according to another embodiment of the present invention.

圖9A、圖9B、圖9C及圖9D繪示根據圖8中之方法之各個製造步驟中之一EUV光罩之一實施例之橫截面圖。9A, FIG. 9B, FIG. 9C, and FIG. 9D show cross-sectional views of an embodiment of the EUV mask in one of the manufacturing steps of the method in FIG. 8.

圖10係繪示根據本發明之各種態樣之曝露用於製造IC之一半導體晶圓之一方法的一流程圖。FIG. 10 shows a flowchart of a method of exposing a semiconductor wafer for manufacturing an IC according to various aspects of the present invention.

圖11繪示根據本發明之各種態樣之一半導體晶圓之一實施例之一橫截面圖。FIG. 11 shows a cross-sectional view of an embodiment of a semiconductor wafer according to various aspects of the present invention.

108:光罩/全反射式相位邊緣光罩(FR-PEM) 108: Mask / Total reflection phase edge mask (FR-PEM)

300:結構 300: structure

305:導電層 305: conductive layer

310:材料層/低熱膨脹材料(LTEM)層/LTEM基板 310: Material layer/Low thermal expansion material (LTEM) layer/LTEM substrate

320:反射多層(ML) 320: reflective multilayer (ML)

330:覆蓋層/保護層 330: cover layer/protective layer

370:圖案化ML 370: Patterned ML

372:溝槽 372: Groove

Claims

一種極紫外光(EUV)微影光罩，其包括：一低熱膨脹材料之一基板；一第一反射多層，其在該基板上方；及一圖案化反射多層，其在該第一反射多層上方，其中該圖案化反射多層包含穿過該圖案化反射多層之溝槽，且該第一反射多層及該圖案化反射多層之各者包含一膜對堆疊。An extreme ultraviolet light (EUV) lithography photomask, which includes: A substrate of a low thermal expansion material; A first reflective multilayer, which is above the substrate; and A patterned reflective multilayer is above the first reflective multilayer, wherein the patterned reflective multilayer includes a trench passing through the patterned reflective multilayer, and each of the first reflective multilayer and the patterned reflective multilayer includes a Film pairs are stacked.

如請求項1之EUV微影光罩，其進一步包括：一蝕刻停止層，其放置於該第一反射多層與該圖案化反射多層之間。Such as the EUV lithography mask of claim 1, which further includes: An etching stop layer is placed between the first reflective multilayer and the patterned reflective multilayer.

如請求項1之EUV微影光罩，其進一步包括：一覆蓋層，其放置於該圖案化反射多層之頂面上。Such as the EUV lithography mask of claim 1, which further includes: A cover layer is placed on the top surface of the patterned reflective multilayer.

如請求項1之EUV微影光罩，其進一步包括：一覆蓋層，其放置於該圖案化反射多層之頂面及側壁表面上及由該等溝槽曝露之該第一反射多層之頂面上。Such as the EUV lithography mask of claim 1, which further includes: A cover layer is placed on the top surface and sidewall surfaces of the patterned reflective multilayer and the top surface of the first reflective multilayer exposed by the grooves.

如請求項1之EUV微影光罩，其中該膜對堆疊包含鉬及矽膜對。Such as the EUV lithography mask of claim 1, wherein the film pair stack includes a molybdenum and silicon film pair.

如請求項1之EUV微影光罩，其中該圖案化反射多層包含與該等溝槽交替之線圖案。Such as the EUV lithography mask of claim 1, wherein the patterned reflective multilayer includes line patterns alternating with the grooves.

如請求項1之EUV微影光罩，其中該等溝槽之一第一子集沿一第一方向定向且該等溝槽之一第二子集沿大體上垂直於該第一方向之一第二方向定向。Such as the EUV lithography mask of claim 1, wherein a first subset of the grooves is oriented along a first direction and a second subset of the grooves is substantially perpendicular to one of the first directions Orientation in the second direction.

如請求項1之EUV微影光罩，其進一步包括放置於該基板下方之一導電層。Such as the EUV lithography mask of claim 1, which further includes a conductive layer placed under the substrate.

一種製造一EUV微影光罩之方法，其包括：接收一結構，該結構具有一低熱膨脹材料之一基板、該基板上方之一第一反射多層、該第一反射多層上方之一蝕刻停止層、該蝕刻停止層上方之一第二反射多層及該第二反射多層上方之一覆蓋層；在該覆蓋層上方形成一圖案化光阻劑；透過該圖案化光阻劑蝕刻該覆蓋層及該第二反射多層，直至曝露該蝕刻停止層；及移除該圖案化光阻劑。A method of manufacturing an EUV lithography mask, which includes: Receive a structure having a substrate with a low thermal expansion material, a first reflective multilayer above the substrate, an etch stop layer above the first reflective multilayer, a second reflective multilayer above the etch stop layer, and the A covering layer above the second reflective multilayer; Forming a patterned photoresist on the cover layer; Etching the cover layer and the second reflective multilayer through the patterned photoresist until the etching stop layer is exposed; and Remove the patterned photoresist.

如請求項9之方法，其中該第二反射多層具有自約60 nm至約120 nm之一範圍內之一厚度。The method of claim 9, wherein the second reflective multilayer has a thickness in a range from about 60 nm to about 120 nm.

如請求項9之方法，其中該第一反射多層及該第二反射多層之各者包含交替鉬及矽對之一堆疊。The method of claim 9, wherein each of the first reflective multilayer and the second reflective multilayer comprises a stack of alternating molybdenum and silicon pairs.

如請求項9之方法，其中該覆蓋層包含Ru、Si、SiC或其等之一組合。The method of claim 9, wherein the covering layer comprises Ru, Si, SiC, or a combination thereof.

如請求項9之方法，其中該蝕刻停止層包含Ru、Si、SiC或其等之一組合。The method of claim 9, wherein the etch stop layer includes Ru, Si, SiC, or a combination thereof.

如請求項9之方法，其中該結構進一步包含放置於該基板下方之一導電層。The method of claim 9, wherein the structure further includes a conductive layer placed under the substrate.

一種製造一EUV微影光罩之方法，其包括：接收一結構，該結構具有一低熱膨脹材料之一基板及該基板上方之一反射多層；在該反射多層上方形成一圖案化光阻劑；透過該圖案化光阻劑蝕刻該反射多層以形成未完全蝕刻穿過該反射多層之一第一深度之溝槽；及移除該圖案化光阻劑。A method of manufacturing an EUV lithography mask, which includes: Receiving a structure having a substrate with a low thermal expansion material and a reflective multilayer above the substrate; Forming a patterned photoresist on the reflective multilayer; Etching the reflective multilayer through the patterned photoresist to form a trench that is not completely etched through a first depth of the reflective multilayer; and Remove the patterned photoresist.

如請求項15之方法，其中該第一深度在60 nm至120 nm之一範圍內。Such as the method of claim 15, wherein the first depth is in a range of 60 nm to 120 nm.

如請求項15之方法，其中該反射多層包含交替鉬及矽對之一堆疊。The method of claim 15, wherein the reflective multilayer comprises a stack of alternating molybdenum and silicon pairs.

如請求項15之方法，其進一步包括：在該反射多層之頂面及該等溝槽之側壁及底面上方沈積一覆蓋層。Such as the method of claim 15, which further includes: A cover layer is deposited on the top surface of the reflective multilayer and the sidewalls and bottom surfaces of the trenches.

如請求項18之方法，其中該覆蓋層在該反射多層之該等頂面及該等溝槽之該側壁及該等底面上方具有約2 nm至約5 nm之一厚度。The method of claim 18, wherein the cover layer has a thickness of about 2 nm to about 5 nm above the top surfaces of the reflective multilayer and the side walls and the bottom surfaces of the trenches.

如請求項18之方法，其中該覆蓋層包含Ru、Si、SiC或其等之一組合。The method of claim 18, wherein the covering layer comprises Ru, Si, SiC, or a combination thereof.