TW202109545A - Memory apparatus and data accessing method thereof - Google Patents
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本發明是有關於一種記憶體裝置及其資料存取方法,且特別是有關於一種具有多個錯誤校正碼(ECC)機制的記憶體裝置。The present invention relates to a memory device and its data access method, and more particularly to a memory device with multiple error correction code (ECC) mechanisms.
在習知技術中,針對非揮發性記憶體,例如為BCH操作的ECC機制可在每個碼字上運行。但是,在統計中,大部分碼字只需要零個或少量的校正位元。也就是說,在習知技術中,由於僅具有一個ECC機制,即使大部分碼字不需要這樣,記憶體裝置始終使用最高的功率來讀取或寫入每個碼字。此外,在習知技術中,即使大部分碼字不要需要這樣,同位檢查位元仍需要針對單一個ECC機制進行最大次數的切換。In the prior art, for non-volatile memory, for example, the ECC mechanism for BCH operation can run on each codeword. However, in statistics, most codewords only require zero or a small number of correction bits. That is to say, in the conventional technology, since there is only one ECC mechanism, even if most codewords do not need this, the memory device always uses the highest power to read or write each codeword. In addition, in the conventional technology, even if most codewords do not need this, the parity check bit still needs to be switched for the maximum number of times for a single ECC mechanism.
本發明提供一種用於降低操作功率的記憶體裝置及其資料存取方法。The invention provides a memory device for reducing operating power and a data access method thereof.
本發明的資料存取方法,包含:基於位址資訊對記憶體裝置執行讀取操作以獲得碼字和指示符,其中指示符對應於碼字;使得第一錯誤校正碼(ECC)操作或第二ECC操作運行在碼字上以用於生成錯誤校正資料,其中,第一ECC操作比第二ECC操作校正較少的位元。The data access method of the present invention includes: performing a read operation on the memory device based on the address information to obtain a codeword and an indicator, wherein the indicator corresponds to the codeword; making the first error correction code (ECC) operation or the first error correction code (ECC) operation or the second Two ECC operations run on the codeword to generate error correction data, wherein the first ECC operation corrects fewer bits than the second ECC operation.
本發明還提供包含記憶胞陣列和控制器的記憶體裝置。控制器耦接記憶胞陣列,且配置以執行上述資料存取方法。The invention also provides a memory device including a memory cell array and a controller. The controller is coupled to the memory cell array and configured to execute the above data access method.
基於上述,本發明根據碼字的訊息位元的錯誤位元數目,來啟用第一ECC操作和第二ECC操作的其中之一。也就是說,不必使用最大功率以在每個碼字上運行ECC操作,可節省記憶體裝置的功率消耗。Based on the above, the present invention enables one of the first ECC operation and the second ECC operation according to the number of error bits of the message bit of the codeword. In other words, it is not necessary to use the maximum power to run the ECC operation on each codeword, which can save the power consumption of the memory device.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.
參看圖1,圖1中的資料存取方法適應於記憶體裝置,且記憶體裝置可以是非揮發性記憶體,例如快閃記憶體。步驟S110基於位址資訊對記憶體裝置執行讀取操作以獲得碼字和指示。詳細地說,在執行讀取操作之前,可由記憶體裝置接收具有位址資訊的資料存取命令。接著,讀取操作可基於位址資訊在記憶體裝置上運行。在本實施例中,基於位址資訊,可在記憶體裝置中預存指示符。此外,通過讀取操作讀出的碼字包含多個訊息位元和多個同位檢查位元。Referring to FIG. 1, the data access method in FIG. 1 is adapted to a memory device, and the memory device may be a non-volatile memory, such as a flash memory. Step S110 performs a read operation on the memory device based on the address information to obtain codewords and instructions. In detail, before performing a read operation, a data access command with address information can be received by the memory device. Then, the read operation can be performed on the memory device based on the address information. In this embodiment, based on the address information, the indicator can be pre-stored in the memory device. In addition, the code word read by the read operation includes multiple message bits and multiple parity check bits.
步驟S120根據指示符,以使第一錯誤碼(ECC)操作或第二ECC操作運行在碼字上以生成錯誤校正資料,其中第一ECC操作比第二ECC操作校正較少的位元。詳細地說,可根據指示符啟動第一ECC操作和第二ECC操作中的其中之一。舉例來說,指示符可為具有一個位元的數位信號。在本實施例中,如果指示符處於第一邏輯準位,則可啟動具有較少錯誤位元校正能力的第一ECC操作;且如果指示符處於第二邏輯準位,則可啟動帶具更多錯誤位元校正能力的第二ECC操作。第一邏輯準位與第二邏輯準位互補,其中第一邏輯準位可以是邏輯準位1,且第二邏輯準位可以是邏輯準位0。In step S120, according to the indicator, the first error code (ECC) operation or the second ECC operation is executed on the code word to generate error correction data, wherein the first ECC operation corrects fewer bits than the second ECC operation. In detail, one of the first ECC operation and the second ECC operation can be initiated according to the indicator. For example, the indicator may be a digital signal with one bit. In this embodiment, if the indicator is at the first logic level, the first ECC operation with less error bit correction capability can be activated; and if the indicator is at the second logic level, the belt replacement can be activated. The second ECC operation with multiple error bit correction capability. The first logic level is complementary to the second logic level. The first logic level can be a logic level 1 and the second logic level can be a logic level 0.
在本發明實施例中,指示符可根據對應碼字的可能錯誤位元數目來設置,並基於位址資訊預存在記憶體裝置中。如果對應碼字的錯誤位元數目小於預設參考,則指示符可設置為第一邏輯準位;且如果對應碼字的錯誤位元數目不小於預設參考,則指示符可設置為第二邏輯準位。In the embodiment of the present invention, the indicator can be set according to the number of possible error bits of the corresponding codeword, and is pre-stored in the memory device based on the address information. If the number of error bits of the corresponding codeword is less than the preset reference, the indicator can be set to the first logic level; and if the number of error bits of the corresponding codeword is not less than the preset reference, the indicator can be set to the second Logic level.
此處可見,在本發明實施例中,針對每個碼字啟動合適的ECC操作。也就是說,記憶體裝置不需要始終對具有最大功率的碼字執行ECC操作。可節省記憶體裝置的功率消耗。It can be seen here that in the embodiment of the present invention, an appropriate ECC operation is started for each codeword. In other words, the memory device does not need to always perform the ECC operation on the codeword with the maximum power. It can save the power consumption of the memory device.
參看圖2,碼字CW和對應的指示符IND可基於位址資訊ADD被讀出。碼字CW可包含多個訊息位元和多個同位檢查位元。Referring to FIG. 2, the code word CW and the corresponding indicator IND can be read based on the address information ADD. The code word CW may include multiple message bits and multiple parity check bits.
另一方面,可對指示符IND的邏輯準位進行檢查。如果指示符IND為邏輯準位1,則可啟動第一ECC操作(ECC1)210以運行在碼字CW上。在此實施例中,舉例來說,第一ECC操作210可由第一ECC編碼器執行(第一ECC編碼器可具有4組),且第一ECC操作210可基於漢明(12,8)碼來運行。On the other hand, the logic level of the indicator IND can be checked. If the indicator IND is a logic level 1, the first ECC operation (ECC1) 210 can be started to run on the code word CW. In this embodiment, for example, the
相反的,如果指示符IND為邏輯準位0,則可啟動第二ECC操作(ECC2)220以運行在碼字CW。在此實施例中,舉例來說,第二ECC操作220可由第二ECC編碼器執行,且第二ECC操作可基於BCH(50,32)碼來運行。Conversely, if the indicator IND is at a logic level of 0, the second ECC operation (ECC2) 220 can be started to run on the code word CW. In this embodiment, for example, the
在本實施例中,第一ECC操作比第二ECC操作校正更少的錯誤位元,且記憶體裝置執行第一ECC操作比執行第二ECC操作消耗更少的功率。In this embodiment, the first ECC operation corrects fewer error bits than the second ECC operation, and the memory device performs the first ECC operation consumes less power than the second ECC operation.
記憶體裝置通過根據指示符IND選擇第一ECC操作210的輸出或第二ECC操作的輸出進一步輸出錯誤校正資料ECD。詳細地說,如果指示符為邏輯準位1,則可選擇第一ECC操作210的輸出以生成錯誤校正資料ECD。相反的,如果指示符為邏輯準位0,則可選擇第第二ECC操作220的輸出以生成錯誤校正資料ECD。The memory device further outputs the error correction data ECD by selecting the output of the
當存取多個碼字時,記憶體裝置可適應性地選擇合適的ECC操作以運行在每個碼字上。可節省記憶體裝置的功率消耗。When accessing multiple codewords, the memory device can adaptively select an appropriate ECC operation to run on each codeword. It can save the power consumption of the memory device.
此處請注意,在一些實施例中,至少一個第三ECC操作可添加到資料存取流程中。第三ECC操作可比第二ECC操作220校正更多錯誤位元。在這種情況下,指示符IND可具有2位元。舉例來說,如果指示符為邏輯準位00,則可啟動第二ECC操作;如果指示符為邏輯準位01,則可啟動第一ECC操作;且如果指示符為邏輯準位10,則可啟動第三ECC操作。當然,指示符與被啟動的ECC操作之間的關係可由記憶體裝置的設計者定義,在此並無特殊限制。Please note here that in some embodiments, at least one third ECC operation can be added to the data access process. The third ECC operation can correct more error bits than the
在此實施例中,第二ECC操作220的輸出的資料大小可以是4位元組,且第一ECC操作210的輸出的資料大小可不大於4位元組。In this embodiment, the output data size of the
參看圖3,步驟S310接收記憶體裝置的寫入命令。接著,步驟S320對記憶體裝置執行預讀取流程。在預讀取流程中,讀取操作可基於寫入命令的位址資訊執行,且指示符IND可通過預讀取流程獲得。步驟S330確定指示符IND是否為邏輯準位1,如果指示符IND不是邏輯準位1,則保持指示符邏輯準位0並且執行步驟S352。相反的,如果指示符IND為邏輯準位1,則可通過寫入驗證讀取流程檢查通過預讀取操作的讀出碼字,且在步驟S340中可檢查錯誤位元的數目。在寫入驗證讀取流程中,讀出寫入記憶體裝置的寫入碼字,且將讀出碼字與寫入驗證讀取流程的寫入碼字進行比較。Referring to FIG. 3, step S310 receives a write command from the memory device. Next, in step S320, a pre-reading process is performed on the memory device. In the pre-reading process, the read operation can be performed based on the address information of the write command, and the indicator IND can be obtained through the pre-reading process. Step S330 determines whether the indicator IND is the logic level 1, and if the indicator IND is not the logic level 1, keep the indicator logic level 0 and execute step S352. Conversely, if the indicator IND is a logic level 1, the read codeword that has passed the pre-read operation can be checked through the write verification read flow, and the number of error bits can be checked in step S340. In the write verification read process, the written code word written in the memory device is read, and the read code word is compared with the written code word of the write verification read process.
如果錯誤位元的數目等於0,則指示符IND保持為邏輯準位1,並且執行步驟S351。相反的,如果錯誤位元的數目不等於0,則指示符IND調整為邏輯準位0,並且執行步驟S352。當指示符IND為邏輯準位1時,步驟S351基於漢明(12,8)碼啟用第一ECC操作(ECC1)。當指示符IND為邏輯準位0時,步驟S352基於BCH(50,32)碼啟用第二ECC操作(ECC2)。If the number of error bits is equal to 0, the indicator IND remains at the logical level 1, and step S351 is executed. Conversely, if the number of error bits is not equal to 0, the indicator IND is adjusted to the logic level 0, and step S352 is executed. When the indicator IND is the logic level 1, step S351 enables the first ECC operation (ECC1) based on the Hamming (12, 8) code. When the indicator IND is the logic level 0, step S352 enables the second ECC operation (ECC2) based on the BCH (50, 32) code.
在步驟S351或步驟S352執行完成後,可生成多個更新的訊息位元和多個更新的同位檢查位元,而更新的訊息位元和更新的同位檢查位元形成更新的碼字UCW。基於寫入命令的位址資訊,可將更新的碼字UCW和對應的指示符IND寫入記憶體裝置。可完成資料寫入操作。After the execution of step S351 or step S352 is completed, a plurality of updated message bits and a plurality of updated parity check bits can be generated, and the updated message bits and the updated parity check bits form an updated codeword UCW. Based on the address information of the write command, the updated code word UCW and the corresponding indicator IND can be written into the memory device. The data writing operation can be completed.
在此,由於指示符IND將僅進行一次寫入(無循環的問題),因此可提供用於將指示符IND寫入記憶體裝置的第一寫入脈衝,並且在寫入操作期間可提供用於將更新的碼字UCW寫入記憶體裝置的第二寫入脈衝,其中第一寫入脈衝與第二寫入脈衝不同。Here, since the indicator IND will be written only once (no loop problem), the first write pulse for writing the indicator IND into the memory device can be provided, and it can be used during the write operation. In the second write pulse for writing the updated codeword UCW into the memory device, the first write pulse is different from the second write pulse.
此處應注意的是,當更新的訊息位元和更新的同位檢查位元寫入記憶體裝置時,更新的訊息位元和更新的同位檢查位元可分別地與多個原始訊息位元和多個原始同位檢查位元進行比較,並且更新的訊息位元和更新的同位檢查位元可基於較少位元變化機制寫入。可通過步驟S330中的預讀取操作獲得原始訊息位元和原始同位檢查位元。較少位元變化機制可由本領域的技術人員熟知的機制來實施,所述較少位元變化機制可減少每次資料寫入操作中時,被程式化的記憶胞的數目。It should be noted here that when the updated message bit and the updated parity check bit are written into the memory device, the updated message bit and the updated parity check bit can be combined with multiple original message bits and A plurality of original parity check bits are compared, and the updated message bit and the updated parity check bit can be written based on a less bit change mechanism. The original message bit and the original parity check bit can be obtained through the pre-read operation in step S330. The less bit change mechanism can be implemented by a mechanism well known to those skilled in the art. The less bit change mechanism can reduce the number of memory cells that are programmed for each data writing operation.
參看圖4,步驟S410接收具有位址資訊的記憶體裝置的寫入命令。接著,步驟S420對記憶體裝置執行預讀取流程。在預讀取流程中,讀取操作可基於寫入命令的位址資訊執行,並且指示符IND可通過預讀取流程獲得。步驟S430確定指示符IND是否為邏輯準位0,如果指示符IND不是邏輯準位0,則運行步驟S440。相反的,如果指示符IND為邏輯準位0,則執行步驟S480。Referring to FIG. 4, step S410 receives a write command from a memory device with address information. Next, step S420 performs a pre-reading process on the memory device. In the pre-reading process, the read operation can be performed based on the address information of the write command, and the indicator IND can be obtained through the pre-reading process. Step S430 determines whether the indicator IND is the logic level 0, and if the indicator IND is not the logic level 0, then step S440 is executed. Conversely, if the indicator IND is at a logic level of 0, step S480 is executed.
在步驟S440中,如果錯誤位元的數目大於0,則執行步驟S450以啟用基於漢明(12,8)碼的第一ECC操作(ECC1)。如果錯誤位元的數目不大於0,則執行步驟S460。In step S440, if the number of error bits is greater than 0, step S450 is executed to enable the first ECC operation (ECC1) based on the Hamming (12, 8) code. If the number of error bits is not greater than 0, step S460 is executed.
在步驟S460中,執行寫入驗證讀取流程。在步驟460中,讀出寫入記憶體裝置的寫入碼字,並將讀出碼字與用於寫入驗證讀取流程的寫入碼字進行比較。如果讀出碼字和寫入碼字相同,則寫入命令已完成。相反的,如果讀出碼字和寫入碼字不同,則執行步驟S480。In step S460, a write verification read process is performed. In step 460, the written code word written in the memory device is read, and the read code word is compared with the written code word used in the write verification read process. If the read code word and the write code word are the same, the write command has been completed. Conversely, if the read codeword and the written codeword are different, step S480 is executed.
在步驟S480中,指示符IND設定為邏輯準位0,且針對基於BCH(50,32)碼的ECC操作啟用第二ECC操作(ECC2)。第二ECC操作可比第一ECC操作校正更多的錯誤位元。可確保碼字的精確性。In step S480, the indicator IND is set to a logic level of 0, and the second ECC operation (ECC2) is enabled for the ECC operation based on the BCH (50, 32) code. The second ECC operation can correct more error bits than the first ECC operation. It can ensure the accuracy of the codeword.
在執行步驟S450或步驟S480後,可生成多個更新的訊息位元和多個更新的同位檢查位元,並且更新的訊息位元和更新的同位檢查位元形成更新的碼字UCW。基於寫入命令的位址資訊,可將更新的碼字UCW和對應的指示符IND寫入記憶體裝置。可完成資料寫入操作。此處應注意的是,當更新的訊息位元和更新的同位檢查位元寫入記憶體裝置時,更新的訊息位元和更新的同位檢查位元可基於如上所提到的較少位變化機制寫入。After performing step S450 or step S480, a plurality of updated message bits and a plurality of updated parity check bits may be generated, and the updated message bits and the updated parity check bits form an updated codeword UCW. Based on the address information of the write command, the updated code word UCW and the corresponding indicator IND can be written into the memory device. The data writing operation can be completed. It should be noted here that when the updated message bit and the updated parity check bit are written into the memory device, the updated message bit and the updated parity check bit can be based on the less bit changes mentioned above Mechanism write.
參看圖5,記憶體裝置500可為非易失性記憶體。舉例來說,記憶體裝置500可為快閃記憶體。記憶體裝置500包含記憶胞陣列510和控制器520。記憶胞陣列510包含多個記憶胞。控制器520配置以執行在先前實施例中提到的資料存取方法的步驟。在上述實施例中已經描述步驟的詳細操作,這裡不再重複描述。Referring to FIG. 5, the
關於控制器520。控制器520可為具有計算功能的處理器。或者,控制器520還可為通過使用硬體描述語言(hardware description language;HDL)或由所屬領域相關技術員熟知的任何數位電路設計方法設計的硬體電路,並通過現場可程式設計閘陣列(field programmable gate array;FPGA)、複雜可程式設計邏輯裝置(complex programmable logic device;CPLD)或專用積體電路(application-specific integrated circuit;ASIC)實現。Regarding the
綜上所述,通過針對每個碼字選擇合適的ECC操作可減少記憶體裝置的功率消耗。此外,通過使用較少位變化機制來寫入碼字,可進一步減少記憶體裝置的功率消耗,並可增加記憶胞(即,快閃記憶體儲單元)的使用壽命。In summary, the power consumption of the memory device can be reduced by selecting an appropriate ECC operation for each codeword. In addition, by using a less bit change mechanism to write codewords, the power consumption of the memory device can be further reduced, and the service life of the memory cell (ie, flash memory storage unit) can be increased.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.
210:第一ECC操作 220:第二ECC操作 500:記憶體裝置 510:記憶胞陣列 520:控制器 S110、S120、S310、S320、S330、S340、S351、S352、S410、S420、S430、S440、S450、S460、S470、S480:步驟 ADD:位址資訊 CW:碼字 ECD:錯誤校正資料 IND:指示符 UCW:更新的碼字210: First ECC operation 220: Second ECC operation 500: Memory device 510: Memory Cell Array 520: Controller S110, S120, S310, S320, S330, S340, S351, S352, S410, S420, S430, S440, S450, S460, S470, S480: steps ADD: address information CW: codeword ECD: Error correction data IND: indicator UCW: updated codeword
圖1繪示本發明的實施例的資料存取方法的流程圖。 圖2繪示本發明的另一實施例的資料存取方法的示意圖。 圖3繪示本發明的另一實施例的資料存取方法的示意圖。 圖4繪示本發明的另一實施例的資料存取方法的示意圖。 圖5繪示本發明的實施例的記憶體裝置的方塊圖。FIG. 1 shows a flowchart of a data access method according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a data access method according to another embodiment of the present invention. FIG. 3 is a schematic diagram of a data access method according to another embodiment of the present invention. FIG. 4 is a schematic diagram of a data access method according to another embodiment of the present invention. FIG. 5 is a block diagram of a memory device according to an embodiment of the invention.
S110~S120:步驟 S110~S120: steps
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