TW202046275A - PWM signal generating circuit, source electrode driving chip and LED display device wherein the circuit includes a first pulse width modulation unit, a multiplexer, a second pulse width modulation unit, a PWM signal generator, and a multi-phase clock signal generating unit - Google Patents

PWM signal generating circuit, source electrode driving chip and LED display device wherein the circuit includes a first pulse width modulation unit, a multiplexer, a second pulse width modulation unit, a PWM signal generator, and a multi-phase clock signal generating unit Download PDF

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TW202046275A
TW202046275A TW109127536A TW109127536A TW202046275A TW 202046275 A TW202046275 A TW 202046275A TW 109127536 A TW109127536 A TW 109127536A TW 109127536 A TW109127536 A TW 109127536A TW 202046275 A TW202046275 A TW 202046275A
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pulse width
width modulation
pwm signal
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display data
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TWI745024B (en
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黃志正
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大陸商北京集創北方科技股份有限公司
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Abstract

The present invention discloses a PWM signal generating circuit, which is applied to a constant current source electrode driving chip and includes a first pulse width modulation unit, a multiplexer, a second pulse width modulation unit, a PWM signal generator, and a multi-phase clock signal generating unit. In particular, the PWM signal generating circuit of the present invention is implemented in the constant current source electrode driving chip in the form of a digital module, so as to be capable of providing a high precision PWM signal to a display gray scale comparison unit in the constant current source electrode driving chip without increasing chip power consumption and causing influence on the original PWM signal generation function. Therefore, the invention can accurately control the gray scale value of each LED element of a LED display panel to a decimal point. Therefore, the PWM signal generating circuit of the present invention facilitates to improve a display accuracy of the LED display panel without increasing additional hardware and system design costs of the constant current source electrode driving chip.

Description

PWM信號產生電路、源極驅動晶片、及LED顯示裝置PWM signal generating circuit, source driver chip, and LED display device

本發明係關於LED顯示驅動之技術領域，尤指應用在一定電流源極驅動晶片之中一種PWM信號產生電路。The present invention relates to the technical field of LED display driving, and particularly refers to a PWM signal generating circuit applied to a certain current source driving chip.

發光二極體(Light-emitting diode , LED)具有體積小、重量輕、使用壽命長、結構堅固、發光效率高等多項優點。LED顯示裝置為一種平板顯示裝置，其使用複數個發光二極體(LED)組成顯示像素陣列，具有色彩鮮艷、動態範圍廣、亮度高、壽命長、可靠度高等優點，是以LED顯示裝置已廣泛地應用於大型廣場、商業廣告、體育場館、信息傳播、新聞發布、證券交易場所，作為一種公眾顯示媒介。Light-emitting diode (LED) has many advantages such as small size, light weight, long service life, solid structure, and high luminous efficiency. The LED display device is a flat panel display device that uses a plurality of light-emitting diodes (LEDs) to form a display pixel array. It has the advantages of bright colors, wide dynamic range, high brightness, long life, and high reliability. It is widely used in large squares, commercial advertisements, stadiums, information dissemination, press releases, and securities trading venues, as a public display medium.

圖1顯示習知的一種LED顯示裝置的架構圖。如圖1所示，習知的LED顯示裝置包括：由複數個LED元件11a組成的一LED顯示面板1a、一閘極驅動電路2a、一源極驅動電路3a、以及一顯示控制器4a。正常工作時，該顯示控制器4a傳送一灰度時鐘信號(GCLK)、一鎖存使能信號(LE)、一串行顯示資料(SDI)、一顯示資料時鐘信號(DCLK)、以及一驅動電流調整信號至該定電流源極驅動晶片3a。習知的定電流源極驅動晶片3a通常內部包含一PWM信號產生單元，其用以依據所述灰度時鐘信號(GCLK)而產生至少一PWM信號傳送至習知的定電流源極驅動晶片3a內部的一顯示灰度比較單元，令該顯示灰度比較單元基於該PWM信號以及複數個顯示資料而生成複數個控制信號，從而控制一定電流驅動單元生成複數個定電流信號，藉以驅動對應的LED元件11a發出對應亮度值的光，達成各顯示像素之灰階調整(控制)。FIG. 1 shows a structure diagram of a conventional LED display device. As shown in FIG. 1, the conventional LED display device includes: an LED display panel 1a composed of a plurality of LED elements 11a, a gate driving circuit 2a, a source driving circuit 3a, and a display controller 4a. In normal operation, the display controller 4a transmits a grayscale clock signal (GCLK), a latch enable signal (LE), a serial display data (SDI), a display data clock signal (DCLK), and a drive The current adjustment signal is sent to the constant current source driving chip 3a. The conventional constant current source driver chip 3a usually includes a PWM signal generating unit, which is used to generate at least one PWM signal according to the gray clock signal (GCLK) and send it to the conventional constant current source driver chip 3a An internal display gray scale comparison unit makes the display gray scale comparison unit generate a plurality of control signals based on the PWM signal and a plurality of display data, thereby controlling a certain current driving unit to generate a plurality of constant current signals, thereby driving the corresponding LED The element 11a emits light corresponding to the brightness value to achieve grayscale adjustment (control) of each display pixel.

可惜的是，製程飄移或誤差導致所述LED顯示面板1a的每個LED元件11a無法顯示出完全相同的發光特性。在此情況下，即使利用相同的定電流來驅動每個LED元件11a發光，各所述LED元件11a也不會顯示出相同的發光亮度，導致LED顯示面板1a發生色偏現象。因此，逐點校正補償方法被提出且應用於校正、補償所述LED顯示面板1a的每個LED元件11a的亮度控制。進行逐點校正補償方法時，必須在每個LED元件11a顯示最高灰階時利用灰階檢測儀器測量其顯示亮度，而後根據測量數據對應於各所述LED元件11a的該PWM信號乘以一調整係數，從而將亮度過高的LED元件11a的PWM信號的脈寬(Pulse width)調小，完成各個LED元件11a的逐點校正補償。Unfortunately, due to process drift or error, each LED element 11a of the LED display panel 1a cannot show exactly the same light-emitting characteristics. In this case, even if each LED element 11a is driven to emit light with the same constant current, each of the LED elements 11a will not show the same light-emitting brightness, causing color shift in the LED display panel 1a. Therefore, a point-by-point correction compensation method is proposed and applied to correct and compensate the brightness control of each LED element 11a of the LED display panel 1a. When performing the point-by-point correction and compensation method, each LED element 11a must be used to measure its display brightness when the highest gray level is displayed, and then the PWM signal corresponding to each LED element 11a is multiplied by one according to the measurement data. Therefore, the pulse width (Pulse width) of the PWM signal of the LED element 11a whose brightness is too high is reduced, and the point-by-point correction compensation of each LED element 11a is completed.

逐點校正補償方法在LED顯示面板1a進行高灰階顯示時展現出非常好的(灰階)補償效果。然而，在所述LED顯示面板1a進行低灰階顯示時，逐點校正補償方法反而可能導致顯示效果變差。更詳細地解釋，在要求LED顯示面板1a顯示一個灰階為10的圖像的情況下，一個LED元件A的灰階在經過補償後變為9.4，而另一個LED元件B的灰階在經過補償後則為9.6，使得兩個LED元件之間的灰階差異只有0.2。然而，現有的市售源極驅動電路3a之集成電路晶片通常為16-bit，故其灰階精度有限。更具體地說明，由於顯示控制器4a所發送的串行資料信號只包含整數部分的(灰階)顯示資料，使得16-bit的源極驅動電路(晶片)3a也只能夠依據僅包含整數部分的(灰階)顯示資料以及灰度時鐘信號(GCLK)而產生複數個所述定電流信號。在此情況下，LED元件A的灰階會被四捨五入成為9，而LED元件B的灰階會被四捨五入成為10，最終反而導致LED元件A和LED元件B之間的灰階差異變得更大。The point-by-point correction compensation method exhibits a very good (gray-scale) compensation effect when the LED display panel 1a performs high-gray-scale display. However, when the LED display panel 1a performs low-gray-scale display, the point-by-point correction compensation method may cause the display effect to deteriorate. To explain in more detail, when the LED display panel 1a is required to display an image with a gray scale of 10, the gray scale of one LED element A becomes 9.4 after compensation, while the gray scale of the other LED element B is After compensation, it is 9.6, making the gray scale difference between the two LED components only 0.2. However, the integrated circuit chip of the existing commercially available source driving circuit 3a is usually 16-bit, so its gray scale accuracy is limited. More specifically, because the serial data signal sent by the display controller 4a only contains the integer part (gray scale) display data, the 16-bit source driver circuit (chip) 3a can only be based on the integer part only. (Grayscale) display data and grayscale clock signal (GCLK) to generate a plurality of the constant current signals. In this case, the gray scale of LED element A will be rounded to 9, and the gray scale of LED element B will be rounded to 10. In the end, the difference in gray scale between LED element A and LED element B becomes larger. .

設換句話說，欲使該顯示控制器4a發出的串行資料信號同時包含整數部分的顯示資料以及小數(浮點數)部分的顯示資料，則必須以17bits或18bits傳送整個顯示資料。但是，現有的市售16-bit的源極驅動電路(晶片)3a並無法直接處理17bits或18bits的顯示資料。唯一的方式是提高灰度時鐘信號(GCLK)的頻率，但此一方式又會造成源極驅動電路(晶片)3a的功耗急劇增加，同時造成電路設計的複雜度增加。In other words, if the serial data signal sent by the display controller 4a contains both the integer part of the display data and the decimal (floating point) part of the display data, the entire display data must be transmitted in 17 bits or 18 bits. However, the existing commercially available 16-bit source driver circuit (chip) 3a cannot directly process 17-bit or 18-bit display data. The only way is to increase the frequency of the grayscale clock signal (GCLK), but this way will cause the power consumption of the source drive circuit (chip) 3a to increase sharply, and at the same time increase the complexity of the circuit design.

由上述說明可知，本領域亟需一種新式的PWM信號產生電路。It can be seen from the above description that there is an urgent need for a new PWM signal generating circuit in the art.

本發明之主要目的在於提供一種PWM信號產生電路，其以數位電路的形式實現在一定電流源極驅動晶片之中，能夠在不增加晶片功耗且不對原PWM信號產生功能造成影響的情況下，提供高精度的PWM信號給該定電流源極驅動晶片內部的顯示灰度比較單元，從而能夠精準地控制LED顯示面板的每個LED元件的灰階值至小數點(浮點數)。因此，利用含有本發明之PWM信號產生電路的定電流源極驅動晶片對一LED顯示面板進行顯示驅動，係能夠有效提高該LED顯示面板的顯示精度，同時不會增加額外的硬體及系統端設計成本。The main purpose of the present invention is to provide a PWM signal generating circuit, which is implemented in a certain current source driving chip in the form of a digital circuit, which can not increase chip power consumption and affect the original PWM signal generating function. A high-precision PWM signal is provided to the display gray scale comparison unit inside the constant current source driver chip, so that the gray scale value of each LED element of the LED display panel can be accurately controlled to a decimal point (floating point number). Therefore, using the constant current source driver chip containing the PWM signal generating circuit of the present invention to display and drive an LED display panel can effectively improve the display accuracy of the LED display panel without adding additional hardware and system terminals. Design cost.

為達成上述目的，本發明提出所述PWM信號產生電路的一實施例，其應用於一定電流源極驅動晶片之中，且包括：To achieve the above objective, the present invention provides an embodiment of the PWM signal generating circuit, which is applied to a certain current source driving chip, and includes:

一第一脈寬調製單元，耦接一第一顯示資料以及一第一灰度時鐘信號，用以依該第一顯示資料和該第一灰度時鐘信號而產生一第一脈寬調製信號；A first pulse width modulation unit, coupled to a first display data and a first grayscale clock signal, for generating a first pulse width modulation signal according to the first display data and the first grayscale clock signal;

一多工器，耦接包含該第一灰度時鐘信號的一多相位灰度時鐘信號和一第二顯示資料，用以依該第二顯示資料而自所述多相位灰度時鐘信號中擇一，從而輸出一選定相位灰度時鐘信號；其中，該第一顯示資料與該第二顯示資料係分離自一串行顯示資料；A multiplexer, coupled to a multi-phase gray clock signal containing the first gray clock signal and a second display data, for selecting from the multi-phase gray clock signal according to the second display data One, thereby outputting a selected phase grayscale clock signal; wherein the first display data and the second display data are separated from a serial display data;

一第一延遲單元，耦接該多工器所傳送的該選定相位時鐘信號以及該第一脈寬調製單元所傳送的該第一脈寬調製信號，且在該選定相位灰度時鐘信號的控制下對所述第一脈寬調製信號進行一信號延遲處理，從而輸出一脈寬調製信號；以及A first delay unit, coupled to the selected phase clock signal transmitted by the multiplexer and the first pulse width modulation signal transmitted by the first pulse width modulation unit, and in the control of the selected phase gray clock signal Performing a signal delay processing on the first pulse width modulation signal to output a pulse width modulation signal; and

一PWM信號產生單元，耦接該第一延遲單元所傳送的該脈寬調製信號及該第一脈寬調製單元所傳送的該第一脈寬調製信號，從而依據所述第一脈寬調製信號和所述脈寬調製信號而產生一PWM信號，且將該PWM信號傳送至所述定電流源極驅動晶片內部的一顯示灰度比較單元。A PWM signal generating unit coupled to the pulse width modulation signal transmitted by the first delay unit and the first pulse width modulation signal transmitted by the first pulse width modulation unit, so as to be based on the first pulse width modulation signal And the pulse width modulation signal to generate a PWM signal, and transmit the PWM signal to a display gray scale comparison unit inside the constant current source driver chip.

在一實施例中，該PWM信號產生單元為選自於由或邏輯閘與及邏輯閘所組成群組之一種邏輯單元。In one embodiment, the PWM signal generating unit is a logic unit selected from the group consisting of OR logic gate and logic gate.

在一實施例中，更包括耦接於該第一脈寬調製單元和該PWM信號產生單元之間的一第二延遲單元，其耦接所述第一灰度時鐘信號以及傳送自耦接該第一脈寬調製單元的該第一脈寬調製信號，從而在該第一灰度時鐘信號的控制下對所述第一脈寬調製信號進行所述信號延遲處理，進以輸出一第二脈寬調製信號傳送至該PWM信號產生單元，使該PWM信號產生單元依所述第二脈寬調製信號和所述脈寬調製信號產生所述PWM信號。In one embodiment, it further includes a second delay unit coupled between the first pulse width modulation unit and the PWM signal generating unit, which is coupled to the first gray-scale clock signal and transmits from the coupling to the The first pulse width modulation signal of the first pulse width modulation unit, so that the signal delay processing is performed on the first pulse width modulation signal under the control of the first gray-scale clock signal to output a second pulse The width modulation signal is transmitted to the PWM signal generating unit, so that the PWM signal generating unit generates the PWM signal according to the second pulse width modulation signal and the pulse width modulation signal.

在一實施例中，該第二延遲單元與該第一延遲單元皆為一D型正反器。In one embodiment, the second delay unit and the first delay unit are both a D-type flip-flop.

在一實施例中，該第一顯示資料和該第二顯示資料係傳送自一顯示控制器，且該第一顯示資料為所述串行顯示資料的整數部分，該第二顯示資料則為所述串行顯示資料的小數部分。In one embodiment, the first display data and the second display data are transmitted from a display controller, and the first display data is an integer part of the serial display data, and the second display data is all The decimal part of the serial display data.

在一實施例中，一顯示控制器將所述第一顯示資料和一小數指示信號傳送至該定電流源極驅動晶片，且該第二顯示資料依據所述小數指示信號而產生。In one embodiment, a display controller transmits the first display data and a decimal indication signal to the constant current source driver chip, and the second display data is generated according to the decimal indication signal.

在一實施例中，一顯示控制器傳送所述串行顯示資料至該定電流源極驅動晶片，且該定電流源極驅動晶片內部的一控制單元將所述串行顯示資料分割為該第一顯示資料和該第二顯示資料。In one embodiment, a display controller transmits the serial display data to the constant current source driver chip, and a control unit inside the constant current source driver chip divides the serial display data into the first One display data and the second display data.

在一實施例中，本發明之PWM信號產生電路更包括一多相位時鐘信號產生單元，用以產生所述多相位灰度時鐘信號。In one embodiment, the PWM signal generating circuit of the present invention further includes a multi-phase clock signal generating unit for generating the multi-phase gray clock signal.

本發明同時提供一種源極驅動晶片，其包含如前所述之PWM信號產生電路。The present invention also provides a source driver chip, which includes the PWM signal generating circuit as described above.

本發明同時提供一種LED顯示裝置，其具有一LED顯示面板及至少一源極驅動晶片，該源極驅動晶片具有如前所述之PWM信號產生電路。The present invention also provides an LED display device, which has an LED display panel and at least one source driver chip, and the source driver chip has the aforementioned PWM signal generating circuit.

為使  貴審查委員能進一步瞭解本發明之結構、特徵、目的、與其優點，茲附以圖式及較佳具體實施例之詳細說明如後。In order to enable your reviewer to further understand the structure, features, purpose, and advantages of the present invention, the drawings and detailed descriptions of preferred specific embodiments are attached as follows.

圖2顯示包含本發明之一定電流源極驅動晶片的一種LED顯示裝置的架構圖。如圖2所示，LED顯示裝置包括：由複數個LED元件11組成的一LED顯示面板1、一閘極驅動電路2、至少一本發明之定電流源極驅動晶片3、以及一顯示控制器4(系統端)。正常工作時，該顯示控制器4傳送一灰度時鐘信號(GCLK)、一鎖存使能信號(LE)、一串行顯示資料(SDI)、一顯示資料時鐘信號(DCLK)、以及一驅動電流調整信號至該定電流源極驅動晶片3。特別地，本發明利用一多相位時鐘信號產生單元依據所述灰度時鐘信號(GCLK)而產生一多相位灰度時鐘信號GCLK＜7:0＞，目的在於依此多相位灰度時鐘信號GCLK＜7:0＞配合本發明之PWM信號產生電路36而對一PWM信號執行一脈寬擴展處理或一脈寬縮減處理。如此，該PWM信號被傳送至該定電流源極驅動晶片3內部的顯示灰度比較單元，從而能夠精準地控制LED顯示面板1的每個LED元件11的灰階值至小數點(浮點數)。FIG. 2 shows a structural diagram of an LED display device including a certain current source driver chip of the present invention. As shown in FIG. 2, the LED display device includes: an LED display panel composed of a plurality of LED elements 11, a gate drive circuit 2, at least one constant current source drive chip 3 of the present invention, and a display controller 4 (System side). In normal operation, the display controller 4 transmits a grayscale clock signal (GCLK), a latch enable signal (LE), a serial display data (SDI), a display data clock signal (DCLK), and a driver The current adjustment signal is sent to the constant current source to drive the chip 3. In particular, the present invention uses a multi-phase clock signal generating unit to generate a multi-phase gray clock signal GCLK<7:0> according to the gray clock signal (GCLK), and the purpose is to use the multi-phase gray clock signal GCLK accordingly <7:0> Cooperate with the PWM signal generating circuit 36 of the present invention to perform a pulse width expansion process or a pulse width reduction process on a PWM signal. In this way, the PWM signal is transmitted to the display gray scale comparison unit inside the constant current source driver chip 3, so that the gray scale value of each LED element 11 of the LED display panel 1 can be accurately controlled to a decimal point (floating point number). ).

在可行的實施例中，所述多相位時鐘信號產生例如為鎖相迴路(Phase-Locked Loop,PLL )、延遲鎖定迴路(Delay-Locked Loop, DLL)或相位內差器(Phase Interpolator)。進一步地，圖3顯多相位灰度時鐘信號GCLK＜7:0＞的工作時序圖，且圖4顯示本發明之一種PWM信號產生電路的第一電路方塊圖。如圖2、圖3和圖4所示，本發明之PWM信號產生電路36應用於一定電流源極驅動晶片3之中，且包括：一第一脈寬調製單元361、一多工器362、一第一延遲單元363、以及一PWM信號產生單元364。其中，該第一脈寬調製單元361耦接一第一顯示資料N＜15:0＞以及一第一灰度時鐘信號GCLK＜0＞，用以依該第一顯示資料N＜15:0＞和該第一灰度時鐘信號GCLK＜0＞而產生一第一脈寬調製信號PWMN1。應可理解，為了在PWM信號的原始脈寬中擴展出用以表示小數點(浮點數)之部分，以3bit浮點數為例，圖3所示之多相位灰度時鐘信號GCLK＜7:0＞包含第一灰度時鐘信號GCLK＜0＞、第二灰度時鐘信號GCLK＜1＞、第三灰度時鐘信號GCLK＜2＞、第四灰度時鐘信號GCLK＜3＞、第五灰度時鐘信號GCLK＜4＞、第六灰度時鐘信號GCLK＜5＞、以及第七灰度時鐘信號GCLK＜6＞。In a feasible embodiment, the multi-phase clock signal generation is, for example, a phase-locked loop (PLL), a delay-locked loop (DLL), or a phase interpolator (Phase Interpolator). Further, FIG. 3 shows a working timing diagram of the multi-phase gray clock signal GCLK<7:0>, and FIG. 4 shows a first circuit block diagram of a PWM signal generating circuit of the present invention. As shown in FIGS. 2, 3, and 4, the PWM signal generating circuit 36 of the present invention is applied to a certain current source driving chip 3, and includes: a first pulse width modulation unit 361, a multiplexer 362, A first delay unit 363 and a PWM signal generating unit 364. Wherein, the first pulse width modulation unit 361 is coupled to a first display data N<15:0> and a first gray-scale clock signal GCLK<0>, so as to comply with the first display data N<15:0> And the first gray clock signal GCLK<0> to generate a first pulse width modulation signal PWMN1. It should be understood that, in order to extend the part used to represent the decimal point (floating point number) in the original pulse width of the PWM signal, taking a 3bit floating point number as an example, the multi-phase grayscale clock signal GCLK<7 as shown in Figure 3 :0> includes the first gray-scale clock signal GCLK<0>, the second gray-scale clock signal GCLK<1>, the third gray-scale clock signal GCLK<2>, the fourth gray-scale clock signal GCLK<3>, the fifth The grayscale clock signal GCLK<4>, the sixth grayscale clock signal GCLK<5>, and the seventh grayscale clock signal GCLK<6>.

更詳細地說明，該多工器362耦接包含該第一灰度時鐘信號GCLK＜0＞之所述多相位灰度時鐘信號GCLK＜7:0＞以及一第二顯示資料F＜2:0＞，用以依該第二顯示資料F＜2:0＞而自所述多相位灰度時鐘信號GCLK＜7:0＞中擇一，從而輸出一選定相位灰度時鐘信號GCLKs。在一可行實施例中，該第一顯示資料N＜15:0＞和該第二顯示資料F＜2:0＞係傳送自該顯示控制器4，且該第一顯示資料N＜15:0＞為所述串行顯示資料的整數部分，該第二顯示資料F＜2:0＞則為所述串行顯示資料的小數部分。並且，當顯示控制器4傳送所述串行顯示資料至該定電流源極驅動晶片3後，且該定電流源極驅動晶片3內部的一控制單元將所述串行顯示資料分割為該第一顯示資料N＜15:0＞和該第二顯示資料F＜2:0＞。然而，必須加以說明的是，在另一可行實施例中，顯示控制器4也可以傳送所述第一顯示資料N＜15:0＞和一小數指示信號至該定電流源極驅動晶片3，使該定電流源極驅動晶片3內部的該控制單元依據所述小數指示信號而自所述串行顯示資料之中分離出該第二顯示資料F＜2:0＞。In more detail, the multiplexer 362 is coupled to the multi-phase gray clock signal GCLK<7:0> including the first gray clock signal GCLK<0> and a second display data F<2:0 > To select one of the multi-phase gray-scale clock signals GCLK<7:0> according to the second display data F<2:0>, so as to output a selected-phase gray-scale clock signal GCLKs. In a possible embodiment, the first display data N<15:0> and the second display data F<2:0> are sent from the display controller 4, and the first display data N<15:0 > Is the integer part of the serial display data, and the second display data F<2:0> is the decimal part of the serial display data. And, after the display controller 4 transmits the serial display data to the constant current source driver chip 3, and a control unit inside the constant current source driver chip 3 divides the serial display data into the first One display data N<15:0> and the second display data F<2:0>. However, it must be noted that in another feasible embodiment, the display controller 4 may also transmit the first display data N<15:0> and a decimal indication signal to the constant current source driver chip 3. The control unit inside the constant current source driving chip 3 separates the second display data F<2:0> from the serial display data according to the decimal indication signal.

如圖3與圖4所示，該第一延遲單元363為一D型正反器，其以一資料信號接收端(D端)耦該第一脈寬調製單元361所傳送的該第一脈寬調製信號PWMN1，且以一時鐘信號接收端(CLK端)耦接該多工器362所傳送的該選定相位灰度時鐘信號GCLKs。並且，在該選定相位灰度時鐘信號GCLKs的控制下，該第一延遲單元363對所述第一脈寬調製信號PWMN1進行一信號延遲處理，從而透過其一資料信號輸出端(Q端)輸出一脈寬調製信號PWMD 。另一方面，該PWM信號產生單元364耦接該第一延遲單元363所傳送的該脈寬調製信號PWMD以及該第一脈寬調製單元361所傳送的該第一脈寬調製信號PWMN1，從而依據所述第一脈寬調製信號PWMN1和所述脈寬調製信號PWMD而產生一PWM信號，且將該PWM信號傳送至所述定電流源極驅動晶片3內部的一顯示灰度比較單元。As shown in FIGS. 3 and 4, the first delay unit 363 is a D-type flip-flop, and a data signal receiving end (end D) is coupled to the first pulse transmitted by the first pulse width modulation unit 361 The wide modulation signal PWMN1 is coupled to the selected phase gray-scale clock signal GCLKs transmitted by the multiplexer 362 via a clock signal receiving terminal (CLK terminal). And, under the control of the selected phase gray-scale clock signal GCLKs, the first delay unit 363 performs a signal delay processing on the first pulse width modulation signal PWMN1, thereby outputting it through one of its data signal output terminals (Q terminals) A pulse width modulation signal PWM D. On the other hand, the PWM signal generating unit 364 is coupled to the pulse width modulation signal PWMD transmitted by the first delay unit 363 and the first pulse width modulation signal PWMN1 transmitted by the first pulse width modulation unit 361, so as to be based on The first pulse width modulation signal PWMN1 and the pulse width modulation signal PWMD generate a PWM signal, and the PWM signal is transmitted to a display gray scale comparison unit inside the constant current source driving chip 3.

圖5顯示第一灰度時鐘信號GCLK＜0＞、第一脈寬調製信號PWMN1、選定相位灰度時鐘信號GCLKs、脈寬調製信號PWMD 、以及PWM信號的工作時序圖。如圖5和圖4所示，在接收第一顯示資料N＜15:0＞和第一灰度時鐘信號GCLK＜0＞之後，該第一脈寬調製單元361生成第一脈寬調製信號PWMN1。另一方面，在接收第二顯示資料F＜2:0＞和多相位灰度時鐘信號GCLK＜7:0＞之後，該多工器362自所述多相位灰度時鐘信號GCLK＜7:0＞中擇一，從而輸出一選定相位灰度時鐘信號GCLKs。進一步地，在接收該選定相位灰度時鐘信號GCLKs和該第一脈寬調製信號PWMN1之後，該第一延遲單元363在該選定相位灰度時鐘信號GCLKs的控制下對所述第一脈寬調製信號PWMN1進行一信號延遲處理，從而輸出所述脈寬調製信號PWMD 。FIG. 5 shows the working sequence diagram of the first grayscale clock signal GCLK<0>, the first pulse width modulation signal PWMN1, the selected phase grayscale clock signal GCLKs, the pulse width modulation signal PWM D , and the PWM signal. As shown in FIG. 5 and FIG. 4, after receiving the first display data N<15:0> and the first grayscale clock signal GCLK<0>, the first pulse width modulation unit 361 generates the first pulse width modulation signal PWMN1 . On the other hand, after receiving the second display data F<2:0> and the multi-phase gray-scale clock signal GCLK<7:0>, the multiplexer 362 obtains data from the multi-phase gray-scale clock signal GCLK<7:0 >Choose one to output a selected phase gray-scale clock signal GCLKs. Further, after receiving the selected phase grayscale clock signal GCLKs and the first pulse width modulation signal PWMN1, the first delay unit 363 modulates the first pulse width under the control of the selected phase grayscale clock signal GCLKs The signal PWMN1 undergoes a signal delay processing to output the pulse width modulation signal PWM D.

圖4顯示該PWM信號產生單元364為一或邏輯閘。因此，如圖4和圖5所示，在接收該脈寬調製信號PWMD 和該第一脈寬調製信號PWMN1之後，該PWM信號產生單元364即對該脈寬調製信號PWMD 與該第一脈寬調製信號PWMN1進行一或邏輯運算，從而產生一PWM信號。值得注意的是，圖5顯示該PWM信號的脈寬已經被擴展。如此，該PWM信號被傳送至該定電流源極驅動晶片3內部的顯示灰度比較單元，從而能夠精準地控制LED顯示面板1的每個LED元件11的灰階值至小數點(浮點數)。FIG. 4 shows that the PWM signal generating unit 364 is an OR logic gate. Accordingly, and as shown in FIG. 4, after receiving the pulse width modulation signal PWM D and the first pulse width modulated signal PWMN1, the PWM signal generating unit 364 i.e. the pulse width modulation signal PWM to the first D in FIG. 5 The pulse width modulation signal PWMN1 performs an OR logic operation to generate a PWM signal. It is worth noting that Figure 5 shows that the pulse width of the PWM signal has been expanded. In this way, the PWM signal is transmitted to the display gray scale comparison unit inside the constant current source driver chip 3, so that the gray scale value of each LED element 11 of the LED display panel 1 can be accurately controlled to a decimal point (floating point number). ).

由圖5可知，該PWM信號是被向左擴展。然而，在可行的實施例中，該PWM信號也可以被向右擴展。圖6顯示本發明之一種PWM信號產生電路的第二電路方塊圖。比較圖6與圖4可知，本發明之PWM信號產生電路36的第二電路結構更包括：耦接於該第一脈寬調製單元361和該PWM信號產生單元364之間的一第二延遲單元365。更詳細地說明，該第二延遲單元365為一D型正反器，其以一時鐘信號接收端(CLK端)耦接該第一灰度時鐘信號GCLK＜0＞，且以一資料信號接收端(D端)耦該第一脈寬調製單元361所傳送的該第一脈寬調製信號PWMN1。如此，從而在該第一灰度時鐘信號GCLK＜0＞的控制下，該第二延遲單元365對所述第一脈寬調製信號PWMN1進行一信號延遲處理，從而輸出一第二脈寬調製信號PWMN2傳送至該PWM信號產生單元364，使該PWM信號產生單元364依所述第二脈寬調製信號PWMN2以及所述脈寬調製信號PWMD 而產生所述PWM信號。It can be seen from Figure 5 that the PWM signal is extended to the left. However, in a feasible embodiment, the PWM signal can also be extended to the right. FIG. 6 shows a second circuit block diagram of a PWM signal generating circuit of the present invention. Comparing FIG. 6 with FIG. 4, the second circuit structure of the PWM signal generating circuit 36 of the present invention further includes: a second delay unit coupled between the first pulse width modulation unit 361 and the PWM signal generating unit 364 365. In more detail, the second delay unit 365 is a D-type flip-flop, which is coupled to the first gray-scale clock signal GCLK<0> by a clock signal receiving terminal (CLK terminal), and receives a data signal The terminal (D terminal) is coupled to the first pulse width modulation signal PWMN1 transmitted by the first pulse width modulation unit 361. In this way, under the control of the first gray-scale clock signal GCLK<0>, the second delay unit 365 performs a signal delay process on the first pulse width modulation signal PWMN1, thereby outputting a second pulse width modulation signal PWMN2 is transmitted to the PWM signal generating unit 364, so that the PWM signal generating unit 364 generates the PWM signal according to the second pulse width modulation signal PWMN2 and the pulse width modulation signal PWM D.

圖7顯示第一灰度時鐘信號GCLK＜0＞、第一脈寬調製信號PWMN1、第二脈寬調製信號PWMN2、選定相位灰度時鐘信號GCLKs、脈寬調製信號PWMD 、以及PWM信號的工作時序圖。如圖7和圖6所示，在接收第一顯示資料N＜15:0＞和第一灰度時鐘信號GCLK＜0＞之後，該第一脈寬調製單元361生成第一脈寬調製信號PWMN1。另一方面，在接收第二顯示資料F＜2:0＞和多相位灰度時鐘信號GCLK＜7:0＞之後，該多工器362自所述多相位灰度時鐘信號GCLK＜7:0＞中擇一，從而輸出一選定相位灰度時鐘信號GCLKs。進一步地，在接收該選定相位灰度時鐘信號GCLKs和該第一脈寬調製信號PWMN1之後，該第一延遲單元363在該選定相位灰度時鐘信號GCLKs的控制下對所述第一脈寬調製信號PWMN1進行一信號延遲處理，從而輸出所述脈寬調製信號PWMD 。另一方面，在接收該第一灰度時鐘信號GCLK＜0＞以及傳送自該第一脈寬調製單元361的該第一脈寬調製信號PWMN1之後，該第二延遲單元365在該選定相位灰度時鐘信號GCLKs的控制下對所述第一脈寬調製信號PWMN1進行一信號延遲處理，從而輸出所述第二脈寬調製信號PWMN2。Figure 7 shows the operation of the first gray-scale clock signal GCLK<0>, the first pulse-width modulation signal PWMN1, the second pulse-width modulation signal PWMN2, the selected phase gray-scale clock signal GCLKs, the pulse-width modulation signal PWM D , and the PWM signal Timing diagram. As shown in FIG. 7 and FIG. 6, after receiving the first display data N<15:0> and the first grayscale clock signal GCLK<0>, the first pulse width modulation unit 361 generates the first pulse width modulation signal PWMN1 . On the other hand, after receiving the second display data F<2:0> and the multi-phase gray-scale clock signal GCLK<7:0>, the multiplexer 362 obtains data from the multi-phase gray-scale clock signal GCLK<7:0 >Choose one to output a selected phase gray-scale clock signal GCLKs. Further, after receiving the selected phase grayscale clock signal GCLKs and the first pulse width modulation signal PWMN1, the first delay unit 363 modulates the first pulse width under the control of the selected phase grayscale clock signal GCLKs The signal PWMN1 undergoes a signal delay processing to output the pulse width modulation signal PWM D. On the other hand, after receiving the first gray-scale clock signal GCLK<0> and the first pulse-width modulation signal PWMN1 transmitted from the first pulse-width modulation unit 361, the second delay unit 365 performs a gray-scale operation in the selected phase. A signal delay process is performed on the first pulse width modulation signal PWMN1 under the control of the degree clock signal GCLKs, so as to output the second pulse width modulation signal PWMN2.

圖6顯示該PWM信號產生單元364為一或邏輯閘。因此，如圖6和圖7所示，在接收該脈寬調製信號PWMD 和該第二脈寬調製信號PWMN2之後，該PWM信號產生單元364即對該脈寬調製信號PWMD 與該第二脈寬調製信號PWMN2進行一或邏輯運算，從而產生一PWM信號。值得注意的是，圖7顯示該PWM信號的脈寬已經被(向右)擴展。如此，該PWM信號被傳送至該定電流源極驅動晶片3內部的顯示灰度比較單元，從而能夠精準地控制LED顯示面板1的每個LED元件11的灰階值至小數點(浮點數)。FIG. 6 shows that the PWM signal generating unit 364 is an OR logic gate. Thus, as shown in FIGS. 6 and 7, after receiving the pulse width modulation signal PWM D and the second pulse width modulated signal PWMN2, the PWM signal generating unit 364 i.e. the pulse width modulated signal and the second PWM D The pulse width modulation signal PWMN2 performs an OR logic operation to generate a PWM signal. It is worth noting that Figure 7 shows that the pulse width of the PWM signal has been extended (to the right). In this way, the PWM signal is transmitted to the display gray scale comparison unit inside the constant current source driver chip 3, so that the gray scale value of each LED element 11 of the LED display panel 1 can be accurately controlled to a decimal point (floating point number). ).

因此，圖5與圖7的工作時序圖顯示，本發明之PWM信號產生電路36可將PWM信號的脈寬進行向左擴展或向右擴展。然而，在可行的實施例中，本發明之PWM信號產生電路36也可以對PWM信號執行一脈寬縮減處理。圖8顯示本發明之一種PWM信號產生電路的第三電路方塊圖。比較圖8與圖4可知，在本發明之PWM信號產生電路36的第二電路結構之中，該PWM信號產生單元364為一及邏輯閘。Therefore, the working timing diagrams of FIGS. 5 and 7 show that the PWM signal generating circuit 36 of the present invention can extend the pulse width of the PWM signal to the left or to the right. However, in a feasible embodiment, the PWM signal generating circuit 36 of the present invention can also perform a pulse width reduction process on the PWM signal. FIG. 8 shows a third circuit block diagram of a PWM signal generating circuit of the present invention. Comparing FIG. 8 with FIG. 4, it can be seen that in the second circuit structure of the PWM signal generating circuit 36 of the present invention, the PWM signal generating unit 364 is an AND logic gate.

圖9顯示第一灰度時鐘信號GCLK＜0＞、第一脈寬調製信號PWMN1、選定相位灰度時鐘信號GCLKs、脈寬調製信號PWMD 、以及PWM信號的工作時序圖。如圖9和圖8所示，在接收該脈寬調製信號PWMD 和該第一脈寬調製信號PWMN1之後，該PWM信號產生單元364即對該脈寬調製信號PWMD 與該第一脈寬調製信號PWMN1進行一及邏輯運算，從而產生一PWM信號。值得注意的是，圖5顯示該PWM信號的脈寬已經被向左縮減。如此，該PWM信號被傳送至該定電流源極驅動晶片3內部的顯示灰度比較單元，從而能夠精準地控制LED顯示面板1的每個LED元件11的灰階值至小數點(浮點數)。FIG. 9 shows the working sequence diagram of the first gray-scale clock signal GCLK<0>, the first pulse width modulation signal PWMN1, the selected phase gray-scale clock signal GCLKs, the pulse width modulation signal PWM D , and the PWM signal. As shown in FIG. 9 and FIG. 8, after receiving the pulse width modulation signal PWM D and the first pulse width modulation signal PWMN1, the PWM signal generation unit 364 performs the pulse width modulation signal PWM D and the first pulse width The modulation signal PWMN1 performs an AND logic operation to generate a PWM signal. It is worth noting that Figure 5 shows that the pulse width of the PWM signal has been reduced to the left. In this way, the PWM signal is transmitted to the display gray scale comparison unit inside the constant current source driver chip 3, so that the gray scale value of each LED element 11 of the LED display panel 1 can be accurately controlled to a decimal point (floating point number). ).

圖9顯示該PWM信號是被向左縮減。然而，在可行的實施例中，該PWM信號也可以被向右縮減。圖10顯示本發明之一種PWM信號產生電路的第四電路方塊圖。比較圖10與圖8可知，本發明之PWM信號產生電路36的第四電路結構更包括：耦接於該第一脈寬調製單元361和該PWM信號產生單元364之間的一第二延遲單元365，該第二延遲單元365為一D型正反器。Figure 9 shows that the PWM signal is reduced to the left. However, in a feasible embodiment, the PWM signal can also be reduced to the right. FIG. 10 shows a fourth circuit block diagram of a PWM signal generating circuit of the present invention. Comparing FIG. 10 with FIG. 8, the fourth circuit structure of the PWM signal generating circuit 36 of the present invention further includes: a second delay unit coupled between the first pulse width modulation unit 361 and the PWM signal generating unit 364 365, the second delay unit 365 is a D-type flip-flop.

圖11顯示第一灰度時鐘信號GCLK＜0＞、第一脈寬調製信號PWMN1、第二脈寬調製信號PWMN2、選定相位灰度時鐘信號GCLKs、脈寬調製信號PWMD 、以及PWM信號的工作時序圖。如圖11和圖10所示，在接收第一顯示資料N＜15:0＞和第一灰度時鐘信號GCLK＜0＞之後，該第一脈寬調製單元361生成第一脈寬調製信號PWMN1。另一方面，在接收第二顯示資料F＜2:0＞和多相位灰度時鐘信號GCLK＜7:0＞之後，該多工器362自所述多相位灰度時鐘信號GCLK＜7:0＞中擇一，從而輸出一選定相位灰度時鐘信號GCLKs。進一步地，在接收該選定相位灰度時鐘信號GCLKs和該第一脈寬調製信號PWMN1之後，該第一延遲單元363在該選定相位灰度時鐘信號GCLKs的控制下對所述第一脈寬調製信號PWMN1進行一信號延遲處理，從而輸出所述脈寬調製信號PWMD 。另一方面，在接收該第一灰度時鐘信號GCLK＜0＞以及傳送自該第一脈寬調製單元361的該第一脈寬調製信號PWMN1之後，該第二延遲單元365在該選定相位灰度時鐘信號GCLKs的控制下對所述第一脈寬調製信號PWMN1進行一信號延遲處理，從而輸出所述第二脈寬調製信號PWMN2。Figure 11 shows the operation of the first gray-scale clock signal GCLK<0>, the first pulse-width modulation signal PWMN1, the second pulse-width modulation signal PWMN2, the selected phase gray-scale clock signal GCLKs, the pulse-width modulation signal PWM D , and the PWM signal Timing diagram. As shown in FIG. 11 and FIG. 10, after receiving the first display data N<15:0> and the first grayscale clock signal GCLK<0>, the first pulse width modulation unit 361 generates the first pulse width modulation signal PWMN1 . On the other hand, after receiving the second display data F<2:0> and the multi-phase gray-scale clock signal GCLK<7:0>, the multiplexer 362 obtains data from the multi-phase gray-scale clock signal GCLK<7:0 >Choose one to output a selected phase gray-scale clock signal GCLKs. Further, after receiving the selected phase grayscale clock signal GCLKs and the first pulse width modulation signal PWMN1, the first delay unit 363 modulates the first pulse width under the control of the selected phase grayscale clock signal GCLKs The signal PWMN1 undergoes a signal delay processing to output the pulse width modulation signal PWM D. On the other hand, after receiving the first gray-scale clock signal GCLK<0> and the first pulse-width modulation signal PWMN1 transmitted from the first pulse-width modulation unit 361, the second delay unit 365 performs a gray-scale operation in the selected phase. A signal delay process is performed on the first pulse width modulation signal PWMN1 under the control of the degree clock signal GCLKs, so as to output the second pulse width modulation signal PWMN2.

圖10顯示該PWM信號產生單元364為一及邏輯閘。因此，如圖10和圖11所示，在接收該脈寬調製信號PWMD 和該第二脈寬調製信號PWMN2之後，該PWM信號產生單元364即對該脈寬調製信號PWMD 與該第二脈寬調製信號PWMN2進行一及邏輯運算，從而產生一PWM信號。值得注意的是，圖11顯示該PWM信號的脈寬已經被向右縮減。如此，該PWM信號被傳送至該定電流源極驅動晶片3內部的顯示灰度比較單元，從而能夠精準地控制LED顯示面板1的每個LED元件11的灰階值至小數點(浮點數)。FIG. 10 shows that the PWM signal generating unit 364 is an AND logic gate. Thus, 10 and 11, after receiving the pulse width modulation signal PWM D and the second pulse width modulated signal PWMN2, the PWM signal generating unit 364 i.e. the pulse width modulated signal and the second PWM D The pulse width modulation signal PWMN2 performs an AND logic operation to generate a PWM signal. It is worth noting that Figure 11 shows that the pulse width of the PWM signal has been reduced to the right. In this way, the PWM signal is transmitted to the display gray scale comparison unit inside the constant current source driver chip 3, so that the gray scale value of each LED element 11 of the LED display panel 1 can be accurately controlled to a decimal point (floating point number). ).

如此，上述已完整且清楚地說明本發明之PWM信號產生電路；並且，經由上述可得知本發明具有下列優點：In this way, the foregoing has completely and clearly described the PWM signal generating circuit of the present invention; and from the foregoing, it can be seen that the present invention has the following advantages:

(1)本發明揭示一種PWM信號產生電路，其以數位電路的形式實現在一定電流源極驅動晶片之中，且能夠在不增加晶片功耗且不對原PWM信號產生功能造成影響的情況下，提供高精度的PWM信號給該定電流源極驅動晶片內部的顯示灰度比較單元，從而能夠精準地控制LED顯示面板的每個LED元件的灰階值至小數點(浮點數)。因此，利用含有本發明之PWM信號產生電路的定電流源極驅動晶片對一LED顯示面板進行顯示驅動，係能夠有效提高該LED顯示面板的顯示精度，同時不會增加額外的硬體及系統端設計成本。(1) The present invention discloses a PWM signal generating circuit, which is implemented in a certain current source drive chip in the form of a digital circuit, and can not increase chip power consumption and affect the original PWM signal generating function. A high-precision PWM signal is provided to the display gray scale comparison unit inside the constant current source driver chip, so that the gray scale value of each LED element of the LED display panel can be accurately controlled to a decimal point (floating point number). Therefore, using the constant current source driver chip containing the PWM signal generating circuit of the present invention to display and drive an LED display panel can effectively improve the display accuracy of the LED display panel without adding additional hardware and system terminals. Design cost.

(2)本發明同時提供一種定電流源極驅動晶片，其具有如前所述之PWM信號產生電路。(2) The present invention also provides a constant current source driver chip, which has the PWM signal generating circuit as described above.

(3)本發明同時提供一種LED顯示裝置，其具有一LED顯示面板及至少一源極驅動晶片，該源極驅動晶片具有如前所述之PWM信號產生電路。(3) The present invention also provides an LED display device, which has an LED display panel and at least one source driver chip, and the source driver chip has the aforementioned PWM signal generating circuit.

必須加以強調的是，前述本案所揭示者乃為較佳實施例，舉凡局部之變更或修飾而源於本案之技術思想而為熟習該項技藝之人所易於推知者，俱不脫本案之專利權範疇。It must be emphasized that the foregoing disclosures in this case are preferred embodiments, and any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by those who are familiar with the art will not deviate from the patent of this case. Right category.

綜上所陳，本案無論目的、手段與功效，皆顯示其迥異於習知技術，且其首先發明合於實用，確實符合發明之專利要件，懇請  貴審查委員明察，並早日賜予專利俾嘉惠社會，是為至禱。In summary, regardless of the purpose, means and effects of this case, it is shown that it is very different from the conventional technology, and its first invention is suitable for practicality, and it does meet the patent requirements of the invention. Please check it out and grant the patent as soon as possible. Society is for the best prayer.

1a:LED顯示面板 11a:LED元件 2a:閘極驅動電路 3a:源極驅動電路 4a:顯示控制器 1:LED顯示面板 11:LED元件 2:閘極驅動電路 3:源極驅動電路 36:PWM信號產生電路 361:第一脈寬調製單元 362:多工器 363:第一延遲單元 364:PWM信號產生單元 365:第二延遲單元 4:顯示控制器1a: LED display panel 11a: LED components 2a: Gate drive circuit 3a: Source drive circuit 4a: display controller 1: LED display panel 11: LED components 2: Gate drive circuit 3: Source drive circuit 36: PWM signal generating circuit 361: The first pulse width modulation unit 362: Multiplexer 363: first delay unit 364: PWM signal generation unit 365: second delay unit 4: display controller

圖1為習知的一種LED顯示裝置的架構圖； 圖2為包含本發明之一定電流源極驅動晶片的一種LED顯示裝置的架構圖； 圖3為本發明之多相位灰度時鐘信號的工作時序圖； 圖4為本發明之一種PWM信號產生電路的第一電路方塊圖； 圖5為本發明之第一灰度時鐘信號、第一脈寬調製信號、選定相位灰度時鐘信號、脈寬調製信號以及PWM信號的工作時序圖； 圖6為本發明之一種PWM信號產生電路的第二電路方塊圖； 圖7為本發明之第一灰度時鐘信號、第一脈寬調製信號、第二脈寬調製信號、選定相位灰度時鐘信號、脈寬調製信號、以及PWM信號的工作時序圖； 圖8為本發明之一種PWM信號產生電路的第三電路方塊圖； 圖9為本發明之第一灰度時鐘信號、第一脈寬調製信號、選定相位灰度時鐘信號、脈寬調製信號以及PWM信號的工作時序圖； 圖10為本發明之一種PWM信號產生電路的第四電路方塊圖；以及 圖11為本發明之第一灰度時鐘信號、第一脈寬調製信號、第二脈寬調製信號、選定相位灰度時鐘信號、脈寬調製信號、以及PWM信號的工作時序圖。Figure 1 is a structural diagram of a conventional LED display device; 2 is a structural diagram of an LED display device including a certain current source driver chip of the present invention; 3 is a working timing diagram of the multi-phase gray-scale clock signal of the present invention; 4 is a first circuit block diagram of a PWM signal generating circuit of the present invention; 5 is a working timing diagram of the first gray-scale clock signal, the first pulse-width modulation signal, the selected phase gray-scale clock signal, the pulse width modulation signal, and the PWM signal of the present invention; Fig. 6 is a second circuit block diagram of a PWM signal generating circuit of the present invention; FIG. 7 is a working sequence diagram of the first grayscale clock signal, the first pulse width modulation signal, the second pulse width modulation signal, the selected phase grayscale clock signal, the pulse width modulation signal, and the PWM signal of the present invention; 8 is a third circuit block diagram of a PWM signal generating circuit of the present invention; 9 is a working timing diagram of the first grayscale clock signal, the first pulse width modulation signal, the selected phase grayscale clock signal, the pulse width modulation signal, and the PWM signal of the present invention; 10 is a fourth circuit block diagram of a PWM signal generating circuit of the present invention; and FIG. 11 is a working timing diagram of the first grayscale clock signal, the first pulse width modulation signal, the second pulse width modulation signal, the selected phase grayscale clock signal, the pulse width modulation signal, and the PWM signal of the present invention.

36:PWM信號產生電路第一脈寬調製單元36: The first pulse width modulation unit of the PWM signal generating circuit

361:第一脈寬調製單元361: The first pulse width modulation unit

362:多工器362: Multiplexer

363:第一延遲單元363: first delay unit

364:PWM信號產生單元364: PWM signal generation unit

Claims (10)

一種PWM信號產生電路，應用於一定電流源極驅動晶片之中，其具有： 一第一脈寬調製單元，耦接一第一顯示資料以及一第一灰度時鐘信號，用以依該第一顯示資料和該第一灰度時鐘信號產生一第一脈寬調製信號； 一多工器，耦接包含該第一灰度時鐘信號的一多相位灰度時鐘信號和一第二顯示資料，用以依該第二顯示資料自所述多相位灰度時鐘信號中擇一，從而輸出一選定相位灰度時鐘信號；其中，該第一顯示資料與該第二顯示資料係分離自一串行顯示資料； 一第一延遲單元，耦接該多工器所傳送的該選定相位時鐘信號以及該第一脈寬調製單元所傳送的該第一脈寬調製信號，且在該選定相位灰度時鐘信號的控制下對所述第一脈寬調製信號進行一信號延遲處理，從而輸出一脈寬調製信號；以及 一PWM信號產生單元，耦接該第一延遲單元所傳送的該脈寬調製信號以及該第一脈寬調製單元所傳送的該第一脈寬調製信號，從而依據所述第一脈寬調製信號和所述脈寬調製信號產生一PWM信號，且將該PWM信號傳送至所述定電流源極驅動晶片內部的一顯示灰度比較單元。A PWM signal generating circuit applied to a certain current source driver chip, which has: A first pulse width modulation unit, coupled to a first display data and a first gray-scale clock signal, for generating a first pulse-width modulation signal according to the first display data and the first gray-scale clock signal; A multiplexer, coupled to a multi-phase gray clock signal containing the first gray clock signal and a second display data, for selecting one of the multi-phase gray clock signals according to the second display data , Thereby outputting a selected phase grayscale clock signal; wherein the first display data and the second display data are separated from a serial display data; A first delay unit, coupled to the selected phase clock signal transmitted by the multiplexer and the first pulse width modulation signal transmitted by the first pulse width modulation unit, and in the control of the selected phase gray clock signal Performing a signal delay processing on the first pulse width modulation signal to output a pulse width modulation signal; and A PWM signal generating unit coupled to the pulse width modulation signal transmitted by the first delay unit and the first pulse width modulation signal transmitted by the first pulse width modulation unit, so as to be based on the first pulse width modulation signal A PWM signal is generated with the pulse width modulation signal, and the PWM signal is transmitted to a display gray scale comparison unit inside the constant current source driving chip. 如請求項1所述之PWM信號產生電路，其中，該PWM信號產生單元為選自於由或邏輯閘與及邏輯閘所組成群組之一種邏輯單元。The PWM signal generating circuit of claim 1, wherein the PWM signal generating unit is a logic unit selected from the group consisting of an OR logic gate and a logic gate. 如請求項2所述之PWM信號產生電路，更包括耦接於該第一脈寬調製單元和該PWM信號產生單元之間的一第二延遲單元，其耦接所述第一灰度時鐘信號以及傳送自該第一脈寬調製單元的該第一脈寬調製信號，從而在該第一灰度時鐘信號的控制下對所述第一脈寬調製信號進行所述信號延遲處理，進以輸出一第二脈寬調製信號傳送至該PWM信號產生單元，使該PWM信號產生單元依所述第二脈寬調製信號和所述脈寬調製信號產生所述PWM信號。The PWM signal generating circuit according to claim 2, further comprising a second delay unit coupled between the first pulse width modulation unit and the PWM signal generating unit, which is coupled to the first gray-scale clock signal And the first pulse width modulation signal transmitted from the first pulse width modulation unit, so that the signal delay processing is performed on the first pulse width modulation signal under the control of the first gray-scale clock signal to output A second pulse width modulation signal is transmitted to the PWM signal generating unit, so that the PWM signal generating unit generates the PWM signal according to the second pulse width modulation signal and the pulse width modulation signal. 如請求項3所述之PWM信號產生電路，其中，該第二延遲單元與該第一延遲單元皆為一D型正反器。The PWM signal generating circuit according to claim 3, wherein the second delay unit and the first delay unit are both a D-type flip-flop. 如請求項1所述之PWM信號產生電路，其中，該第一顯示資料和該第二顯示資料係傳送自一顯示控制器，且該第一顯示資料為所述串行顯示資料的整數部分，該第二顯示資料則為所述串行顯示資料的小數部分。The PWM signal generating circuit of claim 1, wherein the first display data and the second display data are transmitted from a display controller, and the first display data is an integer part of the serial display data, The second display data is the decimal part of the serial display data. 如請求項1所述之PWM信號產生電路，其中，一顯示控制器將所述第一顯示資料和一小數指示信號傳送至該定電流源極驅動晶片，且該第二顯示資料依據所述小數指示信號而產生。The PWM signal generation circuit of claim 1, wherein a display controller transmits the first display data and a decimal indication signal to the constant current source driver chip, and the second display data is based on the decimal The indicator signal is generated. 如請求項1所述之PWM信號產生電路，其中，一顯示控制器傳送所述串行顯示資料至該定電流源極驅動晶片，且該定電流源極驅動晶片內部的一控制單元將所述串行顯示資料分割為該第一顯示資料和該第二顯示資料。The PWM signal generating circuit of claim 1, wherein a display controller transmits the serial display data to the constant current source driver chip, and a control unit inside the constant current source driver chip controls the The serial display data is divided into the first display data and the second display data. 如請求項1所述之PWM信號產生電路，更包括一多相位時鐘信號產生單元，用以產生所述多相位灰度時鐘信號。The PWM signal generating circuit as described in claim 1 further includes a multi-phase clock signal generating unit for generating the multi-phase gray clock signal. 一種源極驅動晶片，其具有如申請專利範圍第1至8項中任一項所述之PWM信號產生電路。A source driver chip having the PWM signal generating circuit as described in any one of items 1 to 8 in the scope of patent application. 一種LED顯示裝置，其具有一LED顯示面板及至少一源極驅動晶片，該源極驅動晶片具有如申請專利範圍第1至8項中任一項所述之PWM信號產生電路。An LED display device has an LED display panel and at least one source driver chip. The source driver chip has a PWM signal generating circuit as described in any one of the first to eighth patent applications.
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