TW202044343A

TW202044343A - Semiconductor device and manufacturing method thereof

Info

Publication number: TW202044343A
Application number: TW108117208A
Authority: TW
Inventors: 蘇嬿如
Original assignee: 旺宏電子股份有限公司
Priority date: 2019-05-17
Filing date: 2019-05-17
Publication date: 2020-12-01

Abstract

The present application discloses a semiconductor device and a method for manufacturing the same, comprising the steps of providing a substrate, depositing semiconducting layers and isolation layers alternatively to form a stack on the substrate, patterning the stack to form a staircase top surface, forming a first dielectric layer on the staircase top surface, removing a part of the first dielectric layer to expose a part of the staircase top surface, forming a second dielectric layer to cover another part of the first dielectric layer and the part of the staircase top surface, and etching the second dielectric layer and the another part of the first dielectric layer, wherein a first etching rate of the another part of the first dielectric layer is higher than a second etching rate of the second dielectric layer.

Description

半導體元件及其製造方法Semiconductor element and its manufacturing method

本發明係關於一種半導體元件及其製造方法，尤其是一種於具有階梯狀頂面結構的半導體裝置。The present invention relates to a semiconductor element and a manufacturing method thereof, in particular to a semiconductor device with a stepped top surface structure.

非揮發性記憶體元件在設計上有一個很大的特性是，當記憶體元件失去或移除電源後仍能保存資料狀態的完整性。目前業界已有許多不同型態的非揮發性記憶體元件被提出。不過相關業者仍不斷研發新的設計或是結合現有技術，進行含記憶胞之記憶體平面的堆疊以達到具有更高儲存容量的記憶體結構。例如已有一些多層薄膜電晶體堆疊之反及閘（NAND）型快閃記憶體結構被提出。相關業者已經提出各種不同結構的三維記憶體元件，例如具單閘極（Single-Gate）之記憶胞、雙閘極（double gate）之記憶胞，和環繞式閘極（surrounding gate）之記憶胞等三維半導體元件。A major feature of non-volatile memory devices in design is that they can retain the integrity of the data state when the memory device loses or removes power. At present, many different types of non-volatile memory devices have been proposed in the industry. However, related industries are still constantly developing new designs or combining existing technologies to stack memory planes containing memory cells to achieve a memory structure with higher storage capacity. For example, some NAND flash memory structures in which multilayer thin film transistors are stacked have been proposed. Relevant industries have proposed various three-dimensional memory devices with different structures, such as single-gate memory cells, double gate memory cells, and surrounding gate memory cells. And other three-dimensional semiconductor components.

相關設計者無不期望可以建構出一三維半導體結構，不僅具有許多層堆疊平面（記憶體層）而達到更高的儲存容量，更具有優異的電子特性（例如具有良好的資料保存可靠性和操作速度），使記憶體可以被穩定和快速的如進行抹除和編程等操作。再者，進一步縮小三維半導體元件尺寸時，雖然有可能從線路的線寬/線距的製程條件上改進使之縮小，接觸孔與後續走線因接觸孔面積減少，而導致留下更少的空間給後續走線降落，這對於製程條件和結構設計都會造成問題。Relevant designers all expect to be able to construct a three-dimensional semiconductor structure, which not only has many layers of stacked planes (memory layers) to achieve higher storage capacity, but also has excellent electronic properties (such as good data retention reliability and operating speed) ), so that the memory can be stably and quickly operated such as erasing and programming. Furthermore, when the size of the three-dimensional semiconductor device is further reduced, although it is possible to reduce the process conditions of the line width/line spacing of the circuit, the contact hole and subsequent traces are reduced due to the reduction of the contact hole area, resulting in less Space for subsequent wiring landing, which will cause problems for process conditions and structural design.

因此，極需要提供一種半導體元件及其製造方法，來解決習知技術所面臨的問題。Therefore, it is extremely necessary to provide a semiconductor device and a manufacturing method thereof to solve the problems faced by the prior art.

本發明之一面向係提供一基板；沉積複數半導體層及複數絕緣層相互交錯形成一堆疊於該基板上；圖形化該堆疊形成一階梯狀頂面；形成一第一介電層於該階梯狀頂面上；去除一部分的該第一介電層，使一部分的該階梯狀頂面露出；形成一第二介電層，覆蓋一另一部分的該第一介電層以及一另一部分的該階梯狀頂面；以及以一蝕刻媒介物蝕刻該第二介電層以及該另一部分的該第一介電層，其中該另一部分的第一介電層對該蝕刻媒介物具有一第一蝕刻速率、該第二介電層對該蝕刻媒介物具有一第二蝕刻速率，且該第一蝕刻速率比該第二蝕刻速率為高。One aspect of the present invention is to provide a substrate; deposit a plurality of semiconductor layers and a plurality of insulating layers interlaced to form a stack on the substrate; pattern the stack to form a stepped top surface; form a first dielectric layer on the stepped On the top surface; remove a part of the first dielectric layer to expose a part of the stepped top surface; form a second dielectric layer covering another part of the first dielectric layer and another part of the step And etch the second dielectric layer and the other part of the first dielectric layer with an etching medium, wherein the other part of the first dielectric layer has a first etching rate for the etching medium , The second dielectric layer has a second etching rate for the etching medium, and the first etching rate is higher than the second etching rate.

本發明之另一面向係提出一種半導體元件，包括：一堆疊，該堆疊包括相互堆疊的複數半導體層及複數絕緣層，且該堆疊具有一階梯狀頂面；一第一介電層，覆蓋該階梯狀頂面的一部分；以及一第二介電層，覆蓋該第一介電層及該階梯狀頂面的另一部分，其中該第一介電層的蝕刻速率大於該第二介電層的蝕刻速率。Another aspect of the present invention is to provide a semiconductor device, including: a stack including a plurality of semiconductor layers and a plurality of insulating layers stacked on each other, and the stack has a stepped top surface; a first dielectric layer covering the A portion of the stepped top surface; and a second dielectric layer covering the first dielectric layer and another portion of the stepped top surface, wherein the etching rate of the first dielectric layer is greater than that of the second dielectric layer Etching rate.

本發明之實施例的詳細描述如下，然而，除了該詳細描述外，本發明還可以廣泛地在其他的實施例施行。亦即，本發明的範圍不受已提出之實施例的限制，而應以本發明提出之申請專利範圍為準。The detailed description of the embodiments of the present invention is as follows. However, in addition to the detailed description, the present invention can also be widely implemented in other embodiments. That is, the scope of the present invention is not limited by the proposed embodiments, but should be subject to the scope of the patent application filed by the present invention.

第1圖為本發明之對比實施例的半導體元件的截面圖。該堆疊111具有一陣列區（未顯示於圖中）與一周邊區120。陣列區為一三維記憶體結構，其訊號藉由周邊區120的階梯區域100，以利訊號藉由周邊區120傳送到陣列區，本案圖示僅畫出周邊區120中位於階梯區域100的部分。階梯區域100包括基板10，基板10具有一堆疊111，該堆疊111包括複數個次堆疊112，該複數個次堆疊112的每一個包括半導體層11及絕緣層12。於一實施例中，於階梯狀頂面17上可優選地形成一蝕刻終止層13（例如氮化矽層），使接觸孔19都能一致地停在蝕刻終止層13上。之後，再同步蝕刻以穿過蝕刻終止層13以及最靠近階梯狀頂面17的絕緣層12。然而，當蝕刻終止層13沉積形成時，蝕刻終止層13在階梯狀頂面17的垂直面上的轉角寬度y1與水平面上所沉積的厚度T接近，兩者厚度幾乎相當於成正比。但是，蝕刻終止層13的轉角寬度y1會佔據接觸降落窗口（contact landing windows）的可用面積（其寬度於第1圖上所示最大為寬度W減去轉角寬度y1），若在發展三維半導體元件時需要形成更高的堆疊數量，以增加記憶體容量。因此接觸孔19將面臨較長的蝕刻時間，因此需要形成更厚的蝕刻終止層13，然蝕刻終止層13的厚度T增加，同時轉角寬度y1也會增加，因此接觸降落窗口的可用面積將下降。Figure 1 is a cross-sectional view of a semiconductor device of a comparative example of the present invention. The stack 111 has an array area (not shown in the figure) and a peripheral area 120. The array area is a three-dimensional memory structure. The signal passes through the step area 100 of the peripheral area 120, and the signal is transmitted to the array area through the peripheral area 120. In this case, only the part of the peripheral area 120 located in the step area 100 is drawn. . The step area 100 includes a substrate 10, and the substrate 10 has a stack 111 including a plurality of sub-stacks 112, and each of the plurality of sub-stacks 112 includes a semiconductor layer 11 and an insulating layer 12. In one embodiment, an etch stop layer 13 (such as a silicon nitride layer) may be preferably formed on the stepped top surface 17 so that the contact holes 19 can be uniformly stopped on the etch stop layer 13. After that, it is etched simultaneously to pass through the etching stop layer 13 and the insulating layer 12 closest to the stepped top surface 17. However, when the etching stop layer 13 is deposited and formed, the corner width y1 of the etching stop layer 13 on the vertical surface of the stepped top surface 17 is close to the thickness T deposited on the horizontal surface, and the thicknesses of the two are almost proportional to each other. However, the corner width y1 of the etch stop layer 13 will occupy the available area of contact landing windows (the width shown in Figure 1 is the maximum width W minus the corner width y1). If three-dimensional semiconductor devices are being developed It is necessary to form a higher number of stacks to increase the memory capacity. Therefore, the contact hole 19 will face a longer etching time, so it is necessary to form a thicker etch stop layer 13. However, the thickness T of the etch stop layer 13 increases, and the corner width y1 will also increase, so the usable area of the contact drop window will decrease .

本發明之實施例係提出一種三維半導體元件及其製造方法。根據實施例，藉由在三維半導體元件中於階梯狀頂面上形成兩層介電層的方式來降低蝕刻終止層的厚度，以大幅增加接觸降落窗口（contact landing windows），無論三維半導體元件之OP層堆疊的層數有多少或是三維半導體元件尺寸是否縮小，都適合應用本案之實施例。因此，根據實施例提出之具有兩層介電層來取代僅使用一層介電層之設計，可以提供所應用之三維半導體元件有足夠寬的接觸降落窗口，進而增進應用元件的電子特性和性能表現。The embodiment of the present invention provides a three-dimensional semiconductor device and a manufacturing method thereof. According to the embodiment, the thickness of the etching stop layer is reduced by forming two dielectric layers on the stepped top surface of the three-dimensional semiconductor device, so as to greatly increase the contact landing windows, regardless of whether the three-dimensional semiconductor device is The number of OP layer stacks or whether the size of the three-dimensional semiconductor device is reduced is suitable for applying the embodiment of this case. Therefore, the design with two dielectric layers proposed according to the embodiment instead of using only one dielectric layer can provide a wide enough contact drop window for the applied three-dimensional semiconductor device, thereby enhancing the electronic characteristics and performance of the applied device .

本發明可應用於許多具不同記憶胞陣列型態的三維半導體元件，例如垂直通道式（vertical-channel，VC）三維半導體元件和垂直閘極式（vertical-gate，VG）三維半導體元件，本揭露對於實施例之應用型態並沒有特別限制。The present invention can be applied to many three-dimensional semiconductor devices with different memory cell array types, such as vertical-channel (VC) three-dimensional semiconductor devices and vertical-gate (VG) three-dimensional semiconductor devices. This disclosure There are no particular restrictions on the application types of the embodiments.

以垂直通道式三維半導體元件為例來作說明。第2~9圖為根據本發明的一種實施例的半導體元件的製造方法於多個步驟中的的截面圖。為了簡化圖示，於第2~9圖中所示的本發明一實施例的半導體元件中，僅繪示周邊區220。Take the vertical channel type three-dimensional semiconductor device as an example for illustration. FIGS. 2-9 are cross-sectional views of a semiconductor device manufacturing method in multiple steps according to an embodiment of the present invention. In order to simplify the illustration, in the semiconductor device of an embodiment of the present invention shown in FIGS. 2-9, only the peripheral region 220 is shown.

如第9圖所示，根據本發明一實施例的一種三維半導體元件包括具有疊置於一基板20上的一多層結構（multi-layers），基板20包括一陣列區域（array area）（圖中未顯示，亦即記憶體區域，可包括控制閘極）和鄰近陣列區域之一階梯區域200（staircase area，亦即接觸區域），其中階梯區域200包括形成次堆疊的N個梯級（N steps），N為大於或等於1的整數。具有多層結構的一堆疊包括N個交錯設置的半導體層21（亦即主動層）與絕緣層22。三維半導體元件更包括複數條上方選擇線（upper selection lines）（圖中未顯示），上方選擇線可為共同源極線（Common Source Line）相互平行地位於半導體層21（亦即位於記憶體層）上方，複數條串列（strings）（圖中未顯示）垂直於半導體層21和上方選擇線，其中該等複數條串列係電性連接至對應之上方選擇線。再者，三維半導體元件更包括複數條導線（圖中未顯示，例如位元線）位於上方選擇線上方，且該些導線係相互平行並垂直於上方選擇線。複數個記憶胞係分別由複數條串列、上方選擇線和導線定義，且記憶胞可排列為複數列（rows）及複數行（columns）以形成記憶體陣列。再者，複數個串列接觸（string contacts）（圖中未顯示）係垂直於半導體層和上方選擇線，且每串列接觸之設置係對應於記憶胞之每串列，其中串列接觸（圖中未顯示）係電性連接至對應的上方選擇線和對應的導線。三維半導體元件還可以包括其他元件，例如記憶體層下方還可以形成下方選擇線（lower select lines）（圖中未顯示），該下方選擇線可為反轉閘極（inversion gate）。As shown in FIG. 9, a three-dimensional semiconductor device according to an embodiment of the present invention includes a multi-layer structure (multi-layers) stacked on a substrate 20, and the substrate 20 includes an array area (FIG. Not shown in, that is, the memory area, which may include a control gate) and a staircase area 200 (that is, a contact area) adjacent to the array area, where the staircase area 200 includes N steps (N steps) forming a sub-stack. ), N is an integer greater than or equal to 1. A stack with a multi-layer structure includes N interleaved semiconductor layers 21 (that is, active layers) and insulating layers 22. The three-dimensional semiconductor device further includes a plurality of upper selection lines (not shown in the figure). The upper selection lines can be Common Source Lines and are located on the semiconductor layer 21 (that is, on the memory layer) parallel to each other. Above, a plurality of strings (not shown in the figure) are perpendicular to the semiconductor layer 21 and the upper selection line, wherein the plurality of strings are electrically connected to the corresponding upper selection line. Furthermore, the three-dimensional semiconductor device further includes a plurality of wires (not shown in the figure, such as bit lines) located above the upper selection line, and these wires are parallel to each other and perpendicular to the upper selection line. A plurality of memory cell systems are respectively defined by a plurality of series, upper selection lines and wires, and the memory cells can be arranged into a plurality of rows and columns to form a memory array. Furthermore, a plurality of string contacts (not shown in the figure) are perpendicular to the semiconductor layer and the upper selection line, and the arrangement of each string contact corresponds to each string of the memory cell, where the string contacts ( (Not shown in the figure) is electrically connected to the corresponding upper selection line and the corresponding wire. The three-dimensional semiconductor device may also include other devices. For example, lower select lines (not shown in the figure) may be formed under the memory layer, and the lower select lines may be inversion gates.

本發明的一實施例之堆疊包括複數個次堆疊形成於基板20上，且階梯區域200中該些複數個次堆疊具有N個梯級以分別形成接觸區域（contact regions）。實施例之三維半導體元件更包括複數個多層結構連接器（multilayered connectors）（未顯示於圖中），分別設置於對應的接觸區域。根據實施例，接觸區域中各個次堆疊的一最上層半導體層（an uppermost active layer）上由一絕緣層（例如氮化物層）覆蓋蓋接觸區域中的接觸降落區域（ex: 一接觸墊，例如字元線接觸（word line pad）），且多層結構連接器係向下延伸以電性連接（例如直接接觸）各次堆疊之半導體層。於一實施例中，階梯區域200中對應接觸區域之次堆疊的半導體層係來自於陣列區域半導體層（例如是作為字元線的多晶矽層）的延伸。以下係以在階梯區域200中形成氮化物作為絕緣層之三維半導體元件之其中之一種態樣為例，作為一種實施例之三維半導體元件的說明，但本發明的揭露內容不限於此。The stack of an embodiment of the present invention includes a plurality of sub-stacks formed on the substrate 20, and the plurality of sub-stacks in the step region 200 have N steps to respectively form contact regions. The three-dimensional semiconductor device of the embodiment further includes a plurality of multilayered connectors (not shown in the figure), which are respectively arranged in the corresponding contact areas. According to an embodiment, an uppermost active layer (an uppermost active layer) of each sub-stack in the contact area is covered by an insulating layer (such as a nitride layer) in the contact landing area (ex: a contact pad, such as A word line pad is used, and the multi-layer structure connector extends downward to electrically connect (for example, directly contact) the stacked semiconductor layers. In one embodiment, the second stacked semiconductor layer corresponding to the contact area in the step area 200 is derived from the extension of the semiconductor layer in the array area (for example, a polysilicon layer as a word line). The following is an example of a three-dimensional semiconductor device in which nitride is formed as an insulating layer in the step region 200 as an example of a three-dimensional semiconductor device, but the disclosure of the present invention is not limited to this.

本發明以第2~9圖所示的截面圖以及第10圖的流程圖作為輔助說明。本發明的一種實施例的一種半導體元件，如第9圖所示，其具有陣列區（未顯示於圖中）與周邊區220，該半導體元件的該周邊區220中的階梯區域200包括：堆疊211，該堆疊211由複數個次堆疊212相互堆疊而成，該複數個次堆疊212的每一個包括半導體層21及絕緣層22，且該堆疊211具有階梯狀頂面27；第一介電層24，覆蓋該階梯狀頂面27的一部分；以及第二介電層25，覆蓋該第一介電層24及該階梯狀頂面27的另一部分。The present invention uses the cross-sectional views shown in Figs. 2-9 and the flowchart in Fig. 10 as an auxiliary description. A semiconductor device according to an embodiment of the present invention, as shown in FIG. 9, has an array area (not shown in the figure) and a peripheral area 220, and the step area 200 in the peripheral area 220 of the semiconductor device includes: stack 211, the stack 211 is formed by stacking a plurality of sub-stacks 212, each of the plurality of sub-stacks 212 includes a semiconductor layer 21 and an insulating layer 22, and the stack 211 has a stepped top surface 27; a first dielectric layer 24, covering a part of the stepped top surface 27; and a second dielectric layer 25 covering the first dielectric layer 24 and another part of the stepped top surface 27.

次堆疊212的層數可依實際需要而設計。為了示例，第2圖中的複數次堆疊212計有8層，亦即具有8個梯級，但本發明不限於此。且可以預期的是，當梯級數目愈多，愈能呈現本發明的成效。The number of layers of the sub-stack 212 can be designed according to actual needs. For the sake of example, the multiple times stack 212 in Figure 2 has 8 layers, that is, 8 steps, but the invention is not limited to this. It can be expected that the greater the number of steps, the more effective the present invention can be presented.

該蝕刻終止層為氮化物層，其可為氮化矽、該半導體層為多晶矽層、而該絕緣層為氧化物層，其可為氧化矽層。The etching stop layer is a nitride layer, which can be silicon nitride, the semiconductor layer is a polysilicon layer, and the insulating layer is an oxide layer, which can be a silicon oxide layer.

再參照第2圖，其中該第一介電層24及該第二介電層25對一蝕刻媒介物具有蝕刻選擇性，該第一介電層24對該蝕刻媒介物具有一第一蝕刻速率、該第二介電層25對該蝕刻媒介物具有一第二蝕刻速率，且該第一蝕刻速率比該第二蝕刻速率為高。根據本發明的一較佳實施例，該第一蝕刻速率比該第二蝕刻速率至少高5埃/秒。然而，依照次堆疊212的層數，該第一蝕刻速率比該第二蝕刻速率的差異可隨著蝕刻條件的最適化而改變。Referring again to FIG. 2, the first dielectric layer 24 and the second dielectric layer 25 have etching selectivity to an etching medium, and the first dielectric layer 24 has a first etching rate for the etching medium The second dielectric layer 25 has a second etching rate for the etching medium, and the first etching rate is higher than the second etching rate. According to a preferred embodiment of the present invention, the first etching rate is at least 5 angstroms/sec higher than the second etching rate. However, according to the number of layers of the sub-stack 212, the difference between the first etch rate and the second etch rate can be changed as the etching conditions are optimized.

該第一介電層24及該第二介電層25的材料為無機含氧矽化物，其材料可獨立地選自不同方式製成的二氧化矽，例如以低溫氧化法製成的二氧化矽（LTO OX）、以TEOS（四乙基正矽酸鹽）製成的二氧化矽（TEOS OX）、高品質氧化法二氧化矽（HQ OX）、高溫熱氧化法二氧化矽（HTO OX）、熱氧化法二氧化矽（thermal OX）、或是不同組成的氧化矽，例如SiO₂ 、SiON、SiC、SiC(OH)或SiOF。然而，該第一介電層24及該第二介電層25的材料的搭配仍需符合前段所述之內容，除了兩者所選擇的材料為不同，對於所使用的蝕刻媒介物，該第一蝕刻速率必須比該第二蝕刻速率為高，搭配蝕刻製程所使用的製程氣體，可知無機含氧矽化物的相對蝕刻速率由快至慢例如為LTO OX ＞ TEOS OX ＞ HQ OX ＞ HTO OX ＞ thermal OX，因而例如可以使用TEOS OX作為第一介電層的材料，來搭配蝕刻速率較慢的Thermal OX作為第二介電層的材料、或是使用LTO OX作為第一介電層的材料，來搭配蝕刻速率較慢的Thermal OX作為第二介電層的材料。由於這些無機含氧矽化物的沉積溫度條件不同，其鍵結方式不同而有不同的緻密性，可以利用這些無機含氧矽化物所具有不同的緻密性，對於蝕刻媒介物來產生不同的蝕刻速率（蝕刻選擇性）。藉由蝕刻選擇性不同的搭配，便能縮減對於階梯區域200中位於不同深度的階梯狀頂面27的蝕刻時間差，因此便可將蝕刻終止層23的厚度減小，致使在階梯區域200的次堆疊的側壁上所沉積的厚度也隨之可以減小，使階梯狀頂面27的可用面積加大，藉此可以使接觸降落窗口的面積增加。The materials of the first dielectric layer 24 and the second dielectric layer 25 are inorganic oxygen-containing silicides, and the materials can be independently selected from silicon dioxide made in different ways, such as silicon dioxide made by low-temperature oxidation. Silicon (LTO OX), silicon dioxide (TEOS OX) made of TEOS (tetraethyl orthosilicate), high-quality oxidation silicon dioxide (HQ OX), high-temperature thermal oxidation silicon dioxide (HTO OX), thermal oxidized silicon dioxide (thermal OX), or silicon oxide of different compositions, such as SiO ₂ , SiON, SiC, SiC (OH) or SiOF. However, the combination of the materials of the first dielectric layer 24 and the second dielectric layer 25 still needs to comply with the content described in the preceding paragraph, except that the materials selected for the two are different. For the etching medium used, the second The first etching rate must be higher than the second etching rate. With the process gas used in the etching process, it can be seen that the relative etching rate of inorganic oxygen-containing silicides ranges from fast to slow. For example, LTO OX> TEOS OX> HQ OX> HTO OX> thermal OX, for example, TEOS OX can be used as the material of the first dielectric layer, Thermal OX with a slower etching rate can be used as the material of the second dielectric layer, or LTO OX can be used as the material of the first dielectric layer. To match Thermal OX with a slower etching rate as the material of the second dielectric layer. Because these inorganic oxygen-containing silicides have different deposition temperature conditions and their bonding methods are different, they have different densities. The different densities of these inorganic oxygen-containing silicides can be used to produce different etching rates for etching media. (Etch selectivity). With the combination of different etching selectivity, the etching time difference for the stepped top surface 27 at different depths in the stepped region 200 can be reduced, so that the thickness of the etching stop layer 23 can be reduced, resulting in the second step in the stepped region 200. The thickness deposited on the side walls of the stack can also be reduced accordingly, so that the usable area of the stepped top surface 27 can be increased, thereby increasing the area of the contact drop window.

第10圖為根據本發明的一種實施例的半導體元件的製造方法的流程圖。如第10圖所示，本發明的半導體元件的製造方法，包括以下的步驟：步驟S101：提供基板20；步驟S102：交錯沉積複數半導體層21及複數絕緣層22形成堆疊211於該基板20上；步驟S103：圖形化該堆疊211形成階梯狀頂面27；步驟S104：形成蝕刻終止層23，以覆蓋該階梯狀頂面27，形成如第2圖所示的結構，此步驟可依需要選擇是否省略；步驟S105：形成第一介電層24於該階梯狀頂面27上，形成如第3圖所示的結構；步驟S106：去除一部分該第一介電層24，使一部分該階梯狀頂面27上的蝕刻終止層23露出，也就是說可以去除一部分該第一介電層24，使最高一層的蝕刻終止層23的表面露出、或是例如像第5圖所示，使從上往下數第3層的蝕刻終止層23的表面露出，但不限於此；步驟S107：形成第二介電層25，其覆蓋另一部分該第一介電層24以及另一部分該階梯狀頂面23上的該部分該蝕刻終止層，形成如第6圖所示的結構；步驟S108：利用遮罩，蝕刻該第二介電層25以及該另一部分的該第一介電層24，形成如第8圖所示的結構；步驟S109：選擇性蝕刻該蝕刻終止層23以及最靠近該階梯狀頂面27的該絕緣層22，以形成接觸孔29；步驟S110：沉積金屬層於該第二介電層25上及該接觸孔29內；以及步驟S111：圖形化該金屬層以形成導電結構30，如第9圖所示的結構。其中該第一介電層24對該蝕刻媒介物具有第一蝕刻速率、該第二介電層25對該蝕刻媒介物具有第二蝕刻速率，且該第一蝕刻速率比該第二蝕刻速率為高。較佳地，該第一蝕刻速率比該第二蝕刻速率至少高5埃/秒。FIG. 10 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention. As shown in FIG. 10, the method of manufacturing a semiconductor device of the present invention includes the following steps: Step S101: Provide a substrate 20; Step S102: Staggerly deposit a plurality of semiconductor layers 21 and a plurality of insulating layers 22 to form a stack 211 on the substrate 20 Step S103: Pattern the stack 211 to form a stepped top surface 27; Step S104: Form an etching stop layer 23 to cover the stepped top surface 27 to form a structure as shown in Figure 2. This step can be selected as needed Whether it is omitted; Step S105: Form a first dielectric layer 24 on the stepped top surface 27 to form the structure shown in Figure 3; Step S106: Remove a part of the first dielectric layer 24 to make a part of the stepped The etching stop layer 23 on the top surface 27 is exposed, that is to say, a part of the first dielectric layer 24 can be removed to expose the surface of the highest etching stop layer 23, or, for example, as shown in FIG. The surface of the etching stop layer 23 of the third layer from the bottom is exposed, but not limited to this; Step S107: forming a second dielectric layer 25, which covers another part of the first dielectric layer 24 and another part of the stepped top surface The part of the etching stop layer on the part 23 is formed as shown in Fig. 6; Step S108: using a mask, the second dielectric layer 25 and the other part of the first dielectric layer 24 are etched to form The structure shown in Figure 8; Step S109: selectively etch the etch stop layer 23 and the insulating layer 22 closest to the stepped top surface 27 to form a contact hole 29; Step S110: deposit a metal layer on the second On the dielectric layer 25 and in the contact hole 29; and step S111: pattern the metal layer to form a conductive structure 30, as shown in FIG. 9. The first dielectric layer 24 has a first etching rate for the etching medium, the second dielectric layer 25 has a second etching rate for the etching medium, and the first etching rate is higher than the second etching rate high. Preferably, the first etching rate is at least 5 angstroms/sec higher than the second etching rate.

本發明的半導體元件的製造方法，如果在形成第一介電層及/或第二介電層時，會因底下的階梯表面的起伏而形成起伏的表面形狀時（如第4及7圖所示）或有必要時，可以在步驟S105之前，還可以包括下列步驟：平整化該第一介電層24，使其表面平坦，成為如第4圖所示的結構；及/或在步驟S107之前，平整化該第二介電層25，使其表面平坦，成為如第7圖所示的結構。平整化的步驟可以使用化學機械研磨（CMP）或是設置遮罩（例如黃光製程）後對於局部凸起部位加以去除。In the manufacturing method of the semiconductor device of the present invention, if the first dielectric layer and/or the second dielectric layer are formed, the undulating surface shape will be formed due to the undulation of the bottom step surface (as shown in Figures 4 and 7). If necessary, before step S105, the following steps may be included: planarizing the first dielectric layer 24 to make its surface flat to form the structure shown in FIG. 4; and/or in step S107 Previously, the second dielectric layer 25 was flattened to make its surface flat and become the structure shown in FIG. 7. The leveling step can use chemical mechanical polishing (CMP) or set a mask (for example, yellow light process) to remove the local protrusions.

本發明的半導體元件的製造方法，在步驟S108中可以包括下列步驟：（a）於該第二介電層的表面製備作為蝕刻該第二介電層以及該絕緣層下之該第一介電層的遮罩（圖中未顯示），使準備要形成接觸孔29的位置露出。此步驟也可以安排在前述平整化該第二介電層25的步驟之後進行。該遮罩的製備可以藉由黃光製程將圖形化的光阻施加於第二介電層的表面上；在步驟S109中還可以包括下列步驟：（b）利用該遮罩，通入的適當製程氣體，進一步非等向性蝕刻該蝕刻終止層以及該絕緣層下之各該梯級表面之最上層的絕緣層，以完整形成接觸孔29。該蝕刻步驟可以在相同或不同的製程設備中，切換所通入的適合製程氣體來進行；以及（c）在後續沉積金屬層以形成線路之前，移除該遮罩（例如，將光阻去除）；在步驟S110中包括下列步驟：（d）沉積金屬層於該第二介電層上及該接觸孔內；以及在步驟S111中包括下列步驟（e）圖形化沉積於該第二介電層上的該金屬層，使該半導體層與該金屬層電性導通，並形成該半導體元件所需要的導電結構30。在本發明的一實施例中，該金屬層可以包括鈷（Co）、鎳（Ni）、鈦（Ti）或其他適合之金屬材料。The manufacturing method of the semiconductor device of the present invention may include the following steps in step S108: (a) Preparation on the surface of the second dielectric layer for etching the second dielectric layer and the first dielectric layer under the insulating layer The layer mask (not shown in the figure) exposes the position where the contact hole 29 is to be formed. This step can also be arranged after the aforementioned step of planarizing the second dielectric layer 25. The mask can be prepared by applying a patterned photoresist on the surface of the second dielectric layer by a yellow light process; step S109 can also include the following steps: (b) using the mask to pass appropriate The process gas further anisotropically etches the etching stop layer and the uppermost insulating layer of each step surface under the insulating layer to form the contact hole 29 completely. The etching step can be performed in the same or different process equipment, by switching the appropriate process gas introduced; and (c) removing the mask (for example, removing the photoresist) before the subsequent deposition of the metal layer to form the circuit ); In step S110, the following steps are included: (d) depositing a metal layer on the second dielectric layer and in the contact hole; and in step S111, including the following step (e) patterned deposition on the second dielectric The metal layer on the layer makes the semiconductor layer and the metal layer electrically conductive, and forms the conductive structure 30 required by the semiconductor element. In an embodiment of the present invention, the metal layer may include cobalt (Co), nickel (Ni), titanium (Ti) or other suitable metal materials.

關於後續製造半導體的製程及相關內容，雖然屬於本領域具有相同知識者所知，在此並未詳述，但仍涵蓋於本發明的範疇中。Regarding the subsequent manufacturing process and related content of semiconductors, although they belong to those with the same knowledge in the art, they are not described in detail here, but they are still covered by the scope of the present invention.

根據本發明的一實施例，藉由比較使用兩種不同的第一介電層24及第二介電層25的厚度組合以及只使用一種介電層的蝕刻時間，來驗證本發明具有改善效果，說明如下。According to an embodiment of the present invention, by comparing two different thickness combinations of the first dielectric layer 24 and the second dielectric layer 25 and the etching time of using only one dielectric layer, it is verified that the present invention has the improvement effect ,described as follows.

第一種實施例The first embodiment

以下實施例中，以第一介電層的第一蝕刻速率為100埃/秒、第二介電層的第二蝕刻速率為50埃/秒的蝕刻條件來進行模擬，此條件符合本發明的第一蝕刻速率大於第二蝕刻速率的要求。並採用不同介電層的種類及厚度條件，包括實施例一：由兩種介電層（第一介電層+第二介電層）材料的組合來形成介電層、比較實施例一：單純由第一介電層來形成介電層、以及比較實施例二：單純由第二介電層來形成介電層，在介電層總厚度為相同的條件下，來比較最深區與最淺區所需的蝕刻時間比值，如第8圖中所示，最深區為最右邊標示為厚度D1處，而最淺區為最右邊標示為厚度D2處，並將第二介電層的厚度設定為D2，而將第一介電層加上第二介電層的總厚度設定為D1，也就是說假設剛好蝕刻至最高的絕緣層表面上層位置即停止的情況。In the following embodiments, the simulation is performed with the etching condition that the first etching rate of the first dielectric layer is 100 angstroms/sec and the second etching rate of the second dielectric layer is 50 angstroms/sec. This condition is consistent with the present invention. The first etching rate is greater than the requirement of the second etching rate. Different types and thickness conditions of the dielectric layer are used, including the first embodiment: a combination of two dielectric layers (first dielectric layer + second dielectric layer) materials to form a dielectric layer, comparative embodiment 1: The dielectric layer is formed solely by the first dielectric layer, and Comparative Example 2: The dielectric layer is formed solely by the second dielectric layer. Under the condition that the total thickness of the dielectric layer is the same, compare the deepest area and the deepest area. The ratio of the etching time required for the shallow area, as shown in Figure 8, the deepest area is the rightmost area marked as thickness D1, and the shallowest area is the rightmost area marked as thickness D2, and the thickness of the second dielectric layer It is set to D2, and the total thickness of the first dielectric layer plus the second dielectric layer is set to D1, that is to say, it is assumed that the etching stops just to the highest position on the surface of the insulating layer.

本發明所使用的第一介電層以及第二介電層的厚度以及相對於蝕刻媒介物的蝕刻速率可以依照半導體元件以及製程的需求來設計，以下說明的第一介電層以及第二介電層的厚度以及蝕刻速率僅作為示例，但並不限於此。The thickness of the first dielectric layer and the second dielectric layer and the etching rate relative to the etching medium used in the present invention can be designed according to the requirements of the semiconductor device and the manufacturing process. The first dielectric layer and the second dielectric layer described below The thickness of the electrical layer and the etching rate are only examples, but not limited thereto.

當第一介電層的厚度為2,500埃以及第二介電層的厚度為5,000埃時，假如第一介電層的第一蝕刻速率為100埃/秒、第二介電層的第二蝕刻速率為50埃/秒，此時D2處的蝕刻時間為將第二介電層的厚度5,000埃除以第二介電層的第二蝕刻速率50埃/秒，得到其蝕刻時間為100秒；而D1處的蝕刻時間，將第二介電層的厚度5,000埃除以第二介電層的第二蝕刻速率50埃/秒得到100秒，以及將第一介電層的厚度2,500埃除以第一介電層的第一蝕刻速率100埃/秒得到25秒，合計D1處的蝕刻時間為125秒，並將D1處的蝕刻時間125秒除以D2處的蝕刻時間25秒，得到兩者蝕刻時間的比值為1.25。同理，若第一層的材料及第二層的材料均為第一介電層的材料，D1總厚度為7,500埃，D2總厚度為5,000埃，第一蝕刻速率為100埃/秒，則D1處的蝕刻時間為75秒，D2處的蝕刻時間為50秒，兩者蝕刻時間的比值為1.5。若第一層的材料及第二層的材料均為第二介電層的材料，D1總厚度為7,500埃，D2總厚度為5,000埃，第二蝕刻速率為50埃/秒，則D1處的蝕刻時間為150秒，D2處的蝕刻時間為100秒，兩者蝕刻時間的比值亦為1.5。經過此等模擬及計算，設定第一層及第二層的不同厚度及比值，得到的結果如表1所示。When the thickness of the first dielectric layer is 2,500 angstroms and the thickness of the second dielectric layer is 5,000 angstroms, if the first etching rate of the first dielectric layer is 100 angstroms/sec, the second etching of the second dielectric layer The rate is 50 angstroms/second. At this time, the etching time at D2 is divided by the thickness of the second dielectric layer of 5,000 angstroms by the second etching rate of the second dielectric layer of 50 angstroms/second, and the etching time is 100 seconds; For the etching time at D1, divide the thickness of the second dielectric layer 5,000 angstroms by the second etch rate of the second dielectric layer 50 angstroms per second to get 100 seconds, and divide the thickness of the first dielectric layer 2,500 angstroms by The first etching rate of the first dielectric layer is 100 angstroms/sec to get 25 seconds, and the total etching time at D1 is 125 seconds, and the etching time at D1 is 125 seconds divided by the etching time at D2 for 25 seconds to get both The ratio of the etching time is 1.25. Similarly, if the material of the first layer and the material of the second layer are both the material of the first dielectric layer, the total thickness of D1 is 7,500 angstroms, the total thickness of D2 is 5,000 angstroms, and the first etching rate is 100 angstroms/sec. The etching time at D1 is 75 seconds, the etching time at D2 is 50 seconds, and the ratio of the etching time between the two is 1.5. If the material of the first layer and the material of the second layer are both the material of the second dielectric layer, the total thickness of D1 is 7,500 angstroms, the total thickness of D2 is 5,000 angstroms, and the second etching rate is 50 angstroms/sec. The etching time is 150 seconds, the etching time at D2 is 100 seconds, and the ratio of the two etching times is also 1.5. After these simulations and calculations, the different thicknesses and ratios of the first layer and the second layer were set, and the results obtained are shown in Table 1.

表1 介電層厚度條件厚度D1與D2處的蝕刻時間比第二層與第一層的厚度比值第一層厚度（埃）第二層厚度（埃）實施例一（兩種介電層的材料）（第一層為第一介電層、第二層為第二介電層）比較實施例一（只有第一介電層）（第一層及第二層均為第一介電層）比較實施例二（只有第二介電層）（第一層及第二層均為第二介電層） 2:1 2,500 5,000 1.25 1.5 1.5 1:1 5,000 5,000 1.5 2 2 1:2 10,000 5,000 2 3 3 1:3 15,000 5,000 2.5 4 4 1:4 20,000 5,000 3 5 5 1:5 25,000 5,000 3.5 6 6 Table 1 Dielectric layer thickness conditions Etching time ratio between thickness D1 and D2 The thickness ratio of the second layer to the first layer Thickness of the first layer (A) Thickness of the second layer (A) Example 1 (Materials of two dielectric layers) (The first layer is the first dielectric layer, and the second layer is the second dielectric layer) Comparative Example 1 (Only the first dielectric layer) (The first and second layers are both the first dielectric layer) Comparative Example 2 (Only the second dielectric layer) (The first and second layers are both second dielectric layers) 2:1 2,500 5,000 1.25 1.5 1.5 1:1 5,000 5,000 1.5 2 2 1:2 10,000 5,000 2 3 3 1:3 15,000 5,000 2.5 4 4 1:4 20,000 5,000 3 5 5 1:5 25,000 5,000 3.5 6 6

由表1的結果可知，D1與D2兩處的蝕刻時間比愈小，表示D1與D2兩處的蝕刻時間差愈小。因此，在第一介電層的第一蝕刻速率大於第二介電層的第二蝕刻速率時，以第二層與第一層的厚度比值為2:1（亦即第二層比第一層為厚）為例，當第一層的材料為第一介電層的材料、第二層的材料為第二介電層的材料時，D1與D2處的蝕刻時間比為1.25；而當第一層及第二層的材料均為第一介電層的材料、或均為第二介電層的材料時，其D1與D2處的蝕刻時間比均為1.5，表示使用不同兩種介電層的材料時，都比僅僅使用一種介電層的材料在D1與D2兩處的時間差來得小。在其餘不同的第二層與第一層的厚度比值（例如厚度比值1:1、1:2直到1:5）的各種組合條件時，也顯示無論第一介電層的厚度與第二介電層的厚度兩者相等或第二層比第一層為薄，也是使用本發明採用不同兩種介電層材料的技術手段時，都會比僅使用一種介電層材料的在D1與D2兩處的時間差來得小。也就是說，在蝕刻時，不論第一層厚度及第二層厚度如何搭配或誰厚誰薄，只要利用對於第一介電層以及第二介電層的蝕刻選擇性差異，且第一介電層的第一蝕刻速率高於第二介電層的第二蝕刻速率，就能使在D1與D2兩處的蝕刻時間差得以減小，參閱第1及9圖，該絕緣層23的沉積形成的轉角寬度y2因而可以比y1為小。由於y2＜y1，使得W減去y2後的寬度可以比習知技術的W減去y1後的寬度為大。因此，各梯級表面上設置在W減去y1後的空間中觸降落窗口的可設計寬度w可以增加。實務上，第一介電層的第一蝕刻速率比第二介電層的第二蝕刻速率至少高於5埃/秒時為較佳。From the results in Table 1, it can be seen that the smaller the etching time ratio between D1 and D2, the smaller the etching time difference between D1 and D2. Therefore, when the first etch rate of the first dielectric layer is greater than the second etch rate of the second dielectric layer, the thickness ratio of the second layer to the first layer is 2:1 (that is, the second layer is greater than the first Layer is thick) as an example, when the material of the first layer is the material of the first dielectric layer and the material of the second layer is the material of the second dielectric layer, the etching time ratio at D1 and D2 is 1.25; When the materials of the first layer and the second layer are both the material of the first dielectric layer or the material of the second dielectric layer, the etching time ratio at D1 and D2 is both 1.5, which means that two different media are used When the materials of the electrical layer are used, the time difference between D1 and D2 is smaller than that of using only one dielectric layer material. In the other different combinations of the thickness ratio of the second layer to the first layer (for example, the thickness ratio of 1:1, 1:2 to 1:5), it also shows that regardless of the thickness of the first dielectric layer and the second dielectric The thickness of the electrical layer is the same or the second layer is thinner than the first layer. When the technical means of using two different dielectric layer materials of the present invention is used, it will be better than the difference between D1 and D2 when using only one dielectric layer material. The time difference here is small. That is to say, during etching, no matter how the thickness of the first layer and the thickness of the second layer are matched or who is thicker or thinner, as long as the difference in etching selectivity for the first dielectric layer and the second dielectric layer is used, and the first dielectric layer The first etching rate of the electrical layer is higher than the second etching rate of the second dielectric layer, which can reduce the etching time difference between D1 and D2. Refer to Figures 1 and 9, the deposition of the insulating layer 23 is formed The corner width y2 can therefore be smaller than y1. Since y2<y1, the width of W minus y2 can be larger than the width of W minus y1 in the prior art. Therefore, the designable width w of the touchdown window provided on the surface of each step in the space after W minus y1 can be increased. In practice, the first etching rate of the first dielectric layer is better than the second etching rate of the second dielectric layer at least higher than 5 angstroms/sec.

第二種實施例The second embodiment

以下實施例中，以第一介電層的第一蝕刻速率為55埃/秒、第二介電層的第二蝕刻速率為50埃/秒的蝕刻條件來進行模擬，此條件符合本發明的第一蝕刻速率大於第二蝕刻速率的要求。並採用如第一種實施例所列的不同介電層的種類及厚度條件，包括實施例二：由兩種介電層（第一介電層+第二介電層）材料的組合來形成介電層、比較實施例三：單純由第一介電層來形成介電層、以及比較實施例四：單純由第二介電層來形成介電層，在介電層總厚度為相同的條件下，來比較最深區與最淺區所需的蝕刻時間比值，其餘條件與第一實施例相同。In the following embodiments, the simulation is performed with the etching condition that the first etching rate of the first dielectric layer is 55 angstroms/sec and the second etching rate of the second dielectric layer is 50 angstroms/sec. This condition complies with the present invention The first etching rate is greater than the requirement of the second etching rate. And use the types and thickness conditions of the different dielectric layers as listed in the first embodiment, including the second embodiment: a combination of two dielectric layers (first dielectric layer + second dielectric layer) materials Dielectric layer, Comparative Example 3: The dielectric layer is formed solely by the first dielectric layer, and Comparative Example 4: The dielectric layer is formed solely by the second dielectric layer, and the total thickness of the dielectric layer is the same Under the conditions, to compare the ratio of the etching time required for the deepest area and the shallowest area, and the remaining conditions are the same as in the first embodiment.

類似於第一種實施例的計算，當第一介電層的厚度為2,500埃以及第二介電層的厚度為5,000埃時，假如第一介電層的第一蝕刻速率為55埃/秒、第二介電層的第二蝕刻速率為50埃/秒，此時D2處的蝕刻時間為將第二介電層的厚度5,000埃除以第二介電層的第二蝕刻速率50埃/秒，得到其蝕刻時間為100秒；而D1處的蝕刻時間，將第二介電層的厚度5,000埃除以第二介電層的第二蝕刻速率50埃/秒得到100秒，以及將第一介電層的厚度2,500埃除以第一介電層的第一蝕刻速率55埃/秒得到45秒，合計D1處的蝕刻時間為145秒，並將D1處的蝕刻時間145秒除以D2處的蝕刻時間100秒，得到兩者蝕刻時間的比值為1.45。同理，若第一層的材料及第二層的材料均為第一介電層的材料，D1總厚度為7,500埃，D2總厚度為5,000埃，第一蝕刻速率為55埃/秒，則D1處的蝕刻時間為136秒，D2處的蝕刻時間為90秒，兩者蝕刻時間的比值為1.5。若第一層的材料及第二層的材料均為第二介電層的材料，D1總厚度為7,500埃，D2總厚度為5,000埃，第二蝕刻速率為50埃/秒，則D1處的蝕刻時間為150秒，D2處的蝕刻時間為100秒，兩者蝕刻時間的比值亦為1.5。經過此等模擬及計算，設定第一層及第二層的不同厚度及比值，得到的結果如表2所示。Similar to the calculation of the first embodiment, when the thickness of the first dielectric layer is 2,500 angstroms and the thickness of the second dielectric layer is 5,000 angstroms, if the first etch rate of the first dielectric layer is 55 angstroms/sec The second etch rate of the second dielectric layer is 50 angstroms/sec. At this time, the etching time at D2 is the thickness of the second dielectric layer 5,000 angstroms divided by the second etch rate of the second dielectric layer 50 angstroms/second Second, the etching time is 100 seconds; and the etching time at D1 is 100 seconds by dividing the thickness of the second dielectric layer 5,000 angstroms by the second etching rate of the second dielectric layer 50 angstroms/second, and the first The thickness of a dielectric layer is 2,500 angstroms divided by the first etch rate of the first dielectric layer 55 angstroms/second to obtain 45 seconds. The total etching time at D1 is 145 seconds, and the etching time at D1 is 145 seconds divided by D2 The etching time is 100 seconds, and the ratio of the two etching times is 1.45. Similarly, if the material of the first layer and the material of the second layer are both the material of the first dielectric layer, the total thickness of D1 is 7,500 angstroms, the total thickness of D2 is 5,000 angstroms, and the first etching rate is 55 angstroms/sec. The etching time at D1 is 136 seconds, the etching time at D2 is 90 seconds, and the ratio of the etching time is 1.5. If the material of the first layer and the material of the second layer are both the material of the second dielectric layer, the total thickness of D1 is 7,500 angstroms, the total thickness of D2 is 5,000 angstroms, and the second etching rate is 50 angstroms/sec. The etching time is 150 seconds, the etching time at D2 is 100 seconds, and the ratio of the two etching times is also 1.5. After these simulations and calculations, the different thicknesses and ratios of the first layer and the second layer were set, and the results obtained are shown in Table 2.

表2 介電層厚度條件厚度D1與D2處的蝕刻時間比第二層與第一層的厚度比值第一層厚度（埃）第二層厚度（埃）實施例二（兩種介電層的材料）（第一層為第一介電層、第二層為第二介電層）比較實施例三（只有第一介電層）（第一層及第二層均為第一介電層）比較實施例四（只有第二介電層）（第一層及第二層均為第二介電層） 2:1 2,500 5,000 1.45 1.5 1.5 1:1 5,000 5,000 1.9 2 2 1:2 10,000 5,000 2.8 3 3 1:3 15,000 5,000 3.7 4 4 1:4 20,000 5,000 4.6 5 5 1:5 25,000 5,000 5.5 6 6 Table 2 Dielectric layer thickness conditions Etching time ratio between thickness D1 and D2 The thickness ratio of the second layer to the first layer Thickness of the first layer (A) Thickness of the second layer (A) Embodiment 2 (materials of two dielectric layers) (the first layer is the first dielectric layer, and the second layer is the second dielectric layer) Comparative Example 3 (only the first dielectric layer) (the first and second layers are both the first dielectric layer) Comparative example four (only the second dielectric layer) (the first layer and the second layer are both the second dielectric layer) 2:1 2,500 5,000 1.45 1.5 1.5 1:1 5,000 5,000 1.9 2 2 1:2 10,000 5,000 2.8 3 3 1:3 15,000 5,000 3.7 4 4 1:4 20,000 5,000 4.6 5 5 1:5 25,000 5,000 5.5 6 6

由表2的結果也可以知道，以第二層與第一層的厚度比值為2:1（亦即第二層比第一層為厚）為例，當第一層的材料為第一介電層的材料、第二層的材料為第二介電層的材料時，D1與D2處的蝕刻時間比為1.45；而當第一層及第二層的材料均為第一介電層的材料、或均為第二介電層的材料時，其D1與D2處的蝕刻時間比均為1.5，表示使用不同兩種介電層的材料時，都比僅僅使用一種介電層的材料在D1與D2兩處的時間差來得小。在其餘不同的第二層與第一層的厚度比值（例如厚度比值1:1、1:2直到1:5）的各種組合條件時，也顯示無論第一介電層的厚度與第二介電層的厚度兩者相等或第二層比第一層為薄，也是使用本發明採用不同兩種介電層材料的技術手段時，都會比僅使用一種介電層材料的在D1與D2兩處的時間差來得小。也就是說，在蝕刻時，不論第一層厚度及第二層厚度如何搭配或誰厚誰薄，只要利用對於第一介電層以及第二介電層的蝕刻選擇性差異，且第一介電層的第一蝕刻速率高於第二介電層的第二蝕刻速率，就能使在D1與D2兩處的蝕刻時間差得以減小，參閱第1及9圖，該絕緣層23的沉積形成的轉角寬度y2因而可以比y1為小。由於y2＜y1，使得W減去y2後的寬度可以比習知技術的W減去y1後的寬度為大。因此，各梯級表面上設置在W減去y1後的空間中觸降落窗口的可設計寬度w可以增加。實務上，第一介電層的第一蝕刻速率比第二介電層的第二蝕刻速率至少高於5埃/秒時為較佳。It can also be known from the results in Table 2 that the thickness ratio of the second layer to the first layer is 2:1 (that is, the second layer is thicker than the first layer) as an example, when the material of the first layer is the first medium When the material of the electrical layer and the material of the second layer are the material of the second dielectric layer, the etching time ratio at D1 and D2 is 1.45; and when the materials of the first layer and the second layer are both the material of the first dielectric layer When the material or both are the material of the second dielectric layer, the etching time ratio at D1 and D2 are both 1.5, which means that when two different dielectric layer materials are used, they are both better than using only one dielectric layer material. The time difference between D1 and D2 is small. In the other different combinations of the thickness ratio of the second layer to the first layer (for example, the thickness ratio of 1:1, 1:2 to 1:5), it also shows that regardless of the thickness of the first dielectric layer and the second dielectric The thickness of the electrical layer is the same or the second layer is thinner than the first layer. When the technical means of using two different dielectric layer materials of the present invention is used, it will be better than the difference between D1 and D2 when using only one dielectric layer material. The time difference here is small. That is to say, during etching, no matter how the thickness of the first layer and the thickness of the second layer are matched or who is thicker or thinner, as long as the difference in etching selectivity for the first dielectric layer and the second dielectric layer is used, and the first dielectric layer The first etching rate of the electrical layer is higher than the second etching rate of the second dielectric layer, which can reduce the etching time difference between D1 and D2. Refer to Figures 1 and 9, the deposition of the insulating layer 23 is formed The corner width y2 can therefore be smaller than y1. Since y2<y1, the width of W minus y2 can be larger than the width of W minus y1 in the prior art. Therefore, the designable width w of the touchdown window provided on the surface of each step in the space after W minus y1 can be increased. In practice, the first etching rate of the first dielectric layer is better than the second etching rate of the second dielectric layer at least higher than 5 angstroms/sec.

綜合以上所述，可以了解，根據本案所提出的具有兩層介電層來取代僅使用一層介電層之設計，並搭配該第一介電層的第一蝕刻速率比該第二介電層的第二蝕刻速率高時，足以提供所應用之三維半導體元件有較習知技術更寬的接觸降落窗口，進而增進應用元件的電子特性和性能表現。Based on the above, it can be understood that the design with two dielectric layers proposed in this case instead of using only one dielectric layer, and the first etch rate of the first dielectric layer is higher than that of the second dielectric layer. When the second etching rate is high, it is sufficient to provide the applied three-dimensional semiconductor device with a wider contact drop window than the conventional technology, thereby improving the electronic characteristics and performance of the applied device.

本發明已以較佳之實施例說明如上，僅用於幫助了解本發明之實施，非用以限定本發明之精神，而熟悉此領域技藝者於領悟本發明之精神後，在不脫離本發明之精神範圍內，當可作些許更動潤飾及等同之變化替換，其專利保護範圍當視後附之申請專利範圍及其等同領域所界定者為準。The present invention has been described above with preferred embodiments, which are only used to help understand the implementation of the present invention, not to limit the spirit of the present invention, and those skilled in the art who understand the spirit of the present invention will not depart from the spirit of the present invention. Within the scope of the spirit, when some modifications and equivalent changes can be made, the scope of patent protection shall be subject to the scope of the attached patent application and its equivalent field.

10、20:基板 11、21:半導體層 12、22:絕緣層 13、23:蝕刻終止層 14:介電層 17、27:階梯狀頂面 19、29:接觸孔 24:第一介電層 25:第二介電層 30:導電結構 100、200:階梯區域 110、220:周邊區 111、211:堆疊 112、212:次堆疊D1、D2、T:厚度 S101~S111:步驟 W、w:寬度 y1、y2:轉角寬度10, 20: substrate 11, 21: semiconductor layer 12, 22: insulating layer 13, 23: etching stop layer 14: Dielectric layer 17, 27: Stepped top surface 19, 29: contact hole 24: The first dielectric layer 25: second dielectric layer 30: conductive structure 100, 200: step area 110, 220: surrounding area 111, 211: Stack 112, 212: sub-stack D1, D2, T: thickness S101~S111: steps W, w: width y1, y2: corner width

本發明的較佳實施例將於實施方式之說明文字中輔以下列圖式做更詳細的說明：第1圖：根據本發明的一種對比實施例的半導體元件的截面圖。第2~9圖：根據本發明的一種實施例的半導體元件的製造方法於多個步驟中的的截面圖。第10圖：根據本發明的一種實施例的半導體元件的製造方法的流程圖。The preferred embodiment of the present invention will be described in more detail with the following figures in the description of the implementation mode: Fig. 1: A cross-sectional view of a semiconductor device according to a comparative example of the present invention. Figures 2-9: cross-sectional views of a method of manufacturing a semiconductor device in multiple steps according to an embodiment of the present invention. Fig. 10: A flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

20:基板 20: substrate

21:半導體層 21: Semiconductor layer

22:絕緣層 22: Insulation layer

23:蝕刻終止層 23: Etch stop layer

24:第一介電層 24: The first dielectric layer

25:第二介電層 25: second dielectric layer

27:階梯狀頂面 27: Stepped top surface

29:接觸孔 29: contact hole

30:導電結構 30: conductive structure

200:半導體裝置 200: Semiconductor device

211:堆疊 211: Stack

212:次堆疊 212: Secondary Stack

220:周邊區 220: Surrounding area

W、w:寬度 W, w: width

y2:轉角寬度 y2: corner width

Claims

一種半導體元件的製造方法，該方法包括下列步驟：提供一基板；沉積複數半導體層及複數絕緣層相互交錯形成一堆疊於該基板上；圖形化該堆疊形成一階梯狀頂面；形成一第一介電層於該階梯狀頂面上；去除一部分的該第一介電層，使一部分的該階梯狀頂面露出；形成一第二介電層，覆蓋一另一部分的該第一介電層以及一另一部分的該階梯狀頂面；以及以一蝕刻媒介物蝕刻該第二介電層以及該另一部分的該第一介電層，其中該另一部分的第一介電層對該蝕刻媒介物具有一第一蝕刻速率、該第二介電層對該蝕刻媒介物具有一第二蝕刻速率，且該第一蝕刻速率比該第二蝕刻速率為高。A method for manufacturing a semiconductor element, the method including the following steps: Provide a substrate; Depositing a plurality of semiconductor layers and a plurality of insulating layers to form a stack on the substrate; Graphic the stack to form a stepped top surface; Forming a first dielectric layer on the stepped top surface; Removing a part of the first dielectric layer to expose a part of the stepped top surface; Forming a second dielectric layer, covering another part of the first dielectric layer and another part of the stepped top surface; and The second dielectric layer and the other part of the first dielectric layer are etched with an etching medium, wherein the other part of the first dielectric layer has a first etching rate for the etching medium, the second medium The electrical layer has a second etching rate for the etching medium, and the first etching rate is higher than the second etching rate.

如申請專利範圍第1項所述的方法，其中該第一蝕刻速率較佳為比該第二蝕刻速率至少高5埃/秒。According to the method described in claim 1, wherein the first etching rate is preferably at least 5 angstroms/sec higher than the second etching rate.

如申請專利範圍第1項所述的方法，還包括下列步驟：於該第二介電層的一表面製備作為蝕刻該第二介電層以及該第一介電層的一遮罩；利用該遮罩，蝕刻該堆疊中一最靠近該階梯狀頂面的該絕緣層，以形成一接觸孔；移除該遮罩；沉積一金屬層於該第二介電層上及該接觸孔內；以及圖形化該金屬層。The method described in item 1 of the scope of patent application also includes the following steps: Preparing a mask on a surface of the second dielectric layer as a mask for etching the second dielectric layer and the first dielectric layer; Using the mask, etching an insulating layer closest to the stepped top surface in the stack to form a contact hole; Remove the mask; Depositing a metal layer on the second dielectric layer and in the contact hole; and Pattern the metal layer.

如申請專利範圍第3項所述的方法，還包括下列步驟：形成一蝕刻終止層，覆蓋該階梯狀頂面，其中當該去除一部分的該第一介電層的步驟被執行後，一部分的該蝕刻終止層露出；以及利用該遮罩，在蝕刻該最靠近該階梯狀頂面的該絕緣層之前，蝕刻該蝕刻終止層，以形成該接觸孔。The method described in item 3 of the scope of patent application also includes the following steps: Forming an etching stop layer to cover the stepped top surface, wherein after the step of removing a part of the first dielectric layer is performed, a part of the etching stop layer is exposed; and Using the mask, before etching the insulating layer closest to the stepped top surface, the etching stop layer is etched to form the contact hole.

一種半導體元件，包括：一堆疊，該堆疊包括相互堆疊的複數半導體層及複數絕緣層，且該堆疊具有一階梯狀頂面；一第一介電層，覆蓋該階梯狀頂面的一部分；以及一第二介電層，覆蓋該第一介電層及該階梯狀頂面的另一部分，其中該第一介電層的蝕刻速率大於該第二介電層的蝕刻速率。A semiconductor component, including: A stack, the stack includes a plurality of semiconductor layers and a plurality of insulating layers stacked on each other, and the stack has a stepped top surface; A first dielectric layer covering a part of the stepped top surface; and A second dielectric layer covers the first dielectric layer and another part of the stepped top surface, wherein the etching rate of the first dielectric layer is greater than the etching rate of the second dielectric layer.

如申請專利範圍第5項所述的半導體元件，還包括：一蝕刻終止層，覆蓋該階梯狀頂面，其中該蝕刻終止層的材料為含氮及矽的化合物。The semiconductor device as described in item 5 of the scope of patent application also includes: An etching stop layer covers the stepped top surface, wherein the material of the etching stop layer is a compound containing nitrogen and silicon.

如申請專利範圍第5項所述的半導體元件，還包括：複數導電結構，設置於該第二介電層上，其中一部分該複數導電結構貫穿該第二介電層，另一部分該複數導電結構貫穿該第一介電層與該第二介電層，從而使該半導體層與該複數導電結構電性導通。The semiconductor device as described in item 5 of the scope of patent application also includes: A plurality of conductive structures are disposed on the second dielectric layer, a part of the plurality of conductive structures penetrates the second dielectric layer, and the other part of the plurality of conductive structures penetrates the first dielectric layer and the second dielectric layer, thereby The semiconductor layer and the plurality of conductive structures are electrically connected.

如申請專利範圍第5項所述的半導體元件，其中該第一介電層及該第二介電層的材料為無機含氧化物層，以及該第一蝕刻速率比該第二蝕刻速率高至少5埃/秒。The semiconductor device according to claim 5, wherein the materials of the first dielectric layer and the second dielectric layer are inorganic oxide-containing layers, and the first etching rate is at least higher than the second etching rate 5 Angstroms/sec.

如申請專利範圍第7項所述的半導體元件，其中該第一介電層及該第二介電層的材料係分別選自於以低溫氧化法製成的二氧化矽（LTO OX）、以TEOS（(四乙基正矽酸鹽)製成的二氧化矽（TEOS OX）、HQ-SIO OX、HTO OX、熱氧化法二氧化矽（thermal OX）、SiO₂ 、SiON、SiC、SiC(OH)或SiOF其中之二。As for the semiconductor device described in claim 7, wherein the materials of the first dielectric layer and the second dielectric layer are selected from silicon dioxide (LTO OX) made by low-temperature oxidation method, and Silicon dioxide (TEOS OX) made of TEOS ((tetraethyl orthosilicate), HQ-SIO OX, HTO OX, thermal OX, SiO ₂ , SiON, SiC, SiC ( OH) or SiOF.

如申請專利範圍第6項所述的半導體元件，其中該蝕刻終止層為一氮化物層、該半導體層為一多晶矽層、而該絕緣層為一氧化物層。According to the semiconductor device described in claim 6, wherein the etch stop layer is a nitride layer, the semiconductor layer is a polysilicon layer, and the insulating layer is an oxide layer.