TW202027248A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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本發明涉及一種半導體元件及其製造方法,特別是涉及一種具有靜電防護層的半導體元件及其製造方法。 The present invention relates to a semiconductor element and a manufacturing method thereof, in particular to a semiconductor element with an electrostatic protection layer and a manufacturing method thereof.
在半導體功率元件的應用領域中,半導體功率元件對靜電放電保護能力已成為重要指標。一些小訊號半導體功率元件因具有較小的晶片尺寸,對靜電放電保護能力較差,甚至無法達到靜電放電保護的最低標準。部分半導體功率元件雖然具有較大的晶片尺寸,而可具有較大的靜電放電保護能力,但可能需要在較嚴苛的環境(如:相對濕度<65%的乾燥環境,或粉塵較多的環境)下操作,因而對半導體功率元件的靜電放電保護能力有更高的要求。 In the application field of semiconductor power components, the ability of semiconductor power components to protect against electrostatic discharge has become an important indicator. Some small-signal semiconductor power components have a small chip size, and have poor ESD protection capabilities, and even fail to meet the minimum standards for ESD protection. Although some semiconductor power components have a larger chip size, they can have a larger electrostatic discharge protection capability, but they may need to be in a harsh environment (such as a dry environment with a relative humidity of <65%, or an environment with more dust ), so there are higher requirements for the electrostatic discharge protection of semiconductor power components.
因此,在現有的技術中,將靜電放電保護結構被整合到半導體功率元件中,以增加半導體功率元件對靜電放電的承受能力。然而,在現有製程中,由於製程條件與製程餘裕度(process window)的限制,靜電放電保護結構的位置容易偏移預定位置。另外,現有的半導體功率元件中,靜電放電保護結構會直接連接漂移區與基體區,且漂移區與基體區之間會形成沿著磊晶層的厚度方向延伸的弧形界面。 Therefore, in the existing technology, the electrostatic discharge protection structure is integrated into the semiconductor power device to increase the ability of the semiconductor power device to withstand electrostatic discharge. However, in the existing manufacturing process, due to the limitation of the process conditions and the process window, the position of the electrostatic discharge protection structure is easily shifted from the predetermined position. In addition, in existing semiconductor power devices, the electrostatic discharge protection structure directly connects the drift region and the base region, and an arc-shaped interface extending along the thickness direction of the epitaxial layer is formed between the drift region and the base region.
因此,當半導體功率元件操作時,在漂移區與基體區之間的弧形界面的電場強度較強,導致崩潰現象經常在弧形界面附近的區域發生,並降低半導體功率元件本身的耐壓。 Therefore, when the semiconductor power device is operating, the electric field strength at the arc-shaped interface between the drift region and the base region is relatively strong, causing the collapse phenomenon to often occur in the area near the arc-shaped interface and reducing the withstand voltage of the semiconductor power device itself.
另一方面,對於現有的半導體功率元件而言,崩潰電壓 (breakdown voltage)以及導通電阻(on-resistance)是較重要的參數,其中導通電阻會影響半導體功率元件的導通損耗(conducting loss)。目前業界傾向於通過提高漂移區的摻雜濃度,以進一步降低半導體功率元件的導通電阻。然而,現有的半導體功率元件在整合靜電放電保護結構之後,已具有相對偏低的耐壓,更難以符合目前業界的趨勢。 On the other hand, for existing semiconductor power devices, the breakdown voltage (breakdown voltage) and on-resistance (on-resistance) are more important parameters. Among them, the on-resistance affects the conducting loss of semiconductor power devices. Currently, the industry tends to increase the doping concentration of the drift region to further reduce the on-resistance of semiconductor power devices. However, the existing semiconductor power devices have relatively low withstand voltage after integrating the electrostatic discharge protection structure, and it is more difficult to comply with the current industry trend.
本發明所欲解決的其中一技術問題在於,克服具有靜電放電防護結構的半導體元件的耐壓偏低的問題。 One of the technical problems to be solved by the present invention is to overcome the problem of low withstand voltage of the semiconductor element with the electrostatic discharge protection structure.
為了解決上述的技術問題,本發明所採用的其中一技術方案是,提供一種半導體元件的製造方法。前述的製造方法包括下列步驟。形成一磊晶層於一基材上,磊晶層被區分為至少一元件區以及一靜電防護區。在元件區形成第一基體區以及在靜電防護區形成第二基體區。在磊晶層的表面上形成一疊層結構,疊層結構位於靜電防護區,並包括一絕緣層以及位於絕緣層上的一半導體層,半導體層具有一第一重摻雜區。半導體層內形成至少一第二重摻雜區,該第二重摻雜區與該第一重摻雜區共同形成一靜電防護層。靜電防護層位於所述第二基體區上方,且靜電防護層完全重疊於所述第二基體區範圍內。 In order to solve the above technical problems, one of the technical solutions adopted by the present invention is to provide a method for manufacturing a semiconductor device. The aforementioned manufacturing method includes the following steps. An epitaxial layer is formed on a substrate, and the epitaxial layer is divided into at least one device area and an electrostatic protection area. A first base area is formed in the element area and a second base area is formed in the electrostatic protection area. A stacked structure is formed on the surface of the epitaxial layer. The stacked structure is located in the electrostatic protection area and includes an insulating layer and a semiconductor layer on the insulating layer. The semiconductor layer has a first heavily doped area. At least one second heavily doped region is formed in the semiconductor layer, and the second heavily doped region and the first heavily doped region together form an electrostatic protection layer. The static electricity protection layer is located above the second base region, and the static electricity protection layer completely overlaps within the range of the second base region.
本發明所採用的另一技術方案是,提供一種半導體元件,其被區分為一元件區以及一靜電防護區,且所述半導體元件包括一磊晶層、一閘極結構以及一靜電防護層。磊晶層包括位於元件區的一第一基體區以及位於靜電防護區的一第二基體區。閘極結構設置於元件區內,並至少連接於第一基體區。靜電防護層設置於磊晶層的一表面上並與磊晶層隔離。靜電防護層位於所述第二基體區上方,且靜電防護層完全重疊於所述第二基體區範圍內。 Another technical solution adopted by the present invention is to provide a semiconductor device, which is divided into a device area and an electrostatic protection area, and the semiconductor device includes an epitaxial layer, a gate structure and an electrostatic protection layer. The epitaxial layer includes a first base area located in the device area and a second base area located in the electrostatic protection area. The gate structure is arranged in the element area and connected to at least the first base area. The electrostatic protection layer is arranged on a surface of the epitaxial layer and is isolated from the epitaxial layer. The static electricity protection layer is located above the second base region, and the static electricity protection layer completely overlaps within the range of the second base region.
本發明的有益效果在於,本發明所提供的半導體元件及其製造方法,其通過“靜電防護層完全重疊於所述第二基體區範圍內” 的技術手段,可以使具有靜電防護層的半導體元件符合靜電放電防護標準,又可具有較高的耐壓。 The beneficial effect of the present invention is that the semiconductor device and the manufacturing method thereof provided by the present invention are implemented by "the electrostatic protection layer is completely overlapped within the range of the second base region" The technical means can make the semiconductor element with the electrostatic protection layer meet the electrostatic discharge protection standard, but also have a higher withstand voltage.
為使能更進一步瞭解本發明的特徵及技術內容,請參閱以下有關本發明的詳細說明與附圖,然而所提供的附圖僅用於提供參考與說明,並非用來對本發明加以限制。 In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings about the present invention. However, the drawings provided are only for reference and description, and are not used to limit the present invention.
M1、M2‧‧‧半導體元件 M1, M2‧‧‧Semiconductor components
10‧‧‧基材 10‧‧‧Substrate
11、11’、11”‧‧‧磊晶層 11, 11’, 11"‧‧‧Epitaxial layer
R1‧‧‧元件區 R1‧‧‧Component area
R2‧‧‧靜電防護區 R2‧‧‧Static protection zone
11h‧‧‧溝槽 11h‧‧‧Groove
11s‧‧‧表面 11s‧‧‧surface
110、110’‧‧‧漂移區 110, 110’‧‧‧Drift Zone
111‧‧‧第一基體區 111‧‧‧First matrix area
112‧‧‧第二基體區 112‧‧‧Second base area
112a‧‧‧延伸部分 112a‧‧‧Extension
113a‧‧‧第一源極區 113a‧‧‧First source region
113b‧‧‧第二源極區 113b‧‧‧Second source region
12‧‧‧閘極結構 12‧‧‧Gate structure
120‧‧‧閘絕緣層 120‧‧‧Gate insulation layer
121‧‧‧閘極 121‧‧‧Gate
13’‧‧‧初始絕緣層 13’‧‧‧Initial insulation
14P‧‧‧未摻雜半導體層 14P‧‧‧Undoped semiconductor layer
P1’‧‧‧疊層結構 P1’‧‧‧Laminated structure
14”‧‧‧初始半導體層 14"‧‧‧Initial semiconductor layer
14’‧‧‧半導體層 14’‧‧‧Semiconductor layer
P1‧‧‧靜電防護疊層 P1‧‧‧Static protection stack
13‧‧‧絕緣層 13‧‧‧Insulation layer
14‧‧‧靜電防護層 14‧‧‧Static protection layer
140、140’‧‧‧第一重摻雜區 140、140’‧‧‧First heavily doped area
141‧‧‧第二重摻雜區 141‧‧‧Second heavily doped area
15、15’‧‧‧層間介電層 15, 15’‧‧‧Interlayer dielectric layer
15h‧‧‧接觸窗 15h‧‧‧Contact window
16‧‧‧導電結構 16‧‧‧Conductive structure
161‧‧‧第一導電柱 161‧‧‧The first conductive pillar
162‧‧‧第二導電柱 162‧‧‧Second conductive pillar
17‧‧‧接墊組 17‧‧‧Pad set
171‧‧‧第一接墊 171‧‧‧First pad
172‧‧‧第二接墊 172‧‧‧Second pad
18‧‧‧保護層 18‧‧‧Protection layer
20‧‧‧基體摻雜步驟 20‧‧‧Matrix doping step
30‧‧‧重摻雜步驟 30‧‧‧Heavy doping step
111’‧‧‧第一初始基體摻雜區 111’‧‧‧First initial matrix doped area
112’‧‧‧第二初始基體摻雜區 112’‧‧‧The second initial matrix doped area
PR‧‧‧光阻層 PR‧‧‧Photoresist layer
S100~S130‧‧‧流程步驟 S100~S130‧‧‧Process steps
圖1繪示本發明其中一實施例的半導體元件的流程圖。 FIG. 1 shows a flowchart of a semiconductor device according to one embodiment of the invention.
圖2A為本發明實施例的半導體元件在製造流程中的局部剖面示意圖。 2A is a schematic partial cross-sectional view of a semiconductor device in a manufacturing process according to an embodiment of the present invention.
圖2B為本發明實施例的半導體元件在製造流程中的局部剖面示意圖。 2B is a schematic partial cross-sectional view of the semiconductor device in the manufacturing process of the embodiment of the present invention.
圖2C為本發明實施例的半導體元件在製造流程中的局部剖面示意圖。 2C is a schematic partial cross-sectional view of the semiconductor device in the manufacturing process of the embodiment of the present invention.
圖2D為本發明實施例的半導體元件在製造流程中的局部剖面示意圖。 2D is a schematic partial cross-sectional view of the semiconductor device in the manufacturing process of the embodiment of the present invention.
圖2E為本發明實施例的半導體元件在製造流程中的局部剖面示意圖。 2E is a schematic partial cross-sectional view of the semiconductor device in the manufacturing process of an embodiment of the present invention.
圖2F為本發明實施例的半導體元件在製造流程中的局部剖面示意圖。 2F is a schematic partial cross-sectional view of the semiconductor device in the manufacturing process of the embodiment of the present invention.
圖2G為本發明實施例的半導體元件在製造流程中的局部剖面示意圖。 2G is a schematic partial cross-sectional view of the semiconductor device in the manufacturing process of the embodiment of the present invention.
圖3為本發明一實施例的半導體元件的局部剖面示意圖。 3 is a schematic partial cross-sectional view of a semiconductor device according to an embodiment of the invention.
圖4為本發明另一實施例的半導體元件在製造流程中的局部剖面示意圖。 4 is a schematic partial cross-sectional view of a semiconductor device in a manufacturing process according to another embodiment of the invention.
圖5為本發明又一實施例的半導體元件在製造流程中的局部剖面示意圖。 5 is a schematic partial cross-sectional view of a semiconductor device in a manufacturing process according to another embodiment of the present invention.
圖6為本發明一實施例的半導體元件的局部剖面示意圖。 6 is a schematic partial cross-sectional view of a semiconductor device according to an embodiment of the invention.
請參閱圖1。圖1為本發明一實施例的半導體元件的製造方法的流程圖。具體而言,本發明提供具有靜電防護層的半導體元件的製造方法,並至少具有下列步驟。 Please refer to Figure 1. FIG. 1 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the invention. Specifically, the present invention provides a method for manufacturing a semiconductor device with an electrostatic protection layer, and at least the following steps are provided.
在步驟S100中,形成一磊晶層於一基材上,其中,磊晶層被區分為至少一元件區以及一靜電防護區。在步驟S110中,分別在元件區以及靜電防護區內形成一第一基體區以及一第二基體區。在步驟S120中,在磊晶層的表面上形成位於靜電防護區的一疊層結構,疊層結構包括一絕緣層以及位於絕緣層上的一半導體層,其中,半導體層具有一第一重摻雜區。在步驟S130中,在半導體層內形成至少一第二重摻雜區,第二重摻雜區與第一重摻雜區共同形成一靜電防護層。靜電防護層位於第二基體區上方,且靜電防護層完全重疊於所述第二基體區範圍內。 In step S100, an epitaxial layer is formed on a substrate, wherein the epitaxial layer is divided into at least one device area and an electrostatic protection area. In step S110, a first base area and a second base area are formed in the device area and the electrostatic protection area, respectively. In step S120, a stacked structure located in the electrostatic protection zone is formed on the surface of the epitaxial layer. The stacked structure includes an insulating layer and a semiconductor layer located on the insulating layer, wherein the semiconductor layer has a first heavily doped Miscellaneous area. In step S130, at least one second heavily doped region is formed in the semiconductor layer, and the second heavily doped region and the first heavily doped region together form an electrostatic protection layer. The static electricity protection layer is located above the second base area, and the static electricity protection layer completely overlaps within the second base area.
以下將詳細說明半導體元件的製造方法中的具體步驟。在本實施例中,以溝槽式半導體功率元件為例,來詳細說明本發明實施例的製造方法。 The specific steps in the manufacturing method of the semiconductor element will be described in detail below. In this embodiment, a trench semiconductor power device is taken as an example to illustrate the manufacturing method of the embodiment of the present invention in detail.
請參照圖2A,其顯示本發明一實施例的半導體元件在製造流程中的局部剖面示意圖。基材10上已經形成一磊晶層(epitaxial layer)11。基材10例如為矽基板(silicon substrate),其具有高摻雜濃度的第一型導電性雜質,以作為半導體功率元件的汲極(drain)。
Please refer to FIG. 2A, which shows a partial cross-sectional view of a semiconductor device in a manufacturing process according to an embodiment of the present invention. An
前述的第一導電型雜質可以是N型或P型導電性雜質。假設基材10為矽基材,N型導電性雜質為五價元素離子,例如磷離子或砷離子,而P型導電性雜質為三價元素離子,例如硼離子、鋁離子或鎵離子。
The aforementioned first conductivity type impurities may be N-type or P-type conductivity impurities. Assuming that the
若溝槽式功率半導體元件為N型功率金氧半場效電晶體,基材10摻雜N型導電性雜質。另一方面,若溝槽式功率半導體元件為P型溝槽式功率金氧半場效電晶體,則基材10摻雜P型導電性雜質。
If the trench power semiconductor device is an N-type power MOSFET, the
磊晶層11”形成於基材10上方,並具有低濃度的第一型導電性雜質。以NMOS電晶體為例,基材10為高濃度的N型摻雜(N+),而磊晶層11”則為低濃度的N型摻雜(N-)。反之,以PMOS電晶體為例,基材10為高濃度的P型摻雜(P+ doping),而磊晶層11”則為低濃度的P型摻雜(P- doping)。
The
在本實施例中,磊晶層11”具有一表面11s,且磊晶層11”被區分為一元件區R1以及一靜電防護區R2。須說明的是,雖然圖2A繪示靜電防護區R2被元件區R1圍繞,但本發明並不限制靜電防護區R2與元件區R1的配置位置。在另一實施例中,元件區R1可位於靜電防護區R2的其中一側。在又一實施例中,元件區R1可被靜電防護區R2圍繞。也就是說,靜電防護區R2與元件區R1的配置位置以及形狀可以根據實際需求更改,本發明並不限制。
In this embodiment, the
如圖2A所示,至少一閘極結構12(圖2A繪示多個為例)已經被形成於元件區R1內,且閘極結構12包括一閘絕緣層120以及一閘極121。另外,閘極結構12可以是平面式閘極結構或者是溝槽式閘極結構。
As shown in FIG. 2A, at least one gate structure 12 (a plurality of which are shown in FIG. 2A as an example) has been formed in the device region R1, and the
在本實施例中,閘極結構12為溝槽式閘極結構。在形成閘極結構12的步驟中,先在磊晶層11”內形成多個位於元件區R1內的溝槽11h,之後在溝槽11h內依序形成閘絕緣層120以及閘極121。
In this embodiment, the
如圖2A所示,對磊晶層11”執行一基體摻雜步驟20,以在元件區R1形成一第一初始基體摻雜區111’以及在靜電防護區R2形成一第二初始基體摻雜區112’。
As shown in FIG. 2A, a
請參照圖2B,依序形成一初始絕緣層13’以及一未摻雜半導體層14P於磊晶層11”的表面11s。初始絕緣層13’會覆蓋磊晶層11”的整個表面11s。初始絕緣層13’的材料可以選擇氧化物或者氮化物,如:氧化矽或者氮化矽。
2B, an initial insulating layer 13' and an
另外,初始絕緣層13’的厚度,是對應於半導體功率元件的閘源極偏壓(Vgs)的大小來調整。當半導體功率元件的閘源極電壓(Vgs)越大,初始絕緣層13’的厚度越厚。 In addition, the thickness of the initial insulating layer 13' is adjusted according to the magnitude of the gate-source bias (Vgs) of the semiconductor power element. As the gate-source voltage (Vgs) of the semiconductor power element is larger, the thickness of the initial insulating layer 13' is thicker.
未摻雜半導體層14P被形成於初始絕緣層13’上,以與磊晶層11”隔離。未摻雜半導體層14P可以是一未摻雜多晶矽層。之後,對未摻雜半導體層14P執行一重摻雜步驟30。
The
請參照圖2C,執行一基體熱趨入步驟,以在磊晶層11’內形成第一基體區111與第二基體區112。另一方面,在基體熱趨入步驟中,也會同步地在未摻雜半導體層14P內形成第一重摻雜區140’,而形成一初始半導體層14”。
Please refer to FIG. 2C, performing a substrate thermal immersion step to form a
在本實施例中,在重摻雜步驟30與基體摻雜步驟20中,都是使用具有相同導電型的雜質。也就是說,第一重摻雜區140’、第一基體區111以及第二基體區112都會具有相同的導電型,但僅做為舉例,並不限制本發明。在其他實施例中,也可以對第一重摻雜區140’、第一基體區111以及第二基體區112做不同導電型加入額外製程步驟達到摻雜結果。
In this embodiment, in the
須說明的是,在本實施例中,形成初始半導體層14”的步驟,是在執行基體熱趨入步驟之前完成。然而,在其他實施例中,也可以先執行基體熱趨入步驟,來形成第一基體區111與第二基體區112。之後,再執行另一次熱趨入步驟,以形成具有第一重摻雜區140'的初始半導體層14”。
It should be noted that, in this embodiment, the step of forming the
在其他實施例中,也可以先形成第一基體區111以及第二基體區112在磊晶層11”內之後,再形成位於元件區R1內的閘極結構12。
In other embodiments, the
如圖2C所示,第一基體區111位於磊晶層11’的元件區R1內,並圍繞閘極結構12。磊晶層11’中的其他區域形成溝槽式半導體元件的漂移區110’。第二基體區112位於靜電防護區R2內,並連接於初始絕緣層13’。
As shown in FIG. 2C, the
請參照圖2D,去除位於元件區R1的一部分初始絕緣層13’以及一部分初始半導體層14”,以形成位於靜電防護區R2的一疊層結構P1’。
2D, a part of the initial insulating layer 13' and a part of the
具體而言,可在初始半導體層14”上形成光阻層PR,以定義出疊層結構P1’的位置,再執行一蝕刻步驟,去除位於元件區R1的一部分初始半導體層14”以及一部分初始絕緣層13’。另一部分被光阻層PR所覆蓋的初始半導體層14”以及初始絕緣層13’會被保留,而形成在靜電防護區R2的疊層結構P1’。
Specifically, a photoresist layer PR can be formed on the
據此,疊層結構P1’包括位於靜電防護區R2內的半導體層14’以及一絕緣層13,且半導體層14’內具有第一重摻雜區140’。通過上述步驟來形成疊層結構P1’,可以避免疊層結構P1’的位置偏移,而導致半導體層14’與磊晶層11’直接接觸。在本實施例中,半導體層14’的橫向寬度會與絕緣層13的橫向寬度大致相同。具體而言,半導體層14’的寬度與絕緣層13的寬度之間的差值小於0.5um。
Accordingly, the stacked structure P1' includes a semiconductor layer 14' and an insulating
請參照圖2E,在半導體層14’內再形成至少一第二重摻雜區141,使至少一第二重摻雜區141與第一重摻雜區140共同形成一靜電防護層14。靜電防護層14設置於絕緣層13上,並且靜電防護層14與絕緣層13共同形成靜電防護疊層P1。
2E, at least one second heavily doped
詳細而言,在半導體層14’上可預先形成遮罩圖案層(圖未示),以定義出第二重摻雜區141的位置。之後,通過依序進行一摻雜步驟以及一熱趨入步驟,可在半導體層14’內形成第二重摻雜區141。
In detail, a mask pattern layer (not shown) can be pre-formed on the semiconductor layer 14' to define the position of the second heavily doped
第二重摻雜區141與第一重摻雜區140分別具有相反的導電型。因此,在第二重摻雜區141與第一重摻雜區140之間的交界面會形成一PN接面。
The second heavily doped
在圖2E的實施例中,在半導體層14’內形成兩個彼此分離的第二重摻雜區141,且第一重摻雜區140位於兩個第二重摻雜區
141之間,而形成雙接面二極體(bipolar diode),如:PNP雙接面二極體或者是NPN雙接面二極體。
In the embodiment of FIG. 2E, two separate second heavily doped
另外,在形成第二重摻雜區141的步驟中,可同步地在元件區R1內形成至少一第一源極區113a(圖2E繪示多個)。據此,第一源極區113a與第二重摻雜區141會具有相同的導電型。
In addition, in the step of forming the second heavily doped
須說明的是,可以通過改變遮罩圖案層,來調整第二重摻雜區141的位置,而形成不同的靜電防護層14。請先參照圖4,其顯示本發明另一實施例的半導體元件在製造流程中的剖面示意圖,且可接續圖2D的步驟。
It should be noted that the position of the second heavily doped
在圖4的實施例中,在半導體層14’內只形成一第二重摻雜區141,而形成PN接面二極體(diode)。因此,只要能達到靜電放電保護的效果,靜電防護層14可以是雙接面二極體、PN二極體或者是其他元件。
In the embodiment of FIG. 4, only a second heavily doped
請再參照圖5,其顯示本發明另一實施例的半導體元件在製造流程中的剖面示意圖,且可接續圖2D的步驟。在形成第二重摻雜區141的步驟中,可同步地在元件區R1內形成至少一第一源極區113a(圖5繪示多個)以及靜電防護區R2內形至少一第二源極區113b(圖5繪示兩個)。
Please refer to FIG. 5 again, which shows a schematic cross-sectional view of a semiconductor device in the manufacturing process of another embodiment of the present invention, and the step of FIG. 2D can be continued. In the step of forming the second heavily doped
在圖5的實施例中,第一源極區113a位於第一基體區111上方,並連接於至少一閘極結構12。另外,第二基體區112具有一延伸部分112a,且延伸部分112a會連接到最靠近靜電防護區R2的閘極結構12。第二源極區113b形成於延伸部分112a上面部份,並連接最靠近靜電防護區R2的閘極結構12。
In the embodiment of FIG. 5, the
值得注意的是,通過上述步驟,可一併在元件R1形成電晶體結構,以及在靜電防護區R2形成靜電防護疊層P1。據此,本發明實施例的製程步驟中,形成靜電防護疊層P1的步驟可以與形成電晶體結構的步驟整合,進而降低製造成本。 It is worth noting that through the above steps, a transistor structure can be formed on the element R1 and an electrostatic protection stack P1 can be formed in the electrostatic protection area R2. Accordingly, in the process steps of the embodiment of the present invention, the step of forming the electrostatic protection layer P1 can be integrated with the step of forming the transistor structure, thereby reducing the manufacturing cost.
請參照圖2F、圖2G以及圖3,形成一重分布線路結構,以
使電晶體結構以及靜電防護疊層P1可電性連接於一外部控制電路。詳細而言,如圖2F所示,形成一層間介電層15’於靜電防護層14以及磊晶層11的表面11s上。接著,如圖2G所示,在層間介電層15形成多個接觸窗15h,以及在多個接觸窗15h內形成多個導電結構16。
Please refer to Figure 2F, Figure 2G and Figure 3 to form a redistributed circuit structure to
The transistor structure and the static protection stack P1 can be electrically connected to an external control circuit. Specifically, as shown in FIG. 2F, an interlayer dielectric layer 15' is formed on the
導電結構16包括多個第一導電柱161與多個第二導電柱162。每一個第一導電柱161通過對應的接觸窗15h,電性連接於對應的第一源極區113a。每一個第二導電柱162通過對應的接觸窗15h電性連接於靜電防護層14的第一重摻雜區140或者第二重摻雜區141。另外,第一重摻雜區140可接亦可不接第二導電柱162,可視應用需求決定。
The
請參照圖3,顯示本發明實施例的半導體元件的局部剖面示意圖。在本實施例中,還進一步在層間介電層15上形成一接墊組17。接墊組17包括多個第一接墊171以及多個第二接墊172。第一接墊171通過對應的第一導電柱161電性連接於第一源極區113a以及第二源極區113b。第二接墊172通過對應的第二導電柱162電性連接於第一重摻雜區140或者第二重摻雜區141。
Please refer to FIG. 3, which shows a schematic partial cross-sectional view of a semiconductor device according to an embodiment of the present invention. In this embodiment, a pad set 17 is further formed on the
之後,形成一保護層18於接墊組17上。保護層18具有多個開口,每一開口暴露出對應的第一接墊171(或第二接墊172),以使多個第一接墊171與多個第二接墊172可電性連接至外部控制電路。
After that, a
據此,如圖3所示,本發明實施例提供一種整合靜電防護層14的半導體元件M1。半導體元件M1例如是溝槽式金氧半電晶體、側向擴散金氧半電晶體或者平面式金氧半電晶體等。
Accordingly, as shown in FIG. 3, an embodiment of the present invention provides a semiconductor device M1 integrated with the
半導體元件M1可被區分為元件區R1與靜電防護區R2。靜電防護區R2的面積實際應用需求來調整。若半導體元件M1需要符合較高的靜電放電防護規格,也就是具有較大的靜電放電承受能力,靜電防護區R2的面積也會越大。 The semiconductor device M1 can be divided into a device area R1 and an electrostatic protection area R2. The area of the electrostatic protection zone R2 can be adjusted according to actual application requirements. If the semiconductor element M1 needs to meet a higher ESD protection specification, that is, it has a greater ESD tolerance, the area of the ESD protection zone R2 will be larger.
半導體元件M1包括基材10、磊晶層11、閘極結構12以及靜電防護疊層P1。磊晶層11設置於基材10上,並具有漂移區110、第一基體區111、第二基體區112以及第一源極區113a。漂移區110位於磊晶層11內靠近基材10的一側,並由元件區R1延伸至靜電防護區R2。
The semiconductor device M1 includes a
第一基體區111位於元件區R1內,並位於遠離基材10的一側。也就是說,第一基體區111位於漂移區110上方。另外,第一源極區113a位於第一基體區111上方,並連接於磊晶層11的表面11s。
The
第二基體區112位於靜電防護區R2內,並位於磊晶層11內遠離基材10的一側,也就是位於漂移區110上方。
The
當半導體元件M1為溝槽式金氧半電晶體時,磊晶層11還包括位於元件區R1內的至少一個溝槽11h,且閘極結構12設置在溝槽11h內。
When the semiconductor device M1 is a trench metal oxide semi-transistor, the
如圖3所示,閘極結構12包括一閘絕緣層120以及一閘極121。閘絕緣層120覆蓋於溝槽11h的內壁面,以使閘極121與磊晶層11電性絕緣。位於元件區R1內的閘極結構12會連接於第一基體區111以及第一源極區113a。
As shown in FIG. 3, the
在本實施例中,第二基體區112會連接於最靠近靜電防護區R2的閘極結構12。
In this embodiment, the
靜電防護疊層P1設置於磊晶層11上,並位於靜電防護區R2,用以保護半導體元件M1免於靜電放電損害。靜電防護疊層P1包括一絕緣層13以及一靜電防護層14,且絕緣層13是位於靜電防護層14與磊晶層11之間,以使靜電防護層14與第二基體區112隔絕。據此,絕緣層13會直接連接於第二基體區112。
The electrostatic protection stack P1 is disposed on the
另外,由於靜電防護層14的其中一端點會與閘極121共電位,因此絕緣層13的厚度可根據施加於半導體元件M1的源閘極偏壓(Vgs)來決定。當源閘極偏壓(Vgs)越大時,絕緣層13的厚度
需要越厚。
In addition, since one end of the
靜電防護層14包括至少一第一重摻雜區140以及至少一第二重摻雜區141。在一實施例中,第一重摻雜區140與第一基體區111以及第二基體區112具有相同的導電型,例如都是P型摻雜區。第二重摻雜區141與第一源極區113a具有相同的導電型,例如都是N型摻雜區,但本發明並不限制。也可以做不同導電型加入額外製程步驟達到摻雜結果。
The
另外,靜電防護層14的橫向寬度與絕緣層13的橫向寬度大致相同。進一步而言,靜電防護層14的寬度與絕緣層13的寬度之間的差值小於0.5um。在一實施例中,靜電防護層14位於第二基體區112上方,且靜電防護層14完全重疊於第二基體區112範圍內。
In addition, the lateral width of the static
值得說明的是,本發明實施例的靜電防護層14的位於所述第二基體區上方,且靜電防護層完全重疊於所述第二基體區範圍內,相較於現有的半導體功率元件,本發明實施例的靜電防護疊層P1的底部不會直接連接漂移區110,而只會連接第二基體區112。因此,在靜電防護區R2內,第二基體區112與漂移區110之間所形成的交界面大致沿著平行表面11s的方向延伸。
It is worth noting that the static
由於在本發明所提供的半導體元件M1中,靜電防護疊層P1只連接第二基體區112,因此當半導體元件M1運作時,在第二基體區112與漂移區110的交界面的電場強度較均勻,從而使本發明實施例的半導體元件M1具有較高的耐壓。據此,相較於現有的半導體功率元件,本發明實施例的半導體元件M1除了具有靜電放電防護能力,還具有一定的耐壓能力。
Since in the semiconductor device M1 provided by the present invention, the static electricity protection stack P1 is only connected to the
請參照圖6,顯示本發明另一實施例的半導體元件的局部剖面示意圖。本實施例與圖3的實施例相同的元件具有相同的標號,且相同的部分不再贅述。 Please refer to FIG. 6, which shows a schematic partial cross-sectional view of a semiconductor device according to another embodiment of the present invention. Elements in this embodiment that are the same as those in the embodiment of FIG. 3 have the same reference numerals, and the same parts are not described again.
本實施例與圖3的實施例之間的差異在於,本實施例的半導
體元件M2中,閘極結構12為平面式閘極結構。也就是說,閘極結構12是設置在磊晶層11的表面11s上。另外,在元件區R1內,磊晶層11包括多個彼此分離的第一基體區111,且每一個第一源極區113a分別被對應的第一基體區111圍繞。
The difference between this embodiment and the embodiment of FIG. 3 is that the semiconductor of this embodiment
In the body element M2, the
另外,在本實施例中,第二基體區112會連接至最靠近靜電防護區R2的閘極結構12。具體而言,第二基體區112會連接到閘極結構12的閘絕緣層120。
In addition, in this embodiment, the
本發明實施例的製造方法也可用來形成半導體元件M2。具體而言,可在形成第一基體區111與第二基體區112之後,再於元件區R1內,形成閘極結構12於磊晶層11的表面11s上。
The manufacturing method of the embodiment of the present invention can also be used to form the semiconductor element M2. Specifically, after forming the
據此,在本發明的半導體元件的製造方法中,只要在靜電防護疊層P1下方可形成與其完全重疊的第二基體區112,步驟的順序皆可根據半導體元件本身的結構或是製程需求來調整。
Accordingly, in the manufacturing method of the semiconductor device of the present invention, as long as the
綜合上述,本發明的有益效果在於本發明技術方案所提供的半導體元件及其製造方法,其通過“形成靜電防護疊層P1之前,先在磊晶層11內形成位於靜電防護區R2的第二基體區112”以及“靜電防護層完全重疊於所述第二基體區範圍內”的技術手段,可以使具有靜電防護疊層P1的半導體元件符合靜電放電防護標準,又可具有較高的耐壓。
Based on the above, the beneficial effect of the present invention lies in the semiconductor device and the manufacturing method provided by the technical solution of the present invention. The second method is to form the second layer located in the electrostatic protection region R2 in the
另外,本發明實施例的半導體元件製造方法中,在靜電防護區R2形成靜電防護疊層P1的步驟可以與在元件R1形成電晶體結構的步驟整合,進而降低製造成本。 In addition, in the semiconductor device manufacturing method of the embodiment of the present invention, the step of forming the ESD protection stack P1 in the ESD protection region R2 can be integrated with the step of forming the transistor structure in the device R1, thereby reducing the manufacturing cost.
以上所公開的內容僅為本發明的優選可行實施例,並非因此侷限本發明的申請專利範圍,所以凡是運用本發明說明書及附圖內容所做的等效技術變化,均包含於本發明的申請專利範圍內。 The content disclosed above is only the preferred and feasible embodiments of the present invention, and does not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the content of the description and drawings of the present invention are included in the application of the present invention. Within the scope of the patent.
S100~S130‧‧‧流程步驟 S100~S130‧‧‧Process steps
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TWI531042B (en) * | 2013-03-01 | 2016-04-21 | 旺宏電子股份有限公司 | Semiconductor element and manufacturing method and operating method of the same |
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2018
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