TW202024649A - Circuit and method for measuring signal period - Google Patents

Circuit and method for measuring signal period Download PDF

Info

Publication number
TW202024649A
TW202024649A TW107147109A TW107147109A TW202024649A TW 202024649 A TW202024649 A TW 202024649A TW 107147109 A TW107147109 A TW 107147109A TW 107147109 A TW107147109 A TW 107147109A TW 202024649 A TW202024649 A TW 202024649A
Authority
TW
Taiwan
Prior art keywords
clock
signal
period
sampling
value
Prior art date
Application number
TW107147109A
Other languages
Chinese (zh)
Other versions
TWI668453B (en
Inventor
朱慶華
張正賢
黃豐猛
Original Assignee
致茂電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 致茂電子股份有限公司 filed Critical 致茂電子股份有限公司
Priority to TW107147109A priority Critical patent/TWI668453B/en
Priority to CN201910730102.1A priority patent/CN111371453A/en
Application granted granted Critical
Publication of TWI668453B publication Critical patent/TWI668453B/en
Publication of TW202024649A publication Critical patent/TW202024649A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Landscapes

  • Manipulation Of Pulses (AREA)
  • Measuring Frequencies, Analyzing Spectra (AREA)
  • Measurement Of Unknown Time Intervals (AREA)

Abstract

A circuit and a method for measuring signal period is disclosed. The circuit for measuring signal period comprises a clock counting module, a waveform generating module, a signal sampling module, and a period recording module. The clock counting module generates a clock count in every period of a first clock signal. The waveform generating module generates M periodical waveforms according to the first clock signal, and the M periodical waveforms relate to M phases of the first clock signal. The signal sampling module, coupled to the waveform generating module, samples an input signal according to the M periodical waveforms, and generates a phase count. The period recording module, coupled to the clock counting module and the signal sampling module, records the current clock count and the corresponding phase count. Wherein M is a natural number larger than 1.

Description

信號週期測量電路與方法Signal period measurement circuit and method

本發明係關於一種信號週期測量電路與方法，特別是關於一種將時脈分成不同相位，再分別進行信號週期測量的電路與方法。The present invention relates to a signal period measurement circuit and method, in particular to a circuit and method for dividing the clock into different phases and then separately measuring the signal period.

傳統的測試裝置要測量週期性的輸入信號時，只能藉由系統時脈(system clock)的正緣去抓取輸入信號，從而藉由標記抓到輸入信號的時間點，估計輸入信號的週期長短。然而，若是系統時脈頻率不高，常常有解析度不足的問題，無法正確估計輸入信號的週期長短。舉例來說，請參考圖1，圖1係繪示傳統的輸入信號與系統時脈的示意圖。如圖1所示，系統時脈clk於第1個週期抓到高位準的輸入信號S_in後，系統時脈clk於第10個週期再次抓到高位準的輸入信號S_in，則可以估計輸入信號的長度是9個系統時脈週期。如果某一個系統時脈的週期是5ns，輸入信號的長度也就是45ns。When the traditional test device wants to measure the periodic input signal, it can only capture the input signal by the positive edge of the system clock, so as to estimate the period of the input signal by marking the time point when the input signal is captured length. However, if the system clock frequency is not high, there is often a problem of insufficient resolution, and the period length of the input signal cannot be accurately estimated. For example, please refer to FIG. 1, which shows a schematic diagram of a traditional input signal and system clock. As shown in Figure 1, after the system clock clk catches the high-level input signal S_in in the first cycle, the system clock clk catches the high-level input signal S_in again in the tenth cycle, and then the input signal can be estimated The length is 9 system clock cycles. If the period of a certain system clock is 5ns, the length of the input signal is 45ns.

然而，從圖1可以看出，實際上輸入信號的長度更接近於8個系統時脈週期，誤差可以達到一個系統時脈。若輸入信號的週期更短，那麼顯然測量出來的週期誤差相對更大。因此，業界需要一種解析度更高的信號週期測量電路與方法。However, it can be seen from Figure 1 that the length of the input signal is actually closer to 8 system clock cycles, and the error can reach one system clock. If the period of the input signal is shorter, then obviously the measured period error is relatively larger. Therefore, the industry needs a signal period measurement circuit and method with higher resolution.

本發明提供了一種信號週期測量電路，可以將時脈分為多個不同相位的週期波形，並依據所述多個週期波形測量輸入信號的週期，從而可以有更高的解析度。The present invention provides a signal period measuring circuit, which can divide the clock into a plurality of periodic waveforms with different phases, and measure the period of an input signal according to the plurality of periodic waveforms, thereby having a higher resolution.

本發明提供一種信號週期測量電路，包含時脈計算模組、波形產生模組、信號取樣模組以及週期記錄模組。時脈計算模組於第一時脈的每一個週期產生時脈計數值。波形產生模組用以由第一時脈的每一個週期產生M個週期波形，所述M個週期波形對應第一時脈的M個相位。信號取樣模組電性連接波形產生模組，用以依據所述M個週期波形取樣輸入信號，以產生相位取樣值。週期記錄模組電性連接時脈計算模組與信號取樣模組，用以記錄目前的時脈計數值與對應的相位取樣值。其中M為大於1的自然數。The invention provides a signal period measurement circuit, which includes a clock calculation module, a waveform generation module, a signal sampling module, and a period recording module. The clock calculation module generates a clock count value in each cycle of the first clock. The waveform generating module is used for generating M periodic waveforms from each period of the first clock, and the M periodic waveforms correspond to the M phases of the first clock. The signal sampling module is electrically connected to the waveform generation module for sampling the input signal according to the M periodic waveforms to generate phase sampling values. The period recording module is electrically connected to the clock calculation module and the signal sampling module for recording the current clock count value and the corresponding phase sampling value. Where M is a natural number greater than 1.

於一些實施例中，波形產生模組可以依序延遲第一時脈以產生所述M個週期波形，其中第i個週期波形的正緣和第i+1個週期波形的正緣有一個時間間隔，i為自然數且i小於M。此外，相位取樣值可以對應所述M個週期波形分別取樣輸入信號的取樣結果。另外，相位取樣值可以具有M個位元，M個位元依序對應第一時脈的M個相位，相位取樣值的第j個位元可以對應第j個週期波形取樣輸入信號的取樣結果，j為自然數且j不大於M。In some embodiments, the waveform generation module may sequentially delay the first clock to generate the M periodic waveforms, where the positive edge of the i-th periodic waveform and the positive edge of the i+1th periodic waveform have a time Interval, i is a natural number and i is less than M. In addition, the phase sampling value may correspond to the sampling results of the input signal respectively sampling the M periodic waveforms. In addition, the phase sample value can have M bits, and the M bits correspond to the M phases of the first clock in sequence, and the jth bit of the phase sample value can correspond to the sampling result of the jth periodic waveform sampling input signal. , J is a natural number and j is not greater than M.

於一些實施例中，信號取樣模組更可以判斷相位取樣值於第一時脈的不同週期是否有變化，當信號取樣模組判斷相位取樣值有變化時，週期記錄模組記錄目前的時脈計數值與對應的相位取樣值。此外，週期記錄模組包含記憶體，記憶體用以儲存目前的時脈計數值與對應的相位取樣值。當信號取樣模組判斷相位取樣值沒有變化時，週期記錄模組不記錄目前的時脈計數值與對應的相位取樣值。In some embodiments, the signal sampling module can further determine whether the phase sampling value changes in different periods of the first clock. When the signal sampling module determines that the phase sampling value has changed, the period recording module records the current clock. The count value and the corresponding phase sampling value. In addition, the period recording module includes a memory, which is used to store the current clock count value and the corresponding phase sampling value. When the signal sampling module determines that the phase sampling value has not changed, the period recording module does not record the current clock count value and the corresponding phase sampling value.

本發明提供了一種信號週期測量方法，可以將時脈分為多個不同相位的週期波形，並依據所述多個週期波形測量輸入信號的週期，從而可以有更高的解析度。The present invention provides a signal period measurement method, which can divide the clock into a plurality of periodic waveforms with different phases, and measure the period of an input signal according to the plurality of periodic waveforms, so that a higher resolution can be achieved.

本發明提供一種信號週期測量方法，包含下列步驟。於第一時脈的每一個週期產生時脈計數值。由第一時脈的每一個週期產生M個週期波形，所述M個週期波形對應第一時脈的M個相位。依據所述M個週期波形取樣輸入信號，以產生相位取樣值。記錄目前的時脈計數值與對應的相位取樣值。其中M為大於1的自然數。The present invention provides a method for measuring signal period, which includes the following steps. The clock count value is generated every cycle of the first clock. Each cycle of the first clock generates M periodic waveforms, and the M periodic waveforms correspond to M phases of the first clock. The input signal is sampled according to the M periodic waveforms to generate phase samples. Record the current clock count value and the corresponding phase sampling value. Where M is a natural number greater than 1.

綜上所述，本發明提供的信號週期測量電路與方法，可以將時脈分為多個不同相位的週期波形，並利用每個週期波形取樣輸入信號，從而取樣次數更多且取樣間隔可以更加地縮短，從而可以更準確、更高解析度地判斷輸入信號的週期。In summary, the signal cycle measurement circuit and method provided by the present invention can divide the clock into multiple periodic waveforms with different phases, and use each periodic waveform to sample the input signal, so that the number of samples is greater and the sampling interval can be increased. The ground is shortened, so that the period of the input signal can be judged more accurately and with higher resolution.

下文將進一步揭露本發明之特徵、目的及功能。然而，以下所述者，僅為本發明之實施例，當不能以之限制本發明之範圍，即但凡依本發明申請專利範圍所作之均等變化及修飾，仍將不失為本發明之要意所在，亦不脫離本發明之精神和範圍，故應將視為本發明的進一步實施態樣。The features, objectives and functions of the present invention will be further disclosed below. However, the following are only examples of the present invention, and should not be used to limit the scope of the present invention, that is, all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention will still be the essence of the present invention. Without departing from the spirit and scope of the present invention, it should be regarded as a further embodiment of the present invention.

請參閱圖2，圖2係繪示依據本發明一實施例的信號週期測量電路的功能方塊圖。如圖2所示，本實施例揭露了信號週期測量電路1用來測量輸入信號S_in的週期，信號週期測量電路1包含時脈計算模組10、波形產生模組12、信號取樣模組14以及週期記錄模組16。實務上，信號週期測量電路1可以用來標記輸入信號S_in的信號開始時間點與信號結束時間點，並將所述信號開始時間點與信號結束時間點記錄起來，再交由其他的測試裝置換算出週期。換句話說，信號週期測量電路1可以組裝在其他的測試裝置中，或者外接到其他的測試裝置。當然，本實施例並不以此為限，例如，信號週期測量電路1也可以自己換算出輸入信號S_in的週期。以下從各個模組分別說明信號週期測量電路1的整體功能。Please refer to FIG. 2. FIG. 2 is a functional block diagram of a signal period measurement circuit according to an embodiment of the present invention. As shown in FIG. 2, this embodiment discloses that the signal period measurement circuit 1 is used to measure the period of the input signal S_in. The signal period measurement circuit 1 includes a clock calculation module 10, a waveform generation module 12, a signal sampling module 14, and Cycle recording module 16. In practice, the signal period measuring circuit 1 can be used to mark the signal start time point and signal end time point of the input signal S_in, and record the signal start time point and signal end time point, and then transfer it to other test devices for conversion Out of the cycle. In other words, the signal period measurement circuit 1 can be assembled in other test devices or connected to other test devices. Of course, this embodiment is not limited to this. For example, the signal period measuring circuit 1 can also convert the period of the input signal S_in by itself. The overall function of the signal period measurement circuit 1 is described below from each module.

時脈計算模組10於第一時脈CLK的每一個週期產生時脈計數值。於一個例子中，第一時脈CLK可以是系統時脈(system clock)、基頻時脈或者任一指定的時脈，本實施例不加以限制。此外，時脈計算模組10接收到第一時脈CLK後，可以受第一時脈CLK的正緣觸發，而計數第一時脈CLK。於所屬技術領域具有通常知識者，應當可以明白正緣觸發或負緣觸發都可以達到同樣的效果，為了方便說明，以下實施例採用正緣觸發說明。為了方便說明，請一併參閱圖2與圖3，圖3係繪示依據本發明一實施例於取樣輸入信號的示意圖。如圖所示，時脈計算模組10產生的時脈計數值可以標示為CLK_count，初始值可以是任一自然數N。The clock calculation module 10 generates a clock count value in each cycle of the first clock CLK. In an example, the first clock CLK can be a system clock, a base frequency clock, or any designated clock, which is not limited in this embodiment. In addition, after the clock calculation module 10 receives the first clock CLK, it can be triggered by the positive edge of the first clock CLK to count the first clock CLK. Those with ordinary knowledge in the technical field should be able to understand that both positive-edge trigger and negative-edge trigger can achieve the same effect. For the convenience of description, the following embodiment uses positive-edge trigger to illustrate. For the convenience of description, please refer to FIG. 2 and FIG. 3 together. FIG. 3 is a schematic diagram of sampling an input signal according to an embodiment of the present invention. As shown in the figure, the clock count value generated by the clock calculation module 10 can be marked as CLK_count, and the initial value can be any natural number N.

於一個例子中，時脈計算模組10計數第一時脈CLK時，可以累加於時脈計數值CLK_count，累加的數值可以是1或其他固定值，本實施例在此不加以限制。換句話說，在圖3繪示的例子中，時脈計算模組10一開始(例如第1個週期)可以傳送時脈計數值CLK_count為N給週期記錄模組16，於第一時脈CLK的下一個週期(例如第2個週期)時，可以傳送時脈計數值CLK_count為N+1給週期記錄模組16，以此類推。In an example, when the clock calculation module 10 counts the first clock CLK, it can be accumulated to the clock count value CLK_count, and the accumulated value can be 1 or other fixed values, which is not limited in this embodiment. In other words, in the example shown in FIG. 3, the clock calculation module 10 can transmit a clock count value CLK_count of N to the period recording module 16 at the beginning (for example, in the first cycle), and the clock count module 16 is at the first clock CLK In the next cycle (for example, the second cycle), the clock count value CLK_count of N+1 can be sent to the cycle recording module 16, and so on.

波形產生模組12用以由第一時脈CLK的每一個週期產生M個週期波形，所述M個週期波形對應第一時脈的M個相位。在圖3繪示的例子中，波形產生模組12可以依據第一時脈CLK，產生4個週期波形CLK_1、CLK_2、CLK_3、CLK_4，每一個週期波形的相位相差90度。於一個例子中，波形產生模組12可以包含鎖相迴路(phase-locked loop，PLL)，利用鎖相迴路延遲第一時脈CLK，以產生多個不同相位的週期波形。本實施例雖然以波形產生模組12產生4個週期波形為例，但不以此為限，例如波形產生模組12也可以產生8個或16個週期波形。The waveform generating module 12 is used for generating M periodic waveforms from each period of the first clock CLK, and the M periodic waveforms correspond to the M phases of the first clock. In the example shown in FIG. 3, the waveform generating module 12 can generate 4 periodic waveforms CLK_1, CLK_2, CLK_3, and CLK_4 according to the first clock CLK, and the phase of each periodic waveform is different by 90 degrees. In one example, the waveform generation module 12 may include a phase-locked loop (PLL), which uses the phase-locked loop to delay the first clock CLK to generate multiple periodic waveforms with different phases. Although this embodiment takes the waveform generation module 12 to generate 4 periodic waveforms as an example, it is not limited to this. For example, the waveform generation module 12 can also generate 8 or 16 periodic waveforms.

信號取樣模組14電性連接波形產生模組12，用以依據所述M個週期波形取樣輸入信號S_in，以產生相位取樣值。於一個例子中，信號取樣模組14可以利用週期波形的正緣取樣輸入信號S_in。以圖3繪示的例子來說，在第一時脈CLK的第1個週期(時脈計數值CLK_count為N到N+1之間)時，信號取樣模組14可以判斷週期波形CLK_1沒有取樣到輸入信號S_in，因為在週期波形CLK_1正緣時，輸入信號S_in仍為低位準。而信號取樣模組14可以判斷週期波形CLK_2、CLK_3、CLK_4有取樣到輸入信號S_in，因為在週期波形CLK_2、CLK_3、CLK_4正緣時，輸入信號S_in為高位準。據此，信號取樣模組14可以將相位取樣值phase_count記錄為0111，表示輸入信號S_in是從第2個相位開始。在此，本實施例示範了相位取樣值phase_count的位元數可以對應週期波形的數目，且經由位元的順序可以了解輸入信號S_in的信號開始時間點可以對應到哪一個相位(哪一個週期波形)。The signal sampling module 14 is electrically connected to the waveform generating module 12 for sampling the input signal S_in according to the M periodic waveforms to generate phase sampling values. In one example, the signal sampling module 14 can use the positive edge of the periodic waveform to sample the input signal S_in. Taking the example shown in FIG. 3 for example, in the first cycle of the first clock CLK (the clock count value CLK_count is between N and N+1), the signal sampling module 14 can determine that the periodic waveform CLK_1 is not sampled To the input signal S_in, because at the positive edge of the periodic waveform CLK_1, the input signal S_in is still at a low level. The signal sampling module 14 can determine that the periodic waveforms CLK_2, CLK_3, and CLK_4 have sampled the input signal S_in, because the input signal S_in is at a high level when the periodic waveforms CLK_2, CLK_3, CLK_4 are positive edges. Accordingly, the signal sampling module 14 can record the phase sampling value phase_count as 0111, indicating that the input signal S_in starts from the second phase. Here, this embodiment demonstrates that the number of bits in the phase sampling value phase_count can correspond to the number of periodic waveforms, and the order of the bits can be used to understand which phase (which periodic waveform) the signal start time point of the input signal S_in corresponds to. ).

同樣地，在第一時脈CLK的第10個週期(時脈計數值CLK_count為N+9到N+10之間)時，信號取樣模組14可以判斷週期波形CLK_1、CLK_2、CLK_3沒有取樣到輸入信號S_in，因為在週期波形CLK_1、CLK_2、CLK_3正緣時，輸入信號S_in仍為低位準。而信號取樣模組14可以判斷週期波形CLK_4有取樣到輸入信號S_in，因為在週期波形CLK_4正緣時，輸入信號S_in為高位準。據此，信號取樣模組14可以將相位取樣值phase_count記錄為0001，表示下一週期的輸入信號S_in是從第4個相位開始。由於輸入信號S_in是連續的信號，藉由測量下一週期的輸入信號S_in信號開始時間點，即等於測知前一週期的輸入信號S_in的信號結束時間點。於一個例子中，信號取樣模組14可以在4個週期波形CLK_1、CLK_2、CLK_3、CLK_4全部取樣完輸入信號S_in之後，再產生相位取樣值phase_count，並且在第一時脈CLK的下一個週期輸出給週期記錄模組16。Similarly, in the 10th cycle of the first clock CLK (clock count value CLK_count is between N+9 and N+10), the signal sampling module 14 can determine that the periodic waveforms CLK_1, CLK_2, and CLK_3 are not sampled. The input signal S_in is because when the periodic waveforms CLK_1, CLK_2, CLK_3 have positive edges, the input signal S_in is still at a low level. The signal sampling module 14 can determine that the periodic waveform CLK_4 has sampled the input signal S_in, because when the periodic waveform CLK_4 has a positive edge, the input signal S_in is at a high level. Accordingly, the signal sampling module 14 can record the phase sampling value phase_count as 0001, which indicates that the input signal S_in of the next cycle starts from the fourth phase. Since the input signal S_in is a continuous signal, by measuring the signal start time point of the input signal S_in of the next cycle, it is equal to the signal end time point of the input signal S_in of the previous cycle. In one example, the signal sampling module 14 may generate the phase sampling value phase_count after all the input signals S_in have been sampled in the 4 cycle waveforms CLK_1, CLK_2, CLK_3, and CLK_4, and output it in the next cycle of the first clock CLK给 cycle record module 16.

於一個例子中，信號取樣模組14可以判斷何種相位取樣值有物理上的意義。舉例來說，如果前一個相位取樣值phase_count記錄為0000，目前的相位取樣值phase_count仍記錄為0000，表示輸入信號S_in一直位於低準位，從而信號取樣模組14記錄這樣的相位取樣值對測量週期沒有幫助。同樣地，如果前一個相位取樣值phase_count記錄為1111，目前的相位取樣值phase_count同樣記錄為1111，表示輸入信號S_in都位於高準位，從而信號取樣模組14記錄這樣的相位取樣值對測量週期也沒有幫助。但是，如果前一個相位取樣值phase_count記錄為0000，目前的相位取樣值phase_count同樣記錄為0111，信號取樣模組14在相位取樣值phase_count上發現變化，則信號取樣模組14可以判斷目前的相位取樣值phase_count有意義，進而可以將相位取樣值phase_count輸出給週期記錄模組16。反之，信號取樣模組14若判斷目前的相位取樣值phase_count沒有意義，則可以不將相位取樣值phase_count輸出給週期記錄模組16。In one example, the signal sampling module 14 can determine which phase sampling value has a physical meaning. For example, if the previous phase sampling value phase_count is recorded as 0000, the current phase sampling value phase_count is still recorded as 0000, which means that the input signal S_in is always at a low level, so that the signal sampling module 14 records such phase sampling value pair measurement Cycle does not help. Similarly, if the previous phase sampling value phase_count is recorded as 1111, the current phase sampling value phase_count is also recorded as 1111, indicating that the input signal S_in is at a high level, so the signal sampling module 14 records such phase sampling value versus the measurement period It didn't help either. However, if the previous phase sampling value phase_count is recorded as 0000, the current phase sampling value phase_count is also recorded as 0111, and the signal sampling module 14 finds a change in the phase sampling value phase_count, the signal sampling module 14 can determine the current phase sampling The value phase_count is meaningful, and the phase sampling value phase_count can be output to the period recording module 16. Conversely, if the signal sampling module 14 determines that the current phase sampling value phase_count is meaningless, it may not output the phase sampling value phase_count to the period recording module 16.

週期記錄模組16電性連接時脈計算模組10與信號取樣模組14，用以記錄目前的時脈計數值CLK_count與對應的相位取樣值phase_count。以圖3繪示的例子來說，雖然輸入信號S_in的正緣在第一時脈CLK的第1個週期內，但是於所屬技術領域具有通常知識者可以明白的是，電路元件無法在同一個週期內既要取樣又要立刻將取樣結果批次送出，因此實際上週期記錄模組16還是要等到第一時脈CLK的下一個週期(第2個週期)才可能收到來自信號取樣模組14的資料。據此，週期記錄模組16會記錄到輸入信號S_in的信號開始時間點，對應到的時脈計數值CLK_count為N+1且相位取樣值phase_count為0111。The period recording module 16 is electrically connected to the clock calculation module 10 and the signal sampling module 14 for recording the current clock count value CLK_count and the corresponding phase sampling value phase_count. Take the example shown in FIG. 3, although the positive edge of the input signal S_in is in the first cycle of the first clock CLK, those skilled in the art can understand that the circuit elements cannot be in the same During the cycle, it is necessary to sample and immediately send the sampling results in batches. Therefore, in fact, the cycle recording module 16 still has to wait until the next cycle (the second cycle) of the first clock CLK to receive the signal from the sampling module. 14 information. Accordingly, the period recording module 16 records the signal start time point of the input signal S_in, the corresponding clock count value CLK_count is N+1, and the phase sampling value phase_count is 0111.

同理，雖然輸入信號S_in的次一個正緣在第一時脈CLK的第10個週期內，實際上週期記錄模組16還是要等到第一時脈CLK的下一個週期(第11個週期)才可能收到來自信號取樣模組14的資料。據此，週期記錄模組16會記錄到輸入信號S_in的信號結束時間點，對應到的時脈計數值CLK_count為N+10且相位取樣值phase_count為0001。換句話說，輸入信號S_in的一個週期在時脈計數值CLK_count相差了9個週期，且相位取樣值phase_count相差了2個相位。假設當第一時脈CLK的1個週期對應4ns時，4個相位的每個相位恰好間隔1ns。以圖3繪示的例子來說，第一時脈CLK的9個週期可換算成36ns，且第一時脈CLK的2個相位可以換算成2ns，因此可以藉由時脈計數值CLK_count與相位取樣值phase_count，很快地推算出輸入信號S_in的週期是38ns。In the same way, although the next positive edge of the input signal S_in is in the 10th cycle of the first clock CLK, in fact the cycle recording module 16 still has to wait until the next cycle (the 11th cycle) of the first clock CLK It is possible to receive data from the signal sampling module 14. Accordingly, the period recording module 16 will record the signal end time point of the input signal S_in, the corresponding clock count value CLK_count is N+10, and the phase sampling value phase_count is 0001. In other words, one period of the input signal S_in differs from the clock count value CLK_count by 9 periods, and the phase sampling value phase_count differs by 2 phases. Assume that when 1 cycle of the first clock CLK corresponds to 4 ns, each of the 4 phases is exactly 1 ns apart. Take the example shown in Figure 3, the 9 cycles of the first clock CLK can be converted into 36ns, and the 2 phases of the first clock CLK can be converted into 2ns, so the clock count value CLK_count and the phase Sampling value phase_count quickly calculates that the period of the input signal S_in is 38ns.

在此，於所屬技術領域具有通常知識者可以發現，週期記錄模組16何時取得相位取樣值phase_count並不影響推算輸入信號S_in的週期。舉例來說，縱使週期記錄模組16等到第一時脈CLK的下5個週期才收到來自信號取樣模組14的資料，則輸入信號S_in的信號開始時間點，改成對應到的時脈計數值CLK_count為N+5且相位取樣值phase_count為0111。同樣的，輸入信號S_in的信號結束時間點，改成對應到的時脈計數值CLK_count為N+14且相位取樣值phase_count為0001。由於延遲誤差會被減除，仍然可以計算出輸入信號S_in的一個週期在時脈計數值CLK_count相差了9個週期，且相位取樣值phase_count相差了2個相位。據此，同樣可以推算出輸入信號S_in的週期是38ns，不影響輸入信號S_in的週期測量的結果。Here, those skilled in the art can find that when the period recording module 16 obtains the phase sampling value phase_count does not affect the estimated period of the input signal S_in. For example, even if the cycle recording module 16 waits until the next 5 cycles of the first clock CLK to receive the data from the signal sampling module 14, the signal start time point of the input signal S_in is changed to the corresponding clock The count value CLK_count is N+5 and the phase sampling value phase_count is 0111. Similarly, the signal end time point of the input signal S_in is changed to the corresponding clock count value CLK_count as N+14 and the phase sampling value phase_count as 0001. Since the delay error will be subtracted, it can still be calculated that one cycle of the input signal S_in differs from the clock count value CLK_count by 9 cycles, and the phase sampling value phase_count differs by 2 phases. Based on this, it can also be calculated that the period of the input signal S_in is 38 ns, which does not affect the result of the period measurement of the input signal S_in.

值得一提的是，雖然前述信號取樣模組14是取樣兩次輸入信號S_in的正緣，從而取得輸入信號S_in一個完整週期的開始與結束時間點。但是，本實施例不以此為限，例如信號取樣模組14也可以取樣輸入信號S_in的正緣與接下來的負緣，從而取得輸入信號S_in一個半週期的開始與結束時間點。如此，仍然可以經由半週期推算出完整週期的時間長度。It is worth mentioning that although the aforementioned signal sampling module 14 samples the positive edge of the input signal S_in twice to obtain the start and end time points of a complete cycle of the input signal S_in. However, this embodiment is not limited to this. For example, the signal sampling module 14 may also sample the positive edge and the following negative edge of the input signal S_in to obtain the start and end time points of one and a half cycles of the input signal S_in. In this way, the time length of the complete cycle can still be calculated from the half cycle.

前述的例子中，週期記錄模組16除了記錄時脈計數值CLK_count與相位取樣值phase_count之外，也可以進一步換算出輸入信號S_in的週期。當然，於另一個例子中，週期記錄模組16可以僅用來標記輸入信號S_in的信號開始時間點與信號結束時間點，並將時脈計數值CLK_count與相位取樣值phase_count存放在一個記憶體中，再交由其他的測試裝置換算出週期。舉例來說，信號週期測量電路1可以是一種現場可程式化邏輯閘陣列(field programmable gate array，FPGA)，而週期記錄模組16的記憶體可以是FPGA中的區塊隨機存取記憶體(block RAM)。In the foregoing example, in addition to recording the clock count value CLK_count and the phase sampling value phase_count, the period recording module 16 can also further convert the period of the input signal S_in. Of course, in another example, the period recording module 16 may only be used to mark the signal start time point and the signal end time point of the input signal S_in, and store the clock count value CLK_count and the phase sampling value phase_count in a memory , And then transfer to other test devices to calculate the cycle. For example, the signal period measurement circuit 1 may be a field programmable gate array (FPGA), and the memory of the period recording module 16 may be a block random access memory in the FPGA ( block RAM).

為了說明本案的信號週期測量方法，請一併參閱圖2、圖3與圖4，圖4係繪示依據本發明一實施例的信號週期測量方法的步驟流程圖。如圖所示，於步驟S20中，時脈計算模組10於第一時脈CLK的每一個週期產生時脈計數值CLK_count。於步驟S22中，波形產生模組12用以由第一時脈CLK的每一個週期產生M個週期波形，所述M個週期波形對應第一時脈的M個相位。於步驟S24中，信號取樣模組14電性連接波形產生模組12，用以依據所述M個週期波形取樣輸入信號S_in，以產生相位取樣值phase_count。於步驟S26中，週期記錄模組16電性連接時脈計算模組10與信號取樣模組14，用以記錄目前的時脈計數值CLK_count與對應的相位取樣值phase_count。由於本實施例的信號週期測量方法，於前述實施例都已經充分說明與支持，在此不予贅述。In order to explain the signal period measurement method in this case, please refer to FIG. 2, FIG. 3 and FIG. 4 together. FIG. 4 is a flowchart of the steps of the signal period measurement method according to an embodiment of the present invention. As shown in the figure, in step S20, the clock calculation module 10 generates a clock count value CLK_count in each cycle of the first clock CLK. In step S22, the waveform generating module 12 is used to generate M periodic waveforms from each cycle of the first clock CLK, and the M periodic waveforms correspond to the M phases of the first clock. In step S24, the signal sampling module 14 is electrically connected to the waveform generating module 12 for sampling the input signal S_in according to the M periodic waveforms to generate a phase sampling value phase_count. In step S26, the period recording module 16 is electrically connected to the clock calculation module 10 and the signal sampling module 14 for recording the current clock count value CLK_count and the corresponding phase sampling value phase_count. Since the signal period measurement method of this embodiment has been fully explained and supported in the foregoing embodiments, it will not be repeated here.

綜上所述，本發明提供的信號週期測量電路與方法，可以將時脈分為多個不同相位的週期波形，並利用每個週期波形取樣輸入信號，從而取樣次數更多且取樣間隔可以更加地縮短，從而可以更準確、更高解析度地判斷輸入信號的週期。In summary, the signal cycle measurement circuit and method provided by the present invention can divide the clock into multiple periodic waveforms with different phases, and use each periodic waveform to sample the input signal, so that the number of samples is greater and the sampling interval can be increased. The ground is shortened, so that the period of the input signal can be judged more accurately and with higher resolution.

1:信號週期測量電路10:時脈計算模組12:波形產生模組14:信號取樣模組16:週期記錄模組S20~S26:步驟流程clk:系統時脈CLK:第一時脈CLK_1~CLK_4:週期波形S_in:輸入信號CLK_count:時脈計數值Phase_count:相位取樣值1: Signal cycle measurement circuit 10: Clock calculation module 12: Waveform generation module 14: Signal sampling module 16: Period recording module S20~S26: Step flow clk: System clock CLK: First clock CLK_1~ CLK_4: Periodic waveform S_in: Input signal CLK_count: Clock count value Phase_count: Phase sampling value

圖1係繪示先前技術取樣輸入信號的示意圖。FIG. 1 is a schematic diagram of sampling input signals in the prior art.

圖2係繪示依據本發明一實施例的信號週期測量電路的功能方塊圖。FIG. 2 is a functional block diagram of a signal period measurement circuit according to an embodiment of the invention.

圖3係繪示依據本發明一實施例於取樣輸入信號的示意圖。FIG. 3 is a schematic diagram of sampling an input signal according to an embodiment of the invention.

圖4係繪示依據本發明一實施例的信號週期測量方法的步驟流程圖。FIG. 4 is a flowchart of the steps of a signal period measurement method according to an embodiment of the present invention.

1:信號週期測量電路 1: Signal period measurement circuit

10:時脈計算模組 10: Clock calculation module

12:波形產生模組 12: Waveform generation module

14:信號取樣模組 14: Signal sampling module

16:週期記錄模組 16: Periodic recording module

CLK:第一時脈 CLK: the first clock

S_in:輸入信號 S_in: input signal

Claims (15)

一種信號週期測量電路，包含： 一時脈計算模組，於一第一時脈的每一該週期產生一時脈計數值； 一波形產生模組，用以由該第一時脈的每一該週期產生M個週期波形，該M個週期波形對應該第一時脈的M個相位； 一信號取樣模組，電性連接該波形產生模組，用以依據該M個週期波形取樣一輸入信號，以產生一相位取樣值；以及 一週期記錄模組，電性連接該時脈計算模組與該信號取樣模組，用以記錄目前的該時脈計數值與對應的該相位取樣值； 其中M為大於1的自然數。A signal period measurement circuit, comprising: a clock calculation module for generating a clock count value in each period of a first clock; a waveform generating module for generating a clock count value from each period of the first clock Generate M periodic waveforms, the M periodic waveforms corresponding to the M phases of the first clock; a signal sampling module, electrically connected to the waveform generation module, to sample an input signal according to the M periodic waveforms, To generate a phase sampling value; and a periodic recording module, electrically connected to the clock calculation module and the signal sampling module, for recording the current clock count value and the corresponding phase sampling value; where M Is a natural number greater than 1. 如請求項1所述之信號週期測量電路，其中該波形產生模組依序延遲該第一時脈以產生該M個週期波形，其中第i個週期波形的正緣和第i+1個週期波形的正緣有一時間間隔，i為自然數且i小於M。The signal period measurement circuit according to claim 1, wherein the waveform generation module sequentially delays the first clock to generate the M period waveform, wherein the positive edge of the i-th period waveform and the i+1-th period The positive edge of the waveform has a time interval, i is a natural number and i is less than M. 如請求項1所述之信號週期測量電路，其中該相位取樣值對應該M個週期波形分別取樣該輸入信號的取樣結果。The signal period measurement circuit according to claim 1, wherein the phase sampling value corresponds to the sampling result of the input signal respectively sampling the M period waveforms. 如請求項3所述之信號週期測量電路，其中該相位取樣值具有M個位元，該M個位元依序對應該第一時脈的該M個相位。The signal period measurement circuit of claim 3, wherein the phase sample value has M bits, and the M bits correspond to the M phases of the first clock in sequence. 如請求項4所述之信號週期測量電路，其中該相位取樣值的第j個位元對應第j個週期波形取樣該輸入信號的取樣結果，j為自然數且j不大於M。The signal period measurement circuit according to claim 4, wherein the jth bit of the phase sample value corresponds to the sampling result of the jth periodic waveform sampling of the input signal, j is a natural number and j is not greater than M. 如請求項1所述之信號週期測量電路，其中該信號取樣模組更判斷該相位取樣值於該第一時脈的不同週期是否有變化，當該信號取樣模組判斷該相位取樣值有變化時，該週期記錄模組記錄目前的該時脈計數值與對應的該相位取樣值。The signal period measurement circuit according to claim 1, wherein the signal sampling module further determines whether the phase sampling value has changed in different periods of the first clock, and when the signal sampling module determines that the phase sampling value has changed At the time, the period recording module records the current clock count value and the corresponding phase sampling value. 如請求項6所述之信號週期測量電路，其中該週期記錄模組包含一記憶體，該記憶體用以儲存目前的該時脈計數值與對應的該相位取樣值。The signal period measurement circuit according to claim 6, wherein the period recording module includes a memory, and the memory is used to store the current clock count value and the corresponding phase sample value. 如請求項6所述之信號週期測量電路，其中當該信號取樣模組判斷該相位取樣值沒有變化時，該週期記錄模組不記錄目前的該時脈計數值與對應的該相位取樣值。The signal period measurement circuit of claim 6, wherein when the signal sampling module determines that the phase sample value has not changed, the period recording module does not record the current clock count value and the corresponding phase sample value. 一種信號週期測量方法，包含： 於一第一時脈的每一該週期產生一時脈計數值； 由該第一時脈的每一該週期產生M個週期波形，該M個週期波形對應該第一時脈的M個相位； 依據該M個週期波形取樣一輸入信號，以產生一相位取樣值；以及 記錄目前的該時脈計數值與對應的該相位取樣值； 其中M為大於1的自然數。A method for measuring signal period includes: generating a clock count value for each period of a first clock; generating M period waveforms for each period of the first clock, the M period waveforms corresponding to the first clock M phases of a clock; sampling an input signal according to the M periodic waveforms to generate a phase sampling value; and recording the current clock count value and the corresponding phase sampling value; where M is a natural value greater than 1. number. 如請求項9所述之信號週期測量方法，其中由該第一時脈的每一該週期產生M個週期波形的步驟中，更包含： 依序延遲該第一時脈以產生該M個週期波形； 其中第i個週期波形的正緣和第i+1個週期波形的正緣有一時間間隔，i為自然數且i小於M。The signal period measurement method according to claim 9, wherein the step of generating M period waveforms from each period of the first clock further comprises: sequentially delaying the first clock to generate the M periods Waveform; There is a time interval between the positive edge of the i-th periodic waveform and the positive edge of the i+1th periodic waveform, i is a natural number and i is less than M. 如請求項9所述之信號週期測量方法，其中該相位取樣值對應該M個週期波形分別取樣該輸入信號的取樣結果。The signal period measurement method according to claim 9, wherein the phase sampling value corresponds to the sampling result of the input signal respectively sampling the M period waveforms. 如請求項11所述之信號週期測量方法，其中該相位取樣值具有M個位元，該M個位元依序對應該第一時脈的該M個相位。The signal period measurement method of claim 11, wherein the phase sampling value has M bits, and the M bits correspond to the M phases of the first clock in sequence. 如請求項12所述之信號週期測量方法，其中該相位取樣值的第j個位元對應第j個週期波形取樣該輸入信號的取樣結果，j為自然數且j不大於M。The signal period measurement method of claim 12, wherein the j-th bit of the phase sample value corresponds to the sampling result of the j-th periodic waveform sample of the input signal, j is a natural number and j is not greater than M. 如請求項9所述之信號週期測量方法，其中於依據該M個週期波形取樣該輸入信號，以產生該相位取樣值的步驟中，更包含： 判斷該相位取樣值於該第一時脈的不同週期是否有變化； 當判斷該相位取樣值有變化時，記錄目前的該時脈計數值與對應的該相位取樣值。The signal period measurement method of claim 9, wherein in the step of sampling the input signal according to the M period waveforms to generate the phase sample value, the method further includes: determining that the phase sample value is at the first clock Whether there is a change in different periods; when it is judged that the phase sample value has changed, the current clock count value and the corresponding phase sample value are recorded. 如請求項14所述之信號週期測量方法，其中當判斷該相位取樣值沒有變化時，不記錄目前的該時脈計數值與對應的該相位取樣值。The signal period measurement method according to claim 14, wherein when it is determined that the phase sample value has not changed, the current clock count value and the corresponding phase sample value are not recorded.
TW107147109A 2018-12-26 2018-12-26 Circuit and method for measuring signal period TWI668453B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW107147109A TWI668453B (en) 2018-12-26 2018-12-26 Circuit and method for measuring signal period
CN201910730102.1A CN111371453A (en) 2018-12-26 2019-08-08 Signal period measuring circuit and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW107147109A TWI668453B (en) 2018-12-26 2018-12-26 Circuit and method for measuring signal period

Publications (2)

Publication Number Publication Date
TWI668453B TWI668453B (en) 2019-08-11
TW202024649A true TW202024649A (en) 2020-07-01

Family

ID=68316192

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107147109A TWI668453B (en) 2018-12-26 2018-12-26 Circuit and method for measuring signal period

Country Status (2)

Country Link
CN (1) CN111371453A (en)
TW (1) TWI668453B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113823245B (en) * 2021-09-08 2022-09-30 富奥汽车零部件股份有限公司 Display screen brightness control method, control device and readable storage medium

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06347569A (en) * 1993-06-07 1994-12-22 Hokuto Denko Kk Frequency multiplier circuit and pulse time interval measuring device
TW445722B (en) * 2000-04-07 2001-07-11 Via Tech Inc Glitch-free phase converting method of timing signal and circuit of the same
US6771103B2 (en) * 2001-03-14 2004-08-03 Denso Corporation Time measurement apparatus, distance measurement apparatus, and clock signal generating apparatus usable therein
JP2003317260A (en) * 2002-04-23 2003-11-07 Matsushita Electric Ind Co Ltd Optical disk drive
CN102334038B (en) * 2009-02-27 2013-11-06 古野电气株式会社 Phase determining device and frequency determining device
CN101599276A (en) * 2009-06-30 2009-12-09 中国科学院上海光学精密机械研究所 Optical disk jitter characteristic testing device and testing method thereof
US9541591B2 (en) * 2014-08-11 2017-01-10 Synopsys, Inc. Periodic signal measurement using statistical sampling

Also Published As

Publication number Publication date
CN111371453A (en) 2020-07-03
TWI668453B (en) 2019-08-11

Similar Documents

Publication Publication Date Title
KR101243627B1 (en) Time measurement using phase shifted periodic waveforms
CN109387776B (en) Method of measuring clock jitter, clock jitter measuring circuit, and semiconductor device
US20070071080A1 (en) Strobe technique for time stamping a digital signal
JP6792602B2 (en) High resolution time-digital converter
US9568889B1 (en) Time to digital converter with high resolution
JP2009510403A (en) Strobe technique for time stamping digital signals
US20140306689A1 (en) High resolution current pulse analog measurement
TW202024649A (en) Circuit and method for measuring signal period
CN103675383B (en) A kind of circuit measuring waveform
US20130015837A1 (en) On-chip signal waveform measurement circuit
CN110729988B (en) Circuit, output device, detection system and method for outputting clock jitter signal
JPH05209781A (en) Ultrasonic transmitter/receiver
JP2002006003A (en) All digital built-in self-inspection circuit for phase lock loop and inspecting method
JP2000035463A (en) Jitter measuring device and integrated circuit incorporating the device
TW200826476A (en) Phase difference detecting apparatus and method thereof
US11397197B2 (en) Voltage detection system and method
TWI514775B (en) Clock edge detection device and method
JPH0743406A (en) Pulse phase measuring apparatus
RU187313U1 (en) DIGITAL FREQUENCY METER FOR LOW POWER INTEGRAL CIRCUITS
CN107317581B (en) Time-to-digital converter with high resolution
Su et al. Just-enough strategy for accurate clock jitter measurement using a cyclic time-to-digital converter
WO2023226074A1 (en) Method and device for performance evaluation of sequential logic element
US20230006903A1 (en) Systems and methods for timing a signal
Machado et al. Designing Synchronizers for Nutt-TDCs
JPH01143978A (en) Delay time measuring circuit

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees