TW202023329A

TW202023329A - Embedded chip package, manufacturing method thereof and package on package structure

Info

Publication number: TW202023329A
Application number: TW107143794A
Authority: TW
Inventors: 林柏丞; 譚瑞敏; 簡俊賢; 陳建州
Original assignee: 欣興電子股份有限公司
Priority date: 2018-12-06
Filing date: 2018-12-06
Publication date: 2020-06-16
Also published as: TWI703902B

Abstract

A embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite the first surface, and a through hole penetrating the glass substrate. The conductive via penetrates the glass substrate. The chip is disposed within the through hole. The dielectric material layer is filled in the through hole and covers the chip. The build-up circuit structure is disposed on the circuit board. The build-up circuit structure is electrically connected to the conductive via. The lower surface of the chip is exposed outside the dielectric material layer.

Description

內埋式晶片封裝及其製作方法與疊層封裝結構Embedded chip package and its manufacturing method and laminated package structure

本發明是有關於一種晶片封裝及其製作方法與疊層封裝結構，且特別是有關於一種內埋式晶片封裝及其製作方法與疊層封裝結構。The present invention relates to a chip package, a manufacturing method thereof, and a stacked package structure, and more particularly to an embedded chip package, a manufacturing method thereof, and a stacked package structure.

目前的晶片封裝的方式皆需要先有一層封裝膠層來保護晶片，之後再繼續增層其他線路或是朝二維的方向做封裝。然後，此時的堆疊以及組裝往往會造成較大的翹曲，進而影響封裝的良率以及後續的可靠度。Current chip packaging methods require a layer of packaging glue to protect the chip, and then continue to build up other circuits or package in a two-dimensional direction. Then, stacking and assembly at this time often cause greater warpage, which in turn affects the package yield and subsequent reliability.

本發明提供一種內埋式晶片封裝，具有較佳的封裝良率及可靠度。The present invention provides an embedded chip package with better package yield and reliability.

本發明提供一種疊層封裝結構，具有可增加堆疊結構和線路的好處。The present invention provides a stacked package structure, which has the advantage of being able to increase the stacked structure and circuits.

本發明提供一種內埋式晶片封裝的製作方法，以製作上述的內埋式晶片封裝，可改善增層線路或封裝所產生的翹曲問題。The present invention provides a manufacturing method of an embedded chip package to fabricate the above-mentioned embedded chip package, which can improve the warpage caused by the build-up circuit or the package.

本發明的內埋式晶片封裝包括線路板、晶片、介電材料層以及增層線路結構。線路板包括玻璃基板以及至少一導電通孔。玻璃基板具有第一表面、與第一表面相對的第二表面以及貫穿玻璃基板的穿槽。導電通孔貫穿玻璃基板。晶片配置於穿槽內。介電材料層填充於穿槽內，且包覆晶片。增層線路結構配置於線路板上。增層線路結構與導電通孔電性連接。晶片的下表面暴露於介電材料層外。The embedded chip package of the present invention includes a circuit board, a chip, a dielectric material layer and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite to the first surface, and a through groove penetrating the glass substrate. The conductive via penetrates the glass substrate. The chip is arranged in the through groove. The dielectric material layer is filled in the through groove and covers the chip. The build-up circuit structure is arranged on the circuit board. The build-up circuit structure is electrically connected with the conductive via. The lower surface of the wafer is exposed outside the dielectric material layer.

在本發明的一實施例中，上述的晶片的下表面與玻璃基板的第二表面齊平。In an embodiment of the present invention, the lower surface of the above-mentioned wafer is flush with the second surface of the glass substrate.

在本發明的一實施例中，上述的增層線路結構包括第一線路層、第一介電層、第二線路層以及至少一第一導通孔。第一介電層覆蓋第一線路層。第二線路層與第一線路層分別位於第一介電層的相對兩側。第一導通孔貫穿第一介電層，以電性連接第一線路層與第二線路層。In an embodiment of the present invention, the above-mentioned build-up circuit structure includes a first circuit layer, a first dielectric layer, a second circuit layer, and at least one first via hole. The first dielectric layer covers the first circuit layer. The second circuit layer and the first circuit layer are respectively located on opposite sides of the first dielectric layer. The first via hole penetrates the first dielectric layer to electrically connect the first circuit layer and the second circuit layer.

在本發明的一實施例中，上述的增層線路結構配置於玻璃基板的第一表面。內埋式晶片封裝更包括圖案化導電層以及錫球或銅柱。圖案化導電層配置於玻璃基板的第二表面，以使增層線路結構與圖案化導電層分別位於玻璃基板的相對兩側。錫球或銅柱配置於圖案化導電層上，以使錫球或銅柱與線路板分別位於圖案化導電層的相對兩側。In an embodiment of the present invention, the above-mentioned build-up circuit structure is disposed on the first surface of the glass substrate. The embedded chip package further includes a patterned conductive layer and tin balls or copper pillars. The patterned conductive layer is disposed on the second surface of the glass substrate, so that the build-up circuit structure and the patterned conductive layer are respectively located on opposite sides of the glass substrate. The tin balls or copper pillars are arranged on the patterned conductive layer, so that the tin balls or copper pillars and the circuit board are respectively located on opposite sides of the patterned conductive layer.

在本發明的一實施例中，上述的晶片的下表面為主動表面。主動表面朝向圖案化導電層且與圖案化導電層電性連接。In an embodiment of the present invention, the lower surface of the aforementioned wafer is the active surface. The active surface faces the patterned conductive layer and is electrically connected to the patterned conductive layer.

在本發明的一實施例中，上述的增層線路結構透過導電通孔與圖案化導電層電性連接。In an embodiment of the present invention, the above-mentioned build-up circuit structure is electrically connected to the patterned conductive layer through the conductive via.

在本發明的一實施例中，上述的增層線路結構配置於玻璃基板的第二表面。內埋式晶片封裝更包括錫球或銅柱。錫球或銅柱配置於增層線路結構上，以使錫球或銅柱與線路板分別位於增層線路結構的相對兩側。In an embodiment of the present invention, the above-mentioned build-up circuit structure is disposed on the second surface of the glass substrate. The embedded chip package further includes solder balls or copper pillars. The solder balls or copper pillars are arranged on the build-up circuit structure so that the solder balls or copper pillars and the circuit board are respectively located on opposite sides of the build-up circuit structure.

在本發明的一實施例中，上述的晶片的下表面為主動表面。主動表面朝向增層線路結構且與增層線路結構電性連接。In an embodiment of the present invention, the lower surface of the aforementioned wafer is the active surface. The active surface faces the build-up circuit structure and is electrically connected to the build-up circuit structure.

在本發明的一實施例中，上述的穿槽連接玻璃基板的第一表面與第二表面。In an embodiment of the present invention, the above-mentioned through groove connects the first surface and the second surface of the glass substrate.

本發明的疊層封裝結構包括電路板、至少一上述內埋式晶片封裝（增層線路結構配置於玻璃基板的第一表面)（以下簡稱為第一內埋式晶片封裝)以及上述內埋式晶片封裝（增層線路結構配置於玻璃基板的第二表面) （以下簡稱為第二內埋式晶片封裝)。第一內埋式晶片封裝配置於電路板上。第二內埋式晶片封裝配置於第一內埋式晶片封裝上。其中，第二內埋式晶片封裝與電路板分別位於第一內埋式晶片封裝的相對兩側。The stacked package structure of the present invention includes a circuit board, at least one of the above-mentioned embedded chip package (the build-up circuit structure is arranged on the first surface of the glass substrate) (hereinafter referred to as the first embedded chip package), and the above-mentioned embedded chip package. Chip package (the build-up circuit structure is arranged on the second surface of the glass substrate) (hereinafter referred to as the second embedded chip package). The first embedded chip package is configured on the circuit board. The second embedded chip package is configured on the first embedded chip package. Wherein, the second embedded chip package and the circuit board are respectively located on opposite sides of the first embedded chip package.

在本發明的一實施例中，第二內埋式晶片封裝的錫球或銅柱與第一內埋式晶片封裝的增層線路結構電性連接。第一內埋式晶片封裝的的錫球或銅柱與電路板電性連接。In an embodiment of the present invention, the solder balls or copper pillars of the second embedded chip package are electrically connected to the build-up circuit structure of the first embedded chip package. The solder balls or copper pillars of the first embedded chip package are electrically connected to the circuit board.

本發明的內埋式晶片封裝的製作方法包括以下步驟。首先，提供載體以及位於載體上的離型層。接著，配置晶片於離型層上。配置線路板於離型層上。其中，線路板包括玻璃基板以及至少一導電通孔。玻璃基板具有第一表面、與第一表面相對的第二表面以及貫穿玻璃基板的穿槽。導電通孔貫穿玻璃基板。在將晶片與線路板配置於離型層上，且使晶片嵌入於穿槽內之後，形成介電材料層於離型層上。其中，介電材料層填充於穿槽內且包覆晶片。然後，移除離型層及載體，以使晶片的下表面暴露於介電材料層外。在移除離型層及載體之後，形成增層線路結構於線路板上，以使增層線路結構與導電通孔電性連接。The manufacturing method of the embedded chip package of the present invention includes the following steps. First, provide a carrier and a release layer on the carrier. Next, the wafer is placed on the release layer. Configure the circuit board on the release layer. Wherein, the circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite to the first surface, and a through groove penetrating the glass substrate. The conductive via penetrates the glass substrate. After disposing the chip and the circuit board on the release layer and embedding the chip in the through groove, a dielectric material layer is formed on the release layer. Wherein, the dielectric material layer is filled in the through groove and covers the chip. Then, the release layer and the carrier are removed so that the lower surface of the wafer is exposed outside the dielectric material layer. After the release layer and the carrier are removed, a build-up circuit structure is formed on the circuit board, so that the build-up circuit structure is electrically connected to the conductive via.

在本發明的一實施例中，上述的增層線路結構配置於玻璃基板的第一表面。內埋式晶片封裝的製作方法更包括以下步驟。形成圖案化導電層於玻璃基板的第二表面，以使增層線路結構與圖案化導電層分別位於玻璃基板的相對兩側。形成錫球或銅柱於圖案化導電層上，以使錫球或銅柱與線路板分別位於圖案化導電層的相對兩側。In an embodiment of the present invention, the above-mentioned build-up circuit structure is disposed on the first surface of the glass substrate. The manufacturing method of the embedded chip package further includes the following steps. A patterned conductive layer is formed on the second surface of the glass substrate, so that the build-up circuit structure and the patterned conductive layer are respectively located on opposite sides of the glass substrate. A tin ball or copper pillar is formed on the patterned conductive layer, so that the tin ball or copper pillar and the circuit board are respectively located on opposite sides of the patterned conductive layer.

在本發明的一實施例中，上述的增層線路結構配置於玻璃基板的第二表面。內埋式晶片封裝的製作方法更包括以下步驟。形成錫球或銅柱於增層線路結構上，以使錫球或銅柱與線路板分別位於增層線路結構的相對兩側。In an embodiment of the present invention, the above-mentioned build-up circuit structure is disposed on the second surface of the glass substrate. The manufacturing method of the embedded chip package further includes the following steps. A solder ball or copper pillar is formed on the build-up circuit structure, so that the solder ball or copper pillar and the circuit board are respectively located on opposite sides of the build-up circuit structure.

基於上述，在本發明的內埋式晶片封裝及其製作方法與疊層封裝結構中，內埋式晶片封裝包括線路板、晶片、介電材料層以及增層線路結構。其中，線路板包括玻璃基板以及導電通孔，玻璃基板具有貫穿玻璃基板的穿槽。接著，將晶片配置於穿槽內，介電材料層填充於穿槽內，並將增層線路結構配置於線路板上。藉此設計，使得本發明的內埋式晶片封裝的製作方法可改善增層線路或封裝所產生的翹曲問題，使得本發明的內埋式晶片封裝具有較佳的封裝良率及可靠度，且使得本發明的疊層封裝結構具有可增加堆疊結構和線路的好處。Based on the above, in the embedded chip package and its manufacturing method and stacked package structure of the present invention, the embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. Wherein, the circuit board includes a glass substrate and conductive through holes, and the glass substrate has a through groove penetrating the glass substrate. Next, the chip is arranged in the through groove, the dielectric material layer is filled in the through groove, and the build-up circuit structure is arranged on the circuit board. With this design, the manufacturing method of the embedded chip package of the present invention can improve the build-up circuit or the warpage caused by the package, so that the embedded chip package of the present invention has better package yield and reliability. Moreover, the stacked package structure of the present invention has the advantage of increasing the stacked structure and circuits.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below and described in detail in conjunction with the accompanying drawings.

有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之各實施例的詳細說明中，將可清楚的呈現。以下實施例中所提到的方向用語，例如：「上」、「下」、「前」、「後」、「左」、「右」等，僅是參考附加圖式的方向。因此，使用的方向用語是用來說明，而並非用來限制本發明。The foregoing and other technical content, features, and effects of the present invention will be clearly presented in the detailed description of each embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, for example: "up", "down", "front", "rear", "left", "right", etc., are just directions for referring to the attached drawings. Therefore, the directional terms used are for illustration, not for limiting the invention.

各實施例的詳細說明中，「第一」、「第二」、「第三」、「第四」等術語可以用於描述不同的元素。這些術語僅用於將元素彼此區分，但在結構中，這些元素不應被這些術語限制。例如，第一元素可以被稱為第二元素，並且，類似地，第二元素可以被稱為第一元素而不背離本發明構思的保護範圍。另外，在製造方法中，除了特定的製程流程，這些元件或構件的形成順續亦不應被這些術語限制。例如，第一元素可以在第二元素之前形成。或是，第一元素可以在第二元素之後形成。亦或是，第一元素與第二元素可以在相同的製程或步驟中形成。In the detailed description of each embodiment, terms such as "first", "second", "third", and "fourth" can be used to describe different elements. These terms are only used to distinguish elements from each other, but in the structure, these elements should not be limited by these terms. For example, the first element may be referred to as the second element, and, similarly, the second element may be referred to as the first element without departing from the protection scope of the inventive concept. In addition, in the manufacturing method, in addition to a specific manufacturing process, the formation of these elements or components should not be limited by these terms. For example, the first element may be formed before the second element. Alternatively, the first element may be formed after the second element. Or, the first element and the second element can be formed in the same manufacturing process or step.

並且，圖式中的層與區域的厚度會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。In addition, the thickness of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

圖1A至圖1F繪示為本發明一實施例的一種內埋式晶片封裝的製作方法的剖面示意圖。圖1G繪示為圖1F的內埋式晶片封裝的仰視示意圖。為了清楚繪示及方便說明，圖1G中省略繪示圖案化導電層160以及錫球170。1A to 1F are schematic cross-sectional views of a manufacturing method of an embedded chip package according to an embodiment of the invention. FIG. 1G is a schematic bottom view of the embedded chip package of FIG. 1F. For clarity of illustration and convenience of description, the patterned conductive layer 160 and the solder balls 170 are omitted in FIG. 1G.

請參照圖1A，先提供一載體110以及配置於載體110上的離型層112，接著將配置晶片120於離型層112上。在本實施例中，載體110可以為金屬基板、矽基板、玻璃基板、陶瓷基板或其他可用於支撐的適宜載板。離型層112可由聚合物系材料形成，所述聚合物系材料可與載體110一起在後續步驟中被移除。在一些實施例中，離型層112是會在受熱時失去其粘著特性的環氧樹脂系熱釋放材料，例如光熱轉換（light-to-heat-conversion，LTHC）釋放塗層。在其他實施例中，離型層112可為在被暴露至紫外光時失去其粘著特性的紫外光（ultra-violet，UV）膠。離型層112可作為液體進行分配並進行固化，離型層112可為被疊層到載體110上的疊層體膜（laminate film），或可為其他形式。1A, a carrier 110 and a release layer 112 disposed on the carrier 110 are provided first, and then the chip 120 is disposed on the release layer 112. In this embodiment, the carrier 110 may be a metal substrate, a silicon substrate, a glass substrate, a ceramic substrate, or other suitable carrier plates that can be used for support. The release layer 112 may be formed of a polymer-based material, and the polymer-based material may be removed together with the carrier 110 in a subsequent step. In some embodiments, the release layer 112 is an epoxy resin heat release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 112 may be an ultraviolet (ultra-violet, UV) glue that loses its adhesive properties when exposed to ultraviolet light. The release layer 112 may be distributed as a liquid and cured, and the release layer 112 may be a laminate film laminated on the carrier 110, or may be in other forms.

請參照圖1B，將線路板130配置於離型層112上。在本實施例中，線路板130包括玻璃基板131以及至少一導電通孔135。其中，玻璃基板131具有第一表面132、與第一表面132相對的第二表面133以及貫穿玻璃基板131的穿槽（through hole)134。在一些實施例中，穿槽134連接玻璃基板131的第一表面132與第二表面133。Referring to FIG. 1B, the circuit board 130 is disposed on the release layer 112. In this embodiment, the circuit board 130 includes a glass substrate 131 and at least one conductive via 135. Wherein, the glass substrate 131 has a first surface 132, a second surface 133 opposite to the first surface 132, and a through hole 134 penetrating the glass substrate 131. In some embodiments, the through groove 134 connects the first surface 132 and the second surface 133 of the glass substrate 131.

接著，可利用以下步驟形成導電通孔135，但不以此為限。首先，以雷射或機械加工的方法對玻璃基板131進行鑽孔，以形成貫穿玻璃基板131的通孔。其中，通孔連接第一表面132與第二表面133。然後，在通孔內形成晶種層（未繪示)，並以電鍍的方式形成導電材料（未繪示)於通孔內，進而形成貫穿玻璃基板131的導電通孔135。此處，導電材料可為金屬或金屬合金，例如銅、鈦、鎢、鋁等或其組合。Next, the following steps can be used to form the conductive via 135, but not limited to this. First, the glass substrate 131 is drilled by laser or mechanical processing to form a through hole penetrating the glass substrate 131. Wherein, the through hole connects the first surface 132 and the second surface 133. Then, a seed layer (not shown) is formed in the through hole, and a conductive material (not shown) is formed in the through hole by electroplating, thereby forming a conductive through hole 135 penetrating the glass substrate 131. Here, the conductive material may be a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, etc., or a combination thereof.

需要說明的是，雖然在本實施例中是先將晶片120配置於離型層112上，再將線路板130配置於離型層112上，且將線路板130的穿槽134對準晶片120，以使晶片120嵌入於線路板130的穿槽134內，但不以此為限。也就是說，在其他實施例中，也可以是先將線路板130配置於離型層112上，再將晶片120配置於離型層112上，且使晶片120嵌入於線路板130的穿槽134內。It should be noted that although in this embodiment, the chip 120 is first disposed on the release layer 112, and then the circuit board 130 is disposed on the release layer 112, and the through grooves 134 of the circuit board 130 are aligned with the chip 120 , So that the chip 120 is embedded in the through slot 134 of the circuit board 130, but not limited to this. That is to say, in other embodiments, the circuit board 130 may be disposed on the release layer 112 first, and then the chip 120 is disposed on the release layer 112, and the chip 120 is embedded in the through groove of the circuit board 130 134 within.

此外，在本實施例中，線路板130的厚度與晶片120的厚度可以相同也可以不同，於本發明中並不加以限制。另外，雖然在本實施例中並不對穿槽134以及晶片120的尺寸加以限制，但需注意的是，線路板130的穿槽134的截面積需大於晶片120的截面積，以使晶片120適宜嵌入於線路板130的穿槽134內。In addition, in this embodiment, the thickness of the circuit board 130 and the thickness of the wafer 120 may be the same or different, which is not limited in the present invention. In addition, although the size of the slot 134 and the size of the chip 120 is not limited in this embodiment, it should be noted that the cross-sectional area of the slot 134 of the circuit board 130 needs to be larger than the cross-sectional area of the chip 120 to make the chip 120 suitable It is embedded in the through slot 134 of the circuit board 130.

接著，請參照圖1C，在將晶片120與線路板130配置於離型層112上，且使晶片120嵌入於穿槽134內之後，形成介電材料層140於離型層112上，以使介電材料層140填充於穿槽134內並包覆晶片120。在本實施例中，例如可以將樹脂（如：環氧樹脂（epoxy））、矽烷（如：六甲基二矽氧烷（hexamethyldisiloxane；HMDSN）、四乙氧基矽烷（tetraethoxysilane；TEOS）、雙二甲基胺二甲基矽氮烷（bis（dimethylamino）dimethylsilane；BDMADMS））或其他適宜的介電材料，塗佈於離型層112上並加以固化，以形成介電材料層140。因此，介電材料層140可以填充於穿槽134內，並位於晶片120與線路板130之間，以使晶片120與線路板130之間具有良好的緩衝。Next, referring to FIG. 1C, after the chip 120 and the circuit board 130 are disposed on the release layer 112, and the chip 120 is embedded in the through groove 134, a dielectric material layer 140 is formed on the release layer 112 to make The dielectric material layer 140 is filled in the through groove 134 and covers the chip 120. In this embodiment, for example, resin (such as epoxy), silane (such as hexamethyldisiloxane (HMDSN), tetraethoxysilane (TEOS), double Dimethylamine dimethylsilane (BDMADMS) or other suitable dielectric materials are coated on the release layer 112 and cured to form the dielectric material layer 140. Therefore, the dielectric material layer 140 can be filled in the through groove 134 and located between the chip 120 and the circuit board 130, so that there is a good buffer between the chip 120 and the circuit board 130.

請參照圖1D，在形成介電材料層140之後，移除離型層112及載體110，以使晶片120的下表面121暴露於介電材料層140外。在一些實施例中，晶片120的下表面121暴露於線路板130的穿槽134外。此外，由於線路板130與晶片120皆是置於離型層112上且與離型層112接觸，因此，晶片120的下表面121可與玻璃基板131的第二表面133齊平。1D, after the dielectric material layer 140 is formed, the release layer 112 and the carrier 110 are removed, so that the lower surface 121 of the wafer 120 is exposed outside the dielectric material layer 140. In some embodiments, the lower surface 121 of the chip 120 is exposed outside the through groove 134 of the circuit board 130. In addition, since the circuit board 130 and the chip 120 are both placed on and in contact with the release layer 112, the lower surface 121 of the chip 120 can be flush with the second surface 133 of the glass substrate 131.

請參照圖1E，在移除離型層112及載體110之後，形成增層線路結構150於線路板130上，並形成圖案化導電層160於線路板130上。其中，增層線路結構150可與導電通孔135電性連接，圖案化導電層160可與導電通孔135電性連接，且圖案化導電層160可與晶片120電性連接。因此，增層線路結構150可透過導電通孔135與圖案化導電層160電性連接。具體來說，增層線路結構150包括第一線路層151、第一介電層152、第二線路層153以及至少一第一導通孔154。第一線路層151覆蓋玻璃基板131的第一表面132，第一介電層152覆蓋第一線路層151以及玻璃基板131的第一表面132。第一導通孔154貫穿第一介電層152，以電性連接第一線路層151與第二線路層153。其中，第二線路層153與第一線路層151分別位於第一介電層152的相對兩側。1E, after the release layer 112 and the carrier 110 are removed, a build-up circuit structure 150 is formed on the circuit board 130, and a patterned conductive layer 160 is formed on the circuit board 130. The build-up circuit structure 150 can be electrically connected to the conductive via 135, the patterned conductive layer 160 can be electrically connected to the conductive via 135, and the patterned conductive layer 160 can be electrically connected to the chip 120. Therefore, the build-up circuit structure 150 can be electrically connected to the patterned conductive layer 160 through the conductive via 135. Specifically, the build-up circuit structure 150 includes a first circuit layer 151, a first dielectric layer 152, a second circuit layer 153, and at least one first via 154. The first circuit layer 151 covers the first surface 132 of the glass substrate 131, and the first dielectric layer 152 covers the first circuit layer 151 and the first surface 132 of the glass substrate 131. The first via hole 154 penetrates the first dielectric layer 152 to electrically connect the first circuit layer 151 and the second circuit layer 153. Wherein, the second circuit layer 153 and the first circuit layer 151 are respectively located on opposite sides of the first dielectric layer 152.

此外，在本實施例中，由於增層線路結構150形成於玻璃基板131的第一表面132，圖案化導電層160形成於玻璃基板131的第二表面133，使得增層線路結構150與圖案化導電層160分別位於玻璃基板131的相對兩側。In addition, in the present embodiment, since the build-up wiring structure 150 is formed on the first surface 132 of the glass substrate 131, the patterned conductive layer 160 is formed on the second surface 133 of the glass substrate 131, so that the build-up wiring structure 150 and the patterned The conductive layers 160 are respectively located on opposite sides of the glass substrate 131.

另外，在本實施例中，晶片120的下表面121可作為主動表面122。其中，主動表面122朝向圖案化導電層160，且主動表面122可與圖案化導電層160電性連接。In addition, in this embodiment, the lower surface 121 of the wafer 120 may serve as the active surface 122. Wherein, the active surface 122 faces the patterned conductive layer 160, and the active surface 122 can be electrically connected to the patterned conductive layer 160.

接著，為了使本實施例的內埋式晶片封裝100與其外部進行電性連接，可在圖案化導電層160上形成導電連接件。在本實施例中，導電連接件可例如是錫球170，但不以此為限。請參照圖1F，形成錫球170於圖案化導電層160上，以使錫球170與線路板130分別位於圖案化導電層160的相對兩側。此時，大致上已製作完成本實施例的內埋式晶片封裝100。Next, in order to electrically connect the embedded chip package 100 of this embodiment to the outside, a conductive connection member may be formed on the patterned conductive layer 160. In this embodiment, the conductive connection member may be, for example, a solder ball 170, but it is not limited thereto. 1F, a solder ball 170 is formed on the patterned conductive layer 160, so that the solder ball 170 and the circuit board 130 are located on opposite sides of the patterned conductive layer 160, respectively. At this time, the embedded chip package 100 of this embodiment has been substantially completed.

此外，請參照圖1G，在本實施例中，穿槽134的形狀可為圓形，但不以此為限。也就是說，在其他實施例中，穿槽的形狀也可以示方形或其他適合的形狀，只要能使晶片能夠嵌入於線路板的穿槽內即可。In addition, referring to FIG. 1G, in this embodiment, the shape of the through slot 134 may be circular, but it is not limited to this. That is to say, in other embodiments, the shape of the slot can also be a square or other suitable shape, as long as the chip can be embedded in the slot of the circuit board.

簡言之，本實施例的內埋式晶片封裝100包括線路板130、晶片120、介電材料層140以及增層線路結構150。線路板130包括玻璃基板131以及至少一導電通孔135。玻璃基板131具有第一表面132、與第一表面132相對的第二表面133以及貫穿玻璃基板131的穿槽134。導電通孔135貫穿玻璃基板131。晶片120配置於穿槽134內。介電材料層140填充於穿槽134內，且包覆晶片120。增層線路結構150配置於線路板130上。增層線路結構150與導電通孔135電性連接。晶片120的下表面121暴露於介電材料層140外。藉此設計，使得本實施例的內埋式晶片封裝100的製作方法可改善增層線路結構150或封裝所產生的翹曲問題，並使得本實施例的內埋式晶片封裝100具有較佳的封裝良率及可靠度。In short, the embedded chip package 100 of this embodiment includes a circuit board 130, a chip 120, a dielectric material layer 140, and a build-up circuit structure 150. The circuit board 130 includes a glass substrate 131 and at least one conductive via 135. The glass substrate 131 has a first surface 132, a second surface 133 opposite to the first surface 132, and a through groove 134 penetrating the glass substrate 131. The conductive via 135 penetrates the glass substrate 131. The wafer 120 is disposed in the through groove 134. The dielectric material layer 140 is filled in the through groove 134 and covers the chip 120. The build-up circuit structure 150 is configured on the circuit board 130. The build-up circuit structure 150 is electrically connected to the conductive via 135. The lower surface 121 of the wafer 120 is exposed outside the dielectric material layer 140. With this design, the manufacturing method of the embedded chip package 100 of this embodiment can improve the build-up circuit structure 150 or the warpage caused by the package, and make the embedded chip package 100 of this embodiment have better Package yield and reliability.

以下將列舉其他實施例以作為說明。在此必須說明的是，下述實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。Other embodiments will be listed below for description. It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

圖1H繪示為本發明另一實施例的一種內埋式晶片封裝的剖面示意圖。請同時參考圖1F與圖1H，本實施例的內埋式晶片封裝100a與圖1F中的內埋式晶片封裝100相似，惟二者主要差異之處在於：本實施例的內埋式晶片封裝100a的導電連接件為銅柱172，且增層線路結構150a還包括第二介電層155以及第二導通孔156。具體來說，在本實施例的內埋式晶片封裝100a的製作方法中，先參照圖1A至圖1D的步驟進行製作之後，再接著參照圖1H，形成增層線路結構150a於線路板130上，並形成圖案化導電層160於線路板130上。其中，增層線路結構150a還包括第二介電層155以及第二導通孔156。第二介電層155覆蓋第二線路層153以及第一介電層152。第二導通孔156貫穿第二介電層155，以電性連接第二線路層153。然後，再接著參照圖1H，形成銅柱172於圖案化導電層160上，以使銅柱172與線路板130分別位於圖案化導電層160的相對兩側。1H is a schematic cross-sectional view of an embedded chip package according to another embodiment of the invention. 1F and 1H at the same time, the embedded chip package 100a of this embodiment is similar to the embedded chip package 100 in FIG. 1F, but the main difference between the two is: the embedded chip package of this embodiment The conductive connection member 100a is a copper pillar 172, and the build-up circuit structure 150a further includes a second dielectric layer 155 and a second via 156. Specifically, in the manufacturing method of the embedded chip package 100a of this embodiment, first, after manufacturing with reference to the steps of FIGS. 1A to 1D, and then referring to FIG. 1H, the build-up circuit structure 150a is formed on the circuit board 130 , And form a patterned conductive layer 160 on the circuit board 130. Wherein, the build-up line structure 150a further includes a second dielectric layer 155 and a second via hole 156. The second dielectric layer 155 covers the second circuit layer 153 and the first dielectric layer 152. The second via 156 penetrates the second dielectric layer 155 to electrically connect to the second circuit layer 153. Then, referring to FIG. 1H again, copper pillars 172 are formed on the patterned conductive layer 160 so that the copper pillars 172 and the circuit board 130 are located on opposite sides of the patterned conductive layer 160 respectively.

圖2A至圖2B繪示為本發明另一實施例的一種內埋式晶片封裝的製作方法的剖面示意圖。圖2A至圖2B所示的實施例與圖1A至圖1F所示的實施例的差異在於：本實施例的內埋式晶片封裝100b的增層線路結構150b的位置、主動表面122與增層線路結構150b的相對關係。此外，本實施例的內埋式晶片封裝100b還不包括圖案化導電層。2A to 2B are schematic cross-sectional diagrams of a manufacturing method of an embedded chip package according to another embodiment of the present invention. The difference between the embodiment shown in FIGS. 2A to 2B and the embodiment shown in FIGS. 1A to 1F lies in the position of the build-up circuit structure 150b, the active surface 122 and the build-up layer of the embedded chip package 100b of this embodiment The relative relationship of the line structure 150b. In addition, the embedded chip package 100b of this embodiment does not include a patterned conductive layer.

具體來說，在本實施例的內埋式晶片封裝100b的製作方法中，先參照圖1A至圖1D的步驟進行製作之後，再接著參照圖2A，形成增層線路結構150b於線路板130上。此時，將增層線路結構150b配置於玻璃基板110的第二表面133，且增層線路結構150b可與導電通孔135電性連接。在本實施例中，晶片120的下表面121可為主動表面122。其中，主動表面122朝向增層線路結構150b，且主動表面122可與增層線路結構150b電性連接。Specifically, in the manufacturing method of the embedded chip package 100b of this embodiment, first, after manufacturing with reference to the steps of FIGS. 1A to 1D, and then referring to FIG. 2A, a build-up circuit structure 150b is formed on the circuit board 130 . At this time, the build-up circuit structure 150b is disposed on the second surface 133 of the glass substrate 110, and the build-up circuit structure 150b can be electrically connected to the conductive via 135. In this embodiment, the lower surface 121 of the wafer 120 may be the active surface 122. The active surface 122 faces the build-up line structure 150b, and the active surface 122 can be electrically connected to the build-up line structure 150b.

然後，參照圖2B，形成錫球170a於增層線路結構150b上，以使錫球170a與線路板130分別位於增層線路結構150b的相對兩側。此時，大致上已製作完成本實施例的內埋式晶片封裝100b。Then, referring to FIG. 2B, solder balls 170a are formed on the build-up circuit structure 150b, so that the solder balls 170a and the circuit board 130 are respectively located on opposite sides of the build-up circuit structure 150b. At this time, the embedded chip package 100b of this embodiment has been substantially completed.

雖然在圖2B中是形成錫球170a於增層線路結構150b上，但不以此為限。也就是說，在其他實施例中，如圖2C所示，也可形成銅柱172a於增層線路結構150b上，以製作完成另一實施例的內埋式晶片封裝100c。Although the solder ball 170a is formed on the build-up circuit structure 150b in FIG. 2B, it is not limited thereto. That is, in other embodiments, as shown in FIG. 2C, copper pillars 172a may also be formed on the build-up circuit structure 150b to complete the buried chip package 100c of another embodiment.

圖3A至圖3B繪示為本發明多種實施例的並列式封裝（side-by-side package）結構的剖面示意圖。所述並列式封裝結構，是將上述製作完成的內埋式晶片封裝100或內埋式晶片封裝100a，以並列的方式配置於電路板200、200a上。請參照圖3A，在本實施例的並列式封裝結構10中，示意地將2個內埋式晶片封裝100配置於電路板200上。其中，2個內埋式晶片封裝100可透過其錫球170與電路板200電性連接。請參照圖3B，在本實施例的並列式封裝結構10a中，示意地將2個內埋式晶片封裝100a配置於電路板200a上。其中，2個內埋式晶片封裝100a皆可透過其銅柱172與電路板200a電性連接。3A to 3B are schematic cross-sectional views of a side-by-side package structure according to various embodiments of the present invention. The side-by-side packaging structure is to arrange the built-in embedded chip package 100 or the embedded chip package 100a that has been completed on the circuit boards 200 and 200a in a parallel manner. 3A, in the side-by-side package structure 10 of this embodiment, two embedded chip packages 100 are schematically arranged on the circuit board 200. Among them, the two embedded chip packages 100 can be electrically connected to the circuit board 200 through the solder balls 170 thereof. Referring to FIG. 3B, in the parallel package structure 10a of this embodiment, two embedded chip packages 100a are schematically arranged on the circuit board 200a. Among them, the two embedded chip packages 100a can be electrically connected to the circuit board 200a through the copper pillars 172 thereof.

需要說明的是，雖然圖3A（或圖3B）示意地將2個內埋式晶片封裝100（或內埋式晶片封裝100a）配置於電路板200（或電路板200a）上，但本發明並不對並列式封裝結構中的內埋式晶片封裝100（或內埋式晶片封裝100a）的數量加以限制。也就是說，在其他未繪示的實施例中，也可以將2個以上的內埋式晶片封裝100（或內埋式晶片封裝100a）配置於電路板200（或電路板200a）上，以形成不同的並列式封裝結構。It should be noted that although FIG. 3A (or FIG. 3B) schematically arranges two embedded chip packages 100 (or embedded chip packages 100a) on the circuit board 200 (or circuit board 200a), the present invention does not There is no limitation on the number of embedded chip packages 100 (or embedded chip packages 100a) in the parallel package structure. That is, in other embodiments not shown, more than two embedded chip packages 100 (or embedded chip packages 100a) may be arranged on the circuit board 200 (or circuit board 200a) to Form different side-by-side package structures.

圖4A至圖4B繪示為本發明多種實施例的疊層封裝（package on package）結構的剖面示意圖。所述疊層封裝結構，是將上述製作完成的內埋式晶片封裝100、內埋式晶片封裝100a、內埋式晶片封裝100b、內埋式晶片封裝100c或其組合，以疊層的方式配置於電路板200b、200c上。請參照圖4A，在本實施例的疊層封裝結構10b中，示意地將1個內埋式晶片封裝100配置於電路板200b上，並將1個內埋式晶片封裝100b配置於內埋式晶片封裝100上。其中，內埋式晶片封裝100b與電路板200b分別位於內埋式晶片封裝100的相對兩側。此外，內埋式晶片封裝100b的錫球170a可與內埋式晶片封裝100的增層線路結構150電性連接。內埋式晶片封裝100的錫球170與電路板200b電性連接。4A to 4B are schematic cross-sectional views of a package on package structure according to various embodiments of the present invention. The stacked package structure is to arrange the above-mentioned embedded chip package 100, embedded chip package 100a, embedded chip package 100b, embedded chip package 100c or a combination thereof in a stacked manner On the circuit boards 200b, 200c. 4A, in the stacked package structure 10b of this embodiment, one embedded chip package 100 is schematically arranged on the circuit board 200b, and one embedded chip package 100b is arranged on the embedded type. Chip package 100 on. Wherein, the embedded chip package 100b and the circuit board 200b are located on opposite sides of the embedded chip package 100, respectively. In addition, the solder balls 170 a of the embedded chip package 100 b can be electrically connected to the build-up circuit structure 150 of the embedded chip package 100. The solder balls 170 of the embedded chip package 100 are electrically connected to the circuit board 200b.

請參照圖4B，在本實施例的疊層封裝結構10c中，示意地將1個內埋式晶片封裝100a配置於電路板200c上，並將1個內埋式晶片封裝100c配置於內埋式晶片封裝100a上。其中，內埋式晶片封裝100c與電路板200c分別位於內埋式晶片封裝100a的相對兩側。此外，內埋式晶片封裝100c的銅柱172a可與內埋式晶片封裝100a的增層線路結構150a電性連接。內埋式晶片封裝100a的銅柱172可與電路板200c電性連接。4B, in the stacked package structure 10c of this embodiment, one embedded chip package 100a is schematically arranged on the circuit board 200c, and one embedded chip package 100c is arranged on the embedded type. On the chip package 100a. Wherein, the embedded chip package 100c and the circuit board 200c are respectively located on opposite sides of the embedded chip package 100a. In addition, the copper pillars 172a of the embedded chip package 100c can be electrically connected to the build-up circuit structure 150a of the embedded chip package 100a. The copper pillar 172 of the embedded chip package 100a can be electrically connected to the circuit board 200c.

需要說明的是，雖然圖4A（或圖4B）示意地將1個內埋式晶片封裝100（或內埋式晶片封裝100a）配置於內埋式晶片封裝100b（或內埋式晶片封裝100c）與電路板200b（或電路板200c）之間，但本發明並不對疊層封裝結構中的內埋式晶片封裝100（或內埋式晶片封裝100a）的數量加以限制。也就是說，在其他未繪示的實施例中，也可以將1個以上的內埋式晶片封裝100（或內埋式晶片封裝100a）配置於內埋式晶片封裝100b（或內埋式晶片封裝100c）與電路板200b（或電路板200c）之間，以形成具有多個疊層的疊層封裝結構。換言之，本實施例的疊層封裝結構10b、10c具有可增加堆疊結構和線路的好處。It should be noted that although FIG. 4A (or FIG. 4B) schematically arranges one embedded chip package 100 (or embedded chip package 100a) in the embedded chip package 100b (or embedded chip package 100c) And the circuit board 200b (or the circuit board 200c), but the present invention does not limit the number of the embedded chip package 100 (or the embedded chip package 100a) in the stacked package structure. That is to say, in other embodiments not shown, more than one embedded chip package 100 (or embedded chip package 100a) may be arranged in the embedded chip package 100b (or embedded chip package). Between the package 100c) and the circuit board 200b (or the circuit board 200c) to form a stacked package structure with multiple stacked layers. In other words, the stacked package structure 10b, 10c of this embodiment has the advantage of increasing the stacked structure and wiring.

綜上所述，在本發明的內埋式晶片封裝及其製作方法與疊層封裝結構中，內埋式晶片封裝包括線路板、晶片、介電材料層以及增層線路結構。其中，線路板包括玻璃基板以及導電通孔，玻璃基板具有貫穿玻璃基板的穿槽。接著，將晶片配置於穿槽內，介電材料層填充於穿槽內，並將增層線路結構配置於線路板上。藉此設計，使得本發明的內埋式晶片封裝的製作方法可改善增層線路或封裝所產生的翹曲問題，使得本發明的內埋式晶片封裝具有較佳的封裝良率及可靠度，且使得本發明的疊層封裝結構具有可增加堆疊結構和線路的好處。In summary, in the embedded chip package and its manufacturing method and stacked package structure of the present invention, the embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. Wherein, the circuit board includes a glass substrate and conductive through holes, and the glass substrate has a through groove penetrating the glass substrate. Next, the chip is arranged in the through groove, the dielectric material layer is filled in the through groove, and the build-up circuit structure is arranged on the circuit board. With this design, the manufacturing method of the embedded chip package of the present invention can improve the build-up circuit or the warpage caused by the package, so that the embedded chip package of the present invention has better package yield and reliability. Moreover, the stacked package structure of the present invention has the advantage of increasing the stacked structure and circuits.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10、10a:並列式封裝結構10b、10c:疊層封裝結構100、100a、100b、100c:內埋式晶片封裝110:載體112:離型層120:晶片121:下表面122:主動表面130:線路板131:玻璃基板132:第一表面133:第二表面134:穿槽135:導電通孔140:介電材料層150、150b:增層線路結構151:第一線路層152:第一介電層153:第二線路層154:第一導通孔155:第二介電層156:第二導通孔160:圖案化導電層170、170a:錫球172、172a:銅柱200、200a、200b、200c:電路板10, 10a: side-by-side package structure 10b, 10c: stacked package structure 100, 100a, 100b, 100c: embedded chip package 110: carrier 112: release layer 120: chip 121: bottom surface 122: active surface 130: Circuit board 131: glass substrate 132: first surface 133: second surface 134: slot 135: conductive via 140: dielectric material layer 150, 150b: build-up circuit structure 151: first circuit layer 152: first dielectric Electrical layer 153: second circuit layer 154: first via 155: second dielectric layer 156: second via 160: patterned conductive layer 170, 170a: tin balls 172, 172a: copper pillars 200, 200a, 200b , 200c: circuit board

圖1A至圖1F繪示為本發明一實施例的一種內埋式晶片封裝的製作方法的剖面示意圖。圖1G繪示為圖1F的內埋式晶片封裝的仰視示意圖。圖1H繪示為本發明另一實施例的一種內埋式晶片封裝的剖面示意圖。圖2A至圖2B繪示為本發明另一實施例的一種內埋式晶片封裝的製作方法的剖面示意圖。圖2C繪示為本發明另一實施例的一種內埋式晶片封裝的剖面示意圖。圖3A至圖3B繪示為本發明多種實施例的並列式封裝結構的剖面示意圖。圖4A至圖4B繪示為本發明多種實施例的疊層封裝結構的剖面示意圖。1A to 1F are schematic cross-sectional views of a manufacturing method of an embedded chip package according to an embodiment of the invention. FIG. 1G is a schematic bottom view of the embedded chip package of FIG. 1F. 1H is a schematic cross-sectional view of an embedded chip package according to another embodiment of the invention. 2A to 2B are schematic cross-sectional diagrams of a manufacturing method of an embedded chip package according to another embodiment of the present invention. 2C is a schematic cross-sectional view of a buried chip package according to another embodiment of the invention. 3A to 3B are schematic cross-sectional views of the parallel package structure according to various embodiments of the present invention. 4A to 4B are schematic cross-sectional diagrams of stacked package structures according to various embodiments of the invention.

100:內埋式晶片封裝 100: Embedded chip package

120:晶片 120: chip

121:下表面 121: lower surface

130:線路板 130: circuit board

131:玻璃基板 131: Glass substrate

132:第一表面 132: First Surface

133:第二表面 133: Second Surface

134:穿槽 134: piercing

135:導電通孔 135: conductive via

140:介電材料層 140: Dielectric material layer

150:增層線路結構 150: Build-up line structure

160:圖案化導電層 160: patterned conductive layer

170:錫球 170: tin ball

Claims

一種內埋式晶片封裝，包括：一線路板，包括：一玻璃基板，具有一第一表面、與該第一表面相對的一第二表面以及貫穿該玻璃基板的一穿槽；以及至少一導電通孔，貫穿該玻璃基板；一晶片，配置於該穿槽內；一介電材料層，填充於該穿槽內且包覆該晶片；以及一增層線路結構，配置於該線路板上，其中該增層線路結構與該導電通孔電性連接，且該晶片的一下表面暴露於該介電材料層外。An embedded chip package includes: a circuit board, including: a glass substrate having a first surface, a second surface opposite to the first surface, and a slot penetrating the glass substrate; and at least one conductive A through hole penetrates the glass substrate; a chip arranged in the through groove; a dielectric material layer filled in the through groove and covering the chip; and a build-up circuit structure arranged on the circuit board, The build-up circuit structure is electrically connected with the conductive via, and the lower surface of the chip is exposed outside the dielectric material layer.

如申請專利範圍第1項所述的內埋式晶片封裝，其中該晶片的該下表面與該玻璃基板的該第二表面齊平。The embedded chip package according to the first item of the scope of patent application, wherein the lower surface of the chip is flush with the second surface of the glass substrate.

如申請專利範圍第1項所述的內埋式晶片封裝，其中該增層線路結構包括：一第一線路層；一第一介電層，覆蓋該第一線路層；一第二線路層，與該第一線路層分別位於該第一介電層的相對兩側；以及至少一第一導通孔，貫穿該第一介電層，以電性連接該第一線路層與該第二線路層。According to the embedded chip package described in claim 1, wherein the build-up circuit structure includes: a first circuit layer; a first dielectric layer covering the first circuit layer; a second circuit layer, And the first circuit layer are respectively located on opposite sides of the first dielectric layer; and at least one first via hole penetrates the first dielectric layer to electrically connect the first circuit layer and the second circuit layer .

如申請專利範圍第1項所述的內埋式晶片封裝，其中該增層線路結構配置於該玻璃基板的該第一表面，該內埋式晶片封裝更包括：一圖案化導電層，配置於該玻璃基板的該第二表面，以使該增層線路結構與該圖案化導電層分別位於該玻璃基板的相對兩側；以及一錫球或一銅柱，配置於該圖案化導電層上，以使該錫球或該銅柱與該線路板分別位於該圖案化導電層的相對兩側。The embedded chip package as described in claim 1, wherein the build-up circuit structure is disposed on the first surface of the glass substrate, and the embedded chip package further includes: a patterned conductive layer disposed on The second surface of the glass substrate such that the build-up circuit structure and the patterned conductive layer are respectively located on opposite sides of the glass substrate; and a tin ball or a copper pillar is disposed on the patterned conductive layer, So that the solder ball or the copper pillar and the circuit board are respectively located on opposite sides of the patterned conductive layer.

如申請專利範圍第4項所述的內埋式晶片封裝，其中該晶片的該下表面為一主動表面，該主動表面朝向該圖案化導電層且與該圖案化導電層電性連接。The embedded chip package as described in claim 4, wherein the lower surface of the chip is an active surface, and the active surface faces the patterned conductive layer and is electrically connected to the patterned conductive layer.

如申請專利範圍第4項所述的內埋式晶片封裝，其中該增層線路結構透過該導電通孔與該圖案化導電層電性連接。According to the embedded chip package described in item 4 of the scope of patent application, the build-up circuit structure is electrically connected to the patterned conductive layer through the conductive via.

如申請專利範圍第1項所述的內埋式晶片封裝，其中該增層線路結構配置於該玻璃基板的該第二表面，該內埋式晶片封裝更包括：一錫球或一銅柱，配置於該增層線路結構上，以使該錫球或該銅柱與該線路板分別位於該增層線路結構的相對兩側。The embedded chip package as described in claim 1, wherein the build-up circuit structure is disposed on the second surface of the glass substrate, and the embedded chip package further includes: a solder ball or a copper pillar, It is arranged on the build-up circuit structure so that the solder ball or the copper pillar and the circuit board are respectively located on opposite sides of the build-up circuit structure.

如申請專利範圍第7項所述的內埋式晶片封裝，其中該晶片的該下表面為一主動表面，該主動表面朝向該增層線路結構且與該增層線路結構電性連接。According to the embedded chip package described in claim 7, wherein the lower surface of the chip is an active surface, and the active surface faces the build-up circuit structure and is electrically connected to the build-up circuit structure.

如申請專利範圍第1項所述的內埋式晶片封裝，其中該穿槽連接該玻璃基板的該第一表面與該第二表面。In the embedded chip package as described in claim 1, wherein the through groove connects the first surface and the second surface of the glass substrate.

一種疊層封裝結構，包括：一電路板；至少一如請求項4所述的內埋式晶片封裝，配置於該電路板上；以及一如請求項7所述的內埋式晶片封裝，配置於該如請求項4所述的內埋式晶片封裝上，其中該如請求項7所述的內埋式晶片封裝與該電路板分別位於該如請求項4所述的內埋式晶片封裝的相對兩側。A stacked package structure, comprising: a circuit board; at least one embedded chip package according to claim 4, configured on the circuit board; and an embedded chip package according to claim 7, configured On the embedded chip package according to claim 4, wherein the embedded chip package according to claim 7 and the circuit board are respectively located on the embedded chip package according to claim 4 Opposite sides.

如申請專利範圍第10項所述的疊層封裝結構，其中該如請求項7所述的內埋式晶片封裝的該錫球或該銅柱與該如請求項4所述的內埋式晶片封裝的該增層線路結構電性連接，且該如請求項4所述的內埋式晶片封裝的該錫球或該銅柱與該電路板電性連接。The stacked package structure according to claim 10, wherein the solder ball or the copper pillar of the embedded chip package according to claim 7 and the embedded chip according to claim 4 The build-up circuit structure of the package is electrically connected, and the solder ball or the copper pillar of the embedded chip package according to claim 4 is electrically connected to the circuit board.

一種內埋式晶片封裝的製作方法，包括：提供一載體以及配置於該載體上的一離型層；配置一晶片於該離型層上；配置一線路板於該離型層上，該線路板包括：一玻璃基板，具有一第一表面、與該第一表面相對的一第二表面以及貫穿該玻璃基板的一穿槽；以及至少一導電通孔，貫穿該玻璃基板；在將該晶片與該線路板配置於該離型層上，且使該晶片嵌入於該穿槽內之後，形成一介電材料層於該離型層上，其中該介電材料層填充於該穿槽內且包覆該晶片；移除該離型層及該載體，以使該晶片的一下表面暴露於該介電材料層外；在移除該離型層及該載體之後，形成一增層線路結構於該線路板上，以使該增層線路結構與該導電通孔電性連接。A manufacturing method of an embedded chip package includes: providing a carrier and a release layer arranged on the carrier; arranging a chip on the releasing layer; arranging a circuit board on the releasing layer, the circuit The board includes: a glass substrate having a first surface, a second surface opposite to the first surface, and a through groove penetrating the glass substrate; and at least one conductive via, penetrating the glass substrate; And the circuit board are arranged on the release layer, and after the chip is embedded in the through groove, a dielectric material layer is formed on the release layer, wherein the dielectric material layer is filled in the through groove and Cladding the chip; removing the release layer and the carrier so that the lower surface of the chip is exposed outside the dielectric material layer; after removing the release layer and the carrier, a build-up circuit structure is formed on On the circuit board, the build-up circuit structure is electrically connected to the conductive via.

如申請專利範圍第12項所述的內埋式晶片封裝的製作方法，其中該晶片的該下表面與該玻璃基板的該第二表面齊平。According to the manufacturing method of the embedded chip package described in item 12 of the scope of patent application, the lower surface of the chip is flush with the second surface of the glass substrate.

如申請專利範圍第12項所述的內埋式晶片封裝的製作方法，其中該增層線路結構包括：一第一線路層；一第一介電層，覆蓋該第一線路層；一第二線路層，與該第一線路層分別位於該第一介電層的相對兩側；以及至少一第一導通孔，貫穿該第一介電層，以電性連接該第一線路層與該第二線路層。According to the manufacturing method of the embedded chip package described in claim 12, the build-up circuit structure includes: a first circuit layer; a first dielectric layer covering the first circuit layer; a second The circuit layer and the first circuit layer are respectively located on opposite sides of the first dielectric layer; and at least one first via hole penetrates the first dielectric layer to electrically connect the first circuit layer and the second The second line layer.

如申請專利範圍第12項所述的內埋式晶片封裝的製作方法，其中該增層線路結構配置於該玻璃基板的該第一表面，該內埋式晶片封裝的製作方法更包括：形成一圖案化導電層於該玻璃基板的該第二表面，以使該增層線路結構與該圖案化導電層分別位於該玻璃基板的相對兩側；以及形成一錫球或一銅柱於該圖案化導電層上，以使該錫球或該銅柱與該線路板分別位於該圖案化導電層的相對兩側。The manufacturing method of the embedded chip package as described in item 12 of the scope of patent application, wherein the build-up circuit structure is disposed on the first surface of the glass substrate, and the manufacturing method of the embedded chip package further includes: forming a Patterning a conductive layer on the second surface of the glass substrate so that the build-up circuit structure and the patterned conductive layer are respectively located on opposite sides of the glass substrate; and forming a tin ball or a copper pillar on the patterned On the conductive layer, so that the solder ball or the copper pillar and the circuit board are respectively located on opposite sides of the patterned conductive layer.

如申請專利範圍第15項所述的內埋式晶片封裝的製作方法，其中該晶片的該下表面為一主動表面，該主動表面朝向該圖案化導電層且與該圖案化導電層電性連接。The manufacturing method of the embedded chip package according to claim 15, wherein the lower surface of the chip is an active surface, and the active surface faces the patterned conductive layer and is electrically connected to the patterned conductive layer .

如申請專利範圍第15項所述的內埋式晶片封裝的製作方法，其中該增層線路結構透過該導電通孔與該圖案化導電層電性連接。According to the manufacturing method of the embedded chip package described in claim 15, wherein the build-up circuit structure is electrically connected to the patterned conductive layer through the conductive via.

如申請專利範圍第12項所述的內埋式晶片封裝的製作方法，其中該增層線路結構配置於該玻璃基板的該第二表面，該內埋式晶片封裝的製作方法更包括：形成一錫球或一銅柱於該增層線路結構上，以使該錫球或該銅柱與該線路板分別位於該增層線路結構的相對兩側。According to the manufacturing method of the embedded chip package described in claim 12, wherein the build-up circuit structure is disposed on the second surface of the glass substrate, the manufacturing method of the embedded chip package further includes: forming a A solder ball or a copper pillar is on the build-up circuit structure so that the solder ball or the copper pillar and the circuit board are respectively located on opposite sides of the build-up circuit structure.

如申請專利範圍第18項所述的內埋式晶片封裝的製作方法，其中該晶片的該下表面為一主動表面，該主動表面朝向該增層線路結構且與該增層線路結構電性連接。The manufacturing method of the embedded chip package as described in claim 18, wherein the lower surface of the chip is an active surface, and the active surface faces the build-up circuit structure and is electrically connected to the build-up circuit structure .

如申請專利範圍第12項所述的內埋式晶片封裝的製作方法，其中該穿槽連接該玻璃基板的該第一表面與該第二表面。According to the manufacturing method of the embedded chip package described in item 12 of the scope of patent application, the through groove connects the first surface and the second surface of the glass substrate.