TW202021282A

TW202021282A - Sar adc with high linearity

Info

Publication number: TW202021282A
Application number: TW107141356A
Authority: TW
Inventors: 張順志; 張力仁
Original assignee: 財團法人成大研究發展基金會; 奇景光電股份有限公司
Priority date: 2018-11-21
Filing date: 2018-11-21
Publication date: 2020-06-01
Also published as: TWI657665B

Abstract

A successive approximation register (SAR) analog-to-digital converter (ADC) with high linearity for generating an n-bit converted output includes a first capacitor digital-to-analog (DAC) and a second capacitor DAC. One of the first capacitor DAC and the second capacitor DAC that has greater output signal is defined as a higher-voltage capacitor DAC, and the other as an un-switching capacitor DAC. In an m-th conversion phase, an (m-1)-th capacitor of the un-switching capacitor DAC is switched according to a comparison between output signals of the higher-voltage capacitor DAC and the un-switching capacitor DAC.

Description

高線性度的循續漸近式類比至數位轉換器High linearity progressive asymptotic analog-to-digital converter

本發明係有關一種類比至數位轉換器(ADC)，特別是關於一種循續漸近式類比至數位轉換器(SAR ADC)。The present invention relates to an analog-to-digital converter (ADC), and in particular to a gradual asymptotic analog-to-digital converter (SAR ADC).

循續漸近式類比至數位轉換器(successive approximation register analog-to-digital converter, SAR ADC)為類比至數位轉換器(ADC)的一種，用以等效轉換類比信號為數位信號。循續漸近式類比至數位轉換器藉由比較與搜尋所有可能的量化階層以執行轉換，用以得到數位輸出。相較於一般的類比至數位轉換器，循續漸近式類比至數位轉換器使用較少的電路面積與相應成本。雖然循續漸近式類比至數位轉換器消耗較少的功率，但是對於電源受限的一些電子裝置而言，循續漸近式類比至數位轉換器的功耗仍然過高。此外，傳統循續漸近式類比至數位轉換器具有非線性與電容不匹配等缺點。A successive approximation register analog-to-digital converter (SAR ADC) is a type of analog-to-digital converter (ADC), which is used to equivalently convert an analog signal to a digital signal. The successive asymptotic analog-to-digital converter performs the conversion by comparing and searching all possible quantization levels to obtain a digital output. Compared with general analog-to-digital converters, successive asymptotic analog-to-digital converters use less circuit area and corresponding cost. Although the progressive-to-analog analog-to-digital converter consumes less power, for some electronic devices with limited power, the power consumption of the progressive-to-analog-to-digital converter is still too high. In addition, the traditional successive asymptotic analog-to-digital converter has the disadvantages of nonlinearity and capacitance mismatch.

因此亟需提出一種新穎的循續漸近式類比至數位轉換器，其具有增強的線性度、功耗與電容匹配。Therefore, there is an urgent need to propose a novel continuous asymptotic analog-to-digital converter, which has enhanced linearity, power consumption and capacitance matching.

鑑於上述，本發明實施例的目的之一在於提出一種高線性度、低功耗與增強電容匹配的循續漸近式類比至數位轉換器。In view of the above, one of the objects of the embodiments of the present invention is to provide a successive asymptotic analog-to-digital converter with high linearity, low power consumption and enhanced capacitance matching.

本發明實施例提出一種循續漸近式類比至數位轉換器，用以產生n位元轉換輸出，該循續漸近式類比至數位轉換器包含第一電容數位至類比轉換器與第二電容數位至類比轉換器。於取樣階段，切換第一電容數位至類比轉換器與第二電容數位至類比轉換器的所有電容器至共電壓。於第一轉換階段，根據第一電容數位至類比轉換器與第二電容數位至類比轉換器的輸出信號的比較結果，以決定轉換輸出的第一最高有效位元。將第一電容數位至類比轉換器與第二電容數位至類比轉換器當中具有較大輸出信號者定義為較高電壓電容數位至類比轉換器，另一者定義為非切換電容數位至類比轉換器。切換較高電壓電容數位至類比轉換器的所有電容器至地，其中共電壓介於電源與地之間。於第m轉換階段(1＜m＜n)，根據第一電容數位至類比轉換器與第二電容數位至類比轉換器的輸出信號的比較結果，以決定轉換輸出的第m最高有效位元。根據較高電壓電容數位至類比轉換器與非切換電容數位至類比轉換器的輸出信號的比較結果，以切換非切換電容數位至類比轉換器的第m-1電容器。於第n轉換階段，根據第一電容數位至類比轉換器與第二電容數位至類比轉換器的輸出信號的比較結果，以決定轉換輸出的最低有效位元。An embodiment of the present invention provides a continuous asymptotic analog-to-digital converter for generating n-bit conversion output. The continuous asymptotic analog-to-digital converter includes a first capacitor digital-to-analog converter and a second capacitor digital-to Analog converter. During the sampling stage, all capacitors of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter are switched to a common voltage. In the first conversion stage, the first most significant bit of the conversion output is determined according to the comparison result of the output signals of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter. The first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter with a larger output signal are defined as higher voltage capacitor digital-to-analog converters, and the other is defined as a non-switching capacitor digital-to-analog converter. . Switch the higher voltage capacitor digital to all capacitors of the analog converter to ground, where the common voltage is between the power supply and ground. In the mth conversion stage (1<m<n), the mth most significant bit of the conversion output is determined according to the comparison result of the output signals of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter. According to the comparison result of the output signals of the higher voltage capacitor digital-to-analog converter and the non-switching capacitor digital-to-analog converter, the m-1th capacitor of the non-switching capacitor digital-to-analog converter is switched. In the nth conversion stage, the least significant bit of the conversion output is determined according to the comparison result of the output signals of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter.

第一圖顯示本發明實施例之高線性度與低功耗的循續漸近式類比至數位轉換器(successive approximation register analog-to-digital converter, SAR ADC)100的方塊圖。The first figure shows a block diagram of a successive approximation register analog-to-digital converter (SAR ADC) 100 with high linearity and low power consumption according to an embodiment of the present invention.

在本實施例中，循續漸近式類比至數位轉換器(以下簡稱類比至數位轉換器)100可包含第一電容數位至類比轉換器11A與第二電容數位至類比轉換器11B，分別接收第一輸入信號Vip(例如正輸入信號)與第二輸入信號Vin(例如負輸入信號)，用以分別產生第一輸出信號Vop(例如正輸出信號)與第二輸出信號Von(例如負輸出信號)。In this embodiment, the successive asymptotic analog-to-digital converter (hereinafter referred to as analog-to-digital converter) 100 may include a first capacitor digital-to-analog converter 11A and a second capacitor digital-to-analog converter 11B, respectively receiving the first An input signal Vip (such as a positive input signal) and a second input signal Vin (such as a negative input signal) for generating a first output signal Vop (such as a positive output signal) and a second output signal Von (such as a negative output signal) .

第二A圖顯示第一圖之第一電容數位至類比轉換器11A的電路。本實施例之類比至數位轉換器100可為n位元，第一電容數位至類比轉換器11A可包含n-1個電容器組成的陣列，其包含第一電容器、第二電容器…第(n-1)電容器。另外，額外的電容器Cd為雜散(parasitic)電容器，其連接至地且為不可切換。在n-1個電容器當中，較大序號(ordinal number)之電容器的電容值小於或等於較小序號之電容器的電容值。例如，從序號1至序號n-1之電容器的電容值分別為2^n-3 C、2^n-4 C…2² C、2¹ C、2¹ C，其中C為預設值，最後二個電容器具相同電容值。如第二A圖所例示，類比至數位轉換器100為5位元，第一電容數位至類比轉換器11A包含4個電容器C1至C4，其電容值依序為4C、2C、1C及1C。n-1個電容器的第一極板(plate)，例如上極板，可經由第一輸入開關SWip連接至第一輸入信號Vip。所有電容器的第二極板(例如下極板)經由相應開關(例如SW1至SW4)可分別切換至共電壓(common voltage)Vcm、電源Vdd或地Gnd，其中共電壓Vcm位於Vdd與Gnd的中間。The second diagram A shows the circuit of the first capacitor digital-to-analog converter 11A of the first diagram. The analog-to-digital converter 100 of this embodiment may be n-bit, and the first capacitor digital-to-analog converter 11A may include an array of n-1 capacitors, which includes a first capacitor, a second capacitor... 1) Capacitor. In addition, the additional capacitor Cd is a parasitic capacitor, which is connected to ground and is not switchable. Among the n-1 capacitors, the capacitance value of the capacitor with a larger ordinal number is less than or equal to the capacitance value of the capacitor with a smaller ordinal number. For example, the capacitance values of the capacitors from serial number 1 to serial number n-1 are 2 ^n-3 C, 2 ^n-4 C…2 ² C, 2 ¹ C, 2 ¹ C, where C is the preset value, the last two The capacitors have the same capacitance value. As illustrated in FIG. 2A, the analog-to-digital converter 100 is 5 bits, and the first capacitor digital-to-analog converter 11A includes four capacitors C1 to C4, and their capacitance values are 4C, 2C, 1C, and 1C in this order. A first plate of n-1 capacitors, such as an upper plate, may be connected to the first input signal Vip via a first input switch SWip. The second plates (eg lower plates) of all capacitors can be switched to common voltage Vcm, power supply Vdd or ground Gnd via corresponding switches (eg SW1 to SW4), wherein the common voltage Vcm is located between Vdd and Gnd .

類似的情形，第二B圖顯示第一圖之第二電容數位至類比轉換器11B的電路。本實施例之類比至數位轉換器100可為n位元，第二電容數位至類比轉換器11B可包含n-1個電容器組成的陣列，其包含第一電容器、第二電容器…第(n-1)電容器。另外，額外的電容器Cd為雜散電容器，其連接至地且為不可切換。在n-1個電容器當中，較大序號之電容器的電容值小於或等於較小序號之電容器的電容值。例如，從序號1至序號n-1之電容器的電容值分別為2^n-3 C、2^n-4 C…2² C、2¹ C、2¹ C，其中C為預設值，最後二個電容器具相同電容值。如第二A圖所例示，類比至數位轉換器100為5位元，第二電容數位至類比轉換器11B包含4個電容器C1至C4，其電容值依序為4C、2C、1C及1C。n-1個電容器的第一極板(例如上極板)可經由第二輸入開關SWin連接至第二輸入信號Vin。所有電容器的第二極板(例如下極板)經由相應開關(例如SW1至SW4)可分別切換至共電壓Vcm、電源Vdd或地Gnd，其中共電壓Vcm位於Vdd與Gnd的中間。In a similar situation, the second diagram B shows the circuit of the second capacitor digital-to-analog converter 11B of the first diagram. The analog-to-digital converter 100 of this embodiment may be n-bit, and the second capacitor digital-to-analog converter 11B may include an array of n-1 capacitors, which includes a first capacitor, a second capacitor... 1) Capacitor. In addition, the additional capacitor Cd is a stray capacitor, which is connected to ground and is not switchable. Among n-1 capacitors, the capacitance value of the capacitor with a larger serial number is less than or equal to the capacitance value of the capacitor with a smaller serial number. For example, the capacitance values of the capacitors from serial number 1 to serial number n-1 are 2 ^n-3 C, 2 ^n-4 C…2 ² C, 2 ¹ C, 2 ¹ C, where C is the preset value, the last two The capacitors have the same capacitance value. As illustrated in FIG. 2A, the analog-to-digital converter 100 is 5 bits, and the second capacitor digital-to-analog converter 11B includes four capacitors C1 to C4, and their capacitance values are 4C, 2C, 1C, and 1C in this order. The first plate (for example, the upper plate) of n-1 capacitors can be connected to the second input signal Vin via the second input switch SWin. The second plates (for example, the lower plates) of all capacitors can be switched to the common voltage Vcm, the power supply Vdd, or the ground Gnd via corresponding switches (for example, SW1 to SW4), where the common voltage Vcm is located between Vdd and Gnd.

參閱第一圖，本實施例之類比至數位轉換器100可包含比較器12(例如運算放大器(operational amplifier))，於比較器12的第一輸入節點(例如正(+)輸入節點)與第二輸入節點(例如負(-)輸入節點)分別接收第一輸出信號Vop與第二輸出信號Von。本實施例之類比至數位轉換器100可包含循續漸近式控制器13，其根據比較器12的比較輸出以產生轉換輸出Dout。循續漸近式控制器13更根據比較器12的比較輸出以控制第一電容數位至類比轉換器11A的開關(例如SW1至SW4)與第二電容數位至類比轉換器11B的開關(例如SW1至SW4)。Referring to the first figure, the analog-to-digital converter 100 of this embodiment may include a comparator 12 (such as an operational amplifier), a first input node (such as a positive (+) input node) and a Two input nodes (for example, a negative (-) input node) respectively receive the first output signal Vop and the second output signal Von. The analog-to-digital converter 100 of this embodiment may include a step-by-step controller 13 which generates a conversion output Dout according to the comparison output of the comparator 12. The step-by-step controller 13 further controls the switches of the first capacitor digital-to-analog converter 11A (such as SW1 to SW4) and the switches of the second capacitor digital-to-analog converter 11B (such as SW1 to SW4).

第三圖顯示本發明實施例之執行第一圖之循續漸近式類比至數位轉換器100的方法的流程圖。第四A圖至第九B圖例示於不同階段(phase)執行循續漸近式類比至數位轉換器100時，第一電容數位至類比轉換器11A與第二電容數位至類比轉換器11B的切換。第四A圖至第九B圖例示的5位元類比至數位轉換器100，第一電容數位至類比轉換器11A的電容器C1至C4的電容值分別為4C、2C、1C、1C，且第二電容數位至類比轉換器11B的電容器C1至C4的電容值分別為4C、2C、1C、1C。The third figure shows a flowchart of the method for performing the successive asymptotic analog-to-digital converter 100 of the first figure according to an embodiment of the present invention. FIGS. 4A to 9B illustrate the switching of the first capacitor digital-to-analog converter 11A and the second capacitor digital-to-analog converter 11B when the successive asymptotic analog-to-digital converter 100 is executed in different phases. . For the 5-bit analog-to-digital converter 100 illustrated in FIGS. 4A to 9B, the capacitance values of the capacitors C1 to C4 of the first capacitor digital-to-analog converter 11A are 4C, 2C, 1C, and 1C, respectively. The capacitance values of the capacitors C1 to C4 of the two-capacitance digital-to-analog converter 11B are 4C, 2C, 1C, and 1C, respectively.

於步驟31的取樣(sampling)階段，如第四A圖所示，第一電容數位至類比轉換器11A的所有電容器的第二極板經由相應開關切換至共電壓Vcm，且第二電容數位至類比轉換器11B的所有電容器的第二極板經由相應開關切換至共電壓Vcm。閉合第一輸入開關SWip因而將第一電容數位至類比轉換器11A的所有電容器的第一極板切換至第一輸入信號Vip，且閉合第二輸入開關SWin因而將第二電容數位至類比轉換器11B的所有電容器的第一極板切換至第二輸入信號Vin。第四B圖例示第一輸出信號Vop與第二輸出信號Von的波形。完成取樣階段(步驟31)後，接著依序執行n個轉換階段，以分別產生轉換輸出Dout的n位元。In the sampling stage of step 31, as shown in the fourth diagram A, the second plates of all capacitors of the first capacitor digital-to-analog converter 11A are switched to the common voltage Vcm via the corresponding switches, and the second capacitor digital The second plates of all capacitors of the analog converter 11B are switched to the common voltage Vcm via corresponding switches. Closing the first input switch SWip thus switches the first plates of all capacitors of the first capacitor digital-to-analog converter 11A to the first input signal Vip, and closing the second input switch SWin thus switches the second capacitor digital-to-analog converter The first plate of all capacitors of 11B is switched to the second input signal Vin. The fourth diagram B illustrates the waveforms of the first output signal Vop and the second output signal Von. After the sampling stage (step 31) is completed, n conversion stages are sequentially executed to generate n bits of the conversion output Dout, respectively.

於步驟32(轉換階段1)，如第五A圖所示，打開第一輸入開關SWip與第二輸入開關SWin。根據比較器12的比較輸出以決定轉換輸出Dout的第一最高有效位元(most significant bit, MSB)(亦即最左位元)位置的位元。例如，如果第一輸出信號Vop大於第二輸出信號Von，則決定第一最高有效位元位置的位元為“1”，否則決定為“0”。In step 32 (transition stage 1), as shown in the fifth diagram A, the first input switch SWip and the second input switch SWin are turned on. According to the comparison output of the comparator 12, the bit at the position of the first most significant bit (MSB) (that is, the leftmost bit) of the conversion output Dout is determined. For example, if the first output signal Vop is greater than the second output signal Von, the bit that determines the position of the first most significant bit is "1", otherwise it is determined to be "0".

接著，根據比較器12的比較輸出以決定第一電容數位至類比轉換器11A與第二電容數位至類比轉換器11B之間何者為較高電壓(higher-voltage)電容數位至類比轉換器。例如，如果第一輸出信號Vop大於第二輸出信號Von，則決定第一電容數位至類比轉換器11A為較高電壓電容數位至類比轉換器，否則決定第二電容數位至類比轉換器11B為較高電壓電容數位至類比轉換器。經由相應開關將較高電壓電容數位至類比轉換器(在這個例子中為第二電容數位至類比轉換器11B)的所有電容器的第二極板(從共電壓Vcm)切換至地Gnd，如第五圖所例示。第五B圖例示第一輸出信號Vop與第二輸出信號Von的波形。在本實施例中，相對於較高電壓電容數位至類比轉換器的另一個電容數位至類比轉換器定義為非切換(un-switching)電容數位至類比轉換器(在這個例子中為第一電容數位至類比轉換器11A)。Next, according to the comparison output of the comparator 12, it is determined whether the first capacitor digital-to-analog converter 11A and the second capacitor digital-to-analog converter 11B are higher-voltage capacitor digital-to-analog converters. For example, if the first output signal Vop is greater than the second output signal Von, the first capacitor digital-to-analog converter 11A is determined to be a higher voltage capacitor digital-to-analog converter, otherwise the second capacitor digital-to-analog converter 11B is determined to be High voltage capacitor digital to analog converter. Switch the second plates (from the common voltage Vcm) of all capacitors of the higher voltage capacitance digital-to-analog converter (in this example, the second capacitance digital-to-analog converter 11B) to the ground Gnd via the corresponding switches, as Illustrated in five figures. The fifth diagram B illustrates the waveforms of the first output signal Vop and the second output signal Von. In this embodiment, the other capacitor digital-to-analog converter relative to the higher voltage capacitor digital-to-analog converter is defined as an un-switching capacitor digital-to-analog converter (in this example, the first capacitor Digital-to-analog converter 11A).

在另一替代實施例中，於步驟32，經由相應開關將較低電壓(lower-voltage)電容數位至類比轉換器(在這個例子中為第一電容數位至類比轉換器11A)的所有電容器的第二極板(從共電壓Vcm)切換至電源Vdd。In another alternative embodiment, in step 32, all capacitors of the lower-voltage capacitor digital-to-analog converter (in this example, the first capacitor digital-to-analog converter 11A) are converted via corresponding switches The second plate (from the common voltage Vcm) is switched to the power supply Vdd.

於轉換階段2，如第六A圖所示，根據比較器12的比較輸出以決定轉換輸出Dout的第二最高有效位元(MSB)(亦即左邊第二位元)位置的位元。例如，如果第一輸出信號Vop大於第二輸出信號Von，則決定第二最高有效位元位置的位元為“1”，否則決定為“0”。接著，根據比較器12的比較輸出，經由相應開關對非切換電容數位至類比轉換器(在這個例子中為第一電容數位至類比轉換器11A)的第一電容器的第二極板進行切換。其中，如果非切換電容數位至類比轉換器的輸出信號大於較高電壓電容數位至類比轉換器的輸出信號，則切換至地Gnd，否則切換至電源Vdd，如第六A圖所示。第六B圖例示第一輸出信號Vop與第二輸出信號Von的波形。In the conversion phase 2, as shown in FIG. 6A, the bit at the position of the second most significant bit (MSB) (that is, the second left bit) of the conversion output Dout is determined according to the comparison output of the comparator 12. For example, if the first output signal Vop is greater than the second output signal Von, the bit that determines the position of the second most significant bit is "1", otherwise it is determined to be "0". Next, according to the comparison output of the comparator 12, the second plate of the first capacitor of the non-switched capacitance digital-to-analog converter (in this example, the first capacitance digital-to-analog converter 11A) is switched via the corresponding switch. Among them, if the output signal of the non-switching capacitor digital-to-analog converter is greater than the output signal of the higher voltage capacitor digital-to-analog converter, it is switched to ground Gnd, otherwise it is switched to the power supply Vdd, as shown in the sixth diagram A. The sixth diagram B illustrates the waveforms of the first output signal Vop and the second output signal Von.

類似的情形，於轉換階段3，如第七A圖所示，根據比較器12的比較輸出以決定轉換輸出Dout的第三最高有效位元(MSB)(亦即左邊第三位元)位置的位元。例如，如果第一輸出信號Vop大於第二輸出信號Von，則決定第三最高有效位元位置的位元為“1”，否則決定為“0”。接著，根據比較器12的比較輸出，經由相應開關對非切換電容數位至類比轉換器(在這個例子中為第一電容數位至類比轉換器11A)的第二電容器的第二極板進行切換。其中，如果非切換電容數位至類比轉換器的輸出信號大於較高電壓電容數位至類比轉換器的輸出信號，則切換至地Gnd，如第七A圖所示，否則切換至電源Vdd。第七B圖例示第一輸出信號Vop與第二輸出信號Von的波形。In a similar situation, in the conversion stage 3, as shown in FIG. 7A, the position of the third most significant bit (MSB) (that is, the third bit on the left) of the conversion output Dout is determined according to the comparison output of the comparator 12 Bit. For example, if the first output signal Vop is greater than the second output signal Von, the bit at the third most significant bit position is determined to be "1", otherwise it is determined to be "0". Next, according to the comparison output of the comparator 12, the second plate of the second capacitor of the non-switching capacitance digital-to-analog converter (in this example, the first capacitance digital-to-analog converter 11A) is switched via the corresponding switch. Among them, if the output signal of the non-switched capacitor digital-to-analog converter is greater than the output signal of the higher voltage capacitor digital-to-analog converter, it is switched to ground Gnd, as shown in the seventh diagram A, otherwise it is switched to the power supply Vdd. The seventh figure B illustrates the waveforms of the first output signal Vop and the second output signal Von.

類似的情形，於轉換階段4，如第八A圖所示，根據比較器12的比較輸出以決定轉換輸出Dout的第四最高有效位元(MSB)(亦即左邊第四位元)位置的位元。例如，如果第一輸出信號Vop大於第二輸出信號Von，則決定第四最高有效位元位置的位元為“1”，否則決定為“0”。接著，根據比較器12的比較輸出，經由相應開關對非切換電容數位至類比轉換器(在這個例子中為第一電容數位至類比轉換器11A)的第三電容器的第二極板進行切換。其中，如果非切換電容數位至類比轉換器的輸出信號大於較高電壓電容數位至類比轉換器的輸出信號，則切換至地Gnd，如第八A圖所示，否則切換至電源Vdd。第八B圖例示第一輸出信號Vop與第二輸出信號Von的波形。In a similar situation, in the conversion stage 4, as shown in Figure 8A, the position of the fourth most significant bit (MSB) (that is, the left fourth bit) of the conversion output Dout is determined according to the comparison output of the comparator 12 Bit. For example, if the first output signal Vop is greater than the second output signal Von, the bit that determines the fourth most significant bit position is "1", otherwise it is determined to be "0". Next, according to the comparison output of the comparator 12, the second plate of the third capacitor of the non-switching capacitance digital-to-analog converter (in this example, the first capacitance digital-to-analog converter 11A) is switched via the corresponding switch. Among them, if the output signal of the non-switched capacitor digital-to-analog converter is greater than the output signal of the higher voltage capacitor digital-to-analog converter, it is switched to ground Gnd, as shown in Figure 8A, otherwise it is switched to the power supply Vdd. The eighth B diagram illustrates the waveforms of the first output signal Vop and the second output signal Von.

一般來說，於轉換階段m(1＜m＜n)，根據比較器12的比較輸出以決定轉換輸出Dout的第m最高有效位元(MSB)位置的位元。例如，如果第一輸出信號Vop大於第二輸出信號Von，則決定第m最高有效位元位置的位元為“1”，否則決定為“0”。接著，根據比較器12的比較輸出，經由相應開關對非切換電容數位至類比轉換器的第m-1電容器的第二極板進行切換。其中，如果非切換電容數位至類比轉換器的輸出信號大於較高電壓電容數位至類比轉換器的輸出信號，則切換至地Gnd，否則切換至電源Vdd。Generally speaking, at the conversion stage m (1<m<n), the bit at the mth most significant bit (MSB) position of the conversion output Dout is determined according to the comparison output of the comparator 12. For example, if the first output signal Vop is greater than the second output signal Von, the bit at the m-th most significant bit position is determined to be "1", otherwise it is determined to be "0". Next, according to the comparison output of the comparator 12, the second plate of the m-1th capacitor of the non-switching capacitor digital-to-analog converter is switched via the corresponding switch. Among them, if the output signal of the non-switching capacitor digital-to-analog converter is greater than the output signal of the higher voltage capacitor digital-to-analog converter, it is switched to ground Gnd, otherwise it is switched to the power supply Vdd.

於步驟34(轉換階段5、轉換階段n或最終轉換階段)，如第九A圖所示，根據比較器12的比較輸出以決定轉換輸出Dout的最低有效位元(least significant bit, LSB)(亦即最右邊位元)位置的位元。例如，如果第一輸出信號Vop大於第二輸出信號Von，則決定最低有效位元位置的位元為“1”，否則決定為“0”。在本步驟中，不需如先前步驟對電容器進行切換。第九B圖例示第一輸出信號Vop與第二輸出信號Von的波形。In step 34 (conversion stage 5, conversion stage n or final conversion stage), as shown in the ninth A diagram, the least significant bit (LSB) of the conversion output Dout is determined according to the comparison output of the comparator 12 ( That is, the bit at the rightmost bit) position. For example, if the first output signal Vop is greater than the second output signal Von, the bit that determines the least significant bit position is "1", otherwise it is determined to be "0". In this step, there is no need to switch the capacitor as in the previous step. The ninth B diagram illustrates the waveforms of the first output signal Vop and the second output signal Von.

上述實施例可應用於其他演算法，例如偵測並跳過(detect-and-skip, DAS)演算法。在一例子中，使用前述實施例以轉換n位元的前面數個位元，因此得到電容數位至類比轉換器因不精確所產生的誤差，將其儲存於查表(lookup table)或實施為邏輯電路。根據所得到的誤差，執行偵測並跳過(DAS)演算法以轉換n位元的其他後面數個位元。有關偵測並跳過(DAS)演算法的細節可參閱戴宏言(Hung-Yen Tai的音譯)等人所提出之“以40奈米互補式金屬氧化半導體的0.85fJ/轉換步驟10b 200kS/s次區循續漸近式類比至數位轉換器(A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS)”，發表於電機電子工程師學會國際固態電路會議(IEEE International Solid-State Circuits Conference)，2014年，其內容視為本說明書的一部份。The above embodiments can be applied to other algorithms, such as a detect-and-skip (DAS) algorithm. In one example, the foregoing embodiment is used to convert the first few bits of n bits, so the error caused by the inaccuracy of the digital-to-analog converter of capacitance is stored in a lookup table or implemented as Logic circuit. Based on the obtained error, a detection and skip (DAS) algorithm is executed to convert the n-bits of the remaining bits. For details of the detection and skip (DAS) algorithm, please refer to the "transformation step of 40nm nanometer complementary metal oxide semiconductor 0.85fJ/ conversion step 10b 200kS/s times" proposed by Dai Hongyan (transliteration of Hung-Yen Tai) and others Zone successive asymptotic analog-to-digital converter (A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS)", published at the IEEE International Solid-State Circuits Conference In 2014, its content was regarded as part of this manual.

以上所述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離發明所揭示之精神下所完成之等效改變或修飾，均應包含在下述之申請專利範圍內。The above are only the preferred embodiments of the present invention and are not intended to limit the scope of the patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit of the invention should be included in the following Within the scope of patent application.

100:循續漸近式類比至數位轉換器11A:第一電容數位至類比轉換器11B:第二電容數位至類比轉換器12:比較器13:循續漸近式控制器31:取樣階段32:(轉換階段1)切換較高電壓電容數位至類比轉換器的所有電容器33:(轉換階段m)對非切換電容數位至類比轉換器的第m-1電容器進行切換34:轉換階段nVip:第一輸入信號Vin:第二輸入信號Vop:第一輸出信號Von:第二輸出信號Dout:轉換輸出Vdd:電源Vcm:共電壓Gnd:地C1~C4:電容器Cd:電容器SWip:第一輸入開關SWin:第二輸入開關SW1~SW4:開關100: Continuous asymptotic analog-to-digital converter 11A: First capacitor digital-to-analog converter 11B: Second capacitor digital-to-analog converter 12: Comparator 13: Continuous asymptotic controller 31: Sampling stage 32: ( Conversion stage 1) Switch all capacitors of the higher voltage capacitor digital to the analog converter 33: (Conversion stage m) Switch the m-1th capacitor of the non-switching capacitor digital to analog converter 34: Conversion stage nVip: First input Signal Vin: Second input signal Vop: First output signal Von: Second output signal Dout: Conversion output Vdd: Power supply Vcm: Common voltage Gnd: Ground C1~C4: Capacitor Cd: Capacitor SWip: First input switch SWin: No. Two input switches SW1~SW4: switch

第一圖顯示本發明實施例之高線性度與低功耗的循續漸近式類比至數位轉換器(SAR ADC)的方塊圖。第二A圖顯示第一圖之第一電容數位至類比轉換器的電路。第二B圖顯示第一圖之第二電容數位至類比轉換器的電路。第三圖顯示本發明實施例之執行第一圖之循續漸近式類比至數位轉換器的方法的流程圖。第四A圖至第九B圖例示於不同階段執行循續漸近式類比至數位轉換器時，第一電容數位至類比轉換器與第二電容數位至類比轉換器的切換。The first figure shows a block diagram of a high linearity and low power continuous asymptotic analog-to-digital converter (SAR ADC) according to an embodiment of the present invention. The second diagram A shows the circuit of the first capacitor digital-to-analog converter of the first diagram. The second figure B shows the circuit of the second capacitor digital-to-analog converter of the first figure. The third figure shows a flowchart of a method for performing the successive asymptotic analog-to-digital converter of the first figure according to an embodiment of the present invention. FIGS. 4A to 9B illustrate the switching of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter when the successive asymptotic analog-to-digital converter is executed at different stages.

31:取樣階段 31: Sampling stage

32:(轉換階段1)切換較高電壓電容數位至類比轉換器的所有電容器 32: (Conversion Phase 1) Switch all the capacitors of the higher voltage capacitor to all capacitors of the analog converter

33:(轉換階段m)對非切換電容數位至類比轉換器的第m-1電容器進行切換 33: (Conversion stage m) Switch the m-1th capacitor of the non-switching capacitor digital to analog converter

34:轉換階段n 34: Conversion stage n

Claims

一種高線性度的循續漸近式類比至數位轉換器，用以產生n位元轉換輸出，包含：一第一電容數位至類比轉換器；及一第二電容數位至類比轉換器；其中於取樣階段，切換該第一電容數位至類比轉換器與該第二電容數位至類比轉換器的所有電容器至共電壓；於第一轉換階段，根據該第一電容數位至類比轉換器與該第二電容數位至類比轉換器的輸出信號的比較結果，以決定該轉換輸出的第一最高有效位元；將該第一電容數位至類比轉換器與該第二電容數位至類比轉換器當中具有較大輸出信號者定義為較高電壓電容數位至類比轉換器，另一者定義為非切換電容數位至類比轉換器；切換該較高電壓電容數位至類比轉換器的所有電容器至地，其中共電壓介於電源與地之間；於第m轉換階段(1＜m＜n)，根據該第一電容數位至類比轉換器與該第二電容數位至類比轉換器的輸出信號的比較結果，以決定該轉換輸出的第m最高有效位元；根據該較高電壓電容數位至類比轉換器與該非切換電容數位至類比轉換器的輸出信號的比較結果，以切換該非切換電容數位至類比轉換器的第m-1電容器；及於第n轉換階段，根據該第一電容數位至類比轉換器與該第二電容數位至類比轉換器的輸出信號的比較結果，以決定該轉換輸出的最低有效位元。A high linearity successive asymptotic analog-to-digital converter for generating n-bit conversion output, including: a first capacitor digital-to-analog converter; and a second capacitor digital-to-analog converter; where in sampling In the stage, switch all capacitors of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter to a common voltage; In the first conversion stage, according to the first capacitor digital-to-analog converter and the second capacitor The comparison result of the output signal of the digital-to-analog converter to determine the first most significant bit of the conversion output; the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter have a larger output The signal receiver is defined as a higher-voltage capacitor digital-to-analog converter, and the other is defined as a non-switching capacitor digital-to-analog converter; switching all capacitors of the higher-voltage capacitor digital-to-analog converter to ground, where the common voltage is between Between the power supply and ground; at the mth conversion stage (1<m<n), the conversion result is determined according to the output signal of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter The mth most significant bit of the output; according to the comparison result of the output signal of the higher voltage capacitor digital-to-analog converter and the non-switching capacitor digital-to-analog converter, to switch the m-th of the non-switching capacitor digital-to-analog converter 1 capacitor; and In the nth conversion stage, the least significant bit of the conversion output is determined according to the comparison result of the output signals of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter.

根據申請專利範圍第1項所述高線性度的循續漸近式類比至數位轉換器，其中該第一電容數位至類比轉換器包含n-1個電容器，其電容值從序號1至n-1依序為2^n-3 C、2^n-4 C…2² C、2¹ C、2¹ C，其中C為預設值。According to the high linearity step-by-step analogue-to-digital converter described in item 1 of the patent application range, wherein the first capacitor digital-to-analog converter contains n-1 capacitors with capacitance values from serial numbers 1 to n-1 In order: 2 ^n-3 C, 2 ^n-4 C... 2 ² C, 2 ¹ C, 2 ¹ C, where C is the default value.

根據申請專利範圍第1項所述高線性度的循續漸近式類比至數位轉換器，其中該第二電容數位至類比轉換器包含n-1個電容器，其電容值從序號1至n-1依序為2^n-3 C、2^n-4 C…2² C、2¹ C、2¹ C，其中C為預設值。According to the high linearity step-by-step analogue-to-digital converter described in item 1 of the patent application range, wherein the second capacitor digital-to-analog converter contains n-1 capacitors with capacitance values from serial numbers 1 to n-1 In order: 2 ^n-3 C, 2 ^n-4 C... 2 ² C, 2 ¹ C, 2 ¹ C, where C is the default value.

根據申請專利範圍第1項所述高線性度的循續漸近式類比至數位轉換器，其中如果該第一電容數位至類比轉換器的輸出信號大於該第二電容數位至類比轉換器的輸出信號，則決定該轉換輸出的第一最高有效位元為“1”，否則決定為“0”。The high linearity progressive asymptotic analog-to-digital converter according to item 1 of the patent application scope, wherein if the output signal of the first capacitor digital-to-analog converter is greater than the output signal of the second capacitor digital-to-analog converter , The first most significant bit of the conversion output is determined to be "1", otherwise it is determined to be "0".

根據申請專利範圍第1項所述高線性度的循續漸近式類比至數位轉換器，其中如果該第一電容數位至類比轉換器的輸出信號大於該第二電容數位至類比轉換器的輸出信號，則決定該轉換輸出的第m最高有效位元為“1”，否則決定為“0”。The high linearity progressive asymptotic analog-to-digital converter according to item 1 of the patent application scope, wherein if the output signal of the first capacitor digital-to-analog converter is greater than the output signal of the second capacitor digital-to-analog converter , The m-th most significant bit of the conversion output is determined to be "1", otherwise it is determined to be "0".

根據申請專利範圍第1項所述高線性度的循續漸近式類比至數位轉換器，其中如果該非切換電容數位至類比轉換器的輸出信號大於該較高電壓電容數位至類比轉換器的輸出信號，則將該非切換電容數位至類比轉換器的第m-1電容器切換至地，否則切換至電源。The high linearity progressive asymptotic analog-to-digital converter according to item 1 of the patent application scope, wherein if the output signal of the non-switching capacitor digital-to-analog converter is greater than the output signal of the higher voltage capacitor digital-to-analog converter , Then switch the m-1th capacitor of the non-switched capacitor digital-to-analog converter to ground, otherwise switch to the power supply.

根據申請專利範圍第1項所述高線性度的循續漸近式類比至數位轉換器，其中如果該第一電容數位至類比轉換器的輸出信號大於該第二電容數位至類比轉換器的輸出信號，則決定該轉換輸出的最低有效位元為“1”，否則決定為“0”。The high linearity progressive asymptotic analog-to-digital converter according to item 1 of the patent application scope, wherein if the output signal of the first capacitor digital-to-analog converter is greater than the output signal of the second capacitor digital-to-analog converter , The least significant bit of the conversion output is determined to be "1", otherwise it is determined to be "0".

根據申請專利範圍第1項所述高線性度的循續漸近式類比至數位轉換器，更包含：根據所產生的該n位元轉換輸出，以執行偵測並跳過演算法。According to the high linearity step-by-step analogue-to-digital converter described in item 1 of the patent scope, it further includes: according to the n-bit conversion output generated to perform detection and skip the algorithm.

根據申請專利範圍第1項所述高線性度的循續漸近式類比至數位轉換器，其中於該取樣階段，該第一電容數位至類比轉換器取樣正輸入信號，且該第二電容數位至類比轉換器取樣負輸入信號。According to the high linearity step-by-step analogue-to-digital converter described in item 1 of the patent application range, in the sampling stage, the first capacitor digital-to-analog converter samples the positive input signal, and the second capacitor digital-to The analog converter samples the negative input signal.

根據申請專利範圍第1項所述高線性度的循續漸近式類比至數位轉換器，更包含一比較器，接收該第一電容數位至類比轉換器的輸出信號與該第二電容數位至類比轉換器的輸出信號。According to the high linearity step-by-step analog-to-digital converter described in item 1 of the patent scope, it further includes a comparator that receives the output signal of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog The output signal of the converter.

一種高線性度的循續漸近式類比至數位轉換器，用以產生n位元轉換輸出，包含：一第一電容數位至類比轉換器；及一第二電容數位至類比轉換器；其中於取樣階段，切換該第一電容數位至類比轉換器與該第二電容數位至類比轉換器的所有電容器至共電壓；於第一轉換階段，根據該第一電容數位至類比轉換器與該第二電容數位至類比轉換器的輸出信號的比較結果，以決定該轉換輸出的第一最高有效位元；將該第一電容數位至類比轉換器與該第二電容數位至類比轉換器當中具有較小輸出信號者定義為較低電壓電容數位至類比轉換器，另一者定義為非切換電容數位至類比轉換器；切換該較低電壓電容數位至類比轉換器的所有電容器至電源，其中共電壓介於電源與地之間；於第m轉換階段(1＜m＜n)，根據該第一電容數位至類比轉換器與該第二電容數位至類比轉換器的輸出信號的比較結果，以決定該轉換輸出的第m最高有效位元；根據該較低電壓電容數位至類比轉換器與該非切換電容數位至類比轉換器的輸出信號的比較結果，以切換該非切換電容數位至類比轉換器的第m-1電容器；及於第n轉換階段，根據該第一電容數位至類比轉換器與該第二電容數位至類比轉換器的輸出信號的比較結果，以決定該轉換輸出的最低有效位元。A high linearity successive asymptotic analog-to-digital converter for generating n-bit conversion output, including: a first capacitor digital-to-analog converter; and a second capacitor digital-to-analog converter; where in sampling In the stage, switch all capacitors of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter to a common voltage; In the first conversion stage, according to the first capacitor digital-to-analog converter and the second capacitor The comparison result of the output signal of the digital-to-analog converter to determine the first most significant bit of the conversion output; the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter have a smaller output The signal receiver is defined as a lower voltage capacitor digital-to-analog converter, and the other is defined as a non-switching capacitor digital-to-analog converter; switching all capacitors of the lower voltage capacitor digital-to-analog converter to the power supply, where the total voltage is between Between the power supply and ground; at the mth conversion stage (1<m<n), the conversion result is determined according to the output signal of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter The mth most significant bit of the output; according to the comparison result of the output signal of the lower voltage capacitor digital-to-analog converter and the non-switching capacitor digital-to-analog converter, to switch the m-th of the non-switching capacitor digital-to-analog converter 1 capacitor; and In the nth conversion stage, the least significant bit of the conversion output is determined according to the comparison result of the output signals of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter.

根據申請專利範圍第11項所述高線性度的循續漸近式類比至數位轉換器，其中如果該非切換電容數位至類比轉換器的輸出信號大於該較低電壓電容數位至類比轉換器的輸出信號，則將該非切換電容數位至類比轉換器的第m-1電容器切換至地，否則切換至電源。The high linearity progressive asymptotic analog-to-digital converter according to item 11 of the patent application scope, wherein if the output signal of the non-switching capacitor digital-to-analog converter is greater than the output signal of the lower voltage capacitor digital-to-analog converter , Then switch the m-1th capacitor of the non-switched capacitor digital-to-analog converter to ground, otherwise switch to the power supply.