TW202020842A - Display panel - Google Patents
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- TW202020842A TW202020842A TW107141101A TW107141101A TW202020842A TW 202020842 A TW202020842 A TW 202020842A TW 107141101 A TW107141101 A TW 107141101A TW 107141101 A TW107141101 A TW 107141101A TW 202020842 A TW202020842 A TW 202020842A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
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Abstract
Description
本揭示文件有關一種顯示面板,尤指一種具有耦接於多個畫素電路之補償電路的顯示面板。 This disclosure relates to a display panel, in particular to a display panel having a compensation circuit coupled to multiple pixel circuits.
低溫多晶矽薄膜電晶體(low temperature poly-silicon thin-film transistor)具有高載子遷移率與尺寸小的特點,適合應用於高解析度、窄邊框以及低耗電的顯示面板。目前業界廣泛使用準分子雷射退火(excimer laser annealing)技術來形成低溫多晶矽薄膜電晶體的多晶矽薄膜。然而,由於準分子雷射每一發的掃描功率並不穩定,不同區域的多晶矽薄膜會具有晶粒尺寸與數量的差異。因此,於顯示面板的不同區域中,低溫多晶矽薄膜電晶體的特性便會不同。例如,不同區域的低溫多晶矽薄膜電晶體會有著不同的臨界電壓(threshold voltage)。 Low temperature poly-silicon thin-film transistor (low temperature poly-silicon thin-film transistor) has the characteristics of high carrier mobility and small size, suitable for high resolution, narrow frame and low power consumption display panel. At present, the industry widely uses excimer laser annealing (excimer laser annealing) technology to form polysilicon thin films of low-temperature polysilicon thin film transistors. However, since the scanning power of each shot of the excimer laser is not stable, the polycrystalline silicon films in different regions will have differences in grain size and number. Therefore, in different areas of the display panel, the characteristics of the low-temperature polysilicon thin film transistor will be different. For example, low-temperature polysilicon thin film transistors in different regions will have different threshold voltages.
目前業界廣泛使用畫素內補償之技術方案,以克服上述臨界電壓變異的問題。然而,具有畫素內補償功能之畫素電路具有複雜之電路結構,使得相關之顯示面板的開口率低下。 At present, the industry widely uses the technical solution of intra-pixel compensation to overcome the above-mentioned critical voltage variation problem. However, the pixel circuit with the internal pixel compensation function has a complicated circuit structure, so that the aperture ratio of the related display panel is low.
有鑑於此,如何提供高開口率且可補償薄膜電 晶體的臨界電壓變異之顯示面板,實為業界有待解決的問題。 In view of this, how to provide high aperture ratio and can compensate for thin film The display panel with the variation of the critical voltage of the crystal is really a problem to be solved in the industry.
本揭示文件提供一種顯示面板,顯示面板包含多個畫素電路和一補償電路。多個畫素電路位於一顯示區。補償電路位於一非顯示區,且耦接於多個畫素電路中的部分畫素電路。補償電路包含一第一開關、一第二開關和一匹配電晶體。第一開關包含一第一端、一第二端和一控制端,第一開關的第一端用於接收一預設高電壓,第一開關的第二端耦接於一第一節點,第一開關的控制端用於接收一第一控制訊號。第二開關包含一第一端、一第二端和一控制端,第二開關的第一端耦接於一第二節點,第二開關的第二端耦接於第一節點,第二開關的控制端用於接收一第二控制訊號。匹配電晶體包含一第一端、一第二端和一控制端,匹配電晶體的第一端用於接收一預設低電壓,匹配電晶體的第二端耦接於第二節點,匹配電晶體的控制端用於接收一參考電壓。其中,補償電路用於透過第一節點選擇性地輸出預設高電壓或匹配電晶體的一臨界電壓至部分畫素電路。 The present disclosure provides a display panel. The display panel includes a plurality of pixel circuits and a compensation circuit. Multiple pixel circuits are located in a display area. The compensation circuit is located in a non-display area and is coupled to a part of the pixel circuits among the plurality of pixel circuits. The compensation circuit includes a first switch, a second switch, and a matching transistor. The first switch includes a first terminal, a second terminal, and a control terminal. The first terminal of the first switch is used to receive a predetermined high voltage. The second terminal of the first switch is coupled to a first node. The control end of a switch is used to receive a first control signal. The second switch includes a first terminal, a second terminal and a control terminal, the first terminal of the second switch is coupled to a second node, the second terminal of the second switch is coupled to the first node, and the second switch The control end of is used to receive a second control signal. The matching transistor includes a first terminal, a second terminal, and a control terminal. The first terminal of the matching transistor is used to receive a predetermined low voltage. The second terminal of the matching transistor is coupled to the second node. The control terminal of the crystal is used to receive a reference voltage. The compensation circuit is used to selectively output a predetermined high voltage or a threshold voltage matching the transistor to some pixel circuits through the first node.
本揭示文件提供另一種顯示面板,顯示面板包含多個畫素電路和一補償電路。多個畫素電路位於一顯示區。補償電路位於一非顯示區,且耦接於多個畫素電路中的部分畫素電路。補償電路包含一電流源電路和一匹配電晶體。電流源電路用於輸出一參考電流至一第六節點。匹配電 晶體包含一第一端、一第二端和一控制端,匹配電晶體的第一端耦接於第六節點,匹配電晶體的第二端和控制端用於接收一參考電壓。其中,當匹配電晶體接收到參考電流時,補償電路透過第六節點將匹配電晶體的一臨界電壓輸出至部分畫素電路。 This disclosure provides another display panel. The display panel includes a plurality of pixel circuits and a compensation circuit. Multiple pixel circuits are located in a display area. The compensation circuit is located in a non-display area and is coupled to a part of the pixel circuits among the plurality of pixel circuits. The compensation circuit includes a current source circuit and a matching transistor. The current source circuit is used to output a reference current to a sixth node. Matching The crystal includes a first terminal, a second terminal and a control terminal. The first terminal of the matching transistor is coupled to the sixth node. The second terminal and the control terminal of the matching transistor are used to receive a reference voltage. Wherein, when the matching transistor receives the reference current, the compensation circuit outputs a critical voltage of the matching transistor to the partial pixel circuit through the sixth node.
本揭示文件提供又一種顯示面板,顯示面板包含多個畫素電路和一補償電路。多個畫素電路位於一顯示區。補償電路位於一非顯示區,且耦接於多個畫素電路中的部分畫素電路。補償電路包含一匹配電晶體和一電流源電路。匹配電晶體包含一第一端、一第二端和一控制端,匹配電晶體的第一端用於接收一參考電壓,匹配電晶體的第二端和控制端耦接於一第十節點。電流源電路耦接於第十節點,用於自匹配電晶體抽取一參考電流。其中,當參考電流流經匹配電晶體時,補償電路透過第十節點將匹配電晶體的一臨界電壓輸出至部分畫素電路。 The present disclosure provides yet another display panel. The display panel includes a plurality of pixel circuits and a compensation circuit. Multiple pixel circuits are located in a display area. The compensation circuit is located in a non-display area and is coupled to a part of the pixel circuits among the plurality of pixel circuits. The compensation circuit includes a matching transistor and a current source circuit. The matching transistor includes a first terminal, a second terminal, and a control terminal. The first terminal of the matching transistor is used to receive a reference voltage. The second terminal and the control terminal of the matching transistor are coupled to a tenth node. The current source circuit is coupled to the tenth node and used to extract a reference current from the matched transistor. Wherein, when the reference current flows through the matching transistor, the compensation circuit outputs a critical voltage of the matching transistor to the partial pixel circuit through the tenth node.
上述的顯示面板在驅動電晶體具有臨界電壓變異的情況下,仍可以提供均勻的顯示畫面。 The above-mentioned display panel can still provide a uniform display picture even when the driving transistor has a critical voltage variation.
100、500、900‧‧‧顯示面板 100, 500, 900 ‧‧‧ display panel
110、510、910‧‧‧畫素電路 110, 510, 910‧‧‧ pixel circuit
120‧‧‧源極驅動器 120‧‧‧ source driver
130‧‧‧閘極驅動器 130‧‧‧Gate driver
140、540、940‧‧‧補償電路 140, 540, 940‧‧‧ Compensation circuit
150‧‧‧顯示區 150‧‧‧Display area
160‧‧‧非顯示區 160‧‧‧non-display area
210、610、1010‧‧‧匹配電晶體 210, 610, 1010‧‧‧ matching transistor
220、620、1020‧‧‧驅動電晶體 220, 620, 1020‧‧‧ drive transistor
230、630、1030‧‧‧發光單元 230, 630, 1030‧‧‧ light unit
CS‧‧‧電流源電路 CS‧‧‧Current source circuit
C1~C5‧‧‧第一電容~第五電容 C1~C5‧‧‧First capacitor~Fifth capacitor
CT1~CT3‧‧‧第一控制訊號~第三控制訊號 CT1~CT3‧‧‧‧ First control signal~ Third control signal
SW1~SW10‧‧‧第一開關~第十開關 SW1~SW10‧‧‧First switch~Tenth switch
N1~N13‧‧‧第一節點~第十三節點 N1~N13‧‧‧First node~Thirteenth node
VDD‧‧‧預設高電壓 VDD‧‧‧ preset high voltage
VSS‧‧‧預設低電壓 VSS‧‧‧ preset low voltage
Vref‧‧‧參考電壓 Vref‧‧‧Reference voltage
Vdata‧‧‧資料電壓 Vdata‧‧‧Data voltage
VE‧‧‧致能準位 VE‧‧‧Enable level
VS‧‧‧禁能準位 VS‧‧‧Enable level
Idri‧‧‧驅動電流 Idri‧‧‧Drive current
Iref‧‧‧參考電流 Iref‧‧‧Reference current
T1‧‧‧補償階段 T1‧‧‧ compensation stage
T2‧‧‧寫入階段 T2‧‧‧ Writing stage
T3‧‧‧發光階段 T3‧‧‧Lighting stage
為讓揭示文件之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下:第1圖為根據本揭示文件一實施例的顯示面板簡化後的功能方塊圖。 In order to make the above and other objects, features, advantages and embodiments of the disclosed document more obvious and understandable, the drawings are described as follows: FIG. 1 is a simplified functional block diagram of a display panel according to an embodiment of the disclosed document .
第2圖為第1圖的顯示面板放大後的局部示意圖。 FIG. 2 is a partial schematic view of the display panel of FIG. 1 after being enlarged.
第3圖為第1圖的顯示面板的一運作實施例的時序變化圖。 FIG. 3 is a timing chart of an operation example of the display panel of FIG. 1.
第4A~4C圖為第1圖的顯示面板的局部等效電路示意圖。 4A to 4C are schematic diagrams of partial equivalent circuits of the display panel of FIG. 1.
第5圖為根據本揭示文件另一實施例的顯示面板簡化後的功能方塊圖。 FIG. 5 is a simplified functional block diagram of a display panel according to another embodiment of the present disclosure.
第6圖為第5圖的顯示面板放大後的局部示意圖。 FIG. 6 is a partial schematic diagram of the display panel of FIG. 5 after being enlarged.
第7圖為第5圖的顯示面板的一運作實施例的時序變化圖。 FIG. 7 is a timing chart of an operation example of the display panel of FIG. 5.
第8A~8C圖為第5圖的顯示面板的局部等效電路示意圖。 8A to 8C are schematic diagrams of partial equivalent circuits of the display panel of FIG. 5.
第9圖為根據本揭示文件又一實施例的顯示面板簡化後的功能方塊圖。 FIG. 9 is a simplified functional block diagram of a display panel according to another embodiment of the present disclosure.
第10圖為第9圖的顯示面板放大後的局部示意圖。 FIG. 10 is a partial schematic view of the display panel of FIG. 9 after being enlarged.
第11圖為第9圖的顯示面板的一運作實施例的時序變化圖。 FIG. 11 is a timing chart of an operation example of the display panel of FIG. 9.
第12A~12B圖為第9圖的顯示面板的局部等效電路示意圖。 12A-12B are partial equivalent circuit diagrams of the display panel of FIG. 9.
以下將配合相關圖式來說明本揭露文件的實施例。在圖式中,相同的標號表示相同或類似的元件或方法流程。 The following will describe embodiments of the disclosed document in conjunction with related drawings. In the drawings, the same reference numerals indicate the same or similar elements or method flows.
第1圖為根據本揭示文件一實施例的顯示面板
100簡化後的功能方塊圖。顯示面板100包含多個畫素電路110、源極驅動器120、閘極驅動器130以及多個補償電路140。顯示面板100還包含顯示區150和非顯示區160,其中多個畫素電路110位於顯示區150內,而多個補償電路140則位於非顯示區160內。
Figure 1 is a display panel according to an embodiment of the
在如第1圖所示,每個補償電路140對應耦接於顯示面板100的一列的畫素電路110。亦即,每個補償電路140耦接於前述多個畫素電路110中的部分畫素電路110。為使圖面簡潔而易於說明,顯示面板100中的其他元件與連接關係並未繪示於第1圖中。
As shown in FIG. 1, each
第2圖為第1圖的顯示面板100放大後的局部示意圖。如第2圖所示,補償電路140包含第一開關SW1、第二開關SW2和匹配電晶體210。第一開關SW1包含第一端、第二端和控制端,其中第一開關SW1的第一端用於接收預設高電壓VDD,第一開關SW1的第二端耦接於第一節點N1,第一開關SW1的控制端則用於接收第一控制訊號CT1。第二開關SW2包含第一端、第二端和控制端,第二開關SW2的第一端耦接於第二節點N2,第二開關SW2的第二端耦接於第一節點N1,第二開關SW2的控制端則用於接收第二控制訊號CT2。
FIG. 2 is a partial schematic view of the
匹配電晶體210包含第一端、第二端和控制端,匹配電晶體210的第一端用於接收預設低電壓VSS,匹配電晶體210的第二端耦接於第二節點N2,匹配電晶體210的控制端則用於接收參考電壓Vref。
The matching
畫素電路110包含驅動電晶體220、第三開關SW3、第四開關SW4、第一電容C1、第二電容C2以及發光單元230。驅動電晶體220包含第一端、第二端和控制端,驅動電晶體220的第一端耦接於第一節點N1,驅動電晶體220的第二端耦接於第三節點N3,驅動電晶體220的控制端耦接於第四節點N4。
The
第三開關SW3包含第一端、第二端和控制端,其中第三開關SW3的第一端用於接收資料電壓Vdata,第三開關SW3的第二端耦接於第四節點N4,第三開關SW3的控制端則用於接收第三控制訊號CT3。第四開關SW4包含第一端、第二端和控制端,第四開關SW4的第一端用於接收預設低電壓VSS,第四開關SW4的第二端耦接於第五節點N5,第四開關SW4的控制端則用於接收第二控制訊號CT2。 The third switch SW3 includes a first terminal, a second terminal, and a control terminal. The first terminal of the third switch SW3 is used to receive the data voltage Vdata. The second terminal of the third switch SW3 is coupled to the fourth node N4. The control terminal of the switch SW3 is used to receive the third control signal CT3. The fourth switch SW4 includes a first terminal, a second terminal, and a control terminal. The first terminal of the fourth switch SW4 is used to receive a preset low voltage VSS, and the second terminal of the fourth switch SW4 is coupled to the fifth node N5. The control terminal of the four switches SW4 is used to receive the second control signal CT2.
第一電容C1耦接於第一節點N1和第五節點N5之間,且第二電容C2耦接於第四節點N4和第五節點N5之間。發光單元230包含陰極端和陽極端,其中陰極端用於接收預設低電壓VSS,而陽極端則耦接於第三節點N3。
The first capacitor C1 is coupled between the first node N1 and the fifth node N5, and the second capacitor C2 is coupled between the fourth node N4 and the fifth node N5. The
在本實施例中,補償電路140和補償電路140耦接的一列畫素電路110,是位於由同一道或相近的多道準分子雷射所形成的多晶矽薄膜區域中。因此,補償電路140的匹配電晶體210的臨界電壓,會相同或幾乎相同於補償電路140所耦接的一列畫素電路110的驅動電晶體220的臨界電壓。
In this embodiment, the
另外,匹配電晶體210、驅動電晶體220、第一
開關SW1、第二開關SW2、第三開關SW3和第四開關SW4可由P型電晶體來實現。發光單元230可以用有機發光二極體(organic light-emitting diode)或是微發光二極體(micro LED)等等發光材料來實現。
In addition, the matching
補償電路140會透過第一節點N1選擇性地輸出匹配電晶體210的臨界電壓或是預設高電壓VDD至補償電路140所耦接的畫素電路110,以補償不同畫素電路110的驅動電晶體220的臨界電壓變異。以下將以第2圖搭配第3圖來進一步說明補償電路140和畫素電路110之配合運作。
The
於補償階段T1中,第一控制訊號CT1和第三控制訊CT3號為禁能準位VS(例如,高電壓準位),而第二控制訊號CT2則為致能準位VE(例如,低電壓準位)。因此,第二開關SW2和第四開關SW4處於導通狀態,第一開關SW1和第三開關SW3處於關斷狀態,且參考電壓Vref之電壓準位會使得匹配電晶體210處於導通狀態。
In the compensation phase T1, the first control signal CT1 and the third control signal CT3 are the disable level VS (for example, high voltage level), and the second control signal CT2 is the enable level VE (for example, low Voltage level). Therefore, the second switch SW2 and the fourth switch SW4 are in the on state, the first switch SW1 and the third switch SW3 are in the off state, and the voltage level of the reference voltage Vref makes the matching
如此一來,補償電路140和畫素電路110會形成如第4A圖所示的等效電路。如第4A圖所示,第五節點N5的電壓準位會被設置為預設低電壓VSS,且第一節點N1的電荷會經由第二開關SW2和匹配電晶體210往預設低電壓VSS洩流,直到第一節點N1的電壓準位等於參考電壓Vref與匹配電晶體210的臨界電壓的絕對值之和。
In this way, the
亦即,於補償階段T1中,第一節點的電壓準位可以由下列的《公式1》表示:V1=Vref+|Vth1| 《公式1》
其中,V1代表第一節點的電壓準位,Vth1代表匹配電晶體210的臨界電壓。另外,《公式1》所示的第一節點N1的電壓準位會低於預設低電壓VSS,以確保發光單元230處於關斷狀態。
That is, in the compensation stage T1, the voltage level of the first node can be expressed by the following "
於寫入階段T2中,第一控制訊號CT1為禁能準位VS,且第二控制訊號CT2和第三控制訊號CT3為致能準位VE。因此,第一開關SW1維持於關斷狀態,而第二開關SW2、第三開關SW3和第四開關SW4處於導通狀態。 In the writing phase T2, the first control signal CT1 is the disable level VS, and the second control signal CT2 and the third control signal CT3 are the enable level VE. Therefore, the first switch SW1 is maintained in the off state, and the second switch SW2, the third switch SW3, and the fourth switch SW4 are in the on state.
如此一來,補償電路140和畫素電路110會形成如第4B圖所示的等效電路。如第4B圖所示,第四節點N4的電壓準位會被設置為資料電壓Vdata,第五節點N5的電壓準位會維持於預設低電壓VSS。並且,第一節點N1的電壓準位會維持於上述《公式1》所述之電壓值,使得發光單元230維持於關斷狀態。
In this way, the
因此,於寫入階段T2中,第一節點N1和第四節點N4的電壓差可以由下列的《公式2》表示:V1-V4=Vref+|Vth1|-Vdata 《公式2》其中,V4代表第四節點N4的電壓準位。 Therefore, in the writing phase T2, the voltage difference between the first node N1 and the fourth node N4 can be expressed by the following "Formula 2": V1-V4=Vref+|Vth1|-Vdata "Formula 2", where V4 represents the first The voltage level of the four node N4.
接著,於發光階段T3中,第一控制訊號CT1為致能準位VE,第二控制訊號CT2和第三控制訊號CT3為禁能準位VS。因此,第一開關SW1處於導通狀態,且第二開關SW2、第三開關SW3以及第四開關SW4處於關斷狀態。 Next, in the lighting phase T3, the first control signal CT1 is the enable level VE, and the second control signal CT2 and the third control signal CT3 are the disable level VS. Therefore, the first switch SW1 is in the on state, and the second switch SW2, the third switch SW3, and the fourth switch SW4 are in the off state.
如此一來,補償電路140和畫素電路110會形成如第4C圖所示的等效電路。如第4C圖所示,第一節點N1
的電壓準位會被設置為預設高電壓VDD。並且,由於第四節點N4和第五節點N5處於浮接(floating)狀態,第一節點N1和第四節點N4的電壓差,會相同於上述《公式2》所示之電壓差值。
In this way, the
因此,於發光階段T3中,畫素電路110的驅動電晶體220會提供驅動電流Idri至第三節點N3(亦即,發光單元230的陽極端),以控制發光單元230產生特定的灰階亮度。其中,驅動電流Idri的大小可以由下列的《公式4》表示:
如前所述,匹配電晶體210和驅動電晶體220的臨界電壓會相同或幾乎相同,所以《公式4》可以進一步簡化為下列的《公式5》:
由上述《公式5》可知,即使顯示面板100中不同區域的畫素電路110的驅動電晶體220具有不同的臨界電壓,每個畫素電路110的驅動電流Idri的大小仍然會與資料電壓Vdata具有固定的對應關係。因此,顯示面板100可以提供均勻的顯示畫面。
It can be seen from the above "Formula 5" that even if the driving
在某些實施例中,顯示面板100的第一開關
SW1、第二開關SW2、第三開關SW3和第四開關SW4是由N型電晶體來實現。在此情況下,顯示面板100的第一控制訊號CT1、第二控制訊號CT2和第三控制訊號CT3的致能準位VE為高電壓準位,而禁能準位VS則為低電壓準位。
In some embodiments, the first switch of the
第5圖為根據本揭示文件另一實施例的顯示面板500簡化後的功能方塊圖。顯示面板500相似於顯示面板100,差異在於顯示面板500包含多個畫素電路510以及多個補償電路540,其中每個補償電路540對應耦接於顯示面板500的一列的畫素電路510。
FIG. 5 is a simplified functional block diagram of a
第6圖為第5圖的顯示面板500放大後的局部示意圖。如第6圖所示,補償電路540包含電流源電路CS和匹配電晶體610。電流源電路CS用於輸出參考電流Iref至第六節點N6。匹配電晶體610包含第一端、第二端和控制端,匹配電晶體610的第一端耦接於第六節點N6,匹配電晶體610的第二端和控制端則皆用於接收參考電壓Vref。
FIG. 6 is a partial schematic diagram of the
畫素電路510包含驅動電晶體620、發光單元630、寫入電路640、重置電路650、第三電容C3和第四電容C4。寫入電路640用於依據第一控制訊號CT1將資料電壓Vdata傳遞至第七節點N7。重置電路650耦接於第六節點N6、第七節點N7和第八節點N8,用於依據第二控制訊號CT2將匹配電晶體610的臨界電壓和預設高電壓VDD分別傳遞至第七節點N7和第八節點N8。
The
具體而言,寫入電路540包含第五開關SW5。第五開關SW5包含第一端、第二端和控制端,第五開關SW5
的第一端用於接收資料電壓Vdata,第五開關SW5的第二端耦接於第七節點N7,第五開關SW5的控制端用於接收第一控制訊號CT1。
Specifically, the
重置電路550則包含第六開關SW6和第七開關SW7。第六開關SW6包含第一端、第二端和控制端,第六開關SW6的第一端用於自補償電路540接收匹配電晶體610的臨界電壓,第六開關SW6的第二端耦接於第七節點N7,第六開關SW6的控制端用於接收第二控制訊號CT2。第七開關SW7包含第一端、第二端和控制端,第七開關SW7的第一端耦接於第八節點N8,第七開關SW7的第二端用於接收預設高電壓VDD,第七開關SW7的控制端用於接收第二控制訊號CT2。
The reset circuit 550 includes a sixth switch SW6 and a seventh switch SW7. The sixth switch SW6 includes a first end, a second end, and a control end. The first end of the sixth switch SW6 is used to receive the threshold voltage of the matching
驅動電晶體620包含第一端、第二端和控制端,驅動電晶體620的第一端用於接收預設高電壓VDD,驅動電晶體620的第二端耦接於第九節點N9,驅動電晶體620的控制端則耦接於第八節點N8。
The driving
另外,第三電容C3耦接於第七節點N7和第八節點N8之間。第四電容C4包含第一端和第二端,第四電容C4的第一端耦接於第七節點N7,第四電容C4的第二端則用於接收預設高電壓VDD。發光單元630包含陰極端和陽極端,陰極端用於接收預設低電壓VSS,陽極端則耦接於第九節點N9。
In addition, the third capacitor C3 is coupled between the seventh node N7 and the eighth node N8. The fourth capacitor C4 includes a first terminal and a second terminal. The first terminal of the fourth capacitor C4 is coupled to the seventh node N7. The second terminal of the fourth capacitor C4 is used to receive a predetermined high voltage VDD. The
實作上,匹配電晶體610、驅動電晶體620、第五開關SW5、第六開關SW6和第七開關SW7可由P型電晶
體來實現。發光單元230可以用有機發光二極體或是微發光二極體等等發光材料來實現。
In practice, the matching
當匹配電晶體610接收到參考電流Iref時,補償電路540會透過第六節點N6將匹配電晶體610的臨界電壓輸出至補償電路540所耦接的畫素電路510,以補償不同畫素電路510的驅動電晶體620的臨界電壓變異。以下將以第6圖搭配第7圖來進一步說明補償電路540和畫素電路510之配合運作。
When the matching
於補償階段T1中,第一控制訊號CT1為禁能準位VS(例如,高電壓準位),第二控制訊號CT2為致能準位VE(例如,低電壓準位)。因此,第五開關SW5處於關斷狀態,第六開關SW6和第七開關SW7處於導通狀態。並且,電流源電路CS會提供參考電流Iref至匹配電晶體610。
In the compensation stage T1, the first control signal CT1 is the disable level VS (for example, a high voltage level), and the second control signal CT2 is the enable level VE (for example, a low voltage level). Therefore, the fifth switch SW5 is in the off state, and the sixth switch SW6 and the seventh switch SW7 are in the on state. Moreover, the current source circuit CS provides the reference current Iref to the matching
如此一來,補償電路540和畫素電路510會形成如第8A圖所示的等效電路。如第8A圖所示,由於匹配電晶體610為二極體耦接形式(diode-connected)的電晶體,當參考電流Iref流經匹配電晶體610時,第六節點N6的電壓準位可以由下列的《公式6》表示:
由於第六節點N6透過第六開關SW6和第七節 點N7互相導通,第七節點N7的電壓準位被設置為如《公式6》所示的電壓值。並且,預設高電壓VDD會透過第七開關SW7傳遞至第八節點N8,使得第八節點N8的電壓準位被設置為預設高電壓VDD。 Since the sixth node N6 passes through the sixth switch SW6 and the seventh section The points N7 are turned on each other, and the voltage level of the seventh node N7 is set to the voltage value shown in "Formula 6". Moreover, the preset high voltage VDD is transmitted to the eighth node N8 through the seventh switch SW7, so that the voltage level of the eighth node N8 is set to the preset high voltage VDD.
在寫入階段T2中,第一控制訊號CT1為致能準位VE,第二控制訊號CT2為禁能準位VS。因此,第五開關SW5處於導通狀態,而第六開關SW6和第七開關SW7處於關斷狀態。 In the writing phase T2, the first control signal CT1 is the enable level VE, and the second control signal CT2 is the disable level VS. Therefore, the fifth switch SW5 is in an on state, and the sixth switch SW6 and the seventh switch SW7 are in an off state.
如此一來,補償電路540和畫素電路510會形成如第8B圖所示的等效電路。如第8B圖所示,第七節點N7的電壓準位會自《公式6》所示的電壓值轉變為資料電壓Vdata,且第七節點N7的電壓變化量會透過第四電容C4的電容耦合效應傳遞至第八節點N8。因此,第八節點N8的電壓準位可以由下列的《公式7》表示:
在發光階段T3中,第一控制訊號CT1和第二控制訊號CT2皆為禁能準位VS。因此,第五開關SW5、第六開關SW6和第七開關SW7都處於關斷狀態。 In the lighting phase T3, both the first control signal CT1 and the second control signal CT2 are at the disabled level VS. Therefore, the fifth switch SW5, the sixth switch SW6, and the seventh switch SW7 are all in the off state.
因此,補償電路540和畫素電路510會形成如第8C圖所示的等效電路。如第8C圖所示,驅動電晶體620會提供驅動電流Idri至第九節點N9(亦即,發光單元630的陽極端),且驅動電流Idri的大小可以由下列的《公式8》表示:
由於匹配電晶體610和驅動電晶體620的臨界電壓會相同或幾乎相同,所以《公式8》可以進一步簡化為下列的《公式9》:
由上述《公式9》可知,即使顯示面板500中不同區域的畫素電路510的驅動電晶體620具有不同的臨界電壓,每個畫素電路510的驅動電流Idri的大小仍然會與資料電壓Vdata具有固定的對應關係。因此,顯示面板500可以提供均勻的顯示畫面。
It can be known from the above-mentioned "Formula 9" that even if the driving
在某些實施例中,顯示面板500的第五開關SW5、第六開關SW6和第七開關SW7是由N型電晶體來實現。在此情況下,顯示面板500的第一控制訊號CT1和第二控制訊號CT2的致能準位VE為高電壓準位,而禁能準位VS則為低電壓準位。
In some embodiments, the fifth switch SW5, the sixth switch SW6, and the seventh switch SW7 of the
第9圖為根據本揭示文件又一實施例的顯示面板900簡化後的功能方塊圖。顯示面板900相似於顯示面板100,差異在於顯示面板900包含多個畫素電路910以及多
個補償電路940,其中每個補償電路940對應耦接於顯示面板900的一列的畫素電路910。
FIG. 9 is a simplified functional block diagram of a
第10圖為第9圖的顯示面板900放大後的局部示意圖。如第10圖所示,補償電路940包含匹配電晶體1010以及電流源電路CS。匹配電晶體1010包含第一端、第二端和控制端,匹配電晶體1010的第一端用於接收參考電壓Vref,匹配電晶體的第二端和控制端耦接於第十節點N10。電流源電路CS耦接於第十節點N10,用於自匹配電晶體1010抽取參考電流Iref。
FIG. 10 is a partial schematic view of the
畫素電路910包含第八開關SW8、第九開關SW9、第十開關SW10、第五電容C5、驅動電晶體1020和發光單元1030。第八開關SW8包含第一端、第二端和控制端,第八開關SW8的第一端耦接於第十節點N10,第八開關SW8的第二端耦接於第十一節點N11,第八開關SW8的控制端用於接收第一控制訊號CT1。第九開關SW9包含第一端、第二端和控制端,第九開關SW9的第一端用於接收預設高電壓VDD,第九開關SW9的第二端耦接於第十二節點N12,第九開關SW9的控制端用於接收第二控制訊號CT2。第十開關SW10包含第一端、第二端和控制端,第十開關SW10的第一端耦接於第十二節點N12,第十開關SW10的第二端用於接收資料電壓Vdata,第十開關SW10的控制端用於接收第一控制訊號CT1。
The
驅動電晶體1020包含第一端、第二端和控制端,驅動電晶體1020的第一端耦接於第十二節點N12,驅
動電晶體1020的第二端耦接於第十三節點N13,驅動電晶體1020的控制端耦接於第十一節點N11。
The driving
另外,第五電容C5耦接於第十一節點N11和第十二節點N12之間。發光單元1030包含陰極端和陽極端,陰極端用於接收預設低電壓VSS,陽極端耦接於第十三節點N13。
In addition, the fifth capacitor C5 is coupled between the eleventh node N11 and the twelfth node N12. The
實作上,匹配電晶體1010、驅動電晶體1020、第八開關SW8、第九開關SW9和第十開關SW10可由P型電晶體來實現。發光單元1030可以用有機發光二極體或是微發光二極體等等發光材料來實現。
In practice, the
當參考電流Iref流經匹配電晶體1010時,補償電路940會透過第十節點N10將匹配電晶體1010的臨界電壓輸出至補償電路940所耦接的畫素電路910,以補償不同畫素電路910的驅動電晶體1020的臨界電壓變異。以下將以第10圖搭配第11圖來進一步說明補償電路940和畫素電路910之運作方式。
When the reference current Iref flows through the
於補償階段T1中,第一控制訊號CT1為致能準位VE(例如,低電壓準位),第二控制訊號CT2為禁能準位VS(例如,高電壓準位)。因此,第八開關SW8和第十開關SW10處於導通狀態,而第九開關SW9則處於關斷狀態。並且,電流源電路CS會自匹配電晶體1010抽取參考電流Iref。
In the compensation stage T1, the first control signal CT1 is the enable level VE (for example, a low voltage level), and the second control signal CT2 is the disable level VS (for example, a high voltage level). Therefore, the eighth switch SW8 and the tenth switch SW10 are in the on state, and the ninth switch SW9 is in the off state. In addition, the current source circuit CS draws the reference current Iref from the matched
因此,補償電路940和畫素電路910會形成如第12A圖所示的等效電路。如第12A圖所示,因為匹配電晶體1010是二極體耦接形式的電晶體,所以當參考電流Iref流
經匹配電晶體1010時,第十節點N10的電壓準位可以由下列的《公式10》表示:
由於第十節點N10經由第八開關SW8和第十一節點N11互相導通,第十一節點N11的電壓準位會被設置為如《公式10》所示的電壓值。並且,資料電壓Vdata會經由第十開關SW10傳遞至第十二節點N12,使得第十二節點N12的電壓準位被設置為資料電壓Vdata。因此,第十一節點N11和第十二節點N12的電壓差可以由下列的《公式11》表示:
由上述可知,畫素電路910的電晶體臨界電壓補償和資料寫入是在同一運作階段中執行。因此,畫素電路910的運作過程省略了前述的寫入階段T2。
As can be seen from the above, the transistor threshold voltage compensation and data writing of the
在發光階段T3中,第一控制訊號CT1為禁能準位VS,第二控制訊號CT2則為致能準位VE。因此,第八開關SW8和第十開關SW10處於關斷狀態,而第九開關SW9則處於導通狀態。 In the lighting phase T3, the first control signal CT1 is the disable level VS, and the second control signal CT2 is the enable level VE. Therefore, the eighth switch SW8 and the tenth switch SW10 are in the off state, and the ninth switch SW9 is in the on state.
如此一來,補償電路940和畫素電路910會形成如第12B圖所示的等效電路。如第12B圖所示,驅動電晶體1020會提供驅動電流Idri至第十三節點N13(亦即,發光單元1030的陽極端)。由於第十一節點N11處於浮接狀態,所以第十一節點N11和第十二節點N12的電壓差,會相同於《公式11》所示的電壓差值。
In this way, the
因此,驅動電流Idri的大小可以由下列的《公式12》表示:
由於匹配電晶體1010和驅動電晶體1020的臨界電壓會相同或幾乎相同,所以《公式12》可以進一步簡化為下列的《公式13》:
由上述《公式13》可知,即使顯示面板900中不同區域的畫素電路910的驅動電晶體1020具有不同的臨界電壓,每個畫素電路910的驅動電流Idri的大小仍然會與資料電壓Vdata具有固定的對應關係。因此,顯示面板900可以提供均勻的顯示畫面。
It can be known from the above-mentioned "Formula 13" that even if the driving
在某些實施例中,顯示面板900的第八開關SW8、第九開關SW9和第十開關SW10是由N型電晶體來實現。在此情況下,顯示面板900的第一控制訊號CT1和第二控制訊號CT2的致能準位VE為高電壓準位,而禁能準位VS則為低電壓準位。
In some embodiments, the eighth switch SW8, the ninth switch SW9, and the tenth switch SW10 of the
在說明書及申請專利範圍中使用了某些詞彙來指稱特定的元件。然而,所屬技術領域中具有通常知識者應可理解,同樣的元件可能會用不同的名詞來稱呼。說明書及申請專利範圍並不以名稱的差異做為區分元件的方式,而是以元件在功能上的差異來做為區分的基準。在說明書及申請專利範圍所提及的「包含」為開放式的用語,故應解釋成「包含但不限定於」。另外,「耦接」在此包含任何直接及間接的連接手段。因此,若文中描述第一元件耦接於第二元件,則代表第一元件可通過電性連接或無線傳輸、光學傳輸等信號連接方式而直接地連接於第二元件,或者通過其他元件或連接手段間接地電性或信號連接至該第二元件。 Certain words are used in the specification and patent application scope to refer to specific elements. However, those of ordinary skill in the art should understand that the same elements may be referred to by different nouns. The specification and the scope of patent application do not use the difference in names as a way to distinguish the components, but the difference in the functions of the components as the basis for distinguishing. "Inclusion" mentioned in the description and the scope of patent application is an open term, so it should be interpreted as "including but not limited to". In addition, "coupling" includes any direct and indirect connection means. Therefore, if it is described that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission, or other signal connection, or through other elements or connections The means is indirectly electrically or signally connected to the second element.
另外,除非說明書中特別指明,否則任何單數格的用語都同時包含複數格的涵義。 In addition, unless otherwise specified in the specification, any singular case also includes the meaning of the plural case.
以上僅為本揭露文件的較佳實施例,凡依本揭露文件的請求項所做的均等變化與修飾,皆應屬本揭露文件的涵蓋範圍。 The above are only the preferred embodiments of the disclosed document, and any changes and modifications made in accordance with the requested items of the disclosed document shall fall within the scope of the disclosed document.
100‧‧‧顯示面板 100‧‧‧Display panel
110‧‧‧畫素電路 110‧‧‧Pixel circuit
120‧‧‧源極驅動器 120‧‧‧ source driver
130‧‧‧閘極驅動器 130‧‧‧Gate driver
140‧‧‧補償電路 140‧‧‧ Compensation circuit
150‧‧‧顯示區 150‧‧‧Display area
160‧‧‧非顯示區 160‧‧‧non-display area
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TWI726712B (en) * | 2020-05-06 | 2021-05-01 | 友達光電股份有限公司 | Driving controller |
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