TW202018880A - Power chip scale package structure - Google Patents

Power chip scale package structure Download PDF

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TW202018880A
TW202018880A TW107138995A TW107138995A TW202018880A TW 202018880 A TW202018880 A TW 202018880A TW 107138995 A TW107138995 A TW 107138995A TW 107138995 A TW107138995 A TW 107138995A TW 202018880 A TW202018880 A TW 202018880A
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power
packaging structure
thinned
support material
chip
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TW107138995A
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TWI678773B (en
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冷中明
謝智正
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尼克森微電子股份有限公司
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Abstract

A power chip package structure is provided. The power chip scale package structure includes a thin chip and a metal sheet. The thin chip has an active side and a back side opposite thereto, and the thin chip is disposed on the circuit board with the active side facing to the circuit board. The conductive supporting sheet is disposed at the back side of the thin chip to enhance the mechanical strength of the chip scale package structure. The conductive supporting sheet has an inner surface facing to the thin chip, and a ratio of the backside surface area to the inner surface area of the supporting sheet is at least between 0.5 and 1.

Description

功率晶片封裝結構 Power chip packaging structure

本發明涉及一種功率晶片封裝結構，特別是涉及一種薄型功率晶片封裝結構。 The invention relates to a power chip packaging structure, in particular to a thin power chip packaging structure.

隨著可攜式與穿戴式電子裝置的發展，開發具有高效能、體積小、高速度、高品質及多功能性的產品成為趨勢。由於利用晶圓級晶片尺寸封裝(Wafer Level Chip Scale Package,WLCSP)技術所製造的晶片尺寸封裝體中，晶片的體積與封裝尺寸接近，而有利於使電子裝置的外形尺寸朝向微型化發展。 With the development of portable and wearable electronic devices, it has become a trend to develop products with high efficiency, small size, high speed, high quality and versatility. Since wafer-level packages manufactured using Wafer Level Chip Scale Package (WLCSP) technology, the volume of the chip is close to the package size, which is conducive to miniaturization of the electronic device.

現有的晶片尺寸封裝體通常會進一步設置於一電路板上，以電性連接於主控晶片。為了使電子裝置的尺寸更進一步地縮小，用於設置晶片尺寸封裝體的電路板的也越來越薄，甚至會利用可彎折或撓曲的軟性電路板來取代硬性電路板。 The existing chip size package is usually further disposed on a circuit board, and is electrically connected to the main control chip. In order to further reduce the size of electronic devices, the circuit boards used to provide chip-size packages are becoming thinner and thinner, and even flexible circuit boards that can be bent or flexed are used to replace rigid circuit boards.

然而，由於厚度相對較小的硬性電路板或者是軟性電路板較容易被彎折，而現有的晶片尺寸封裝體的厚度也非常薄，因此，晶片很容易因為電路板(薄型硬性電路板或者軟性電路板)彎折而破裂或損壞。 However, due to the relatively small thickness of the rigid circuit board or the flexible circuit board, it is easier to be bent, and the thickness of the existing chip size package is also very thin, therefore, the wafer is easily due to the circuit board (thin rigid circuit board or flexible The circuit board) is bent and broken or damaged.

本發明所要解決的其中一技術問題在於，如何避免厚度偏薄的晶片因為薄化的電路板彎折而損壞。 One of the technical problems to be solved by the present invention is how to prevent the thinner wafer from being damaged due to the bending of the thinned circuit board.

為了解決上述的技術問題，本發明所採用的其中一技術方案是，提供一種功率晶片封裝結構。功率晶片封裝結構包括一薄化 晶片以及一導電支撐材。薄化晶片具有一主動側以及一相反於主動側的背側。導電支撐材設置於薄化晶片的背側。導電支撐材具有面向所述薄化晶片的一內表面，且薄化晶片的一背側表面的面積與內表面面積的比值範圍是由0.5至1。 In order to solve the above technical problems, one of the technical solutions adopted by the present invention is to provide a power chip packaging structure. The power chip package structure includes a thinning Wafer and a conductive support material. The thinned chip has an active side and a back side opposite to the active side. The conductive support material is disposed on the back side of the thinned wafer. The conductive support material has an inner surface facing the thinned wafer, and the ratio of the area of the back surface of the thinned wafer to the inner surface area ranges from 0.5 to 1.

本發明的有益效果在於，本發明所提供的功率晶片封裝結構，其通過“設置導電支撐材在薄化晶片的背側，且薄化晶片的一背側表面的面積與內表面面積的比值範圍是由0.5至1”的技術手段，可增加晶片封裝結構的機械強度，以避免設置在基板上的薄化晶片，因為基板的彎折而被損壞。 The beneficial effect of the present invention is that the power chip package structure provided by the present invention, by "providing a conductive support material on the backside of the thinned wafer, and the ratio of the area of the backside surface of the thinned wafer to the inner surface area" It is a technical means of 0.5 to 1", which can increase the mechanical strength of the chip packaging structure to avoid the thinned wafer provided on the substrate, which is damaged due to the bending of the substrate.

為使能更進一步瞭解本發明的特徵及技術內容，請參閱以下有關本發明的詳細說明與附圖，然而所提供的附圖僅用於提供參考與說明，並非用來對本發明加以限制。 In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and description only, and are not intended to limit the present invention.

1‧‧‧功率晶片封裝結構 1‧‧‧Power chip packaging structure

10‧‧‧薄化晶片 10‧‧‧thinned chip

10a‧‧‧主動側 10a‧‧‧Active side

10b‧‧‧背側 10b‧‧‧back

10S‧‧‧側表面 10S‧‧‧Side surface

T1、T2‧‧‧功率電晶體 T1, T2‧‧‧Power transistor

11‧‧‧導電支撐材 11‧‧‧Conductive support material

11a‧‧‧內表面 11a‧‧‧Inner surface

11S‧‧‧側面 11S‧‧‧Side

12‧‧‧膠層 12‧‧‧adhesive layer

Z1、Z2‧‧‧二極體 Z1, Z2‧‧‧ diode

13‧‧‧背電極 13‧‧‧Back electrode

S1、S2‧‧‧源極接墊 S1, S2‧‧‧‧ source pad

G1、G2‧‧‧閘極接墊 G1, G2‧‧‧Gate pad

2‧‧‧線路基板 2‧‧‧ circuit board

21、22‧‧‧焊墊 21, 22‧‧‧ solder pad

11R‧‧‧電阻 11R‧‧‧Resistance

P1‧‧‧功率晶片級封裝結構的元件 P1‧‧‧ Components of power chip-level packaging structure

圖1為本發明其中一實施例的功率晶片封裝結構的立體示意圖。 FIG. 1 is a schematic perspective view of a power chip package structure according to an embodiment of the invention.

圖2為本發明其中一實施例的功率晶片封裝結構的剖面示意圖。 2 is a schematic cross-sectional view of a power chip package structure according to an embodiment of the invention.

圖3為本發明一實施例的功率晶片封裝結構的電路示意圖。 3 is a schematic circuit diagram of a power chip packaging structure according to an embodiment of the invention.

圖4為本發明一實施例的功率晶片封裝結構的元件的剖面示意圖。 4 is a schematic cross-sectional view of an element of a power chip packaging structure according to an embodiment of the invention.

請參閱圖1以及圖2。圖1為本發明一實施例的功率晶片封裝結構(Power Chip Scale Package)的立體示意圖，而圖2為本發明其中一實施例的功率晶片封裝結構的剖面示意圖。 Please refer to Figure 1 and Figure 2. FIG. 1 is a schematic perspective view of a power chip package structure (Power Chip Scale Package) according to an embodiment of the invention, and FIG. 2 is a schematic cross-sectional view of a power chip package structure according to an embodiment of the invention.

本發明實施例的晶片封裝結構1包括一薄化晶片10以及一導電支撐材11。薄化晶片10具有一主動側10a以及與所述主動側10a相反的背側10b。 The chip package structure 1 of the embodiment of the present invention includes a thinned chip 10 and a conductive support material 11. The thinned wafer 10 has an active side 10a and a back side 10b opposite to the active side 10a.

在本實施例中，薄化晶片10為半導體晶片，且經過摻雜、蝕刻、微影、薄化、線路重佈等製程，而在薄化晶片10內部形成至少一元件(圖未示)以及在薄化晶片10上形成用以連接外部線路的線路重佈層。線路重佈層位於主動側10a，並可根據實際需求而具 有接墊以及線路層。 In this embodiment, the thinned wafer 10 is a semiconductor wafer, and after doping, etching, lithography, thinning, circuit redistribution and other processes, at least one element (not shown) is formed inside the thinned wafer 10 and A circuit redistribution layer for connecting external circuits is formed on the thinned wafer 10. The circuit redistribution layer is located on the active side 10a, and can be provided according to actual needs There are pads and circuit layers.

薄化晶片10的厚度範圍是由50μm至125μm。因此，薄化晶片10很容易因受到外部應力，而被損壞或者產生裂縫。據此，本發明實施例的晶片封裝結構1還包括一導電支撐材11，且導電支撐材11設置於薄化晶片10的背側10b，以增加晶片封裝結構1的機械強度。 The thickness of the thinned wafer 10 ranges from 50 μm to 125 μm. Therefore, the thinned wafer 10 is easily damaged or cracked due to external stress. Accordingly, the chip packaging structure 1 of the embodiment of the present invention further includes a conductive support material 11, and the conductive support material 11 is disposed on the back side 10 b of the thinned wafer 10 to increase the mechanical strength of the chip packaging structure 1.

如圖1與圖2所示，功率晶片封裝結構1還進一步包括一膠層12，膠層12是位於薄化晶片10與導電支撐材11之間，而導電支撐材11通過膠層12固定於薄化晶片10的背側。 As shown in FIGS. 1 and 2, the power chip packaging structure 1 further includes an adhesive layer 12. The adhesive layer 12 is located between the thinned wafer 10 and the conductive support material 11, and the conductive support material 11 is fixed to the conductive layer 11 through the adhesive layer 12. The back side of the wafer 10 is thinned.

請參照圖2，在一實施例中，導電支撐材11會完全遮蓋薄化晶片10的背側10b的表面，並由背側的表面向外延伸而超過背側的表面的至少一邊緣。具體而言，導電支撐材11具有面向薄化晶片10設置的一內表面11a，且內表面11a的面積會大於或等於薄化晶片10的背側10b的表面面積。 Please refer to FIG. 2. In an embodiment, the conductive support material 11 completely covers the surface of the backside 10 b of the thinned wafer 10, and extends outward from the surface of the backside beyond at least one edge of the surface of the backside. Specifically, the conductive support material 11 has an inner surface 11 a disposed facing the thinned wafer 10, and the area of the inner surface 11 a will be greater than or equal to the surface area of the back side 10 b of the thinned wafer 10.

薄化晶片10的背側表面的面積是導電支撐材11的內表面11a面積的50%至100%。也就是說，薄化晶片10的背側表面面積與導電支撐材11的內表面11a面積的比值範圍是0.5至1。 The area of the backside surface of the thinned wafer 10 is 50% to 100% of the area of the inner surface 11 a of the conductive support material 11. That is, the ratio of the area of the back surface of the thinned wafer 10 to the area of the inner surface 11a of the conductive support 11 ranges from 0.5 to 1.

另外，在本發明實施例的功率晶片封裝結構1中，導電支撐材11並未包覆薄化晶片10的側表面10S，而使薄化晶片10的側表面10S裸露出來。 In addition, in the power chip packaging structure 1 of the embodiment of the present invention, the conductive support material 11 does not cover the side surface 10S of the thinned wafer 10, but the side surface 10S of the thinned wafer 10 is exposed.

在另一實施例中，導電支撐材11的側面11S會與薄化晶片10的側表面10S切齊。也就是說，薄化晶片10的背側10b的表面面積與導電支撐材11的內表面11a的面積相同。 In another embodiment, the side surface 11S of the conductive support material 11 is aligned with the side surface 10S of the thinned wafer 10. That is, the surface area of the back side 10b of the thinned wafer 10 is the same as the area of the inner surface 11a of the conductive support 11.

據此，設置於薄化晶片10背側10b的導電支撐材11可以增加晶片封裝結構1的機械強度，並保護薄化晶片10，以減少薄化晶片10因受到外部應力而損壞或產生裂縫的機率。在本發明實施例中，導電支撐材11的厚度大於或等於50μm。 Accordingly, the conductive support material 11 disposed on the back side 10b of the thinned wafer 10 can increase the mechanical strength of the chip packaging structure 1 and protect the thinned wafer 10 to reduce the damage or cracks caused by external stress on the thinned wafer 10 Probability. In the embodiment of the present invention, the thickness of the conductive support material 11 is greater than or equal to 50 μm.

須說明的是，本發明實施例的功率晶片封裝結構1可應用於 電路保護元件中。因此，請配合參照圖1至圖3。圖3顯示本發明一實施例的功率晶片封裝結構的電路示意圖。薄化晶片10可包括兩個相互並聯的功率電晶體T1、T2。 It should be noted that the power chip packaging structure 1 of the embodiment of the present invention can be applied to Circuit protection components. Therefore, please refer to Figures 1-3. FIG. 3 shows a schematic circuit diagram of a power chip packaging structure according to an embodiment of the invention. The thinned wafer 10 may include two power transistors T1, T2 connected in parallel to each other.

功率電晶體T1、T2例如是垂直式功率電晶體、絕緣閘雙極型電晶體(Insulated Gate Bipolar Transistor,IGBT)或是底部源極橫向雙擴散金氧半場效電晶體(bottom-source lateral diffusion MOSFET)。本發明實施例中，以垂直式功率電晶體為例來進行說明。 The power transistors T1 and T2 are, for example, vertical power transistors, insulated gate bipolar transistors (IGBTs) or bottom-source lateral diffusion MOSFETs (bottom-source lateral diffusion MOSFETs) ). In the embodiments of the present invention, a vertical power transistor is taken as an example for description.

據此，如圖1所示，本實施例的薄化晶片10至少包括兩組源極接墊S1、S2以及兩個閘極接墊G1、G2。其中一組源極接墊S1以及其中一閘極接墊G1電性連接於其中一功率電晶體T1的源極以及閘極，而另一組源極接墊S2以及另一個閘極接墊G2是分別電性連接於另一個功率電晶體T2的源極以及閘極。 Accordingly, as shown in FIG. 1, the thinned wafer 10 of this embodiment includes at least two sets of source pads S1 and S2 and two gate pads G1 and G2. One set of source pads S1 and one of the gate pads G1 are electrically connected to the source and gate of one of the power transistors T1, and the other set of source pads S2 and the other gate pad G2 It is electrically connected to the source and gate of another power transistor T2, respectively.

此外，晶片封裝結構1還包括一背電極13，且背電極13是位於薄化晶片10的背側，並可電性連接於兩個功率電晶體T1、T2的汲極而作為汲極接墊。換句話說，其中一個功率電晶體T1的汲極可通過背電極13電性連接於另一功率電晶體T2的汲極。 In addition, the chip package structure 1 further includes a back electrode 13, and the back electrode 13 is located on the back side of the thinned chip 10 and can be electrically connected to the drains of the two power transistors T1 and T2 as a drain pad . In other words, the drain of one power transistor T1 can be electrically connected to the drain of another power transistor T2 through the back electrode 13.

背電極13可以具有單層結構或者是多層結構。背電極13的材料可以選擇銅、鈦、鎳、銀、錫、金等金屬材料。在本實施例中，背電極13具有多層結構，而至少包括相互堆疊的鈦層、鎳層以及銀層。然而，本發明並未限制背電極13的材料。 The back electrode 13 may have a single-layer structure or a multi-layer structure. The material of the back electrode 13 can be selected from metal materials such as copper, titanium, nickel, silver, tin, and gold. In the present embodiment, the back electrode 13 has a multilayer structure, and at least includes a titanium layer, a nickel layer, and a silver layer stacked on top of each other. However, the invention does not limit the material of the back electrode 13.

如圖3所示，在本實施例中，每一個功率電晶體T1(T2)還串聯一二極體Z1(Z2)。詳細而言，功率電晶體T1(T2)的源極會電性連接於二極體Z1(Z2)的正極(anode)，而功率電晶體T1(T2)的汲極會電性連接於二極體Z1(Z2)的負極(cathode)。因此，圖1中所繪示的兩組源極接墊S1、S2，實際上會分別電性連接於兩個二極體Z1、Z2的正極。也就是說，其中一組源極接墊S1會電性連接於二極體Z1的正極，而另一組源極接墊S2會電性連接於二極體Z2 的正極。 As shown in FIG. 3, in this embodiment, each power transistor T1 (T2) is also connected in series with a diode Z1 (Z2). In detail, the source of the power transistor T1 (T2) is electrically connected to the anode of the diode Z1 (Z2), and the drain of the power transistor T1 (T2) is electrically connected to the diode Cathode of body Z1 (Z2). Therefore, the two sets of source pads S1 and S2 shown in FIG. 1 are actually electrically connected to the positive electrodes of the two diodes Z1 and Z2, respectively. In other words, one set of source pads S1 will be electrically connected to the positive electrode of diode Z1, and the other set of source pads S2 will be electrically connected to diode Z2 The positive pole.

須說明的是，通過使薄化晶片10內部具有不同的摻雜區以及摻雜濃度，可以形成上述兩個功率電晶體T1、T2，以及兩個二極體Z1、Z2。另外，兩個功率電晶體T1、T2以及兩個二極體Z1、Z2可以通過線路重佈層以及背電極13，而建立如圖3所示的電性連接關係。 It should be noted that by making the thinned wafer 10 have different doping regions and doping concentrations, the above two power transistors T1 and T2 and the two diodes Z1 and Z2 can be formed. In addition, the two power transistors T1 and T2 and the two diodes Z1 and Z2 can establish an electrical connection relationship as shown in FIG. 3 through the line redistribution layer and the back electrode 13.

導電支撐材11除了減少薄化晶片10因受到外部應力而損壞或產生裂縫的機率之外，還可以在功率電晶體T1、T2運作時，降低電路中的電阻，並可對薄化晶片10進行散熱。 In addition to reducing the probability of the thinned wafer 10 being damaged or cracked due to external stress, the conductive support material 11 can also reduce the resistance in the circuit when the power transistors T1 and T2 are in operation, and can be used for the thinned wafer 10 Heat dissipation.

據此，導電支撐材11可以是選擇導電性與散熱性較佳的導電材料。在一實施例中，導電支撐材11可以是金屬片材，如：銅片或者鋁片等等。 Accordingly, the conductive support material 11 may be a conductive material with better conductivity and heat dissipation. In an embodiment, the conductive support material 11 may be a metal sheet, such as a copper sheet or an aluminum sheet.

在這個實施例中，位於導電支撐材11以及薄化晶片10的背電極13之間的膠層12為導電膠層，且導電膠層的材料可以是焊料或者是含金屬的膠材。導電支撐材11可通過導電膠層固定於薄化晶片10的背側10b。 In this embodiment, the adhesive layer 12 between the conductive support material 11 and the back electrode 13 of the thinned wafer 10 is a conductive adhesive layer, and the material of the conductive adhesive layer may be solder or a metal-containing adhesive material. The conductive support material 11 can be fixed to the back side 10b of the thinned wafer 10 through a conductive adhesive layer.

請參照圖2以及圖3，也就是說，導電支撐材11也會通過導電膠層電性連接於背電極13，進而電性連接於兩個功率電晶體T1、T2的汲極之間。因此，當薄化晶片10應用於元件中時，導電支撐材11的電阻11R也會影響整個電路的總電阻值。 Please refer to FIGS. 2 and 3, that is to say, the conductive support material 11 is also electrically connected to the back electrode 13 through the conductive adhesive layer, and then electrically connected between the drains of the two power transistors T1 and T2. Therefore, when the thinned wafer 10 is applied to an element, the resistance 11R of the conductive support material 11 will also affect the total resistance value of the entire circuit.

相較於使用絕緣材料作為支撐材或者是使用絕緣膠材，在本實施例中，將導電支撐材11通過導電膠層貼附於薄化晶片10背側，不僅可增加晶片封裝結構1的機械強度，也可以進一步降低整個電路的總電阻值。 Compared with using an insulating material as a supporting material or using an insulating adhesive material, in this embodiment, the conductive support material 11 is attached to the back side of the thinned wafer 10 through the conductive adhesive layer, which not only increases the machinery of the wafer packaging structure 1 The strength can also further reduce the total resistance of the entire circuit.

本發明實施例並提供一種應用上述晶片封裝結構1的元件。請參照圖4，顯示本發明一實施例的功率晶片級封裝結構的元件P1的剖面示意圖。 An embodiment of the present invention also provides an element using the above-mentioned chip packaging structure 1. Please refer to FIG. 4, which is a schematic cross-sectional view of a component P1 of a power chip-level packaging structure according to an embodiment of the invention.

功率晶片級封裝結構的元件P1包括線路基板2以及設置於線 路基板2上的晶片封裝結構1。線路基板2可以是硬性線路板或者軟性線路板。在線路基板2中，已經佈設線路並具有用以與晶片封裝結構1電性連接的多個焊墊21、22。 The element P1 of the power wafer-level packaging structure includes the circuit substrate 2 and the line The wafer package structure 1 on the road substrate 2. The circuit board 2 may be a rigid circuit board or a flexible circuit board. In the circuit substrate 2, the circuit has been routed and has a plurality of bonding pads 21 and 22 for electrically connecting with the chip package structure 1.

另外，要說明的是，雖然圖4中並未繪示，但應可了解功率晶片級封裝結構的元件P1實質上還可能包含其他設置於線路基板2上並具有其他功能晶片，如：主控晶片，以配合本發明實施例的薄化晶片10中的功率電晶體T1、T2共同運作。 In addition, it should be noted that although not shown in FIG. 4, it should be understood that the element P1 of the power chip-level packaging structure may actually include other chips provided on the circuit substrate 2 and having other functions, such as: The chip cooperates with the power transistors T1 and T2 in the thinned chip 10 of the embodiment of the present invention.

當晶片封裝結構1設置於線路基板2上時，是以薄化晶片10的主動側10a朝向線路基板2而設置。進一步而言，薄化晶片10的源極接墊S1、S2以及閘極接墊G1、G2會分別對應於線路基板2上的多個焊墊21、22，而使薄化晶片10可通過焊接而設置於線路基板2上。 When the chip package structure 1 is disposed on the circuit substrate 2, the active side 10 a of the thinned chip 10 is disposed toward the circuit substrate 2. Further, the source pads S1 and S2 and the gate pads G1 and G2 of the thinned wafer 10 correspond to the plurality of pads 21 and 22 on the circuit substrate 2 respectively, so that the thinned wafer 10 can be soldered It is provided on the circuit board 2.

另一方面，薄化晶片10的功率電晶體T1、T2可通過源極接墊S1、S2、閘極接墊G1、G2以及分別對應於源極接墊S1、S2與閘極接墊G1、G2的多個焊墊21、22，電性連接於線路基板2上的其他功能晶片。 On the other hand, the power transistors T1 and T2 of the thinned wafer 10 can pass through the source pads S1 and S2, the gate pads G1 and G2, and correspond to the source pads S1 and S2 and the gate pad G1 respectively The plurality of bonding pads 21 and 22 of G2 are electrically connected to other functional chips on the circuit board 2.

須說明的是，為了盡可能薄型化電子裝置，功率晶片級封裝結構的元件P1的線路基板2也越來越薄。因此，本實施例的線路基板2的厚度會小於0.5mm。 It should be noted that in order to make the electronic device as thin as possible, the circuit substrate 2 of the element P1 of the power wafer-level packaging structure is also getting thinner. Therefore, the thickness of the circuit board 2 of this embodiment will be less than 0.5 mm.

由於線路基板2的厚度偏薄，而很容易被彎折，從而使設置於線路基板2上的薄化晶片10受到應力而損壞或產生裂縫。因此，本發明實施例的功率晶片封裝結構1在薄化晶片10的背側10b設置導電支撐材11，可減少薄化晶片10因線路基板2彎折而受損的機率。 Since the thickness of the circuit substrate 2 is thin, it is easily bent, so that the thinned wafer 10 provided on the circuit substrate 2 is stressed and damaged or cracked. Therefore, the power chip packaging structure 1 of the embodiment of the present invention is provided with the conductive support material 11 on the back side 10 b of the thinned wafer 10, which can reduce the probability of the thinned wafer 10 being damaged due to the bending of the circuit substrate 2.

在本實施例中，導電支撐材11的厚度至少50μm。然而，導電支撐材11的厚度若太厚，會使功率晶片級封裝結構的元件P1的總厚度增加，並增加成本。據此，導電支撐材11的厚度可大於50μm，並根據實際需求調整。 In this embodiment, the thickness of the conductive support material 11 is at least 50 μm. However, if the thickness of the conductive support material 11 is too thick, the total thickness of the element P1 of the power wafer-level packaging structure will increase and the cost will increase. According to this, the thickness of the conductive support material 11 may be greater than 50 μm, and adjusted according to actual needs.

綜合上述，本發明的有益效果在於，本發明所提供的晶片封裝結構1及應用其的功率晶片級封裝結構的元件P1，其通過“設置導電支撐材11在薄化晶片10的背側，且薄化晶片10的一背側表面的面積與內表面11a面積的比值至少是0.5與1之間”的技術手段，可增加晶片封裝結構1的機械強度。當晶片封裝結構1應用於元件P1中時，導電支撐材11可提供薄化晶片10支撐強度，以減少在線路基板2上的薄化晶片10因為線路基板2彎折而被損壞的機率。 In summary, the beneficial effect of the present invention lies in that the chip package structure 1 provided by the present invention and the element P1 of the power wafer-level package structure using the same are provided with the conductive support material 11 on the back side of the thinned wafer 10, and The technical means of thinning the area of a back surface of the wafer 10 to the area of the inner surface 11a is at least between 0.5 and 1" can increase the mechanical strength of the chip packaging structure 1. When the chip packaging structure 1 is applied to the element P1, the conductive support material 11 can provide the support strength of the thinned wafer 10 to reduce the probability of the thinned wafer 10 on the circuit substrate 2 being damaged due to the bending of the circuit substrate 2.

另外，導電支撐材11除了減少薄化晶片10因受到外部應力而損壞或產生裂縫的機率之外，還可以在功率電晶體T1、T2運作時，降低電路的電阻。此外，導電支撐材11還可增加薄化晶片10的散熱路徑，以提高薄化晶片10運作時的散熱效率。 In addition, the conductive support 11 not only reduces the probability of the thinned wafer 10 being damaged or cracked due to external stress, but also reduces the resistance of the circuit when the power transistors T1 and T2 operate. In addition, the conductive support material 11 can also increase the heat dissipation path of the thinned wafer 10 to improve the heat dissipation efficiency of the thinned wafer 10 during operation.

以上所公開的內容僅為本發明的優選可行實施例，並非因此侷限本發明的申請專利範圍，所以凡是運用本發明說明書及附圖內容所做的等效技術變化，均包含於本發明的申請專利範圍內。 The content disclosed above is only a preferred and feasible embodiment of the present invention, and does not limit the scope of the patent application of the present invention, so all equivalent technical changes made by using the description and drawings of the present invention are included in the application of the present invention. Within the scope of the patent.

1‧‧‧功率晶片封裝結構 1‧‧‧Power chip packaging structure

10‧‧‧薄化晶片 10‧‧‧thinned chip

10a‧‧‧主動側 10a‧‧‧Active side

10b‧‧‧背側 10b‧‧‧back

10S‧‧‧側表面 10S‧‧‧Side surface

11‧‧‧導電支撐材 11‧‧‧Conductive support material

11a‧‧‧內表面 11a‧‧‧Inner surface

11S‧‧‧側面 11S‧‧‧Side

12‧‧‧膠層 12‧‧‧adhesive layer

13‧‧‧背電極 13‧‧‧Back electrode

S1、S2‧‧‧源極接墊 S1, S2‧‧‧‧ source pad

G1、G2‧‧‧閘極接墊 G1, G2‧‧‧Gate pad

Claims (8)

一種功率晶片封裝結構，其包括：一薄化晶片，其具有一主動側以及一相反於所述主動側的背側；以及一導電支撐材，其設置於所述薄化晶片的所述背側，其中，所述導電支撐材具有面向所述薄化晶片的一內表面，所述薄化晶片的一背側的表面的面積與所述內表面的面積的比值範圍是由0.5至1。 A power chip packaging structure includes: a thinned chip having an active side and a back side opposite to the active side; and a conductive support material disposed on the back side of the thinned chip , Wherein the conductive support material has an inner surface facing the thinned wafer, and the ratio of the area of the surface on the back side of the thinned wafer to the area of the inner surface ranges from 0.5 to 1. 如請求項1所述的功率晶片封裝結構，還進一步包括一導電膠層，所述導電膠層位於所述薄化晶片與所述導電支撐材之間，且所述導電支撐材通過所述導電膠固定於所述薄化晶片的所述背側。 The power chip packaging structure according to claim 1, further comprising a conductive adhesive layer, the conductive adhesive layer is located between the thinned wafer and the conductive support material, and the conductive support material passes through the conductive The glue is fixed to the back side of the thinned wafer. 如請求項2所述的功率晶片封裝結構，其中，所述導電膠層為焊料層或者是含金屬的膠層。 The power chip packaging structure according to claim 2, wherein the conductive adhesive layer is a solder layer or a metal-containing adhesive layer. 如請求項1所述的功率晶片封裝結構，其中，所述薄化晶片具有至少兩個相互並聯的功率電晶體。 The power chip packaging structure according to claim 1, wherein the thinned chip has at least two power transistors connected in parallel with each other. 如請求項4所述的功率晶片封裝結構，其中，每一所述功率電晶體與一二極體串聯。 The power chip packaging structure according to claim 4, wherein each of the power transistors is connected in series with a diode. 如請求項4所述的功率晶片封裝結構，還進一步包括：一背電極，所述背電極位於所述薄化晶片的背側，並電性連接於兩個所述功率電晶體的兩個汲極。 The power chip packaging structure according to claim 4, further comprising: a back electrode, the back electrode is located on the back side of the thinned wafer, and is electrically connected to two power transistors of the two power transistors pole. 如請求項1所述的功率晶片封裝結構，其中，所述薄化晶片的厚度範圍由50μm至125μm。 The power wafer packaging structure according to claim 1, wherein the thickness of the thinned wafer ranges from 50 μm to 125 μm. 如請求項1所述的功率晶片封裝結構，其中，所述導電支撐材的厚度大於或等於50μm。 The power chip packaging structure according to claim 1, wherein the thickness of the conductive support material is greater than or equal to 50 μm.
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