TW202017188A - Power semiconductor device capable of achieving less loss for turn-on operation and high voltage endurance - Google Patents

Abstract

The present invention relates to a semiconductor device for realizing high voltage endurance, large current, low turn-on voltage, low switching loss and low noise on SiC-MOSFET. SiC-MOSFET is a combination of Si-MOSFET with high channel mobility and a drifting layer formed by SiC with high bulk mobility. The first conductive type of SiC wafer forming the drifting layer is bonded with the second conductive type of Si wafer, and the trench gate is dug out to a part of SiC to fabricate the MOSFET. A second conductive type of barrier area is disposed in the Si area adjacent to SiC.

Description

功率半導體元件 Power semiconductor components

本發明係關於一種適用於電力用開關元件等之MOS型電晶體元件及其製造方法。 The present invention relates to a MOS transistor element suitable for power switching elements and the like and a method for manufacturing the same.

電力用半導體裝置的領域中，以往常用由矽製成之IGBT或MOSFET等的功率開關，但對於低碳社會之能源效率化的目標，上述的性能被認為已接近極限。另一方面，近年來利用稱為寬能帶隙之新結晶素材的替代技術之發展受到期待，但性能、成本及可靠性方面有許多技術性問題，不容易量產，故亟需改善。 In the field of power semiconductor devices, power switches such as IGBTs or MOSFETs made of silicon have been commonly used in the past, but for the goal of energy efficiency in a low-carbon society, the above-mentioned performance is considered to be close to the limit. On the other hand, in recent years, the development of alternative technologies using new crystalline materials called wide energy band gaps is expected, but there are many technical problems in performance, cost, and reliability, which are not easy for mass production, so there is an urgent need for improvement.

以往的技術例如可參考美國專利第5,506,421號(專利文獻1)、第5,396,085號(專利文獻2)、第5,323,040號(專利文獻3)、第5,614,749號(專利文獻4)、日本特許第5,610,492號(專利文獻5)、日本特開第2013-243333號(專利文獻6)等文獻。 For a conventional technique, for example, refer to U.S. Patent Nos. 5,506,421 (Patent Document 1), 5,396,085 (Patent Document 2), 5,323,040 (Patent Document 3), 5,614,749 (Patent Document 4), and Japanese Patent No. 5,610,492 ( Patent Document 5), Japanese Patent Laid-Open No. 2013-243333 (Patent Document 6) and other documents.

又，亦可參考”Lateral n-channel inversion mode 4H-SiC MOSFETs”,S.Sridenvan et.al.IEEE Electron Device Letters,(Volume：19,Issue：7,July 1998)(非專利文獻1)、Determination of intrinsic phonon-limited mobility and carrier transport property extraction of 4H-SiC MOSFET,Noguchi,et.al.9.3.1 IEDM17,pp219-222.(2017)(非專利文獻2)、”1800V Bipolar mode MOSFETs：a first application of Silicon wafer Direct Bonding(SDB)technique to a power device”,A.Nakagawa,IEDM86,5.6,pp122-125(非專利文獻3)、「用於創造能源、省能源裝置之異種半導體材料的貼合」，重川直輝、J.Vac.Soc.Jpn.Vol.60,No.11,(2017)421-427(非專利文獻4)、"Impact Ionization in Silicon：A REVIEW AND UPDATE" W.MAES,et.al.Solid State Electronics Vol.33,No.6pp705-718,1990(非專利文獻5)等文獻。 Also refer to "Lateral n-channel inversion mode 4H-SiC MOSFETs", S. Sridenvan et.al. IEEE Electron Device Letters, (Volume: 19, Issue: 7, July 1998) (Non-Patent Document 1), Determination of intrinsic phonon-limited mobility and carrier transport property extraction of 4H-SiC MOSFET, Noguchi, et.al. 9.3.1 IEDM17, pp219-222. (2017) (Non-Patent Document 2), "1800V Bipolar mode MOSFETs: a first application of Silicon wafer Direct Bonding (SDB) technique to a power device", A. Nakagawa, IEDM86, 5.6, pp122-125 (Non-Patent Document 3), "Lamination of heterogeneous semiconductor materials for energy-saving and energy-saving devices", Naogawa Shigekawa, J.Vac.Soc .Jpn.Vol.60,No.11,(2017)421-427 (Non-Patent Document 4), "Impact Ionization in Silicon: A REVIEW AND UPDATE" W.MAES,et.al.Solid State Electronics Vol.33, No. 6pp705-718, 1990 (Non-Patent Document 5) and other documents.

功率電晶體的主流為矽材料(下稱Si)製成之IGBT及MOSFET。IGBT為雙極型元件，故藉由載子的傳導調變效應，可以使P型集極層上之低濃度N型漂移層低電阻化，可實現高耐壓及大電流。然而，關斷動作時，高階注入之電子與電洞復合而載體消滅時需要下降時間，該下降時間導致開關動作變慢，因此關斷損耗增加。相對於此，Si製成之MOSFET(下稱Si-MOSFET)為單極型元件，故高濃度汲極擴散層上的低濃度汲極擴散層(下稱漂移層)的再結合速度不構成問題，因此有關斷損耗少的優點。但為了提升在高電壓下的耐壓而增厚漂移層的情況下，導通狀態時的電阻升高，導通電壓上升，會有使能量損耗增加這樣的缺點而不適合高電壓用途。第3圖(1)表示習知的Si-MOSFET截面圖。 The mainstream of power transistors is IGBT and MOSFET made of silicon material (hereinafter referred to as Si). The IGBT is a bipolar device, so the carrier's conduction modulation effect can reduce the resistance of the low concentration N-type drift layer on the P-type collector layer, and can achieve high withstand voltage and large current. However, during the turn-off operation, the higher-order injected electrons and holes recombine and the carrier is destroyed, which requires a fall time. This fall time causes the switching action to become slower, so the turn-off loss increases. In contrast, the MOSFET made of Si (hereinafter referred to as Si-MOSFET) is a unipolar device, so the recombination speed of the low concentration drain diffusion layer (hereinafter referred to as drift layer) on the high concentration drain diffusion layer does not pose a problem , So the advantage of less off loss. However, when the drift layer is thickened in order to increase the withstand voltage at high voltage, the resistance in the on-state increases and the on-voltage increases, which has the disadvantage of increasing energy loss and is not suitable for high-voltage applications. Fig. 3 (1) shows a cross-sectional view of a conventional Si-MOSFET.

有鑑於上述Si裝置的技術極限，近年來寬能帶隙半導體被期待作為可替代的次世代功率半導體材料。其中，碳化矽(下稱SiC)及氮化鎵(下稱GaN)的能帶隙皆為Si的三倍程度，絕緣耐壓亦為約10倍高，另一方面與Si有同等的移動度。由於這樣的優點，在高電壓用途亦可將晶圓薄化來使用，降低導通電阻故可達到高電壓且高速作動。此外，可在高溫作動，熱傳導率高而散熱性優異故容易冷卻，因此作為高速且大電力用途之功率半導體受到極大的期待。然而，SiC的晶圓成本高，以及與Si相較起來在晶圓製程中需要高溫的熱處理步驟，被視為製造方面的問題。 In view of the technical limits of the above Si devices, in recent years, wide band gap semiconductors are expected as alternative next-generation power semiconductor materials. Among them, the energy band gap of silicon carbide (hereinafter referred to as SiC) and gallium nitride (hereinafter referred to as GaN) are three times that of Si, and the insulation withstand voltage is also approximately 10 times higher, on the other hand, it has the same mobility as Si . Due to such advantages, the wafer can be thinned and used in high-voltage applications, and the on-resistance is reduced, so high-voltage and high-speed operation can be achieved. In addition, it can operate at a high temperature, has high thermal conductivity and excellent heat dissipation, and is therefore easy to cool. Therefore, it is highly expected as a power semiconductor for high-speed and large-power applications. However, the high cost of SiC wafers and the need for high-temperature heat treatment steps in the wafer process compared to Si are considered manufacturing issues.

由SiC結晶製作之MOSFET(下稱習知SiC-MOSFET)自從 開始研究(非專利文獻1)已經過漫長時間，但閘極熱氧化膜界面的品質導致傳導電子的低通道移動度(比Si少兩位數)的問題，其原因尚未被充分解開。其原因推測為在閘極絕緣膜與SiC之界面的缺陷(介面能態密度)較多，故通道移動度變低(非專利文獻2)。亦即，雖然已知在SiC整體(bulk)結晶中電子移動度為800-1000cm/v‧sec，但MOSFET的表面通道移動度極低，為10cm/v‧sec(Si面)。 MOSFET made of SiC crystal (hereinafter referred to as conventional SiC-MOSFET) It has been a long time since the start of research (Non-Patent Document 1), but the quality of the interface of the gate thermal oxide film leads to the problem of low channel mobility of conductive electrons (two digits less than Si), the reason for which has not been fully solved. The reason for this is presumed to be that there are many defects (interface energy density) at the interface between the gate insulating film and SiC, so the channel mobility becomes low (Non-Patent Document 2). That is, although it is known that the electron mobility in the SiC bulk crystal is 800-1000 cm/v‧sec, the surface channel mobility of the MOSFET is extremely low, which is 10 cm/v‧sec (Si plane).

因此，裝置作動受制於嚴重的問題為，基板汲極擴散層上形成之SiC漂移層的電阻雖然夠低，但MOSFET的通道電阻過高。結果使得導通電壓上升而增加能量損耗，無法充分發揮SiC的優點。第3圖(2)為習知SiC-MOSFET的截面圖。在此，閘極氧化膜下的介面能態71阻礙通道電子傳導，故電流增益變小。又，溝槽型的縱向SiC-MOSFET構造(專利文獻1)中，即使薄化閘極氧化膜以提升驅動能力，因SiC熱氧化膜的品質容易惡化且低耐壓，故在閘極底面角部73經常發生絕緣破壞缺陷。儘管已經針對SiC界面狀態之多種缺陷或為了改善熱氧化膜的品質，已嘗試許多退火方法，但惡化的根本原因未被充分解開。因此，關於從基本原理理解界面狀態，需要從基礎重新檢視(非專利文獻2)。在這樣的狀況下，本發明需解決的問題是實現一種使用SiC結晶之MOSFET，其導通作動損耗少且可高耐壓化。 Therefore, the device operation is subject to a serious problem. Although the resistance of the SiC drift layer formed on the drain diffusion layer of the substrate is low enough, the channel resistance of the MOSFET is too high. As a result, the on-voltage rises and energy loss increases, and the advantages of SiC cannot be fully utilized. Figure 3 (2) is a cross-sectional view of a conventional SiC-MOSFET. Here, the interface energy state 71 under the gate oxide film hinders channel electron conduction, so the current gain becomes small. In addition, in the trench-type vertical SiC-MOSFET structure (Patent Document 1), even if the gate oxide film is thinned to improve the driving ability, the quality of the SiC thermal oxide film is likely to deteriorate and the low withstand voltage, so the bottom angle of the gate The part 73 often suffers from insulation breakdown defects. Although many annealing methods have been tried for various defects in the SiC interface state or to improve the quality of the thermal oxide film, the root cause of the deterioration has not been fully solved. Therefore, in order to understand the interface state from the basic principle, it is necessary to reexamine from the basics (Non-Patent Document 2). Under such circumstances, the problem to be solved by the present invention is to realize a MOSFET using SiC crystals, which has less conduction loss and can withstand higher voltage.

為了解決以往之問題，專利文獻2提出在SiC上積層Si-MOSFET之構造。第11圖表示該習知例的截面圖。其構造中，凸型Si-MOSFET使用側壁閘極50，在溝槽底設置SiC之蕭特基接面電極62的MESFET作為主動負載。此構造推測係藉由Si-MOSFET降低通道電阻，並藉由在漂移層使用電阻低之SiC基板48，以降低元件整體的導通電阻。在Si中的擊穿電場強度(0.33MV/cm)僅為SiC的1/10程度，故若不使SiC中的高電場(>1MV/cm)減少一位數以上，則會發生突崩潰，但該凸型Si底部形 成有N+層57，故在關閉狀態反而會因為該SiC漂移層的強電場導致Si電位上升。然而，該專利雖說明為了降低電場，將凸丘寬度(通道寬度)盡可能縮小，藉由窄通道效應使電位下降，而可以抑制電場進入Si，惟高密度N型空間電荷會引起電位大幅上升，作用相反而無法期待功效。 In order to solve the conventional problems, Patent Document 2 proposes a structure in which Si-MOSFETs are stacked on SiC. Fig. 11 shows a cross-sectional view of the conventional example. In its structure, the convex Si-MOSFET uses a sidewall gate 50, and a MESFET with a Schottky junction electrode 62 of SiC provided at the bottom of the trench as an active load. This structure presumably reduces the channel resistance by Si-MOSFETs, and uses the SiC substrate 48 with low resistance in the drift layer to reduce the on-resistance of the entire device. The breakdown electric field strength (0.33MV/cm) in Si is only about 1/10 of SiC, so if the high electric field (>1MV/cm) in SiC is not reduced by more than one digit, a sudden breakdown will occur. But the convex Si bottom shape Since the N+ layer 57 is formed, the Si potential rises due to the strong electric field of the SiC drift layer in the off state. However, the patent states that in order to reduce the electric field, the width of the ridge (channel width) is reduced as much as possible, and the potential is reduced by the narrow channel effect, which can suppress the electric field from entering Si, but the high-density N-type space charge will cause the potential to rise significantly , The effect is the opposite and the effect cannot be expected.

另一方面，該專利中，導通狀態下第11圖之側壁型溝槽閘極50的下端比Si與SiC異質接面位置56更上方，故SiC區的表面電位不受到來自溝槽閘極的電場效應，電子無法跨越傳導帶落差而妨礙通道傳導。然而，該專利的構造中，為了在溝槽底面及側面構成MESFET，必須形成蕭特基接面電極62，有必要將該電極上端盡可能靠近該SiC/Si界面，故就物理上不可能使側壁閘極下端的位置比異質接面位置更低。 On the other hand, in this patent, the lower end of the sidewall-type trench gate 50 in FIG. 11 in the on state is higher than the position 56 of the Si-SiC heterojunction, so the surface potential of the SiC region is not affected by the trench gate Due to the electric field effect, electrons cannot cross the conduction band drop and hinder channel conduction. However, in the structure of this patent, in order to form a MESFET on the bottom and sides of the trench, a Schottky junction electrode 62 must be formed. It is necessary to place the upper end of the electrode as close to the SiC/Si interface as possible, so it is physically impossible The position of the lower end of the sidewall gate is lower than that of the heterojunction.

本發明對具有高通道移動度之Si-MOSFET積層由具有高整體移動度之SiC所形成之漂移層，藉此提出可達到高性能之新裝置及其製造方法，解決上述既有裝置的問題。以下列舉出具體的解決手段。 The present invention provides a drift layer formed by SiC having a high overall mobility for a Si-MOSFET with a high channel mobility, thereby proposing a new device capable of achieving high performance and a manufacturing method thereof to solve the above-mentioned problems of the existing device. The specific solutions are listed below.

本發明之功率半導體元件，係在第一導電型SiC基板上直接接合第二導電型Si基板，該第一導電型SiC基板由底面開始依序具有汲極、第一導電型之擴散層及第一導電型之漂移層。由Si的表面挖溝槽(凹陷)至該Si基板及SiC基板的一部分，經由閘極氧化膜埋入多晶矽，形成溝槽閘極。在此，該閘極的底面位置比SiC與Si之接合位置更下方。另一方面，第二導電型Si基板中水平方向的溝槽閘極之間的底邊附近形成比該Si基板更高濃度之第二導電型雜質區域(下稱阻隔層)，以製作在第二導電型Si基板表面方面的上部具有閘極導線及源極導線之MOSFET。 The power semiconductor device of the present invention is directly bonded to the second conductivity type Si substrate on the first conductivity type SiC substrate, the first conductivity type SiC substrate has a drain, a first conductivity type diffusion layer and a A conductive drift layer. A trench (recess) is dug from the surface of Si to a part of the Si substrate and the SiC substrate, and polysilicon is buried through the gate oxide film to form a trench gate. Here, the bottom surface position of the gate electrode is lower than the bonding position of SiC and Si. On the other hand, a second conductivity type impurity region (hereinafter referred to as a barrier layer) with a higher concentration than the Si substrate is formed near the bottom edge between the trench gates in the horizontal direction in the second conductivity type Si substrate The upper part of the surface of the two-conductivity type Si substrate has a MOSFET with a gate wire and a source wire.

較佳使該溝槽閘極的下端位置在比第一導電型SiC的漂移層 與第二導電型Si基板之異質接面位置更深0.5微米以上，藉此在導通狀態下電場效應到達SiC漂移層的MOS界面，使傳導電子容易地跨越Si/SiC傳導帶異質接面的能量障壁，汲極電流可順暢地流動。另一方面，關閉狀態下為逆向偏壓狀態，故必須使來自第一導電型SiC漂移層之高電場在第二導電型Si基板衰減，而藉由將該SiC漂移層與Si基板界面配置於溝槽閘極之間向內方向，形成電場的障壁，緩和電場進入Si中。並且，若溝槽閘極底部的角為尖角，則可能因電場集中而導致絕緣破壞，故有必要使角部變圓。曲率半徑較佳為例如0.05微米以上。此係因電場強度與閘極的曲率半徑呈反比，曲率半徑較佳為閘極寬度的一半。 Preferably, the lower end of the trench gate is located at a lower level than the drift layer of the first conductivity type SiC The position of the heterojunction with the second conductivity type Si substrate is more than 0.5 microns deeper, so that the electric field effect reaches the MOS interface of the SiC drift layer in the on state, so that the conduction electrons easily cross the Si/SiC conduction energy barrier with heterojunction , Drain current can flow smoothly. On the other hand, the off state is the reverse bias state, so it is necessary to attenuate the high electric field from the first conductivity type SiC drift layer in the second conductivity type Si substrate, and by disposing the interface between the SiC drift layer and the Si substrate at Between the trench gates and inward direction, the barrier of the electric field is formed, and the electric field is eased into Si. In addition, if the corner of the bottom of the trench gate is sharp, the insulation may be damaged due to the concentration of the electric field, so it is necessary to round the corner. The radius of curvature is preferably, for example, 0.05 μm or more. This is because the electric field strength is inversely proportional to the radius of curvature of the gate, and the radius of curvature is preferably half the width of the gate.

本發明之功率半導體中，在該關閉狀態必須更大幅緩和在第二導電型Si基板之電場。較佳為設定窄間隔以藉由溝槽閘極之間產生的窄通道效應，Si內電位分布受到空間調變而降低，使電場強度降低。此外，提出在第二導電型Si基板底部設置第二導電型阻隔區，藉此進一步阻止電場進入Si之對策。藉由設置該阻隔層，可以在關閉狀態限制空乏層寬度，故不需要依賴於過度地僅將溝槽閘極間隔縮小。且在導通狀態下，該阻隔層決定通道表面電位，並決定實質上的通道長度，故可穩定地供給電流而不受該Si基板厚度影響。上述本發明中，藉由該溝槽的SiC凹陷、閘極間窄通道效應及形成阻隔層，在導通狀態及關閉狀態可實現穩定的高性能。 In the power semiconductor of the present invention, in this off state, the electric field on the second conductivity type Si substrate must be more greatly relaxed. It is preferable to set a narrow interval so that, due to the narrow channel effect generated between the trench gates, the potential distribution in Si is reduced by spatial modulation and the electric field intensity is reduced. In addition, it is proposed to provide a second conductivity type blocking region at the bottom of the second conductivity type Si substrate, thereby further preventing the electric field from entering Si. By providing the barrier layer, the width of the depletion layer can be limited in the off state, so there is no need to rely on excessively narrowing the trench gate interval. And in the on state, the barrier layer determines the channel surface potential and determines the substantial channel length, so the current can be supplied stably without being affected by the thickness of the Si substrate. In the present invention described above, by the SiC recess of the trench, the narrow channel effect between the gates, and the formation of the barrier layer, stable high performance can be achieved in the on state and the off state.

本發明之功率半導體元件的製造方法，係將形成有第一導電型漂移層之SiC晶圓與第二導電型Si晶圓藉由表面活化接合技術(非專利文獻3、4)結合後，研磨並薄膜化之後，由該Si方面挖出溝槽，且挖至該Si基板及該SiC基板的一部分(凹陷)。之後，使閘極氧化膜成膜後，以多晶矽在該溝槽形成埋入的閘極。MOSFET係在溝槽閘極間的第二導電型Si基板底部形成有第二導電型阻隔層，並形成第一、第二導電型擴散層及連接該擴散層 之電極，以將源極區域及基板電性連接。 The method for manufacturing a power semiconductor device of the present invention is to combine a SiC wafer with a first conductivity type drift layer and a second conductivity type Si wafer by surface activation bonding technology (Non-Patent Documents 3 and 4), and then grind After being thinned, trenches were dug from the Si side, and dug into a part (depression) of the Si substrate and the SiC substrate. Then, after forming the gate oxide film, a buried gate is formed in the trench with polysilicon. In the MOSFET, a second conductivity type barrier layer is formed on the bottom of the second conductivity type Si substrate between the trench gates, and the first and second conductivity type diffusion layers are formed and connected to the diffusion layer Electrodes to electrically connect the source region and the substrate.

藉由本發明之裝置構造及其適合的製造方法，設計出損耗少且可高耐壓化之MOSFET。在導通動作中，亦即需要解決的SiC氧化膜界面缺陷導致通道移動度惡化之問題，可以藉由轉換為使用Si結晶之MOS通道來避免。特別是對於SiC/Si異質接合部分，使溝槽閘極充分重疊SiC(凹陷)方面，藉此在導通狀態下使電子容易跨越傳導帶落差，可以得到較大汲極電流。並且，藉由將第二導電型阻隔層設於同型Si基板底部，則決定實質上的通道長度，故即使該基板厚度有些許不均，亦可保持穩定的電流流動。藉由此構造，涵蓋由源極至汲極之Si及SiC全導電區域可穩定地維持高導電度，可達成低導通電壓。且由於輸入係採用Si-MOSFET構造，閘極輸入脈衝振幅可以比以往的SiC-MOSFET低，故亦可減少振動雜訊或輻射。 With the device structure of the present invention and its suitable manufacturing method, a MOSFET with low loss and high voltage resistance is designed. In the turn-on operation, that is, the problem that the interface defect of the SiC oxide film that needs to be solved leads to the deterioration of the channel mobility can be avoided by switching to a Si crystal MOS channel. Especially in the SiC/Si heterojunction portion, the trench gate is sufficiently overlapped with SiC (depression), thereby making it easier for electrons to cross the conduction band drop in the on state, and a large drain current can be obtained. Furthermore, by providing the second conductivity type barrier layer at the bottom of the same-type Si substrate, the actual channel length is determined, so that even if the thickness of the substrate is slightly uneven, a stable current flow can be maintained. With this structure, the Si and SiC fully conductive regions covering the source to the drain can stably maintain a high conductivity and can achieve a low on-voltage. And because the input system adopts Si-MOSFET structure, the gate input pulse amplitude can be lower than that of the conventional SiC-MOSFET, so it can also reduce vibration noise or radiation.

另一方面，以往在關閉狀態的Si-MOSFET中，對於高耐壓化，除了增厚漂移層以外無其他對策，但本發明中，因為在漂移層使用SiC，故可以大幅提升性能。阻止來自該SiC漂移層的強電場進入Si區的對策，有使溝槽閘極之間變窄以產生窄通道效應、以及在Si面區域形成之第二導電型阻隔層增強該窄通道效應，藉此可有效地阻止電場進入Si中。此外，使該溝槽閘極形成至SiC區域(凹陷)，亦可有效地抑制電場進入該第二導電型Si基板。藉由適當組合上述對策，可以實現低導通電阻，抑制高電壓關閉狀態下Si基板中的突崩潰，可達成以往Si-MOSFET、Si-IGBT、及SiC-MOSFET無法實現的高元件性能。 On the other hand, in the conventional off-state Si-MOSFET, there is no countermeasure other than thickening the drift layer to increase the withstand voltage. However, in the present invention, since SiC is used for the drift layer, performance can be greatly improved. The countermeasures to prevent the strong electric field from the SiC drift layer from entering the Si region include narrowing the trench gates to produce a narrow channel effect, and the second conductivity type barrier layer formed in the Si plane region enhances the narrow channel effect, This can effectively prevent the electric field from entering Si. In addition, forming the trench gate to the SiC region (recess) can also effectively suppress the electric field from entering the second conductivity type Si substrate. By properly combining the above measures, low on-resistance can be achieved, and sudden collapse in the Si substrate in the high-voltage off state can be suppressed, and high device performance that cannot be achieved with conventional Si-MOSFETs, Si-IGBTs, and SiC-MOSFETs can be achieved.

9‧‧‧基板P+擴散層 9‧‧‧Substrate P+ diffusion layer

10‧‧‧N+擴散層 10‧‧‧N+ diffusion layer

11‧‧‧閘極 11‧‧‧Gate

12‧‧‧源極 12‧‧‧Source

13‧‧‧P型Si整體區域 13‧‧‧P-type Si overall area

14‧‧‧P型阻隔層區 14‧‧‧P-type barrier layer area

15‧‧‧Si/SiC界面 15‧‧‧Si/SiC interface

16‧‧‧N型SiC漂移層 16‧‧‧N-type SiC drift layer

17‧‧‧N型SiC汲極擴散層 17‧‧‧N-type SiC drain diffusion layer

18‧‧‧汲極 18‧‧‧ Jiji

19‧‧‧絕緣保護膜 19‧‧‧Insulation protective film

21‧‧‧硬光罩 21‧‧‧ Hard Mask

22‧‧‧溝槽 22‧‧‧Groove

23‧‧‧多晶矽 23‧‧‧ Polycrystalline silicon

25‧‧‧閘極氧化膜 25‧‧‧ Gate oxide film

27‧‧‧電位分布等高線 27‧‧‧potential contour

28‧‧‧P型基板底部N型區之形成 28‧‧‧Formation of N-type region at the bottom of P-type substrate

29‧‧‧溝槽閘極底面氧化膜 29‧‧‧Trench gate bottom oxide film

A‧‧‧能帶圖區 A‧‧‧Energy zone

B‧‧‧專利文獻1之溝槽閘極側面的SiC重疊區 B‧‧‧ Patent document 1 SiC overlap region on the side of the trench gate

30‧‧‧習知SiC-MOSFET的N型源極擴散層 30‧‧‧N-type source diffusion layer of conventional SiC-MOSFET

31‧‧‧習知SiC-MOSFET的閘極 31‧‧‧Know SiC-MOSFET gate

32‧‧‧習知SiC-MOSFET的閘極 32‧‧‧Know SiC-MOSFET gate

33‧‧‧習知SiC-MOSFET的P型SiC區 33‧‧‧P-type SiC region of conventional SiC-MOSFET

36‧‧‧習知Si-MOSFET的N型漂移區 36‧‧‧N-type drift region of conventional Si-MOSFET

37‧‧‧習知Si-MOSFET的N型汲極擴散區 37‧‧‧N-type drain diffusion region of conventional Si-MOSFET

38‧‧‧習知Si-MOSFET的汲極 38‧‧‧Know Si-MOSFET drain

39‧‧‧習知SiC-MOSFET的絕緣保護膜 39‧‧‧ Known SiC-MOSFET insulation protective film

42‧‧‧專利文獻1之公知例的裝置截面圖 42. Cross-sectional view of a known example of Patent Document 1

48‧‧‧同公知例的SiC基板 48‧‧‧Similar SiC substrate

49‧‧‧同公知例的側壁閘極 49‧‧‧Side gate gate of the same known example

50‧‧‧同公知例的側壁閘極 50‧‧‧Side gate gate of the same known example

52‧‧‧同公知例的源極 52‧‧‧The source of the same public example

54‧‧‧同公知例的汲極 54‧‧‧The drain of the same common law

56’‧‧‧同公知例的N型層SiC漂移層與N型Si層界面 56’‧‧‧ The interface between the N-type SiC drift layer and the N-type Si layer in the same well-known example

57‧‧‧同公知例的N型層Si之MESFET擴散層 57‧‧‧ Same type of MESFET diffusion layer of N-type Si

58‧‧‧同公知例的N型Si源極擴散層 58‧‧‧N-type Si source diffusion layer of the same known example

59‧‧‧同公知例的N型層Si之汲極擴散層 59‧‧‧Drain diffusion layer of N-type layer Si of the same known example

60‧‧‧同公知例的P型Si基板 60‧‧‧P-type Si substrate of the same known example

61‧‧‧同公知例的閘極氧化膜 61‧‧‧ Gate oxide film of the same known example

62‧‧‧同公知例的蕭特基接面電極 62‧‧‧ Schottky junction electrode of the same known example

71‧‧‧習知SiC-MOSFET的介面能態 71‧‧‧Know SiC-MOSFET interface energy state

72‧‧‧習知SiC-MOSFET的汲極擴散層 72‧‧‧Know SiC-MOSFET drain diffusion layer

73‧‧‧習知SiC-MOSFET的溝槽角閘極氧化膜 73‧‧‧The conventional SiC-MOSFET trench angle gate oxide film

〔第1圖〕本發明之裝置的截面構造圖。 [Figure 1] A cross-sectional structural view of the device of the present invention.

〔第2圖〕本發明的能帶圖，a)表示導通狀態，b)表示關閉狀態。 [Figure 2] The energy band diagram of the present invention, a) shows an on state and b) shows an off state.

〔第3圖〕習知例的說明圖，(1)為習知Si-MOSFET的截面圖，(2)為習知SiC-MOSFET的截面圖。 [FIG. 3] An explanatory diagram of a conventional example, (1) is a sectional view of a conventional Si-MOSFET, and (2) is a sectional view of a conventional SiC-MOSFET.

〔第4圖〕a)及b)表示本發明中通道寬度的差異造成電位分布之調變效應概略圖，b)及c)表示有無形成P型阻隔層之差異造成電位分布之調變效應概略圖。 [Figure 4] a) and b) are schematic diagrams showing the modulation effect of the potential distribution caused by the difference in channel widths in the present invention, b) and c) are schematic diagrams showing the modulation effect of the potential distribution caused by the difference in the presence or absence of forming a P-type barrier layer Figure.

〔第5圖〕裝置模擬結果，係針對本發明中閘極間產生之窄通道效應造成之閘極間中央位置的電場分布，以及有無在閘極間中央位置之Si表層部的P型阻隔層之電場分布。 [Figure 5] The device simulation results are based on the electric field distribution of the central position between the gates caused by the narrow channel effect generated between the gates of the present invention, and the presence or absence of the P-type barrier layer at the Si surface portion at the central position between the gates The electric field distribution.

〔第6圖〕說明本發明之製造方法的主要部分步驟圖(1)及(2)。 [Figure 6] Step diagrams (1) and (2) illustrating the main steps of the manufacturing method of the present invention.

〔第7圖〕同樣說明本發明之製造方法的主要部分步驟圖(3)及(4)。 [Figure 7] Similarly, steps (3) and (4) of the main part of the manufacturing method of the present invention will be described.

〔第8圖〕同樣說明本發明之製造方法的主要部分步驟圖(5)及(6)。 [Figure 8] The steps (5) and (6) of the main part of the manufacturing method of the present invention will also be described.

〔第9圖〕同樣說明本發明之製造方法的主要部分步驟圖(7)及(8)。 [Figure 9] Similarly, steps (7) and (8) of the main part of the manufacturing method of the present invention will be described.

〔第10圖〕本發明其他實施例之裝置構造，(1)使整體P型Si層為高濃度之情況下的截面圖，(2)使溝槽閘極正下方氧化膜的厚度比側面更厚之情況下的截面圖。 [Figure 10] A device structure of another embodiment of the present invention, (1) a cross-sectional view when the entire P-type Si layer is at a high concentration, (2) a thickness of the oxide film directly below the trench gate is greater than that of the side Sectional view in the thick case.

〔第11圖〕專利文獻1之習知例的元件截面圖。 [Figure 11] A cross-sectional view of a device of a conventional example of Patent Document 1.

本發明提出以Si構成MOSFET部分且以SiC構成漂移層部分的新穎功率MOSFET構造，以及藉由直接接合方法可將Si晶圓及SiC晶圓形成一體之製程作為該功率MOSFET的製造方法。 The present invention proposes a novel power MOSFET structure in which Si constitutes a MOSFET part and SiC constitutes a drift layer part, and a process in which a Si wafer and a SiC wafer can be integrated by a direct bonding method is used as a manufacturing method of the power MOSFET.

以下用第1圖及第2圖詳細說明第一實施例。圖中的符號9為第二導電型，例如P型擴散層，10為第一導電型，例如N型源極擴散層。以 下將第一導電型作為N型，將第二導電型作為P型，反過來亦可。11為閘極，12為源極，13為P型Si整體區域，14為比P型基板更高濃度之P型基板，係記載為阻隔區，16為N型SiC形成之漂移層，17為N型SiC之汲極擴散層，18為汲極，19為保護膜。與習知SiC-MOSFET不同的是，MOSFET區內的P型阻隔層區14、N型源極擴散層10、P型擴散層9及P型整體層13形成於Si基板內，N型汲極17及N型漂移層16形成於SiC基板內。如圖所示，閘極多晶矽23的溝槽方向深度達到比Si/SiC界面15更深之該SiC內部區域。又，閘極係以多晶矽及金屬形成，但以下記載為閘極多晶矽。P型Si基板之P型阻隔層14的位置形成在該SiC漂移層與該Si基板之界面15附近。在此，將閘極多晶矽23的底部與該異質接面重疊(overlap)，以使閘極電場及通道電流道不被該漂移區阻斷。此外，本實施例中，此藉由下述之製造方法，分別在Si基板形成P型整體層13以及在SiC基板形成N型漂移層16及N型汲極17，該P型整體層13係在相當於MOSFET部分之源極10及閘極11的下部形成通道區，用使P型Si基板及N型SiC漂移層16相對的方式直接接合。 The first embodiment will be described in detail below with reference to FIGS. 1 and 2. Symbol 9 in the figure is a second conductivity type, such as a P-type diffusion layer, and 10 is a first conductivity type, such as an N-type source diffusion layer. To In the following, the first conductivity type is referred to as N type, and the second conductivity type is referred to as P type, or vice versa. 11 is the gate electrode, 12 is the source electrode, 13 is the entire P-type Si region, 14 is a P-type substrate with a higher concentration than the P-type substrate, which is described as a barrier region, 16 is a drift layer formed by N-type SiC, and 17 is N-type SiC's drain diffusion layer, 18 is the drain, and 19 is the protective film. Unlike the conventional SiC-MOSFET, the P-type barrier layer region 14, the N-type source diffusion layer 10, the P-type diffusion layer 9 and the P-type integral layer 13 are formed in the Si substrate, and the N-type drain 17 and the N-type drift layer 16 are formed in the SiC substrate. As shown in the figure, the groove depth of the gate polysilicon 23 reaches the inner region of the SiC deeper than the Si/SiC interface 15. In addition, the gate system is formed of polysilicon and metal, but the following description is referred to as gate polysilicon. The position of the P-type barrier layer 14 of the P-type Si substrate is formed near the interface 15 between the SiC drift layer and the Si substrate. Here, the bottom of the gate polysilicon 23 is overlapped with the heterojunction, so that the gate electric field and channel current channel are not blocked by the drift region. In addition, in this embodiment, the P-type monolithic layer 13 is formed on the Si substrate and the N-type drift layer 16 and the N-type drain 17 are formed on the SiC substrate by the following manufacturing method. A channel region is formed in the lower part of the source electrode 10 and the gate electrode 11 corresponding to the MOSFET part, and the P-type Si substrate and the N-type SiC drift layer 16 are directly joined so as to face each other.

關於如此製作出之接面，由能帶的觀點來說明本MOSFET之作動。第2圖a)為第1圖所示之虛線部分A之導通狀態的能帶圖，係圖解對導通狀態之Si/SiC異質界面15的漂移層注入電子之機制Si/SiC異質界面15。如圖所示，在導通狀態之該能帶圖中，傳導帶端的能態係SiC僅比Si高0.5eV，故對傳導電子而言形成障壁，在MOS構造中該Si基板中的自由電子藉由閘極電場充滿至SiC的能量傳導帶端。為了使傳導電子跨越此能量障壁，在該SiC(凹陷，recess)內的MOS構造中由溝槽閘極擴大電場使SiC表面電位上升，則電子可容易地跨越SiC之該能量障壁，電子可被注入至N型漂移層16。另一方面，在P型阻隔層14中通道電位降低，故在此區域中 電流藉由電場效應被控制，因此實質上可視為通道長度。如此一來，汲極電流保持固定，不與該基板的厚度相關聯。 Regarding the junction thus fabricated, the operation of this MOSFET will be explained from the viewpoint of energy band. FIG. 2 a) is an energy band diagram of the on-state of the broken line portion A shown in FIG. 1 and illustrates the mechanism of injecting electrons into the drift layer of the on-state Si/SiC hetero-interface 15 of the Si/SiC hetero-interface 15. As shown in the figure, in the on-state energy band diagram, the energy state of the conduction band end is only 0.5eV higher than that of Si, so a barrier is formed for conduction electrons. In the MOS structure, free electrons in the Si substrate borrow The gate electric field is filled to the end of the SiC energy conduction band. In order to make the conduction electron cross the energy barrier, in the MOS structure in the SiC (recess), the trench gate expands the electric field to increase the surface potential of the SiC, then the electron can easily cross the energy barrier of the SiC, and the electron can be Implanted into the N-type drift layer 16. On the other hand, the channel potential in the P-type barrier layer 14 decreases, so in this region The current is controlled by the effect of the electric field, so it can be essentially regarded as the channel length. In this way, the drain current remains fixed and is not related to the thickness of the substrate.

另一方面，第2圖b)表示關閉狀態的能帶圖。在此係形成逆向偏壓狀態，故電場由SiC漂移層進入P型Si基板，在產生電場強度超過Si中的容許程度(0.33MV/cm)的情況下，可能在Si中產生電子撞擊而引起突崩潰。對此，第一對策為P型Si基板內之窄通道效應。此係將2個閘極間的P型Si基板寬度縮小，藉由具有接地電位之閘極端產生的邊緣效應，使電位分布調變，藉此抑制電場進入Si。為了更能抑制電場，有必要將Si區域的寬度縮小至半導體微細化之極限。第4圖a)及b)表示電位分布因通道寬度不同而受到空間調變的情形，a)表示通道寬度寬的情況，b)表示通道寬度窄的情況。 On the other hand, FIG. 2 b) shows the energy band diagram in the closed state. In this system, the reverse bias state is formed, so the electric field enters the P-type Si substrate from the SiC drift layer. When the electric field strength exceeds the allowable level in Si (0.33MV/cm), electron impact may occur in Si. Suddenly collapse. In this regard, the first countermeasure is the narrow channel effect in the P-type Si substrate. This is to reduce the width of the P-type Si substrate between the two gates, and to modulate the potential distribution by the edge effect generated by the gate terminal with the ground potential, thereby suppressing the electric field from entering the Si. In order to suppress the electric field more, it is necessary to reduce the width of the Si region to the limit of semiconductor miniaturization. Figure 4 a) and b) show the situation where the potential distribution is spatially modulated due to different channel widths, a) shows the case where the channel width is wide, and b) shows the case where the channel width is narrow.

另一方面，第二對策係對於由SiC漂移層進入之電場，在Si基板底面區域形成比Si基板更高濃度之P型阻隔擴散層3，藉此可有效地阻止電場進入Si區域。第4圖b)及c)表示有無阻隔層之差異。 On the other hand, the second countermeasure is to form a P-type barrier diffusion layer 3 with a higher concentration in the bottom surface area of the Si substrate than the Si substrate for the electric field entered by the SiC drift layer, thereby effectively preventing the electric field from entering the Si area. Figure 4 b) and c) show the difference between the presence and absence of barrier layers.

為了預測上述兩種電場緩和方法的效果，第5圖a)及b)表示關閉狀態的深度方向電場分布。在此，溝槽閘極設為0V，對汲極18施加1000V，SiC漂移層設為10微米。第5圖a)表示在第一實施例中，為了測試第一對策之窄通道效應，將閘極間隔W由4.2微米(虛線)縮小至1.2微米(實線)的情況下，Si/SiC界面附近的Si中每1微米的平均電場變化。由此可知電場因窄通道(W=1.2微米)而被大幅降低。此正是藉由邊緣效應，使得來自SiC之電場調變，使位能降低。又，第5圖b)表示有無第二對策之Si面的P型阻隔區3的結果。由此可知存在有阻隔層的情況(實線)電場強度被進一步降低。 In order to predict the effects of the above two electric field relaxation methods, Fig. 5 a) and b) show the depth direction electric field distribution in the off state. Here, the trench gate is set to 0V, 1000V is applied to the drain 18, and the SiC drift layer is set to 10 microns. Fig. 5a) shows that in the first embodiment, in order to test the narrow channel effect of the first countermeasure, when the gate interval W is reduced from 4.2 μm (dashed line) to 1.2 μm (solid line), the Si/SiC interface The average electric field per 1 micrometer in nearby Si changes. It can be seen from this that the electric field is greatly reduced due to the narrow channel (W=1.2 microns). This is precisely because of the edge effect, so that the electric field from SiC is modulated and the potential energy is reduced. FIG. 5 b) shows the results of the P-type barrier region 3 on the Si plane with or without the second countermeasure. From this, it can be seen that the presence of a barrier layer (solid line) further reduces the electric field strength.

此外，設置如第2圖的B所示之閘極與汲極層重疊區(凹陷)， 亦可有效地阻止在關閉狀態下電場過度進入Si中。此係因為該溝槽閘極作為障壁，電場難以到達異質接面。由非專利文獻7的解離常數之電場相依性已知，像這樣藉由組合該閘極之間的窄通道效應、P型阻隔層的效果及對異質接面之閘極重疊效應，進入Si中的電場在深度1微米之平均值低於0.2MV/cm，電離係數為0.1程度，已充分降低至不會發生突崩潰的程度。 In addition, the overlapping area (recess) of the gate and the drain layer as shown in B of FIG. 2 is provided, It can also effectively prevent the electric field from entering the Si excessively in the off state. This is because the trench gate acts as a barrier, making it difficult for the electric field to reach the heterojunction. The electric field dependence of the dissociation constant of Non-Patent Document 7 is known. As such, by combining the narrow channel effect between the gates, the effect of the P-type barrier layer and the gate overlap effect on the heterojunction, it enters Si The average value of the electric field at a depth of 1 micron is less than 0.2MV/cm, and the ionization coefficient is about 0.1, which has been sufficiently reduced to the point that sudden collapse does not occur.

以下詳細說明本發明之第二實施例。第二實施例係關於藉由將該SiC與該Si兩個晶圓直接接合為一體後形成的MOSFET之製造方法。 The second embodiment of the present invention will be described in detail below. The second embodiment relates to a method of manufacturing a MOSFET formed by directly bonding two wafers of SiC and Si into one body.

目前為止亦有在功率半導體之製造中使用晶圓直接接合(例如非專利文獻3)，但像這樣不同半導體晶圓彼此直接接合的方法，已有對表面照射中性原子束，去除自然氧化膜，並使表面層非結晶化且壓接以保持結晶完整性的表面活化接合技術(Surface Activated Bonding，下稱SAB)，實現異質接面裝置(非專利文獻4)。又，非結晶化的部分在壓接後藉由後退火進行再結晶而得到連續的結晶界面。非專利文獻5揭示n⁺-Si：n-4H-SiC的接合例以及藉由退火得到改善的二極體特性。此外，存在於晶圓接合面的介面能態係藉由在SAB接合後的退火處理而被大幅改善。 Until now, direct wafer bonding has been used in the manufacture of power semiconductors (for example, Non-Patent Document 3), but in this way, different semiconductor wafers are directly bonded to each other, and the surface has been irradiated with a neutral atomic beam to remove the natural oxide film. The surface activated bonding technology (Surface Activated Bonding, hereinafter referred to as SAB) which makes the surface layer non-crystallized and pressure-bonded to maintain crystalline integrity realizes a heterojunction device (Non-Patent Document 4). In addition, the non-crystallized portion is recrystallized by post annealing after crimping to obtain a continuous crystal interface. Non-Patent Document 5 discloses an n ⁺ -Si: n-4H-SiC bonding example and diode characteristics improved by annealing. In addition, the interface energy state existing on the wafer bonding surface is greatly improved by the annealing treatment after SAB bonding.

以下用第6圖至第9圖詳細說明本發明之製造方法的一例子。第6圖(1)的步驟中，藉由在第一P型Si晶圓的表面注入例如硼之P型離子，形成該阻隔層14。另一方面，第二SiC晶圓係在作為汲極擴散層之N+SiC基板17上藉由磊晶成長使SiC漂移層成長所形成者。之後在第6圖(2)中對第一Si晶圓及第二SiC晶圓分別照射離子或Ar等中性原子束，去除自然氧化膜使其活化後，藉由SAB法結合。 Hereinafter, an example of the manufacturing method of the present invention will be described in detail using FIGS. 6 to 9. In the step of FIG. 6 (1), the barrier layer 14 is formed by implanting P-type ions such as boron on the surface of the first P-type Si wafer. On the other hand, the second SiC wafer is formed by growing the SiC drift layer by epitaxial growth on the N+SiC substrate 17 as the drain diffusion layer. Then, in FIG. 6 (2), the first Si wafer and the second SiC wafer are irradiated with neutral atomic beams such as ions or Ar, respectively, and the natural oxide film is removed and activated, and then combined by the SAB method.

在第7圖(3)將P型Si晶圓的背面研磨至厚度約1微米，並藉由CMP(Chemical Mechanical Polishing)法平坦化。之後在(4)形成硬光罩21，將P型Si基板13及N型SiC漂移層16的一部分藉由RIE等蝕刻。 SiC的蝕刻深度(凹陷)較佳為0.5微米程度。又，溝槽角若為例如0.05微米以上，則由氧化膜中緩和電場的觀點而言，最大可以給予閘極寬度的一半之曲率半徑為佳。之後第8圖(5)之步驟中形成閘極氧化膜25，(6)之步驟中在溝槽內使多晶矽成長，以CMP研磨至Si表面且平坦化。第9圖(6)之步驟中將高濃度N型擴散層10及高濃度P型擴散層9以高電流離子注入，分別形成源極12、基板電極12用的雜質擴散層。(8)中經由絕緣保護膜19及導線連接製程以形成11、12的導線電極。 In FIG. 7 (3), the back surface of the P-type Si wafer is polished to a thickness of about 1 μm, and planarized by the CMP (Chemical Mechanical Polishing) method. Thereafter, a hard mask 21 is formed in (4), and a part of the P-type Si substrate 13 and the N-type SiC drift layer 16 is etched by RIE or the like. The etching depth (depression) of SiC is preferably about 0.5 micrometer. In addition, if the groove angle is, for example, 0.05 μm or more, from the viewpoint of relaxing the electric field in the oxide film, it is preferable that the radius of curvature that can be given to the half of the gate width is at most. After that, the gate oxide film 25 is formed in the step (5) of FIG. 8, and the polysilicon is grown in the trench in the step (6), polished to the Si surface by CMP and planarized. In the step of FIG. 9 (6), the high-concentration N-type diffusion layer 10 and the high-concentration P-type diffusion layer 9 are ion-implanted with high current to form impurity diffusion layers for the source electrode 12 and the substrate electrode 12, respectively. In (8), the connection electrodes 11 and 12 are formed through the insulating protective film 19 and the wire connection process.

此外，第10圖中說明其他兩個實施例。(1)係將該P型基板13整體形成與阻隔區14相同濃度。該Si基板的厚度非常薄的情況下可以使整體有相同濃度。(2)係將溝槽閘極正下方的氧化膜的厚度形成比側面的氧化膜更厚。為了降低漂移層的電阻，必須提升N型SiC漂移層16的施體濃度，但漂移層內電場及閘極氧化膜的電場會上升。對此，將該閘極底面氧化膜29形成比側面的氧化膜25更厚，則電場被緩和，不容易發生氧化膜的絕緣破壞。 In addition, FIG. 10 illustrates two other embodiments. (1) The entire concentration of the P-type substrate 13 is the same as that of the barrier region 14. When the thickness of the Si substrate is very thin, the entire concentration can be the same. (2) The thickness of the oxide film directly under the trench gate is formed to be thicker than the oxide film on the side. In order to reduce the resistance of the drift layer, the donor concentration of the N-type SiC drift layer 16 must be increased, but the electric field in the drift layer and the electric field of the gate oxide film will increase. On the other hand, if the oxide film 29 on the bottom surface of the gate electrode is formed to be thicker than the oxide film 25 on the side surface, the electric field is relaxed, and the insulation breakdown of the oxide film is unlikely to occur.

藉由本發明，可以實現大電力、高效率且低雜訊之功率半導體，對於降低社會基礎建設的總電力使用量產生貢獻，有助改善地球暖化等之環境問題。 With the present invention, a power semiconductor with high power, high efficiency, and low noise can be realized, which contributes to the reduction of the total power usage of social infrastructure, and helps to improve environmental problems such as global warming.

9‧‧‧基板P+擴散層 9‧‧‧Substrate P+ diffusion layer

10‧‧‧N+擴散層 10‧‧‧N+ diffusion layer

11‧‧‧閘極 11‧‧‧Gate

12‧‧‧源極 12‧‧‧Source

13‧‧‧P型Si整體區域 13‧‧‧P-type Si overall area

14‧‧‧P型阻隔層區 14‧‧‧P-type barrier layer area

15‧‧‧Si/SiC界面 15‧‧‧Si/SiC interface

16‧‧‧N型SiC漂移層 16‧‧‧N-type SiC drift layer

17‧‧‧N型SiC汲極擴散層 17‧‧‧N-type SiC drain diffusion layer

18‧‧‧汲極 18‧‧‧ Jiji

19‧‧‧絕緣保護膜 19‧‧‧Insulation protective film

23‧‧‧多晶矽 23‧‧‧ Polycrystalline silicon

25‧‧‧閘極氧化膜 25‧‧‧ Gate oxide film

A‧‧‧能帶圖區 A‧‧‧Energy zone

Claims (10)

一種功率半導體元件，係在第一導電型SiC基板的上部直接接合第二導電型Si基板，該第一導電型SiC基板由背面開始依序具有汲極、第一導電型之第一汲極擴散層及比該第一汲極擴散層更低濃度之第一導電型之第二汲極擴散層，由該第二導電型Si基板的表面挖溝槽至比該Si/SiC接合界面更深之SiC層內部，在涵蓋該Si基板-該Si/SiC界面-該SiC基板之側面設置氧化膜及電極，以形成在該Si基板上部具有第一導電型之汲極擴散層及第二導電型基板擴散層之MOS構造。 A power semiconductor element is directly connected to a second conductivity type Si substrate on the top of a first conductivity type SiC substrate, the first conductivity type SiC substrate has a drain and a first conductivity type first drain diffusion in sequence from the back Layer and a second drain diffusion layer of the first conductivity type having a lower concentration than the first drain diffusion layer, trenches are dug from the surface of the second conductivity type Si substrate to SiC deeper than the Si/SiC junction interface Inside the layer, an oxide film and electrodes are provided on the side of the Si substrate-the Si/SiC interface-the SiC substrate to form a diffusion layer of the first conductivity type and the second conductivity type on the upper portion of the Si substrate MOS structure of the layer. 如申請專利範圍第1項所述之功率半導體元件，其中，在該第一導電型SiC基板的上部直接接合第二導電型Si基板的方法為表面活化接合技術。 The power semiconductor device as described in item 1 of the patent application range, wherein the method of directly bonding the second conductivity type Si substrate on the upper portion of the first conductivity type SiC substrate is a surface activation bonding technology. 如申請專利範圍第1項所述之功率半導體元件，其中，該MOS構造中閘極的形狀為溝槽閘極型，該溝槽閘極的頂端位於第一導電型SiC漂移層內深度0.5微米以上之處。 The power semiconductor device as described in item 1 of the patent application range, wherein the shape of the gate in the MOS structure is a trench gate, and the tip of the trench gate is located in the first conductivity type SiC drift layer to a depth of 0.5 μm The above. 如申請專利範圍第1項所述之功率半導體元件，其中，該MOS構造中閘極的形狀為溝槽閘極型，該溝槽閘極的頂端角具有弧度，該弧度的曲率半徑最小為0.05微米且最大為閘極寬度的一半。 The power semiconductor device as described in item 1 of the patent application scope, wherein the shape of the gate in the MOS structure is a trench gate type, the tip angle of the trench gate has an arc, and the minimum radius of curvature of the arc is 0.05 Micron and maximum half of the gate width. 如申請專利範圍第1項所述之功率半導體元件，其中，數個溝槽閘極為平行設置以增加通道寬度，夾於閘極之間的第二導電型Si基板的水平方向寬度為2微米以下。 The power semiconductor device as described in item 1 of the patent application scope, in which several trench gates are arranged in parallel to increase the channel width, and the horizontal width of the second conductivity type Si substrate sandwiched between the gates is 2 microns or less . 如申請專利範圍第1項所述之功率半導體元件，其中，該第二導電型Si基板中接合於該第一導電型SiC界面之底部，形成有比該第二導電型Si基板更高濃度之第二導電型阻隔擴散區。 The power semiconductor device as described in item 1 of the patent application range, wherein the second conductivity type Si substrate is bonded to the bottom of the first conductivity type SiC interface, and a higher concentration is formed than the second conductivity type Si substrate The second conductivity type blocks the diffusion region. 如申請專利範圍第1項所述之功率半導體元件，其中，該第二 導電型Si基板中接合於該第一導電型SiC界面之該第二導電型Si基板。 The power semiconductor device as described in item 1 of the patent application scope, wherein the second The second conductivity type Si substrate bonded to the interface of the first conductivity type SiC in the conductivity type Si substrate. 如申請專利範圍第1項所述之功率半導體元件，其中，使該第二導電型Si基板及第一導電型SiC漂移層的一部分內形成之溝槽閘極的底部的該氧化膜厚度，比該側面的氧化膜更厚。 The power semiconductor device according to item 1 of the patent application range, wherein the thickness of the oxide film at the bottom of the trench gate formed in a part of the second conductivity type Si substrate and the first conductivity type SiC drift layer is greater than The oxide film on this side is thicker. 如申請專利範圍第1項所述之功率半導體元件，其中，該第二導電型Si基板直接接合之第一導電型基板材料係使用SiC以外的寬能帶隙材料，該材料為GaN、Ga₂O₃及鑽石。 The power semiconductor device as described in item 1 of the patent application range, wherein the first conductivity type substrate material directly bonded to the second conductivity type Si substrate uses a wide bandgap material other than SiC, and the material is GaN, Ga ₂ O ₃ and diamonds. 一種功率半導體元件的製造方法，係在第二導電型之第一半導體基板表面形成第二導電型區域，對於該第一半導體基板及第一導電型之第二半導體基板上所形成之第一導電型磊晶半導體層，分別對表面照射離子或Ar中性原子束，去除自然氧化膜並活化，使該第一半導體基板表面與該第二磊晶半導體層表面相對，藉由直接接合來結合後，將第一半導體基板研磨至厚度為0.5~1.2微米。 A method for manufacturing a power semiconductor element is to form a second conductivity type region on the surface of a second conductivity type first semiconductor substrate, and for the first conductivity formed on the first semiconductor substrate and the first conductivity type second semiconductor substrate The epitaxial semiconductor layer is irradiated with ions or Ar neutral atomic beams to the surface, respectively, to remove the natural oxide film and activate, so that the surface of the first semiconductor substrate and the surface of the second epitaxial semiconductor layer are opposed by direct bonding , Grinding the first semiconductor substrate to a thickness of 0.5-1.2 microns.

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