TW202011694A - Pulse frequency modulation controlling method and power converting circuit using same - Google Patents

Pulse frequency modulation controlling method and power converting circuit using same Download PDF

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TW202011694A
TW202011694A TW107131201A TW107131201A TW202011694A TW 202011694 A TW202011694 A TW 202011694A TW 107131201 A TW107131201 A TW 107131201A TW 107131201 A TW107131201 A TW 107131201A TW 202011694 A TW202011694 A TW 202011694A
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time
tri
pulse frequency
frequency modulation
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TWI653829B (en
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李東
金寧
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大陸商北京集創北方科技股份有限公司
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Abstract

A pulse frequency modulation controlling method includes the following steps: when detecting that a feedback voltage is less than a reference voltage, a control circuit starts the ON phase of the pulse frequency modulation period, wherein the feedback voltage is generated according to an output voltage, and the ON duration of the ON phase is controlled by a three-state feedback control signal; when the ON duration is over, the control circuit enables the pulse frequency modulation period to enter an OFF phase from the ON phase; when detecting that a zero-crossing detection signal is active, the control circuit enables the pulse frequency modulation period to enter a tri-state phase from the OFF phase; and, when detecting that the feedback voltage is less than the reference voltage, the control circuit ends the tri-state phase, and then starts the next pulse frequency modulation period.

Description

脈衝頻率調變的控制方法和利用其之電源轉換電路Control method of pulse frequency modulation and power conversion circuit using the same

本發明係有關於一種脈衝頻率調變的控制方法，特別是有關於一種利用前一個脈衝頻率調變週期的三態時間(或稱死區時間)決定下一個脈衝頻率調變週期的導通期間，以有效抑制輸出電壓的靜態紋波的控制方法。The present invention relates to a control method for pulse frequency modulation, and in particular to a three-state time (or dead time) of the previous pulse frequency modulation period to determine the conduction period of the next pulse frequency modulation period. To effectively suppress the static ripple of the output voltage.

圖1a顯示一傳統降壓轉換器的電路圖，圖1b顯示一傳統升壓轉換器的電路圖，其中，該傳統降壓轉換器和該傳統升壓轉換器均包含一電晶體101、一電晶體102、一電感103、一輸入電容104和一輸出電容105。FIG. 1a shows a circuit diagram of a conventional buck converter, and FIG. 1b shows a circuit diagram of a conventional boost converter. The conventional buck converter and the conventional boost converter both include a transistor 101 and a transistor 102. , An inductor 103, an input capacitor 104 and an output capacitor 105.

在該傳統降壓轉換器的操作中，當一PWM(pulse width modulation；脈衝寬度調變)信號為低邏輯電位時，電晶體102為導通，電晶體101為斷開，以使輸入電壓VIN 對電感103及輸出電容105充電，且此時輸出電容105上的輸出電壓VOUT 低於輸入電壓VIN ；當PWM信號為高邏輯電位時，電晶體102為斷開，電晶體101為導通，以使輸入電壓VIN 被隔絕並使電感103釋放其儲存的電能。In the operation of the conventional buck converter, when a PWM (pulse width modulation; pulse width modulation) signal is at a low logic potential, the transistor 102 is turned on and the transistor 101 is turned off, so that the input voltage V IN The inductor 103 and the output capacitor 105 are charged, and the output voltage V OUT on the output capacitor 105 is lower than the input voltage V IN at this time; when the PWM signal is at a high logic potential, the transistor 102 is off and the transistor 101 is on, In order to isolate the input voltage V IN and allow the inductor 103 to release its stored electrical energy.

在該傳統升壓轉換器的操作中，當一PWM信號為高邏輯電位時，電晶體101為導通，電晶體102為斷開，此時輸入電壓VIN 對電感103充電；當PWM信號為低邏輯電位時，電晶體101為斷開，電晶體102為導通，以使電感103釋放其儲存的電能，且此時輸出電容105上的輸出電壓VOUT 高於輸入電壓VIN 。In the operation of the conventional boost converter, when a PWM signal is at a high logic potential, the transistor 101 is turned on and the transistor 102 is turned off. At this time, the input voltage V IN charges the inductor 103; when the PWM signal is low At the logic potential, the transistor 101 is off and the transistor 102 is on, so that the inductor 103 releases its stored electrical energy, and the output voltage V OUT on the output capacitor 105 is higher than the input voltage V IN at this time .

然而，随着電晶體101和電晶體102的導通和斷開，電感103中的電流是在輸出電流的有效值之間上下波動的，所以輸出電壓VOUT 會出現一個與電晶體101和電晶體102的導通和斷開同頻率的一輸出紋波。另外，一般的開關電源轉換器在驅動一低功耗負載時，為了提高效率，其控制電路會工作在一脈衝頻率調變(phase frequency modulation；PFM)模式下。然而，在所述脈衝頻率調變模式下所產生的所述輸出紋波，一般而言會大於在連續導通模式(continuous conduction mode；CCM)下所產生的所述輸出紋波。However, as transistor 101 and transistor 102 are turned on and off, the current in inductor 103 fluctuates between the effective value of the output current, so the output voltage V OUT will appear a 102 turns on and off an output ripple at the same frequency. In addition, in order to improve efficiency when a general switching power converter drives a low-power load, its control circuit will work in a phase frequency modulation (PFM) mode. However, the output ripple generated in the pulse frequency modulation mode is generally larger than the output ripple generated in continuous conduction mode (CCM).

圖2a和圖2b分別顯示一降壓轉換及一升壓轉換在脈衝頻率調變模式下的操作波形圖，其中20代表一電感電流，21代表一輸出電壓。如圖2a和圖2b所示，每一PFM週期可分為導通時間TON 、斷開時間TOFF 和三態時間TTRI 三個階段。在導通時間TON ，一輸入電源會對一電感進行充電，在斷開時間TOFF ，該電感會進行放電，而在三態時間TTRI ，該電感的電流為零。2a and 2b respectively show the operation waveforms of a buck conversion and a boost conversion in the pulse frequency modulation mode, where 20 represents an inductor current and 21 represents an output voltage. As shown in FIG. 2a and FIG. 2b, each PFM cycle can be divided into three stages of on-time T ON , off-time T OFF and tri-state time T TRI . During the on time T ON , an input power source will charge an inductor, and during the off time T OFF , the inductor will discharge, and during the tri-state time T TRI , the current of the inductor is zero.

在降壓轉換的導通時間TON 中，由於一輸入電源在對一電感充電的同時，所產生的電流也會供給一輸出電容及一負載，所以在該輸出電容上所產生的輸出電壓，其最大上升斜率會在該電感的電流峰值處。另外，在斷開時間TOFF 內，該電感的電流會逐漸變小，而當該電感的電流等於供給該負載的電流時，該輸出電壓會到達其峰值，然後逐漸降低，且該輸出電壓的下降趨勢會持續至下個週期的導通時間TON 內，直到該電感電流等於供給該負載的電流時，才逐漸上升。During the on-time T ON of the buck conversion, since an input power source charges an inductor, the generated current will also supply an output capacitor and a load, so the output voltage generated on the output capacitor The maximum rising slope will be at the peak current of the inductor. In addition, during the off time T OFF , the current of the inductor will gradually become smaller, and when the current of the inductor is equal to the current supplied to the load, the output voltage will reach its peak value, and then gradually decrease, and the output voltage The downward trend will continue until the turn-on time T ON of the next cycle until the inductor current is equal to the current supplied to the load, and then gradually increase.

在升壓轉換的導通時間TON 中，由於一輸入電源在對一電感充電時，只靠一輸出電容上的一輸出電壓供電給一負載，所以該輸出電壓在一週期的導通時間TON 結束時會達到一最低點。另外，在該週期的斷開時間TOFF 內，該輸入電源會串聯該電感以驅動該輸出電容及該負載，且在此過程中，該電感的電流會逐漸變小，該輸出電壓會逐漸上升，且在當該電感的電流等於供給該負載的電流時，該輸出電壓會到達其峰值，然後逐漸降低，且該輸出電壓的下降趨勢會在該週期的三態時間TTRI 及下個週期的導通時間TON 內持續，直到下個週期的斷開時間TOFF 開始時才逐漸上升。In the on-time T ON of the boost conversion, since an input power source charges an inductor, it only relies on an output voltage on an output capacitor to supply a load, so the on-time T ON of one cycle of the output voltage ends Will reach a nadir. In addition, during the off time T OFF of the period, the input power will connect the inductor in series to drive the output capacitor and the load, and in the process, the current of the inductor will gradually decrease and the output voltage will gradually increase , And when the current of the inductor is equal to the current supplied to the load, the output voltage will reach its peak value, and then gradually decrease, and the downward trend of the output voltage will be in the tri-state time T TRI of the cycle and the next cycle The on-time T ON continues until the off-time T OFF of the next cycle begins to rise gradually.

另外，一般的PFM模式轉換器是直接利用一控制迴路控制導通時間Ton 來使輸出穩定，因此導通時間TON 先變化，然後借助三態時間TTRI 的長短來間接控制輸出電壓紋波的大小。當導通時間TON 的時間設置不合適的時候，三態時間TTRI 可能變長或是變短，而使輸出波形可能連續出現幾個較短的三態時間TTRI ，然後出現一個較長的三態時間TTRI 。也就是說，一般的PFM模式轉換器雖然能使輸出電壓在一定的範圍內波動，但其輸出紋波即使在固定的靜態負載下仍然會表現出頻率不規律的現象。也就是說，一般的PFM模式轉換器只是單純直接控制導通時間TON 的長短，但是尋找到一個合適的導通時間TON 是一個間接的過程，在這個過程中，三態時間TTRI 可能會有極長或極短的反覆變動，從而使輸出紋波突然大增並使轉換器的開關頻率出現抖動的現象。In addition, the general PFM mode converter directly uses a control loop to control the on-time T on to stabilize the output. Therefore, the on-time T ON changes first, and then the size of the output voltage ripple is indirectly controlled by the length of the tri-state time T TRI . When the setting of the ON time T ON is inappropriate, the tri-state time T TRI may become longer or shorter, and the output waveform may appear several short tri-state times T TRI continuously, and then a longer Tristate time T TRI . That is to say, although the general PFM mode converter can make the output voltage fluctuate within a certain range, its output ripple will still show an irregular frequency even under a fixed static load. In other words, the general PFM mode converter simply directly controls the length of the ON time T ON , but finding an appropriate ON time T ON is an indirect process. In this process, the tri-state time T TRI may have Very long or very short and repeated changes, which suddenly increase the output ripple and make the switching frequency of the converter jitter.

因此，為解決上述問題，本領域亟需一種能有效抑制靜態輸出電壓紋波的PFM模式電源轉換方案。Therefore, in order to solve the above problems, a PFM mode power conversion solution that can effectively suppress the static output voltage ripple is urgently needed in the art.

本發明之一目的在提出的一種脈衝頻率調變的控制方法，對於PFM模式下降壓/升壓架構來說具有通用性，在輸出頻率穩定的前提下能夠有效的控制紋波的大小，並且對於負載的變化也能夠進行快速的回應，從而保證輸出的穩定。An object of the present invention is to provide a pulse frequency modulation control method that is versatile for the PFM mode buck/boost architecture and can effectively control the size of the ripple under the premise of stable output frequency, and It can also respond quickly to changes in load, thereby ensuring the stability of the output.

本發明之另一目的在提出一種脈衝頻率調變的控制方法，其係依前一週期的三態時間，步階式的調整下一週期的導通時間，以穩定且有效的控制輸出紋波的大小，而其原理在於：在脈衝頻率調變模式下，三態時間一般而言會遠大於導通時間，因此，能夠有效控制三態時間，就能穩定操作頻率及抑制輸出紋波。Another object of the present invention is to provide a control method for pulse frequency modulation, which adjusts the on-time of the next cycle step by step according to the three-state time of the previous cycle to stably and effectively control the output ripple The principle is that in the pulse frequency modulation mode, the tri-state time is generally much longer than the on-time. Therefore, the tri-state time can be effectively controlled to stabilize the operating frequency and suppress the output ripple.

根據上述的目的，本發明揭露一種脈衝頻率調變的控制方法，該控制方法係應用在一電源轉換電路，該電源轉換電路至少包含一電感、一第一電晶體、一第二電晶體、一輸出電容及一控制電路，該控制電路係藉由控制該第一電晶體和該第二電晶體以產生一脈衝頻率調變週期，該脈衝頻率調變週期包含一導通階段、一斷開階段和一三態階段，其中，在該導通階段內，該第一電晶體係被斷開且該第二電晶體係被導通以使一輸入電壓對該電感充電，在該斷開階段內，該第一電晶體係被導通且該第二電晶體係被斷開以使該電感會對該輸出電容放電，以在該輸出電容產生一輸出電壓，以及在該三態階段內，該第一電晶體和該第二電晶體均被斷開以使該電感處於被隔絕的狀態，該控制方法包含步驟：According to the above purpose, the present invention discloses a control method for pulse frequency modulation. The control method is applied to a power conversion circuit. The power conversion circuit includes at least an inductor, a first transistor, a second transistor, a An output capacitor and a control circuit, the control circuit generates a pulse frequency modulation period by controlling the first transistor and the second transistor, the pulse frequency modulation period includes an on phase, an off phase and A three-state phase, in which, during the conduction phase, the first transistor system is turned off and the second transistor system is turned on to charge an inductor with an input voltage, and during the off phase, the first A transistor system is turned on and the second transistor system is turned off so that the inductor will discharge the output capacitor to generate an output voltage in the output capacitor, and in the tri-state phase, the first transistor Both the second transistor and the second transistor are disconnected so that the inductor is in an isolated state. The control method includes the following steps:

當偵測到一回授電壓小於一參考電壓時，該控制電路開啟所述脈衝頻率調變週期之所述導通階段，其中該回授電壓係依該輸出電壓產生，且所述導通階段之導通時間係由一三態回授控制信號控制；When it is detected that a feedback voltage is less than a reference voltage, the control circuit starts the conduction phase of the pulse frequency modulation period, wherein the feedback voltage is generated according to the output voltage, and the conduction in the conduction phase is turned on Time is controlled by a three-state feedback control signal;

當所述導通時間結束後，該控制電路使所述脈衝頻率調變週期由所述導通階段進入所述斷開階段；When the on-time is over, the control circuit causes the pulse frequency modulation period to enter the off-phase from the on-phase;

當偵測到一過零檢測訊號為作用狀態時，該控制電路使所述脈衝頻率調變週期由所述斷開階段進入所述三態階段；以及When it is detected that a zero-crossing detection signal is in an active state, the control circuit causes the pulse frequency modulation period to enter the tri-state phase from the off phase; and

當偵測到該回授電壓小於該參考電壓時，該控制電路結束所述三態階段，然後再開啟下一個所述脈衝頻率調變週期；When detecting that the feedback voltage is less than the reference voltage, the control circuit ends the three-state phase, and then starts the next pulse frequency modulation period;

其中，該三態回授控制信號係依前一個所述脈衝頻率調變週期之所述三態階段的一持續時間決定其狀態，當該持續時間長於一最長限制時間時，該三態回授控制信號呈現一第一狀態以使所述導通時間下降一預定時間，當該持續時間短於一最短限制時間時，該三態回授控制信號呈現一第二狀態以使所述導通時間上升所述預定時間，以及當該持續時間介於該最短限制時間和該最長限制時間時，該三態回授控制信號呈現一第三狀態以使所述導通時間維持不變。Wherein, the tri-state feedback control signal determines its state according to a duration of the tri-state phase of the previous pulse frequency modulation period. When the duration is longer than a maximum limit time, the tri-state feedback The control signal assumes a first state to decrease the on-time by a predetermined time. When the duration is shorter than a minimum limit time, the tri-state feedback control signal assumes a second state to increase the on-time The predetermined time, and when the duration is between the shortest limit time and the longest limit time, the tri-state feedback control signal assumes a third state to maintain the on-time.

在一實施例中，該控制電路包含一脈衝頻率調變單擊元件、一脈衝頻率調變控制邏輯元件、一三態時間檢測器、一比較器和一過零檢測電路。In an embodiment, the control circuit includes a pulse frequency modulation click element, a pulse frequency modulation control logic element, a tri-state time detector, a comparator, and a zero-crossing detection circuit.

在一實施例中，該過零檢測電路係依該第一電晶體之通道跨壓決定該過零檢測訊號的狀態。In one embodiment, the zero-crossing detection circuit determines the state of the zero-crossing detection signal according to the channel voltage across the first transistor.

在一實施例中，該脈衝頻率調變控制邏輯元件係依該過零檢測訊號及該回授電壓與該參考電壓之一比較結果決定一所述脈衝頻率調變週期之所述三態時間。In one embodiment, the pulse frequency modulation control logic element determines the three-state time of the pulse frequency modulation period according to a comparison result of the zero-crossing detection signal and the feedback voltage and the reference voltage.

在一實施例中，該三態時間檢測器是依所述三態時間和所述最長限制時間及所述最短限制時間的比較結果決定該三態回授控制信號的狀態。In an embodiment, the tri-state time detector determines the state of the tri-state feedback control signal according to the comparison result of the tri-state time and the longest limited time and the shortest limited time.

在一實施例中，該脈衝頻率調變單擊元件係用以依該脈衝頻率調變控制邏輯元件的控制產生一所述脈衝頻率調變週期之所述導通時間。In an embodiment, the pulse frequency modulation click element is used to generate the on-time of a pulse frequency modulation period according to the control of the pulse frequency modulation control logic element.

本發明的另一目的在提出一種脈衝頻率調變電源轉換電路，其對於PFM模式下降壓/升壓架構來說具有通用性，在輸出頻率穩定的前提下能夠有效的控制紋波的大小，並且對於負載的變化也能夠進行快速的回應，從而保證輸出的穩定。Another object of the present invention is to provide a pulse frequency modulation power conversion circuit, which is versatile for the PFM mode buck/boost architecture and can effectively control the size of the ripple when the output frequency is stable. And can respond quickly to changes in the load, so as to ensure the stability of the output.

根據上述的目的，本發明揭露一種電源轉換電路，至少包含一電感、一第一電晶體、一第二電晶體、一輸出電容及一控制電路，該控制電路係用以執行一控制方法，以藉由控制該第一電晶體和該第二電晶體以產生一脈衝頻率調變週期，該脈衝頻率調變週期包含一導通階段、一斷開階段和一三態階段，其中，在該導通階段內，該第一電晶體係被斷開且該第二電晶體係被導通以使一輸入電壓對該電感充電，在該斷開階段內，該第一電晶體係被導通且該第二電晶體係被斷開以使該電感會對該輸出電容放電，以在該輸出電容產生一輸出電壓，以及在該三態階段內，該第一電晶體和該第二電晶體均被斷開以使該電感處於被隔絕的狀態，該控制方法包含步驟：According to the above purpose, the present invention discloses a power conversion circuit including at least an inductor, a first transistor, a second transistor, an output capacitor, and a control circuit. The control circuit is used to execute a control method to By controlling the first transistor and the second transistor to generate a pulse frequency modulation period, the pulse frequency modulation period includes a conduction phase, a disconnection phase and a three-state phase, wherein, in the conduction phase The first transistor system is turned off and the second transistor system is turned on to charge an inductor with an input voltage. During the off phase, the first transistor system is turned on and the second transistor The crystal system is disconnected so that the inductor will discharge the output capacitor to generate an output voltage in the output capacitor, and in the tri-state phase, both the first transistor and the second transistor are disconnected to To make the inductance in an isolated state, the control method includes steps:

當偵測到該回授電壓小於該參考電壓時，該控制電路開啟所述脈衝頻率調變週期之所述導通階段，其中該回授電壓係依該輸出電壓產生，且所述導通階段之導通時間係由一三態回授控制信號控制；When it is detected that the feedback voltage is less than the reference voltage, the control circuit starts the conduction phase of the pulse frequency modulation period, wherein the feedback voltage is generated according to the output voltage, and the conduction in the conduction phase Time is controlled by a three-state feedback control signal;

當所述導通時間結束後，該控制電路使所述脈衝頻率調變週期由所述導通階段進入所述斷開階段；When the on-time is over, the control circuit causes the pulse frequency modulation period to enter the off-phase from the on-phase;

當偵測到一過零檢測訊號為作用狀態時，該控制電路使所述脈衝頻率調變週期由所述斷開階段進入所述三態階段；以及When it is detected that a zero-crossing detection signal is in an active state, the control circuit causes the pulse frequency modulation period to enter the tri-state phase from the off phase; and

當偵測到該回授電壓小於該參考電壓時，該控制電路結束所述三態階段，然後再開啟下一個所述脈衝頻率調變週期；When detecting that the feedback voltage is less than the reference voltage, the control circuit ends the three-state phase, and then starts the next pulse frequency modulation period;

其中，該三態回授控制信號係依前一個所述脈衝頻率調變週期之所述三態階段的一三態時間決定其狀態，當該三態時間長於一最長限制時間時，該三態回授控制信號呈現一第一狀態以使所述導通時間下降一預定時間，當該三態時間短於一最短限制時間時，該三態回授控制信號呈現一第二狀態以使所述導通時間上升所述預定時間，以及當該三態時間介於該最短限制時間和該最長限制時間時，該三態回授控制信號呈現一第三狀態以使所述導通時間維持不變。Wherein, the tri-state feedback control signal determines its state according to a tri-state time of the tri-state stage of the previous pulse frequency modulation period. When the tri-state time is longer than a longest limit time, the tri-state The feedback control signal assumes a first state to decrease the on-time by a predetermined time. When the tri-state time is shorter than a minimum limit time, the tri-state feedback control signal assumes a second state to make the on-state The time rises by the predetermined time, and when the tri-state time is between the shortest limit time and the longest limit time, the tri-state feedback control signal assumes a third state to maintain the on-time.

在一實施例中，該控制電路具有一過零檢測電路以依該第一電晶體之通道跨壓決定該過零檢測訊號的狀態。In one embodiment, the control circuit has a zero-crossing detection circuit to determine the state of the zero-crossing detection signal according to the channel voltage across the first transistor.

在一實施例中，該控制電路具有一脈衝頻率調變控制邏輯元件以依該過零檢測訊號及該回授電壓與該參考電壓之一比較結果決定一所述脈衝頻率調變週期之所述三態時間。In one embodiment, the control circuit has a pulse frequency modulation control logic element to determine the pulse frequency modulation period according to the comparison result of the zero-crossing detection signal and the feedback voltage with the reference voltage Tristate time.

在一實施例中，該控制電路具有一三態時間檢測器以依一所述三態時間和所述最長限制時間及所述最短限制時間的比較結果決定該三態回授控制信號的狀態。In an embodiment, the control circuit has a tri-state time detector to determine the state of the tri-state feedback control signal according to a comparison result of the tri-state time and the longest limited time and the shortest limited time.

為使　貴審查委員能進一步瞭解本發明之結構、特徵及其目的，茲附以圖式及較佳具體實施例之詳細說明如後。In order to enable your reviewing committee to further understand the structure, features and purpose of the present invention, the drawings and the detailed description of the preferred embodiments are attached as follows.

圖3顯示本發明之電源轉換電路之一實施例的電路圖，圖4顯示本發明之脈衝頻率調變的控制方法之一實施例的流程圖。本發明的電源轉換電路30主要包含一電感301、一第一電晶體302、一第二電晶體303、一輸出電容304和一控制電路305。該控制電路305係藉由控制該第一電晶體302和該第二電晶體303以產生一脈衝頻率調變週期，該脈衝頻率調變週期包含一導通階段、一斷開階段和一三態階段，其中，在該導通階段內，該第一電晶體302係被斷開且該第二電晶體303係被導通以使一輸入電壓VIN 對該電感301充電，在該斷開階段內，該第一電晶體302係被導通且該第二電晶體303係被斷開以使該電感301對該輸出電容304放電，以在該輸出電容304產生一輸出電壓VOUT ，以及在該三態階段內，該第一電晶體302和該第二電晶體303均被斷開以使該電感301處於被隔絕的狀態。另外，該控制電路305包含一脈衝頻率調變單擊元件306、一脈衝頻率調變控制邏輯元件307、一三態時間檢測器308、一比較器309和一過零檢測電路(zero crossing detector)310。FIG. 3 shows a circuit diagram of an embodiment of the power conversion circuit of the present invention, and FIG. 4 shows a flowchart of an embodiment of the control method of the pulse frequency modulation of the present invention. The power conversion circuit 30 of the present invention mainly includes an inductor 301, a first transistor 302, a second transistor 303, an output capacitor 304, and a control circuit 305. The control circuit 305 generates a pulse frequency modulation period by controlling the first transistor 302 and the second transistor 303. The pulse frequency modulation period includes an on phase, an off phase, and a tristate phase Where, in the on-phase, the first transistor 302 is turned off and the second transistor 303 is turned on to charge an inductor 301 with an input voltage V IN . In the off-stage, the The first transistor 302 is turned on and the second transistor 303 is turned off to discharge the inductor 301 to the output capacitor 304 to generate an output voltage V OUT at the output capacitor 304 and during the three-state stage Inside, both the first transistor 302 and the second transistor 303 are disconnected so that the inductor 301 is in an isolated state. In addition, the control circuit 305 includes a pulse frequency modulation click element 306, a pulse frequency modulation control logic element 307, a tri-state time detector 308, a comparator 309 and a zero crossing detector circuit (zero crossing detector) 310.

如圖4所示，本發明之脈衝頻率調變的控制方法包含步驟S401、步驟S402、步驟S403及步驟S404。As shown in FIG. 4, the pulse frequency modulation control method of the present invention includes step S401, step S402, step S403, and step S404.

在步驟S401中，當偵測到一回授電壓(VFB )小於一參考電壓(VREF )時，該控制電路305開啟所述脈衝頻率調變週期之所述導通階段，其中該回授電壓係依該輸出電壓產生，且所述導通階段之導通時間係由一三態回授控制信號(TTRI-FEEDBACK )控制。也就是說，請參照圖3，當回授電壓VFB 小於參考電壓VREF 時，比較器309輸出的一比較輸出訊號CMP_OUT 會呈現一高邏輯電位，表示此時的輸出電壓VOUT 低於一目標值(參考電壓VREF )，此時需要開啟一所述脈衝頻率調變週期之所述導通階段以對電感301進行充電，其中，回授電壓VFB 是根據第一電阻312和第二電阻313對輸出電壓VOUT 的分壓作用而得，以及所述導通階段具有一導通時間(TON )，且導通時間TON 的長短是由上個週期的三態時間TTRI 決定。In step S401, when it is detected that a feedback voltage (V FB ) is less than a reference voltage (V REF ), the control circuit 305 starts the conduction phase of the pulse frequency modulation period, wherein the feedback voltage It is generated according to the output voltage, and the conduction time of the conduction phase is controlled by a tri-state feedback control signal (T TRI-FEEDBACK ). That is, referring to FIG. 3, when the feedback voltage V FB is less than the reference voltage V REF , a comparison output signal C MP_OUT output by the comparator 309 will show a high logic potential, indicating that the output voltage V OUT at this time is lower than A target value (reference voltage V REF ), at this time it is necessary to turn on the conduction phase of the pulse frequency modulation period to charge the inductor 301, wherein the feedback voltage V FB is based on the first resistor 312 and the second The resistance 313 divides the output voltage V OUT , and the conduction phase has a conduction time (T ON ), and the length of the conduction time T ON is determined by the tristate time T TRI of the previous cycle.

在步驟S402中，當所述導通時間結束後，該控制電路305使所述脈衝頻率調變週期由所述導通階段進入所述斷開階段。In step S402, when the on-time is over, the control circuit 305 causes the pulse frequency modulation period to enter the off-phase from the on-phase.

在步驟S403，當偵測到一過零檢測訊號(ZCD_OUT)為作用狀態時，該控制電路305使所述脈衝頻率調變週期由所述斷開階段進入所述三態階段。In step S403, when a zero-crossing detection signal (ZCD_OUT) is detected to be in an active state, the control circuit 305 causes the pulse frequency modulation period to enter the tri-state phase from the off-phase.

在步驟S404中，當偵測到該回授電壓小於該參考電壓時，該控制電路305結束所述三態階段，然後再開啟下一個所述脈衝頻率調變週期。具體而言，該三態回授控制信號(TTRI-FEEDBACK )係依前一個所述脈衝頻率調變週期之所述三態階段的一三態時間決定其狀態，當該三態時間長於一最長限制時間時，該三態回授控制信號呈現一第一狀態以使所述導通時間下降一預定時間，當該三態時間短於一最短限制時間時，該三態回授控制信號呈現一第二狀態以使所述導通時間上升所述預定時間，以及當該三態時間介於該最短限制時間和該最長限制時間時，該三態回授控制信號呈現一第三狀態以使所述導通時間維持不變。In step S404, when it is detected that the feedback voltage is less than the reference voltage, the control circuit 305 ends the three-state phase, and then starts the next pulse frequency modulation period. Specifically, the tri-state feedback control signal (T TRI-FEEDBACK ) determines its state according to a tri-state time of the tri-state stage of the previous pulse frequency modulation period, when the tri-state time is longer than one At the longest limit time, the tri-state feedback control signal assumes a first state to decrease the on-time by a predetermined time. When the tri-state time is shorter than a shortest limit time, the tri-state feedback control signal assumes a A second state to increase the on-time by the predetermined time, and when the tri-state time is between the shortest and the longest limit time, the tri-state feedback control signal assumes a third state to make the The on-time remains unchanged.

另外，請參照圖3，該過零檢測電路310係依該第一電晶體302之通道跨壓決定過零檢測訊號ZCD_OUT的狀態。該脈衝頻率調變控制邏輯元件307係依過零檢測訊號ZCD_OUT及回授電壓VFB 與參考電壓VREF 之一電壓比較結果決定一所述脈衝頻率調變週期之所述三態時間TTRI 。該三態時間檢測器308是依所述三態時間TTRI 和所述最長限制時間及所述最短限制時間的比較結果決定該三態回授控制信號TTRI-FEEDBACK 的狀態。該脈衝頻率調變單擊元件306係用以依該脈衝頻率調變控制邏輯元件307的控制產生一所述脈衝頻率調變週期之所述導通時間。In addition, referring to FIG. 3, the zero-crossing detection circuit 310 determines the state of the zero-crossing detection signal ZCD_OUT according to the channel voltage across the first transistor 302. The pulse frequency modulation control logic element 307 determines the tri-state time T TRI of a pulse frequency modulation period according to the voltage comparison result of the zero-crossing detection signal ZCD_OUT and the feedback voltage V FB and the reference voltage V REF . The tri-state time detector 308 determines the state of the tri-state feedback control signal T TRI-FEEDBACK according to the comparison result of the tri-state time T TRI with the longest limited time and the shortest limited time. The pulse frequency modulation click element 306 is used to generate the on-time of a pulse frequency modulation period according to the control of the pulse frequency modulation control logic element 307.

依舊參閱圖3，輸入電容311連接一輸入電源，電感301連接輸入電容311，第一電晶體302和第二電晶體303分別連接電感301，脈衝頻率調變單擊元件306連接第二電晶體303，脈衝頻率調變控制邏輯元件307的輸出端分別連接脈衝頻率調變單擊元件306、三態時間檢測器308的輸入端和第一電晶體302，脈衝頻率調變控制邏輯元件307的輸入端分別連接三態時間檢測器308的輸出端、過零檢測電路310的輸出端和比較器309的輸出端，比較器309的正輸入端連接參考電壓VREF ，其負輸入端連接回授電壓VFB 。Still referring to FIG. 3, the input capacitor 311 is connected to an input power source, the inductor 301 is connected to the input capacitor 311, the first transistor 302 and the second transistor 303 are respectively connected to the inductor 301, and the pulse frequency modulation click element 306 is connected to the second transistor 303 , The output terminal of the pulse frequency modulation control logic element 307 is respectively connected to the input terminal of the pulse frequency modulation click element 306, the input of the tristate time detector 308 and the first transistor 302, and the input end of the pulse frequency modulation control logic element 307 The output terminal of the tri-state time detector 308, the output terminal of the zero-crossing detection circuit 310 and the output terminal of the comparator 309 are respectively connected. The positive input terminal of the comparator 309 is connected to the reference voltage V REF , and the negative input terminal thereof is connected to the feedback voltage V FB .

具體而言，圖5顯示了本發明以三態時間的狀態對導通時間進行步階式調控的流程圖，該控制流程包含：利用一脈衝頻率調變控制邏輯元件提供前一個週期的三態時間給一三態時間檢測器(步驟S501)；該三態時間檢測器依該三態時間和一最長限制時間及一最短限制時間的比較結果產生一三態回授控制訊號，其中，當該三態時間大於該最長限制時間時，該三態回授控制訊號會呈現一第一狀態，當該三態時間小於該最短限制時間時，該三態回授控制訊號會呈現一第二狀態，以及當該三態時間小於該最長限制時間且大於該最短限制時間時，該三態回授控制訊號會呈現一第三狀態(步驟S502)；以及當該三態回授控制訊號呈現所述第一狀態時，該脈衝頻率調變控制邏輯元件會使下一個週期的導通時間降低一個位階，當該三態回授控制訊號呈現所述第二狀態時，該脈衝頻率調變控制邏輯元件會使下一個週期的導通時間增加一個位階，以及當該三態回授控制訊號呈現所述第三狀態時，該脈衝頻率調變控制邏輯元件會使下一個週期的導通時間維持不變(步驟S503)。Specifically, FIG. 5 shows a flowchart of the present invention for step-by-step regulation of the on-time in the state of three-state time. The control process includes: using a pulse frequency modulation control logic element to provide the three-state time of the previous cycle Give a tri-state time detector (step S501); the tri-state time detector generates a tri-state feedback control signal according to the comparison result of the tri-state time with a longest limit time and a shortest limit time, wherein when the three When the tristate time is greater than the maximum limit time, the tristate feedback control signal will assume a first state, and when the tristate time is less than the minimum limit time, the tristate feedback control signal will assume a second state, and When the tri-state time is less than the longest limit time and greater than the shortest limit time, the tri-state feedback control signal will assume a third state (step S502); and when the tri-state feedback control signal presents the first In the state, the pulse frequency modulation control logic element reduces the turn-on time of the next cycle by one level. When the tri-state feedback control signal assumes the second state, the pulse frequency modulation control logic element causes the following The turn-on time of one cycle is increased by one level, and when the tri-state feedback control signal assumes the third state, the pulse frequency modulation control logic element will keep the turn-on time of the next cycle unchanged (step S503).

也就是說，根據脈衝頻率調變控制邏輯元件307所提供的上一個週期的三態時間TTRI ，三態時間檢測器308會決定一三態回授控制訊號TTRI-FEEDBACK 的狀並將該三態回授控制訊號TTRI-FEEDBACK 回饋給脈衝頻率調變控制邏輯元件307以決定是否改變下一個週期的導通時間，且其決定方式如下：當前一個週期的三態時間大於一最長限制時間時，表示前一個週期的導通時間過長，因此三態回授控制訊號TTRI-FEEDBACK 會呈現一第一狀態，而脈衝頻率調變控制邏輯元件307會依所述第一狀態決定一導通時間控制訊號TON_CTRL 的對應狀態，並以導通時間控制訊號TON_CTRL 驅動脈衝頻率調變單擊元件306以使下一個週期的導通時間降低一個位階；當前一個週期的三態時間小於一最短限制時間時，表示前一個週期的導通時間過短，因此三態回授控制訊號TTRI-FEEDBACK 會呈現一第二狀態，而脈衝頻率調變控制邏輯元件307會依所述第二狀態決定導通時間控制訊號TON_CTRL 的對應狀態，並以導通時間控制訊號TON_CTRL 驅動脈衝頻率調變單擊元件306以使下一個週期的導通時間增加一個位階；以及當前一個週期的三態時間大於該最短限制時間且小於該最長限制時間，表示該導通時間合適，那麼三態回授控制訊號TTRI-FEEDBACK 會呈現一第三狀態使導通時間維持不變。也就是說，通過以三態回授控制訊號TTRI-FEEDBACK 決定導通時間是要降低一個位階、增加一個位階或維持不變，三態時間TTRI 將迅速被限制在一預設的範圍內而使系統能夠有效的控制紋波的大小。That is, according to the tri-state time T TRI of the previous cycle provided by the pulse frequency modulation control logic element 307, the tri-state time detector 308 will determine the state of a tri-state feedback control signal T TRI-FEEDBACK and The tri-state feedback control signal T TRI-FEEDBACK is fed back to the pulse frequency modulation control logic element 307 to determine whether to change the on-time of the next cycle, and its decision method is as follows: When the tri-state time of the current cycle is greater than a maximum limit time , Indicating that the on-time of the previous cycle is too long, so the tri-state feedback control signal T TRI-FEEDBACK will assume a first state, and the pulse frequency modulation control logic element 307 will determine an on-time control according to the first state The corresponding state of the signal T ON_CTRL , and the on-time control signal T ON_CTRL drives the pulse frequency to adjust the click element 306 to reduce the on-time of the next cycle by one step; when the tri-state time of the current cycle is less than a minimum limit time, It means that the on-time of the previous cycle is too short, so the tri-state feedback control signal T TRI-FEEDBACK will assume a second state, and the pulse frequency modulation control logic element 307 will determine the on-time control signal T according to the second state The corresponding state of ON_CTRL , and the on-time control signal T ON_CTRL drives the pulse frequency modulation click element 306 to increase the on-time of the next cycle by one step; and the tri-state time of the current cycle is greater than the minimum limit time and less than the The longest limit time indicates that the on-time is appropriate, then the tri-state feedback control signal T TRI-FEEDBACK will assume a third state to keep the on-time unchanged. In other words, by using the tri-state feedback control signal T TRI-FEEDBACK to determine whether the on-time is to decrease a level, increase a level, or remain unchanged, the tri-state time T TRI will be quickly limited to a preset range. The system can effectively control the size of the ripple.

圖6a-圖6c為負載電流穩定時在脈衝頻率調變工作模式下的電感電流60波形圖。由圖6a-圖6c可以看到，在不同的輸出負載下，只要滿足三態時間TTRI 的時間在一定的範圍內，那麼根據此時的三態時間TTRI 所產生的TON 就可以既達到預定的VOUT 電壓又能有效抑制VOUT 電壓的紋波。也就是說，通過將三態時間TTRI 限制在TTRI_MIN 和TTRI-MAX 之間，當負載變動時，儘管頻率會跟著變動，但是VOUT 電壓的紋波基本上不會產生大的異動。此外，本發明依前一個週期的三態時間TTRI 自動使下一個週期的導通時間TON 降低一個位階、增加一個位階或維持不變的技術方案，不僅可應用於降壓轉換，亦可應用於升壓轉換。也就是說，本發明的技術方案可將降壓轉換和升壓轉換兩種不同架構歸一化，以使電源轉換電路的實現更加簡易。Figures 6a-6c are waveforms of the inductor current 60 in the pulse frequency modulation operating mode when the load current is stable. As can be seen from Figures 6a-6c, under different output loads, as long as the time that satisfies the tri-state time T TRI is within a certain range, then the T ON generated by the tri-state time T TRI at this time can be both Reaching the predetermined V OUT voltage can effectively suppress the ripple of the V OUT voltage. That is to say, by limiting the tri-state time T TRI between T TRI_MIN and T TRI-MAX , when the load fluctuates, although the frequency will fluctuate, the ripple of the V OUT voltage basically does not produce large changes. In addition, according to the present invention, the three-state time T TRI of the previous cycle automatically reduces the on-time T ON of the next cycle by one level, increases one level, or maintains the same technical solution, which can be applied not only to buck conversion, but also to For boost conversion. In other words, the technical solution of the present invention can normalize the two different architectures of buck conversion and boost conversion, so as to make the implementation of the power conversion circuit easier.

圖7a和圖7b分別顯示電感電流70對於負載電流變化的響應波形圖。如圖7a所示，當負載電流突然從重負載向輕負載切換時，TTRI-1 ＞TTRI-MAX ，TTRI-1 為前一週期的三態時間，系統根據TTRI-1 和TTRI-MAX 和TTRI_MIN 的比較關係可迅速得到一個小的且匹配的TON-2 ，以在下一個週期使得TTRI_MIN ＜TTRI-2 ＜TTRI-MAX 。同理，如圖7b所示，當負載電流突然從輕負載向重負載切換時，TTRI-1 ＜TTRI_MIN ，系統根據TTRI-1 和TTRI-MAX 和TTRI_MIN 的比較關係可迅速得到一個大的且匹配的TON-2 ，以在下一個週期使得TTRI_MIN ＜TTRI-2 ＜TTRI-MAX 。也就是說，本發明的好處在於系統能夠在不同負載的情況下，根據前一週期的三態時間TTRI-1 時間快速的單向回饋到TON 的控制上，因此其瞬間的負載狀態回應能夠及時而且有效。7a and 7b show waveforms of the response of the inductor current 70 to changes in load current, respectively. As shown in Figure 7a, when the load current suddenly switches from heavy load to light load, T TRI-1 > T TRI-MAX , T TRI-1 is the tri-state time of the previous cycle, the system according to T TRI-1 and T TRI comparison between the relation -MAX and T TRI_MIN can quickly get a match and small T ON-2, in the next cycle such that T TRI_MIN <T TRI-2 < T TRI-MAX. Similarly, as shown in Figure 7b, when the load current suddenly switches from light load to heavy load, T TRI-1 <T TRI_MIN , the system can quickly obtain according to the comparison relationship between T TRI-1 and T TRI-MAX and T TRI_MIN A large and matching T ON-2 to make T TRI_MIN <T TRI-2 <T TRI-MAX in the next cycle. In other words, the benefit of the present invention is that the system can quickly feed back to the control of T ON according to the tri-state time T TRI-1 time of the previous cycle under different loads, so its instantaneous load status response Can be timely and effective.

藉由前述所揭露的設計，本發明乃具有以下的優點：With the design disclosed above, the present invention has the following advantages:

1.本發明的脈衝頻率調變的控制方法對於PFM模式下的降壓/升壓架構來說具有通用性。1. The control method of the pulse frequency modulation of the present invention is versatile for the buck/boost architecture in the PFM mode.

2.本發明的脈衝頻率調變的控制方法在輸出頻率穩定的前提下能夠有效的控制輸出紋波的大小。2. The control method of pulse frequency modulation of the present invention can effectively control the size of output ripple under the premise of stable output frequency.

3.本發明的脈衝頻率調變的控制方法對於負載的變化能夠進行快速的回應，從而保證輸出的穩定。3. The control method of the pulse frequency modulation of the present invention can respond quickly to the change of the load, thereby ensuring the stability of the output.

4. 本發明的脈衝頻率調變的控制方法通過依前一週期的三態時間步階式的調整下一週期的導通時間，可穩定且有效的控制輸出紋波的大小，其原因在於在脈衝頻率調變模式下，三態時間一般而言會遠大於導通時間，而能夠有效控制三態時間，就能穩定操作頻率及抑制輸出紋波。4. The control method of the pulse frequency modulation of the present invention can stably and effectively control the size of the output ripple by adjusting the on-time of the next cycle according to the three-state time step of the previous cycle, the reason is that the pulse In the frequency modulation mode, the tri-state time is generally much longer than the on-time, and the tri-state time can be effectively controlled to stabilize the operating frequency and suppress the output ripple.

本案所揭示者，乃較佳實施例，舉凡局部之變更或修飾而源於本案之技術思想而為熟習該項技藝之人所易於推知者，俱不脫本案之專利權範疇。The case disclosed in this case is a preferred embodiment, and any part of the modification or modification that originates from the technical idea of this case and can be easily inferred by those skilled in the art, does not deviate from the patent scope of this case.

綜上所陳，本案無論就目的、手段與功效，在在顯示其迥異於習知之技術特徵，且其首先發明合於實用，亦在在符合發明之專利要件，懇請　貴審查委員明察，並祈早日賜予專利，俾嘉惠社會，實感德便。In summary, regardless of the purpose, means and efficacy, this case is showing that it has a technical feature that is very different from conventional knowledge, and its first invention is in practical use, and it is also in compliance with the patent requirements of the invention. Granted patents as soon as possible to benefit the society and feel virtuous.

101:電晶體102:電晶體103:電感104:輸入電容105:輸出電容20:電感電流21:輸出電壓30:電源轉換電路301:電感302:第一電晶體303:第二電晶體304:輸出電容305:控制電路306:脈衝頻率調變單擊元件307:脈衝頻率調變控制邏輯元件308:三態時間檢測器309:比較器310:過零檢測電路311:輸入電容312:第一電阻313:第二電阻S401-S404:步驟S501-S503:步驟60:電感電流70:電感電流101: Transistor 102: Transistor 103: Inductor 104: Input capacitor 105: Output capacitor 20: Inductor current 21: Output voltage 30: Power conversion circuit 301: Inductor 302: First transistor 303: Second transistor 304: Output Capacitor 305: control circuit 306: pulse frequency modulation click element 307: pulse frequency modulation control logic element 308: tristate time detector 309: comparator 310: zero-crossing detection circuit 311: input capacitor 312: first resistor 313 : Second resistance S401-S404: steps S501-S503: step 60: inductor current 70: inductor current

圖1a顯示一傳統降壓轉換器的電路圖。 圖1b顯示一傳統升壓轉換器的電路圖。 圖2a和圖2b分別顯示一降壓轉換及一升壓轉換在脈衝頻率調變模式下的操作波形圖。 圖3顯示本發明之電源轉換電路之一實施例的電路圖。 圖4顯示本發明之脈衝頻率調變的控制方法之一實施例的流程圖。 圖5顯示本發明之三態時間檢測器對導通時間TON 的控制流程圖。 圖6A-圖6C為負載電流穩定時在脈衝頻率調變工作模式下的電感電流波形圖。 圖7a和圖7b分別顯示電感電流對於負載電流變化的響應波形圖。Figure 1a shows a circuit diagram of a conventional buck converter. Figure 1b shows a circuit diagram of a conventional boost converter. Figures 2a and 2b show the operation waveforms of a buck conversion and a boost conversion in pulse frequency modulation mode, respectively. FIG. 3 shows a circuit diagram of an embodiment of the power conversion circuit of the present invention. FIG. 4 shows a flowchart of an embodiment of the control method of the pulse frequency modulation of the present invention. FIG. 5 shows a control flowchart of the on-time T ON of the tri-state time detector of the present invention. 6A-6C are waveform diagrams of the inductor current under the pulse frequency modulation operating mode when the load current is stable. Figures 7a and 7b show the waveforms of inductor current response to load current changes, respectively.

S401~S404:步驟 S401~S404: Steps

Claims (10)

一種脈衝頻率調變的控制方法，該控制方法係應用在一電源轉換 電路，該電源轉換電路至少包含一電感、一第一電晶體、一第二電晶體、一輸出電容及一控制電路，該控制電路係藉由控制該第一電晶體和該第二電晶體以產生一脈衝頻率調變週期，該脈衝頻率調變週期包含一導通階段、一斷開階段和一三態階段，其中，在該導通階段內，該第一電晶體係被斷開且該第二電晶體係被導通以使一輸入電壓對該電感充電，在該斷開階段內，該第一電晶體係被導通且該第二電晶體係被斷開以使該電感會對該輸出電容放電，以在該輸出電容產生一輸出電壓，以及在該三態階段內，該第一電晶體和該第二電晶體均被斷開以使該電感處於被隔絕的狀態，該控制方法包含步驟： 當偵測到一回授電壓小於一參考電壓時，該控制電路開啟所述脈衝頻率調變週期之所述導通階段，其中該回授電壓係依該輸出電壓產生，且所述導通階段之導通時間係由一三態回授控制信號控制； 當所述導通時間結束後，該控制電路使所述脈衝頻率調變週期由所述導通階段進入所述斷開階段； 當偵測到一過零檢測訊號為作用狀態時，該控制電路使所述脈衝頻率調變週期由所述斷開階段進入所述三態階段；以及 當偵測到該回授電壓小於該參考電壓時，該控制電路結束所述三態階段，然後再開啟下一個所述脈衝頻率調變週期； 其中，該三態回授控制信號係依前一個所述脈衝頻率調變週期之所述三態階段的一三態時間決定其狀態，當該三態時間長於一最長限制時間時，該三態回授控制信號呈現一第一狀態以使所述導通時間下降一預定時間，當該三態時間短於一最短限制時間時，該三態回授控制信號呈現一第二狀態以使所述導通時間上升所述預定時間，以及當該三態時間介於該最短限制時間和該最長限制時間時，該三態回授控制信號呈現一第三狀態以使所述導通時間維持不變。A control method for pulse frequency modulation is applied to a power conversion circuit. The power conversion circuit includes at least an inductor, a first transistor, a second transistor, an output capacitor, and a control circuit. The control circuit generates a pulse frequency modulation period by controlling the first transistor and the second transistor. The pulse frequency modulation period includes an on phase, an off phase, and a three-state phase, in which During the turn-on phase, the first transistor system is turned off and the second transistor system is turned on to charge an inductor with an input voltage. During the turn-off phase, the first transistor system is turned on and the The second transistor system is disconnected so that the inductor will discharge the output capacitor to generate an output voltage in the output capacitor, and in the tri-state phase, the first transistor and the second transistor are both The control method includes the following steps: when the feedback voltage is less than a reference voltage, the control circuit turns on the conduction phase of the pulse frequency modulation period, wherein The feedback voltage is generated according to the output voltage, and the conduction time of the conduction phase is controlled by a three-state feedback control signal; when the conduction time is over, the control circuit makes the pulse frequency modulation period from The conduction phase enters the disconnection phase; when a zero-crossing detection signal is detected to be in an active state, the control circuit causes the pulse frequency modulation period to enter the tri-state phase from the disconnection phase; and When it is detected that the feedback voltage is less than the reference voltage, the control circuit ends the three-state phase, and then starts the next pulse frequency modulation period; wherein, the three-state feedback control signal is based on the previous one A tri-state time of the tri-state phase of the pulse frequency modulation period determines its state. When the tri-state time is longer than a longest limit time, the tri-state feedback control signal assumes a first state to make the The on-time decreases by a predetermined time, and when the tri-state time is shorter than a minimum limit time, the tri-state feedback control signal assumes a second state to increase the on-time by the predetermined time, and when the tri-state time Between the shortest limit time and the longest limit time, the tri-state feedback control signal assumes a third state to maintain the on-time unchanged. 如請求項1所述之脈衝頻率調變的控制方法，其中該控制電路包 含一脈衝頻率調變單擊元件、一脈衝頻率調變控制邏輯元件、一三態時間檢測器、一比較器和一過零檢測電路。The control method of pulse frequency modulation according to claim 1, wherein the control circuit includes a pulse frequency modulation click element, a pulse frequency modulation control logic element, a tri-state time detector, a comparator and a Zero-crossing detection circuit. 如請求項2所述之脈衝頻率調變的控制方法，其中該過零檢測電 路係依該第一電晶體之通道跨壓決定該過零檢測訊號的狀態。The control method of pulse frequency modulation according to claim 2, wherein the zero-crossing detection circuit determines the state of the zero-crossing detection signal according to the channel voltage across the first transistor. 如請求項2所述之脈衝頻率調變的控制方法，其中該脈衝頻率調 變控制邏輯元件係依該過零檢測訊號及該回授電壓與該參考電壓之一比較結果決定一所述脈衝頻率調變週期之所述三態時間。The control method of pulse frequency modulation according to claim 2, wherein the pulse frequency modulation control logic element determines a pulse frequency according to a comparison result of the zero-crossing detection signal and the feedback voltage with the reference voltage The three-state time of the modulation period. 如請求項2所述之脈衝頻率調變的控制方法，其中該三態時間檢 測器是依所述三態時間和所述最長限制時間及所述最短限制時間的比較結果決定該三態回授控制信號的狀態。The control method of pulse frequency modulation according to claim 2, wherein the tri-state time detector determines the tri-state feedback according to the comparison result of the tri-state time and the longest limited time and the shortest limited time The state of the control signal. 如請求項2所述之脈衝頻率調變的控制方法，其中該脈衝頻率調 變單擊元件係用以依該脈衝頻率調變控制邏輯元件的控制產生一所述脈衝頻率調變週期之所述導通時間。The control method of pulse frequency modulation according to claim 2, wherein the pulse frequency modulation click element is used to generate a said pulse frequency modulation period according to the control of the pulse frequency modulation control logic element Turn-on time. 一種 電源轉換電路，至少包含一電感、一第一電晶體、一第二 電晶體、一輸出電容及一控制電路，該控制電路係用以執行一控制方法，以藉由控制該第一電晶體和該第二電晶體以產生一脈衝頻率調變週期，該脈衝頻率調變週期包含一導通階段、一斷開階段和一三態階段，其中，在該導通階段內，該第一電晶體係被斷開且該第二電晶體係被導通以使一輸入電壓對該電感充電，在該斷開階段內，該第一電晶體係被導通且該第二電晶體係被斷開以使該電感會對該輸出電容放電，以在該輸出電容產生一輸出電壓，以及在該三態階段內，該第一電晶體和該第二電晶體均被斷開以使該電感處於被隔絕的狀態，該控制方法包含步驟： 當偵測到該回授電壓小於該參考電壓時，該控制電路開啟所述脈衝頻率調變週期之所述導通階段，其中該回授電壓係依該輸出電壓產生，且所述導通階段之導通時間係由一三態回授控制信號控制； 當所述導通時間結束後，該控制電路使所述脈衝頻率調變週期由所述導通階段進入所述斷開階段； 當偵測到一過零檢測訊號為作用狀態時，該控制電路使所述脈衝頻率調變週期由所述斷開階段進入所述三態階段；以及 當偵測到該回授電壓小於該參考電壓時，該控制電路結束所述三態階段，然後再開啟下一個所述脈衝頻率調變週期； 其中，該三態回授控制信號係依前一個所述脈衝頻率調變週期之所述三態階段的一三態時間決定其狀態，當該三態時間長於一最長限制時間時，該三態回授控制信號呈現一第一狀態以使所述導通時間下降一預定時間，當該三態時間短於一最短限制時間時，該三態回授控制信號呈現一第二狀態以使所述導通時間上升所述預定時間，以及當該三態時間介於該最短限制時間和該最長限制時間時，該三態回授控制信號呈現一第三狀態以使所述導通時間維持不變。A power conversion circuit includes at least an inductor, a first transistor, a second transistor, an output capacitor, and a control circuit. The control circuit is used to execute a control method to control the first transistor And the second transistor to generate a pulse frequency modulation period, the pulse frequency modulation period includes a conduction phase, an off phase and a three-state phase, wherein, in the conduction phase, the first transistor system Is turned off and the second transistor system is turned on to charge an inductor with an input voltage, during the turn-off phase, the first transistor system is turned on and the second transistor system is turned off to make the The inductor discharges the output capacitor to produce an output voltage at the output capacitor, and during the tri-state phase, both the first transistor and the second transistor are disconnected to keep the inductor in an isolated state The control method includes the steps of: when it is detected that the feedback voltage is less than the reference voltage, the control circuit starts the conduction phase of the pulse frequency modulation period, wherein the feedback voltage is generated according to the output voltage, And the conduction time of the conduction phase is controlled by a three-state feedback control signal; when the conduction time ends, the control circuit causes the pulse frequency modulation period to enter the disconnection phase from the conduction phase; When a zero-crossing detection signal is detected to be in an active state, the control circuit causes the pulse frequency modulation period to enter the tri-state phase from the off phase; and when it is detected that the feedback voltage is less than the reference When the voltage is high, the control circuit ends the three-state phase, and then starts the next pulse frequency modulation period; wherein, the three-state feedback control signal is based on the three of the previous pulse frequency modulation period A three-state time of the three-state phase determines its state. When the three-state time is longer than a longest limit time, the three-state feedback control signal assumes a first state to decrease the on-time by a predetermined time. When the time is shorter than a minimum limit time, the tri-state feedback control signal assumes a second state to increase the on-time by the predetermined time, and when the tri-state time is between the minimum limit time and the maximum limit time At this time, the tri-state feedback control signal assumes a third state to maintain the on-time unchanged. 如請求項7所述之電源轉換電路，其中該控制電路具有一過零檢 測電路以依該第一電晶體之通道跨壓決定該過零檢測訊號的狀態。The power conversion circuit according to claim 7, wherein the control circuit has a zero-crossing detection circuit to determine the state of the zero-crossing detection signal according to the channel voltage across the first transistor. 如請求項7所述之電源轉換電路，其中該控制電路具有一脈衝頻 率調變控制邏輯元件以依該過零檢測訊號及該回授電壓與該參考電壓之一比較結果決定一所述脈衝頻率調變週期之所述三態時間。The power conversion circuit according to claim 7, wherein the control circuit has a pulse frequency modulation control logic element to determine a pulse frequency according to a comparison result of the zero-crossing detection signal and the feedback voltage with the reference voltage The three-state time of the modulation period. 如請求項7所述之電源轉換電路，其中該控制電路具有一三態時 間檢測器以依一所述三態時間和所述最長限制時間及所述最短限制時間的比較結果決定該三態回授控制信號的狀態。The power conversion circuit according to claim 7, wherein the control circuit has a tri-state time detector to determine the tri-state return according to a comparison result of the tri-state time and the longest limited time and the shortest limited time The status of the control signal.
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