TW202010018A

TW202010018A - Semiconductor device structures and methods for manufacturing the same

Info

Publication number: TW202010018A
Application number: TW107129785A
Authority: TW
Inventors: 周政偉; 林信志; 周鈺傑
Original assignee: 世界先進積體電路股份有限公司
Priority date: 2018-08-27
Filing date: 2018-08-27
Publication date: 2020-03-01
Also published as: TWI670775B

Abstract

Methods for manufacturing a semiconductor device structure are provided. The methods include providing a base substrate. The methods also include forming a buffer layer over the base substrate. The methods further include forming a patterned silicon layer over the buffer layer. The patterned silicon has an opening exposing a portion of the buffer layer. In addition, the methods include forming a patterned channel layer, a patterned barrier layer over a top surface of the patterned silicon layer. A carrier channel is formed at an interface between the channel layer and the barrier layer. The methods further include a gate electrode over the barrier layer.

Description

半導體裝置結構及其製造方法 Semiconductor device structure and manufacturing method thereof

本揭露係有關於半導體裝置結構，且特別係有關於一種具有複合式基板的半導體裝置結構。 The present disclosure relates to a semiconductor device structure, and particularly relates to a semiconductor device structure with a composite substrate.

近年來，半導體裝置結構在電腦、消費電子等領域中發展快速。目前，半導體裝置技術在金屬氧化物半導體場效電晶體的產品市場中已被廣泛接受，具有很高的市場佔有率。 In recent years, the structure of semiconductor devices has developed rapidly in the fields of computers and consumer electronics. At present, semiconductor device technology has been widely accepted in the product market of metal oxide semiconductor field effect transistors and has a high market share.

近年來，矽上氮化鎵(GaN-on-Si)材料為主之裝置已成為電源裝置的一個具有吸引力的選項。GaN電晶體裝置結構可在靠近AlGaN與GaN異結構間的二維電子雲中提供高電子移動率。高電子移動率使得在高頻的射頻裝置仍可得到良好的功率增益。然而，目前的GaN電晶體裝置結構並非各方面皆令人滿意。因此，業界仍須一種可更進一步提昇品質或降低製造成本之GaN電晶體裝置結構。 In recent years, devices based on gallium nitride (GaN-on-Si) materials have become an attractive option for power devices. The GaN transistor device structure can provide high electron mobility in the two-dimensional electron cloud between the AlGaN and GaN heterostructures. The high electronic mobility makes it possible to obtain good power gain for high-frequency RF devices. However, the current GaN transistor device structure is not satisfactory in all aspects. Therefore, the industry still needs a GaN transistor device structure that can further improve the quality or reduce the manufacturing cost.

本揭露實施例提供一種半導體裝置結構的製造方法。上述製造方法包含提供基底基板。上述製造方法亦包含形成緩衝層於基底基板上。上述製造方法更包含形成圖案化矽層於緩衝層上。圖案化矽層具有開口露出部分的緩衝層。此外，上述製造方法包含依序磊晶成長圖案化通道層及圖案化障壁層於圖案化矽層的上表面上。載子通道形成於圖案化通道層與圖案化障壁層之間的界面上。上述製造方法亦包含形成閘極電極於圖案化障壁層上。 The disclosed embodiments provide a method for manufacturing a semiconductor device structure. The above manufacturing method includes providing a base substrate. The above manufacturing method also includes forming a buffer layer on the base substrate. The above manufacturing method further includes forming a patterned silicon layer on the buffer layer. The patterned silicon layer has a buffer layer with an exposed portion of the opening. In addition, the above manufacturing method includes sequentially epitaxially growing a patterned channel layer and a patterned barrier layer on the upper surface of the patterned silicon layer. The carrier channel is formed on the interface between the patterned channel layer and the patterned barrier layer. The above manufacturing method also includes forming a gate electrode on the patterned barrier layer.

本揭露之一些實施例提供一種半導體裝置結構。上述半導體裝置結構包含基底基板。上述半導體裝置結構亦包含設置於基底基板上的緩衝層。上述半導體裝置結構更包含設置於緩衝層上的圖案化矽層。此外，上述半導體裝置結構包含設置於圖案化矽層的上表面上的通道層。上述半導體裝置結構亦包含設置於通道層上的障壁層。載子通道形成於通道層與障壁層之間的界面上。上述半導體裝置結構更包含設置於障壁層上的閘極電極。 Some embodiments of the present disclosure provide a semiconductor device structure. The above semiconductor device structure includes a base substrate. The above semiconductor device structure also includes a buffer layer provided on the base substrate. The above-mentioned semiconductor device structure further includes a patterned silicon layer disposed on the buffer layer. In addition, the above-mentioned semiconductor device structure includes a channel layer disposed on the upper surface of the patterned silicon layer. The above semiconductor device structure also includes a barrier layer disposed on the channel layer. The carrier channel is formed on the interface between the channel layer and the barrier layer. The above semiconductor device structure further includes a gate electrode provided on the barrier layer.

為讓本揭露實施例之特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下。 In order to make the features and advantages of the disclosed embodiments more obvious and understandable, the preferred embodiments are specifically listed below and described in detail in conjunction with the accompanying drawings.

100A-100E‧‧‧半導體裝置結構 100A-100E‧‧‧Semiconductor device structure

102‧‧‧複合基板 102‧‧‧composite substrate

104‧‧‧基底基板 104‧‧‧ Base substrate

106‧‧‧緩衝層 106‧‧‧buffer layer

108a-108d‧‧‧圖案化矽層 108a-108d‧‧‧patterned silicon layer

110‧‧‧開口 110‧‧‧ opening

112‧‧‧通道層 112‧‧‧channel layer

114‧‧‧障壁層 114‧‧‧ Barrier layer

116‧‧‧載子通道 116‧‧‧Carrier channel

118‧‧‧閘極電極 118‧‧‧Gate electrode

120‧‧‧導體層 120‧‧‧Conductor layer

120’‧‧‧導電材料 120’‧‧‧ conductive material

122‧‧‧介電層 122‧‧‧Dielectric layer

124‧‧‧源/汲極結構 124‧‧‧ source/drain structure

126‧‧‧隔離區 126‧‧‧ Quarantine

128‧‧‧導線 128‧‧‧Wire

202‧‧‧矽基板 202‧‧‧Silicon substrate

202a‧‧‧部分 202a‧‧‧Part

204‧‧‧圖案化遮罩 204‧‧‧patterned mask

206‧‧‧開口 206‧‧‧ opening

208‧‧‧凹陷 208‧‧‧Sag

210‧‧‧離子植入製程 210‧‧‧Ion implantation process

212、212’‧‧‧摻雜區 212, 212’‧‧‧ doped regions

214、214’‧‧‧摻雜區 214, 214’‧‧‧doped regions

216‧‧‧離子植入製程 216‧‧‧Ion implantation process

218‧‧‧圖案化遮罩 218‧‧‧patterned mask

220‧‧‧開口 220‧‧‧ opening

222‧‧‧離子植入製程 222‧‧‧Ion implantation process

224‧‧‧摻雜區 224‧‧‧Doped area

A‧‧‧主要裝置區 A‧‧‧Main installation area

B‧‧‧切割道區 B‧‧‧Cutting area

D1、D2‧‧‧長度 D1, D2‧‧‧Length

I1、I2‧‧‧界面 I1, I2‧‧‧Interface

S1-S5‧‧‧表面 S1-S5‧‧‧Surface

T1-T3‧‧‧厚度 T1-T3‧‧‧thickness

第1A-1G圖為根據本揭露的一些實施例之形成半導體裝置結構的製程各階段的剖面示意圖。 1A-1G are schematic cross-sectional views of various stages of the process of forming a semiconductor device structure according to some embodiments of the present disclosure.

第2圖為根據本揭露的一些實施例之半導體裝置結構的剖面示意圖。 FIG. 2 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments of the present disclosure.

第3A-3F圖為根據本揭露的一些實施例之形成半導體裝置結構的製程各階段的剖面示意圖。 3A-3F are schematic cross-sectional views of various stages of the process of forming a semiconductor device structure according to some embodiments of the present disclosure.

第4A-4D圖為根據本揭露的一些實施例之形成半導體裝置結構的製程各階段的剖面示意圖。 4A-4D are schematic cross-sectional views of various stages of the process of forming a semiconductor device structure according to some embodiments of the present disclosure.

第5A-5E圖為根據本揭露的一些實施例之形成半導體裝置結構的製程各階段的剖面示意圖。 5A-5E are schematic cross-sectional views of various stages of the process of forming a semiconductor device structure according to some embodiments of the present disclosure.

以下揭露提供了許多的實施例或範例，用於實施所提供的半導體裝置之不同元件。各元件和其配置的具體範例描述如下，以簡化本發明實施例之說明。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例而言，敘述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接觸的實施例，也可能包含額外的元件形成在第一和第二元件之間，使得它們不直接接觸的實施例。此外，本發明實施例可能在不同的範例中重複參考數字及/或字母。如此重複是為了簡明和清楚，而非用以表示所討論的不同實施例之間的關係。 The following disclosure provides many embodiments or examples for implementing different elements of the provided semiconductor device. Specific examples of components and their configurations are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the first element is formed on the second element in the description, it may include an embodiment where the first and second elements are in direct contact, or may include additional elements formed between the first and second elements , So that they do not directly contact the embodiment. In addition, embodiments of the present invention may repeat reference numerals and/or letters in different examples. This repetition is for conciseness and clarity, not for expressing the relationship between the different embodiments discussed.

以下描述實施例的一些變化。在不同圖式和說明的實施例中，相似的元件符號被用來標明相似的元件。可以理解的是，在方法的前、中、後可以提供額外的步驟，且一些敘述的步驟可為了該方法的其他實施例被取代或刪除。 Some variations of the embodiments are described below. In different drawings and illustrated embodiments, similar element symbols are used to indicate similar elements. It can be understood that additional steps may be provided before, during, and after the method, and some of the described steps may be replaced or deleted for other embodiments of the method.

本發明的實施例係揭露半導體裝置結構之實施例，且上述實施例可被包含於例如微處理器、記憶元件及/或其他元件之積體電路(integrated circuit,IC)中。上述積體電路也可包含不同的被動和主動微電子元件，例如薄膜電阻器(thin-film resistor)、其他類型電容器例如，金屬-絕緣體-金屬電容(metal-insulator-metal capacitor,MIMCAP)、電感、二極體、金屬氧化物半導體場效電晶體(Metal-Oxide-Semiconductor field-effect transistors,MOSFETs)、互補式MOS電晶體、雙載子接面電晶體(bipolar junction transistors,BJTs)、橫向擴散型MOS電晶體、高功率MOS電晶體或其他類型的電晶體。在本發明所屬技術領域中具有通常知識者可以了解也可將半導體裝置使用於包含其他類型的半導體元件於積體電路之中。 Embodiments of the present invention disclose embodiments of semiconductor device structures, and the above embodiments may be included in integrated circuits (ICs) such as microprocessors, memory devices, and/or other devices. The above integrated circuit may also include different passive and active microelectronic components, such as thin-film resistors, other types of capacitors such as metal-insulator-metal capacitors (MIMCAP), inductors , Diodes, metal oxide semiconductor field-effect transistors (MOSFETs), complementary MOS transistors, bipolar junction transistors (BJTs), lateral diffusion Type MOS transistor, high power MOS transistor or other types of transistor. Those with ordinary knowledge in the technical field to which the present invention belongs can understand that the semiconductor device can also be used in an integrated circuit including other types of semiconductor elements.

參閱第1A-1F圖，第1A-1F圖為根據本揭露的一些實施例之形成半導體裝置結構100A的製程各階段的剖面示意圖。在一些實施例，如第1A圖所示，提供複合基板102。複合基板102包含基底基板104及形成於其上的緩衝層106。在一些實施例，基底基板104包含陶瓷材料。陶瓷材料包含金屬無機材料。在一些實施例，基底基板104包含AlN基板、藍寶石基板或其他適合的基板。上述藍寶石基板為氧化鋁及形成在其上方的氮化鎵組成。在一些實施例，基底基板104的楊氏係數大於矽的楊氏係數。例如，基底基板104介於約200GPa至約1000GPa的範圍間。當基底基板104的楊氏係數越大，能承受越強的應力。因此，有助於後續形成的膜具有較厚的厚度。在一些實施例，基底基板104的韌度(toughness)大於矽的韌度。當基底基板104的韌度越大，能支撐越重的重量，抵抗越大的應力。因此，可以在該基板上成長更厚的膜而不至於使得基板破裂。在一些實施例，基底基板104的硬度大於矽的硬度。當基底基板104的硬度越大，有助於後續形成的膜具有較厚的厚度。 Referring to FIGS. 1A-1F, FIGS. 1A-1F are schematic cross-sectional views of various stages of the process of forming a semiconductor device structure 100A according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 1A, a composite substrate 102 is provided. The composite substrate 102 includes a base substrate 104 and a buffer layer 106 formed thereon. In some embodiments, the base substrate 104 includes a ceramic material. Ceramic materials include metallic inorganic materials. In some embodiments, the base substrate 104 includes an AlN substrate, a sapphire substrate, or other suitable substrates. The sapphire substrate is composed of aluminum oxide and gallium nitride formed thereon. In some embodiments, the Young's coefficient of the base substrate 104 is greater than that of silicon. For example, the base substrate 104 is in the range of about 200 GPa to about 1000 GPa. The larger the Young's coefficient of the base substrate 104, the stronger the stress it can withstand. Therefore, the film contributing to the subsequent formation has a relatively thick thickness. In some embodiments, the toughness of the base substrate 104 is greater than the toughness of silicon. When the toughness of the base substrate 104 is greater, it can support a heavier weight and resist greater stress. Therefore, a thicker film can be grown on the substrate without cracking the substrate. In some embodiments, the hardness of the base substrate 104 is greater than the hardness of silicon. When the hardness of the base substrate 104 is greater, the film that contributes to the subsequent formation has a thicker thickness.

如第1A圖所示，緩衝層106形成於基底基板104上。緩衝層106的設置是用來作為後續形成的矽層與基底基板104的間隔層，避免矽層直接與基底基板104接觸。緩衝層106的材料例如為氧化矽、氮氧化矽或其他材料。第1A圖繪示複合基板102由基底基板104和緩衝層106構成，但複合基板102亦可包含其他層膜，本揭露並不以此為限。 As shown in FIG. 1A, the buffer layer 106 is formed on the base substrate 104. The buffer layer 106 is provided as a spacer layer between the silicon layer and the base substrate 104 to prevent the silicon layer from directly contacting the base substrate 104. The material of the buffer layer 106 is, for example, silicon oxide, silicon oxynitride, or other materials. FIG. 1A shows that the composite substrate 102 is composed of a base substrate 104 and a buffer layer 106, but the composite substrate 102 may also include other layer films, which is not limited in this disclosure.

在一些實施例，如第1B圖所示，形成圖案化矽層108a於緩衝層106上。圖案化矽層108a具有開口110，露出一部分的緩衝層106的上表面。在一些實施例，圖案化矽層108a的表面S1具有(111)晶面。在一些實施例，先藉由沉積製程形成一層包含矽的材料層於緩衝層106上，再藉由微影與蝕刻製程將其圖案化。結果，形成的圖案化矽層108a具有表面S1及與表面S1相鄰的表面S2。表面S1具有(111)晶面，表面S2則不具有(111)晶面。表面S2可視為圖案化矽層108a的側面。在一些實施例，圖案化矽層108a的厚度約介於300nm-600nm的範圍間。 In some embodiments, as shown in FIG. 1B, a patterned silicon layer 108a is formed on the buffer layer 106. The patterned silicon layer 108a has an opening 110 exposing a portion of the upper surface of the buffer layer 106. In some embodiments, the surface S1 of the patterned silicon layer 108a has a (111) crystal plane. In some embodiments, a material layer containing silicon is formed on the buffer layer 106 by a deposition process, and then patterned by a lithography and etching process. As a result, the formed patterned silicon layer 108a has a surface S1 and a surface S2 adjacent to the surface S1. The surface S1 has a (111) crystal plane, and the surface S2 does not have a (111) crystal plane. The surface S2 can be regarded as the side of the patterned silicon layer 108a. In some embodiments, the thickness of the patterned silicon layer 108a is approximately in the range of 300nm-600nm.

上述包含矽的材料層可藉由選擇性磊晶成長(selective epitaxy growth,SEG)製程、化學氣相沉積法(chemical vapor deposition,CVD)製程(例如，氣相磊晶(vapor-phase epitaxy,VPE)製程、低壓化學氣相沉積(low pressure chemical vapor deposition,LPCVD)製程，及/或超高真空化學氣相沉積(ultra-high vacuum chemical vapor deposition,UHV-CVD)製程)、分子束磊晶製程，沉積經摻雜的非晶半導體(例如，Si)之後固相磊晶再結晶(solid-phase epitaxial recrystallization,SPER)步驟、其他適合的製程，或上述組合形成。上述包含矽的材料層的形成製程可使用氣態及/或液態的前驅物，例如SiH₄。 The above-mentioned silicon-containing material layer can be formed by a selective epitaxy growth (SEG) process or a chemical vapor deposition (CVD) process (for example, vapor-phase epitaxy (VPE) ) Process, low pressure chemical vapor deposition (LPCVD) process, and/or ultra-high vacuum chemical vapor deposition (UHV-CVD) process), molecular beam epitaxy process After the doped amorphous semiconductor (for example, Si) is deposited, a solid-phase epitaxial recrystallization (SPER) step, other suitable processes, or a combination thereof are formed. The formation process of the silicon-containing material layer may use gaseous and/or liquid precursors, such as SiH ₄ .

上述微影製程包含光阻塗佈(例如，自旋塗佈)、軟烤、遮罩對準、曝光、曝光後烤、光阻顯影、清洗、乾燥(例如，硬烤)、其他適合製程或其組合來形成。微影製程也可藉由無遮罩微影、電子束寫入、離子束寫入或分子壓印(molecular imprint)替代。蝕刻製程包含乾蝕刻、濕蝕刻或其他蝕刻方法(例如，反應式離子蝕刻)。上述蝕刻製程也可以是純化學蝕刻(電漿蝕刻)、純物理蝕刻(離子研磨)或其組合。 The above photolithography process includes photoresist coating (for example, spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, drying (for example, hard baking), other suitable processes or Its combination to form. The lithography process can also be replaced by maskless lithography, electron beam writing, ion beam writing, or molecular imprint. The etching process includes dry etching, wet etching or other etching methods (for example, reactive ion etching). The above etching process may also be pure chemical etching (plasma etching), pure physical etching (ion polishing), or a combination thereof.

在一些實施例，如第1C圖所示，依序形成通道層112及障壁層114於圖案化矽層108a的表面S1上。在一些實施例，通道層112及障壁層114是具有不同能帶隙(band gap)的材料層。在一實施例中，通道層112及障壁層114是由週期表上第III-V族的元素所形成的化合物所構成，然而，通道層112及障壁層114彼此在組成上是不同的。在一些實施例，通道層112包含GaN層，障壁層114包含Al_xGa_1-xN層，其中0<x<1。通道層112與障壁層114彼此直接接觸。由於通道層112及障壁層114具有不同能帶隙(band gap)，因此在通道層112及障壁層114的界面形成一異質接面(heterojunction)。 In some embodiments, as shown in FIG. 1C, the channel layer 112 and the barrier layer 114 are sequentially formed on the surface S1 of the patterned silicon layer 108a. In some embodiments, the channel layer 112 and the barrier layer 114 are material layers with different band gaps. In one embodiment, the channel layer 112 and the barrier layer 114 are composed of a compound formed of elements of Group III-V on the periodic table, however, the channel layer 112 and the barrier layer 114 are different in composition from each other. In some embodiments, the channel layer 112 includes a GaN layer, and the barrier layer 114 includes an Al _x Ga _1-x N layer, where 0<x<1. The channel layer 112 and the barrier layer 114 directly contact each other. Since the channel layer 112 and the barrier layer 114 have different band gaps, a heterojunction is formed at the interface of the channel layer 112 and the barrier layer 114.

通道層112可使用含鎵的前驅物以及含氮的前驅物，藉由有機金屬氣相磊晶法(metal organic vapor phase epitaxy,MOVPE)磊晶長成，含鎵的前驅物包含三甲基鎵(trimethylgallium,TMG)、三乙基鎵(triethylgallium,TEG)或其他合適的化學品；含氮的前驅物包含氨(ammonia,NH₃)、叔丁胺(tertiarybutylamine,TBAm)、苯肼(phenyl hydrazine)或其他合適的化學品。在一些實施例，通道層112的厚度T1介於約5μm-20μm的範圍間。在一些實施例，通道層112的厚度T1介於約7μm-15μm的範圍間。 The channel layer 112 may use a gallium-containing precursor and a nitrogen-containing precursor, which are epitaxially grown by metal organic vapor phase epitaxy (MOVPE). The gallium-containing precursor includes trimethylgallium (trimethylgallium, TMG), triethyl gallium (triethylgallium, TEG) or other suitable chemicals; nitrogen precursor comprises ammonia (ammonia, NH _3), t-butylamine (tertiarybutylamine, TBAm), phenyl hydrazine (phenyl hydrazine), or Other suitable chemicals. In some embodiments, the thickness T1 of the channel layer 112 is in the range of about 5-20 μm. In some embodiments, the thickness T1 of the channel layer 112 is in the range of about 7-15 μm.

通道層112的厚度T1影響半導體裝置結構100A的崩潰電壓的大小。當通道層112的厚度T1越大，半導體裝置結構100A的崩潰電壓越大。然而，若未使用基底基板104，直接在矽層上成長通道層112，此時通道層112的厚度應不能大於5μm。若在沒有基底基板104的情況下，通道層112的厚度大於5μm時，可能會因為通道層112太重或應力過大導致半導體裝置結構破片。若有楊氏係數或韌度大於矽的基底基板104作為支撐基板，則通道層112的厚度T1可大於5μm。在一些情況，通道層112的厚度應不大於20μm，若通道層112的厚度大於20μm，則可能導致半導體裝置結構100A破片。在一些實施例，使用楊氏係數或韌度大於矽的基底基板104承載圖案化矽層108a，有助於形成較厚的通道層112，因此有助於提升半導體裝置結構100A的崩潰電壓，藉此改善半導體裝置結構100A的可靠度。 The thickness T1 of the channel layer 112 affects the magnitude of the breakdown voltage of the semiconductor device structure 100A. As the thickness T1 of the channel layer 112 is greater, the breakdown voltage of the semiconductor device structure 100A is greater. However, if the base substrate 104 is not used, the channel layer 112 is grown directly on the silicon layer. At this time, the thickness of the channel layer 112 should not be greater than 5 μm. If the thickness of the channel layer 112 is greater than 5 μm without the base substrate 104, the semiconductor device structure may be broken due to the channel layer 112 being too heavy or excessive stress. If a base substrate 104 having a Young's coefficient or toughness greater than silicon is used as a supporting substrate, the thickness T1 of the channel layer 112 may be greater than 5 μm. In some cases, the thickness of the channel layer 112 should not be greater than 20 μm. If the thickness of the channel layer 112 is greater than 20 μm, it may cause the semiconductor device structure 100A to break. In some embodiments, using a base substrate 104 with a Young's modulus or toughness greater than silicon to carry the patterned silicon layer 108a helps to form a thicker channel layer 112, and thus helps to increase the breakdown voltage of the semiconductor device structure 100A. This improves the reliability of the semiconductor device structure 100A.

障壁層114磊晶成長在通道層112上方，障壁層114可使用含鋁的前驅物、含鎵的前驅物以及含氮的前驅物，藉由有機金屬氣相磊晶法(MOVPE)磊晶長成，含鋁的前驅物包含三甲基鋁(trimethylaluminum,TMA)、三乙基鋁(triethylaluminum,TEA)或其他合適的化學品；含鎵的前驅物包含三甲基鎵(TMG)、三乙基鎵(TEG)或其他合適的化學品；含氮的前驅物包含氨(NH₃)、叔丁胺(TBAm)、苯肼(phenyl hydrazine)或其他合適的化學品。在一例子中，障壁層114的厚度範圍介於約5nm至約50nm之間。 The barrier layer 114 is epitaxially grown above the channel layer 112. The barrier layer 114 may use aluminum-containing precursors, gallium-containing precursors, and nitrogen-containing precursors, by organometallic vapor phase epitaxy (MOVPE) epitaxial growth The precursor containing aluminum contains trimethylaluminum (TMA), triethylaluminum (TEA) or other suitable chemicals; the precursor containing gallium contains trimethylgallium (TMG), triethyl Based on gallium (TEG) or other suitable chemicals; nitrogen-containing precursors include ammonia (NH ₃ ), t-butylamine (TBAm), phenyl hydrazine (phenyl hydrazine) or other suitable chemicals. In one example, the thickness of the barrier layer 114 ranges from about 5 nm to about 50 nm.

通道層112與障壁層114之間的能帶差異(band gap discontinuity)與壓電效應(piezo-electric effect)在通道層112與障壁層114之間的界面附近產生具有高移動傳導電子的載子通道116，此載子通道116稱為二維電子氣(two-dimensional electron gas,2-DEG)，其形成於通道層112與障壁層114的界面上。 The band gap discontinuity and the piezo-electric effect between the channel layer 112 and the barrier layer 114 generate carriers with highly mobile conductive electrons near the interface between the channel layer 112 and the barrier layer 114 The channel 116, this carrier channel 116 is called two-dimensional electron gas (2-DEG), which is formed on the interface between the channel layer 112 and the barrier layer 114.

在一些實施例，由GaN形成的通道層112在圖案化矽層108a上之具有(111)晶片的表面S1上的成長速度遠大於在不具有(111)晶片的表面S2上的成長速度。此外，通道層112亦不會磊晶成長在緩衝層106上。因此，藉由磊晶成長形成的通道層112所具有的圖案與圖案化矽層108a相同或相似。另外，藉由磊晶成長形成的障壁層114所具有的圖案與圖案化矽層108a相同或相似。 In some embodiments, the growth rate of the channel layer 112 formed of GaN on the patterned silicon layer 108a on the surface S1 with (111) wafer is much higher than the growth speed on the surface S2 without (111) wafer. In addition, the channel layer 112 will not grow epitaxially on the buffer layer 106. Therefore, the channel layer 112 formed by epitaxial growth has the same or similar pattern as the patterned silicon layer 108a. In addition, the barrier layer 114 formed by epitaxial growth has the same or similar pattern as the patterned silicon layer 108a.

在一些實施例，如第1D圖所示，形成閘極電極118於障壁層114上。在一些實施例，閘極電極118為p型摻雜III-V族層或金屬。在一些實施例，p型摻雜III-V族層，其包含p型摻雜氮化鎵(p-GaN)；金屬包含一或多層導體材料，例如包含金、鉑、銠、銥、鈦、鋁、銅、鉭、鎢、上述合金或其他適合的材料。閘極電極118的作用為降低其下方的二維電子氣(例如載子通道116)的電子濃度，以提高導通電阻。在一些實施例，閘極電極118的厚度介於約50nm至約半導體裝置結構100nm之間。 In some embodiments, as shown in FIG. 1D, a gate electrode 118 is formed on the barrier layer 114. In some embodiments, the gate electrode 118 is a p-type doped III-V group layer or metal. In some embodiments, the p-type doped III-V group layer includes p-type doped gallium nitride (p-GaN); the metal includes one or more layers of conductive materials, such as gold, platinum, rhodium, iridium, titanium, Aluminum, copper, tantalum, tungsten, the above alloys or other suitable materials. The role of the gate electrode 118 is to reduce the electron concentration of the two-dimensional electron gas (for example, the carrier channel 116) below it to increase the on-resistance. In some embodiments, the thickness of the gate electrode 118 is between about 50 nm and about 100 nm of the semiconductor device structure.

閘極電極118可例如藉由有機金屬氣相磊晶法(MOVPE)磊晶形成，並使用乾蝕刻製程而圖案化。乾蝕刻製程例如反應性離子蝕刻(reactive ion etching,RIE)製程或高密度電漿蝕刻製程(high density plasma etching)。在一些實施例，乾蝕刻製程的蝕刻劑包含鹵素，例如氟。含有氟的蝕刻劑例如為CH₃F、CH₂F₂、CHF₃、CF₄或其他適合的氣體。 The gate electrode 118 may be formed by, for example, organometallic vapor phase epitaxy (MOVPE) epitaxy, and patterned using a dry etching process. The dry etching process is, for example, a reactive ion etching (RIE) process or a high density plasma etching process. In some embodiments, the etchant of the dry etching process includes halogen, such as fluorine. The etchant containing fluorine is, for example, CH ₃ F, CH ₂ F ₂ , CHF ₃ , CF ₄ or other suitable gas.

在一些實施例，形成閘極電極118後，通道層112與障壁層114的界面中位於閘極電極118正下方的部分，載子通道116的電子濃度降低或未產生載子通道116。如此，在未對閘極電極118施加偏壓的狀態下，半導體裝置結構100A處於未導通的狀態，在此狀態下，半導體裝置結構100A為常關型(normally off)裝置。 In some embodiments, after the gate electrode 118 is formed, the portion of the interface between the channel layer 112 and the barrier layer 114 directly under the gate electrode 118 reduces the electron concentration of the carrier channel 116 or does not generate the carrier channel 116. As such, in a state where the gate electrode 118 is not biased, the semiconductor device structure 100A is in a non-conducting state, and in this state, the semiconductor device structure 100A is a normally off device.

在一些實施例，如第1E圖所示，沉積導電材料120’於障壁層114及閘極電極118上，並填入開口110。在一些實施例，導電材料120’可包含經摻雜的多晶矽或金屬。導電材料120’藉由化學氣相沉積(chemical vapor deposition,CVD)製程、物理氣相沉積製程、其他適合的製程，或上述組合沉積。 In some embodiments, as shown in FIG. 1E, a conductive material 120' is deposited on the barrier layer 114 and the gate electrode 118, and fills the opening 110. In some embodiments, the conductive material 120' may include doped polysilicon or metal. The conductive material 120' is deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition process, other suitable processes, or a combination thereof.

在一些實施例，如第1F圖所示，移除導電材料120’中超出障壁層114的上表面的部分，以形成導體層120於緩衝層106的表面上，並且位於開口110內。在一些實施例，先對導電材料120’執行蝕刻製程、平坦化製程及/或回蝕刻(etching back)製程來薄化導電材料120’，來移除超出障壁層114的上表面的部分而形成導體層120。平坦化製程可包含化學機械研磨 (chemical mechanical polishing,CMP)製程、研磨製程、蝕刻製程、其他適合的製程，或上述組合。 In some embodiments, as shown in FIG. 1F, the portion of the conductive material 120' that exceeds the upper surface of the barrier layer 114 is removed to form the conductor layer 120 on the surface of the buffer layer 106 and within the opening 110. In some embodiments, the conductive material 120' is first subjected to an etching process, a planarization process, and/or an etching back process to thin the conductive material 120' to remove the portion beyond the upper surface of the barrier layer 114 to form Conductive层120。 The conductor layer 120. The planarization process may include a chemical mechanical polishing (CMP) process, a polishing process, an etching process, other suitable processes, or a combination thereof.

如第1F圖所示，導體層120貫穿圖案化矽層108a、通道層112及障壁層114。此外，導體層120與複合基板102的上表面(例如緩衝層106)直接接觸。在一些情況，先形成並未圖案化的矽層、通道層及障壁層時，再藉由蝕刻製程圖案化矽層、通道層及障壁層，以形成用來設置隔離區的凹槽時，可能難以形成具有較高深寬比的凹槽。在本實施例，在未對通道層112及障壁層114執行蝕刻製程的情況下，通道層112及障壁層114仍具有與圖案化矽層108a相同或相似的圖案。此外，開口110的深寬比隨著通道層112及障壁層114的形成而變大。在本發明實施例，可以容易地形成具有高深寬比的開口110。 As shown in FIG. 1F, the conductor layer 120 penetrates the patterned silicon layer 108a, the channel layer 112, and the barrier layer 114. In addition, the conductor layer 120 directly contacts the upper surface of the composite substrate 102 (for example, the buffer layer 106). In some cases, when the unpatterned silicon layer, the channel layer and the barrier layer are formed first, and then the silicon layer, the channel layer and the barrier layer are patterned by an etching process to form a groove for setting the isolation region, it may be It is difficult to form a groove with a high aspect ratio. In this embodiment, when the etching process is not performed on the channel layer 112 and the barrier layer 114, the channel layer 112 and the barrier layer 114 still have the same or similar pattern as the patterned silicon layer 108a. In addition, the aspect ratio of the opening 110 becomes larger as the channel layer 112 and the barrier layer 114 are formed. In the embodiment of the present invention, the opening 110 having a high aspect ratio can be easily formed.

在一些實施例，如第1G圖所示，形成介電層122、源/汲極結構124及導線128。在一些實施例，形成介電層122前，沉積半導體材料(未繪示)於導體層120及障壁層114上方，並藉由圖案化製程使半導體材料中位於導體層120正上方的部分留下，使導體層120凸出於障壁層114的上表面上方。之後，形成介電層122於障壁層114、導體層120及閘極電極118上方。介電層122包含氧化矽、氮化矽，氮氧化矽、低介電常數(low-K)介電材料、其他適合的材料，或上述組合。介電層122可藉由物理氣相沈積法(physical vapor deposition,PVD)、化學氣相沉積法、原子層沉積法(atomic layer deposition,ALD)、塗佈、濺鍍或其他適合的技術形成。 In some embodiments, as shown in FIG. 1G, a dielectric layer 122, a source/drain structure 124, and a wire 128 are formed. In some embodiments, before forming the dielectric layer 122, a semiconductor material (not shown) is deposited over the conductor layer 120 and the barrier layer 114, and a portion of the semiconductor material directly above the conductor layer 120 is left by a patterning process , So that the conductor layer 120 protrudes above the upper surface of the barrier layer 114. After that, a dielectric layer 122 is formed over the barrier layer 114, the conductor layer 120, and the gate electrode 118. The dielectric layer 122 includes silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, other suitable materials, or a combination thereof. The dielectric layer 122 may be formed by physical vapor deposition (PVD), chemical vapor deposition, atomic layer deposition (ALD), coating, sputtering, or other suitable techniques.

沉積介電層122後，執行微影製程及蝕刻製程，移除介電層122及障壁層114的一部分，以形成溝槽(未繪示)。接下來，將導電材料填入上述溝槽，以形成源/汲極結構124及導線128。源/汲極結構124形成在閘極電極118的相對兩側，並且接觸通道層。源/汲極結構124包含一種或一種以上的導電材料。源/汲極結構124例如包含金屬，其係選自於由銅、鈦、鋁、鎳、金或其他金屬。源/汲極結構124可藉由物理氣相沈積法、化學氣相沉積法、原子層沉積法、塗佈、濺鍍或其他適合的技術形成。 After the dielectric layer 122 is deposited, a lithography process and an etching process are performed to remove a portion of the dielectric layer 122 and the barrier layer 114 to form a trench (not shown). Next, fill the trench with conductive material to form the source/drain structure 124 and the wire 128. The source/drain structures 124 are formed on opposite sides of the gate electrode 118 and contact the channel layer. The source/drain structure 124 includes one or more conductive materials. The source/drain structure 124 includes, for example, a metal selected from copper, titanium, aluminum, nickel, gold, or other metals. The source/drain structure 124 may be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, coating, sputtering, or other suitable techniques.

導線128由鎢、鋁、銅、金、鈀、鈦、其他適合的材料，或上述組合形成。在一些實施例，導線128藉由使用物理氣相沈積法、化學氣相沉積法、原子層沉積法、塗佈、濺鍍或其他適合的技術形成。導線128的材料與源/汲極結構124的材料可相同或不同。在一些實施例，形成源/汲極結構124的步驟與形成導線128可為同一個步驟。可在本發明實施例作各種變化及/或調整。在一些實施例，源/汲極結構124的形成步驟與導線128的形成步驟不同。 The wire 128 is formed of tungsten, aluminum, copper, gold, palladium, titanium, other suitable materials, or a combination thereof. In some embodiments, the wire 128 is formed by using physical vapor deposition, chemical vapor deposition, atomic layer deposition, coating, sputtering, or other suitable techniques. The material of the wire 128 and the material of the source/drain structure 124 may be the same or different. In some embodiments, the step of forming the source/drain structure 124 and the formation of the wire 128 may be the same step. Various changes and/or adjustments can be made in the embodiments of the present invention. In some embodiments, the source/drain structure 124 is formed differently from the wire 128.

在一些實施例，半導體裝置結構100A包含主要裝置(main device)區A與切割道(scribe line)區B。如第1G圖所示，導線128形成在主要裝置區A的導體層120上，並且與導體層120電性連接。導線128並未形成在切割道區B的導體層120上。在一些實施例，可對切割道區B的導體層120與源/汲極結構124之間的區域執行切割製程，以分離主要裝置區A和切割道區B。 In some embodiments, the semiconductor device structure 100A includes a main device area A and a scribe line area B. As shown in FIG. 1G, the wire 128 is formed on the conductor layer 120 of the main device area A, and is electrically connected to the conductor layer 120. The wire 128 is not formed on the conductor layer 120 of the scribe line area B. In some embodiments, a dicing process may be performed on the area between the conductor layer 120 and the source/drain structure 124 of the scribe line area B to separate the main device area A and the scribe area B.

第1G圖繪示一部分的源/汲極結構124鑲入障壁層 114內。可在本發明實施例作各種變化及/或調整。在一些實施例，源/汲極結構124穿透障壁層114及通道層112。 FIG. 1G shows a part of the source/drain structure 124 embedded in the barrier layer 114. Various changes and/or adjustments can be made in the embodiments of the present invention. In some embodiments, the source/drain structure 124 penetrates the barrier layer 114 and the channel layer 112.

在一些實施例，提供具有楊氏係數大於矽的基底基板104，能在避免破片的情況下形成厚度較厚的通道層112。據此，能提升半導體裝置結構100A的崩潰電壓及可靠度。另外，在形成通道層112前，先形成上表面具有(111)晶面的圖案化矽層108a，之後形成的通道層112及障壁層114的圖案會具有與圖案化矽層108a相同或相似的圖案。由上述方法可以較容易地形成具有較高深寬比的開口110。據此，即使形成具有厚度較厚的通道層112亦不會影響具有較高深寬比的開口110的形成難度。 In some embodiments, providing a base substrate 104 having a Young's coefficient greater than silicon can form a thicker channel layer 112 without fragmentation. Accordingly, the breakdown voltage and reliability of the semiconductor device structure 100A can be improved. In addition, before the channel layer 112 is formed, a patterned silicon layer 108a with a (111) crystal plane on the upper surface is formed first, and the pattern of the channel layer 112 and the barrier layer 114 formed later will have the same or similar pattern as the patterned silicon layer 108a pattern. The opening 110 with a higher aspect ratio can be formed more easily by the above method. According to this, even forming the channel layer 112 with a thick thickness will not affect the difficulty of forming the opening 110 with a higher aspect ratio.

第1F-1G圖繪示形成貫穿圖案化矽層108a、通道層112及障壁層114的導體層120。可在本發明實施例作各種變化及/或調整。參閱第2圖，第2圖為根據本揭露的一些實施例之半導體裝置結構100B的剖面示意圖。第2圖所示的半導體裝置結構100B與第1F圖所示的半導體裝置結構100A相同或相似，其中之一的不同處在於：半導體裝置結構100B包含取代了導體層120的隔離區126。 FIGS. 1F-1G illustrate a conductor layer 120 formed through the patterned silicon layer 108a, the channel layer 112, and the barrier layer 114. Various changes and/or adjustments can be made in the embodiments of the present invention. Referring to FIG. 2, FIG. 2 is a schematic cross-sectional view of a semiconductor device structure 100B according to some embodiments of the present disclosure. The semiconductor device structure 100B shown in FIG. 2 is the same as or similar to the semiconductor device structure 100A shown in FIG. 1F, and one of the differences is that the semiconductor device structure 100B includes an isolation region 126 instead of the conductor layer 120.

在一些實施例，隔離區126的材料包含氧化矽、氮化矽，氮氧化矽、旋塗玻璃(spin-on glass)、低介電常數(low-K)介電材料、其他適合的材料，或上述組合。在一些實施例，每一個隔離區126具有多重層結構。在一些實施例，隔離區藉由化學氣相沉積(chemical vapor deposition,CVD)製程、物理氣相沉積製程、其他適合的製程，或上述組合沉積介電材料而形成。 In some embodiments, the material of the isolation region 126 includes silicon oxide, silicon nitride, silicon oxynitride, spin-on glass, low-k dielectric material, other suitable materials, Or a combination of the above. In some embodiments, each isolation region 126 has a multi-layer structure. In some embodiments, the isolation region is formed by depositing a dielectric material by a chemical vapor deposition (CVD) process, a physical vapor deposition process, other suitable processes, or a combination of the above.

參閱第3A-3F圖，第3A-3F圖為根據本揭露的一些實施例之形成半導體裝置結構100C的製程各階段的剖面示意圖。在一些實施例，如第3A圖所示，提供矽基板202。矽基板202可為包含矽的基底、絕緣上覆矽(semiconductor-on-insulation,SOI)基底或其他適合的基底。矽基板202為之後用來形成圖案化矽層的基板。在一些實施例，矽基板202具有(111)晶面。如第3A圖所示，圖案化遮罩204形成於矽基板202上。圖案化遮罩204例如為光阻。圖案化遮罩204可藉由微影製程而形成在矽基板202上。此外，圖案化遮罩204具有開口206，露出一部分的矽基板202的表面。 Referring to FIGS. 3A-3F, FIGS. 3A-3F are schematic cross-sectional views of various stages of the process of forming a semiconductor device structure 100C according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 3A, a silicon substrate 202 is provided. The silicon substrate 202 may be a silicon-containing substrate, a semiconductor-on-insulation (SOI) substrate, or other suitable substrate. The silicon substrate 202 is a substrate for forming a patterned silicon layer later. In some embodiments, the silicon substrate 202 has a (111) crystal plane. As shown in FIG. 3A, the patterned mask 204 is formed on the silicon substrate 202. The patterned mask 204 is, for example, a photoresist. The patterned mask 204 can be formed on the silicon substrate 202 by a lithography process. In addition, the patterned mask 204 has an opening 206 exposing a part of the surface of the silicon substrate 202.

在一些實施例，如第3B圖所示，執行蝕刻製程，在對應開口206處形成凹陷208。如第3B圖所示，矽基板202具有未被蝕刻的表面S3，以及位於凹陷208上的表面S4。 In some embodiments, as shown in FIG. 3B, an etching process is performed to form a recess 208 at the corresponding opening 206. As shown in FIG. 3B, the silicon substrate 202 has an unetched surface S3 and a surface S4 on the recess 208.

在一些實施例，如第3C圖所示，執行離子植入製程210，形成圖案化摻雜區212鄰近於表面S3，並形成圖案化摻雜區214鄰近表面S4。在一些實施例，使用一種或多種適合的摻雜質植入矽基板202。例如，使用氫、硼、氮或其他元素形成圖案化摻雜區212及圖案化摻雜區214。在一些實施例，執行多個植入製程以形成圖案化摻雜區212及圖案化摻雜區214。 In some embodiments, as shown in FIG. 3C, an ion implantation process 210 is performed to form a patterned doped region 212 adjacent to the surface S3, and a patterned doped region 214 adjacent to the surface S4. In some embodiments, one or more suitable dopants are used to implant the silicon substrate 202. For example, patterned doped regions 212 and patterned doped regions 214 are formed using hydrogen, boron, nitrogen, or other elements. In some embodiments, multiple implantation processes are performed to form patterned doped regions 212 and patterned doped regions 214.

如第3C圖所示，圖案化摻雜區212及圖案化摻雜區214具有厚度T2。厚度T2可取決於之後欲形成的圖案化矽層的厚度。在一些實施例，厚度T2介於400nm-700nm的範圍間。在一些實施例，圖案化摻雜區212由矽基板202的表面S3延伸至離表面S3相當於厚度T2的距離，圖案化摻雜區214由矽基板202的表面S4延伸至離表面S4相當於厚度T2的距離。在一些實施例，圖案化摻雜區212及圖案化摻雜區214的摻雜濃度可介於約10¹⁸atoms/cm³至約10²¹atoms/cm³的範圍間。在一些實施例，圖案化摻雜區212並不會直接接觸圖案化摻雜區214。 As shown in FIG. 3C, the patterned doped region 212 and the patterned doped region 214 have a thickness T2. The thickness T2 may depend on the thickness of the patterned silicon layer to be formed later. In some embodiments, the thickness T2 is in the range of 400nm-700nm. In some embodiments, the patterned doped region 212 extends from the surface S3 of the silicon substrate 202 to a distance equivalent to the thickness T2, and the patterned doped region 214 extends from the surface S4 of the silicon substrate 202 to the equivalent surface S4 Thickness T2 distance. In some embodiments, the doping concentration of the patterned doped region 212 and the patterned doped region 214 may be in the range of about 10 ¹⁸ atoms/cm ³ to about 10 ²¹ atoms/cm ³ . In some embodiments, the patterned doped region 212 does not directly contact the patterned doped region 214.

形成圖案化摻雜區212及圖案化摻雜區214的區域的Si-Si鍵會被破壞。在圖案化摻雜區212與未被摻雜的區域的界面的Si-Si鍵亦被破壞掉，使得圖案化摻雜區212與未被摻雜的區域之間的鍵結力減低。因此，形成圖案化摻雜區212及圖案化摻雜區214有助於之後將分離矽基板202中被摻雜的區域與未被摻雜的區域。 The Si-Si bonds in the regions where the patterned doped region 212 and the patterned doped region 214 are formed are broken. The Si-Si bond at the interface of the patterned doped region 212 and the undoped region is also broken, so that the bonding force between the patterned doped region 212 and the undoped region is reduced. Therefore, forming the patterned doped region 212 and the patterned doped region 214 helps to separate the doped region from the undoped region in the silicon substrate 202 later.

在一些實施例，如第3D圖所示，將矽基板202貼合至複合基板102的緩衝層106上。在一些實施例，表面S3與複合基板102的上表面(例如緩衝層106)黏合，表面S4並未接觸複合基板102。如第3D圖所示，矽基板202的圖案化摻雜區212接觸緩衝層106，而凹陷208介於圖案化摻雜區214與緩衝層106之間。在一些實施例，將矽基板202貼合至複合基板102後，執行退火製程。 In some embodiments, as shown in FIG. 3D, the silicon substrate 202 is attached to the buffer layer 106 of the composite substrate 102. In some embodiments, the surface S3 is bonded to the upper surface of the composite substrate 102 (such as the buffer layer 106 ), and the surface S4 does not contact the composite substrate 102. As shown in FIG. 3D, the patterned doped region 212 of the silicon substrate 202 contacts the buffer layer 106, and the recess 208 is between the patterned doped region 214 and the buffer layer 106. In some embodiments, after the silicon substrate 202 is bonded to the composite substrate 102, an annealing process is performed.

在一些實施例，如第3E圖所示，移除矽基板202，並留下圖案化摻雜區212於複合基板102上，以形成圖案化矽層108b。由於圖案化摻雜區212與未被摻雜的區域的界面的Si-Si鍵被破壞掉，因此可以用物理方式分離圖案化摻雜區212與矽基板202中未被摻雜的區域。在此實施例，可藉由調整圖案化遮罩204的圖案和離子植入製程210的條件，改變圖案化矽層 108b的圖案和厚度。在一些實施例，形成圖案化矽層108b後，執行清潔製程，例如以氫氟酸對圖案化矽層108b的上表面(例如表面S3)進行處理。 In some embodiments, as shown in FIG. 3E, the silicon substrate 202 is removed, and the patterned doped regions 212 are left on the composite substrate 102 to form a patterned silicon layer 108b. Since the Si-Si bond at the interface between the patterned doped region 212 and the undoped region is broken, the patterned doped region 212 and the undoped region in the silicon substrate 202 can be physically separated. In this embodiment, the pattern and thickness of the patterned silicon layer 108b can be changed by adjusting the pattern of the patterned mask 204 and the conditions of the ion implantation process 210. In some embodiments, after the patterned silicon layer 108b is formed, a cleaning process is performed, such as treating the upper surface (eg, surface S3) of the patterned silicon layer 108b with hydrofluoric acid.

在一些實施例，如第3F圖所示，形成通道層112、障壁層114、閘極電極118、導體層120、介電層122、源/汲極結構124及導線128，以形成半導體裝置結構100C。從第3E圖所示的結構至3F圖所示的結構所實施的製程和使用的材料與從第1B圖所示的結構至1G圖所示的結構所實施的製程和使用的材料相同或相似，在此不再贅述。 In some embodiments, as shown in FIG. 3F, a channel layer 112, a barrier layer 114, a gate electrode 118, a conductor layer 120, a dielectric layer 122, a source/drain structure 124, and a wire 128 are formed to form a semiconductor device structure 100C. The processes and materials used from the structure shown in Figure 3E to the structure shown in Figure 3F are the same as or similar to the processes and materials used from the structure shown in Figure 1B to the structure shown in Figure 1G , Will not repeat them here.

參閱第4A-4F圖，第4A-4F圖為根據本揭露的一些實施例之形成半導體裝置結構100D的製程各階段的剖面示意圖。至4A圖所示的結構之前所執行的製程或使用的材料與從第3A圖所示的結構至3B圖所示的結構所實施的製程和使用的材料相同或相似，在此不再贅述。 Referring to FIGS. 4A-4F, FIGS. 4A-4F are schematic cross-sectional views of various stages of the process of forming a semiconductor device structure 100D according to some embodiments of the present disclosure. The processes or materials used before the structure shown in FIG. 4A are the same as or similar to the processes and materials used from the structure shown in FIG. 3A to the structure shown in FIG. 3B, and are not repeated here.

在一些實施例，如第4A圖所示，執行離子植入製程216，形成圖案化摻雜區212’鄰近於表面S3，並形成圖案化摻雜區214’鄰近表面S4。在一些實施例，使用一種或多種適合的摻雜質植入矽基板202。例如，使用氫、硼、氮或其他元素形成圖案化摻雜區212’及圖案化摻雜區214’。在一些實施例，執行多個植入製程以形成圖案化摻雜區212’及圖案化摻雜區214’。 In some embodiments, as shown in FIG. 4A, an ion implantation process 216 is performed to form a patterned doped region 212' adjacent to the surface S3, and a patterned doped region 214' adjacent to the surface S4. In some embodiments, one or more suitable dopants are used to implant the silicon substrate 202. For example, patterned doped regions 212' and patterned doped regions 214' are formed using hydrogen, boron, nitrogen, or other elements. In some embodiments, multiple implantation processes are performed to form patterned doped regions 212' and patterned doped regions 214'.

在一些實施例，位於表面S3的部分是矽基板202中未被摻雜的部分202a。在一些實施例，部分202a與矽基板202藉由圖案化摻雜區212’隔開。在此實施例，圖案化摻雜區212’ 與未被摻雜的區域的界面I1和界面I2離表面S3的距離分別為長度D1與長度D2。可藉由控制長度D1與長度D2，決定後續形成的圖案化矽層的厚度。在一些實施例，圖案化摻雜區212’並不會直接接觸圖案化摻雜區214’。 In some embodiments, the portion located on the surface S3 is the undoped portion 202a of the silicon substrate 202. In some embodiments, the portion 202a is separated from the silicon substrate 202 by patterned doped regions 212'. In this embodiment, the distances between the interface I1 and the interface I2 of the patterned doped region 212' and the undoped region from the surface S3 are the length D1 and the length D2, respectively. The thickness of the patterned silicon layer to be formed later can be determined by controlling the length D1 and the length D2. In some embodiments, the patterned doped region 212' does not directly contact the patterned doped region 214'.

如先前所述，圖案化摻雜區212’與未被摻雜的區域的界面的Si-Si鍵被破壞掉。因此，形成圖案化摻雜區212’及圖案化摻雜區214’有助於之後將矽基板202中分離被摻雜的區域與未被摻雜的區域。 As described previously, the Si-Si bond at the interface of the patterned doped region 212' and the undoped region is broken. Therefore, forming the patterned doped regions 212' and the patterned doped regions 214' helps to separate the doped regions from the undoped regions in the silicon substrate 202 later.

在一些實施例，如第4B圖所示，將矽基板202貼合至複合基板102的緩衝層106上。在一些實施例，表面S3與緩衝層106黏合，表面S4並未接觸緩衝層106。如第4B圖所示，圖案化摻雜區212’並未直接接觸複合基板102，與複合基板102直接接觸的是部分202a。 In some embodiments, as shown in FIG. 4B, the silicon substrate 202 is bonded to the buffer layer 106 of the composite substrate 102. In some embodiments, the surface S3 is bonded to the buffer layer 106 and the surface S4 does not contact the buffer layer 106. As shown in FIG. 4B, the patterned doped region 212' does not directly contact the composite substrate 102, and the portion 202a directly contacts the composite substrate 102.

在一些實施例，如第4C圖所示，移除矽基板202，並留下圖案化摻雜區212’及部分202a於複合基板102上，以形成圖案化矽層108c。在一些實施例，圖案化矽層108c包含具有摻雜質的圖案化摻雜區212’及未被摻雜的部分202a。由於圖案化摻雜區212’與未被摻雜的區域的界面I2的Si-Si鍵被破壞掉，因此可以用物理方式分離圖案化摻雜區212’與矽基板202中未被摻雜的區域。可在本發明實施例作各種變化及/或調整。在一些實施例，移除圖案化摻雜區212’與矽基板202，並留下部分202a於複合基板102上。在此實施例，圖案化矽層108c並未被摻雜。 In some embodiments, as shown in FIG. 4C, the silicon substrate 202 is removed, and a patterned doped region 212' and a portion 202a are left on the composite substrate 102 to form a patterned silicon layer 108c. In some embodiments, the patterned silicon layer 108c includes a doped patterned doped region 212' and an undoped portion 202a. Since the Si-Si bond at the interface I2 between the patterned doped region 212' and the undoped region is broken, the patterned doped region 212' and the undoped silicon substrate 202 can be physically separated area. Various changes and/or adjustments can be made in the embodiments of the present invention. In some embodiments, the patterned doped region 212' and the silicon substrate 202 are removed, leaving a portion 202a on the composite substrate 102. In this embodiment, the patterned silicon layer 108c is not doped.

在一些實施例，如第4D圖所示，形成通道層112、障壁層114、閘極電極118、導體層120、介電層122、源/汲極結構124及導線128，以形成半導體裝置結構100D。從第4C圖所示的結構至4D圖所示的結構所實施的製程和使用的材料與從第1B圖所示的結構至1G圖所示的結構所實施的製程和使用的材料相同或相似，在此不再贅述。 In some embodiments, as shown in FIG. 4D, a channel layer 112, a barrier layer 114, a gate electrode 118, a conductor layer 120, a dielectric layer 122, a source/drain structure 124, and a wire 128 are formed to form a semiconductor device structure 100D. The processes and materials used from the structure shown in Figure 4C to the structure shown in Figure 4D are the same as or similar to the processes and materials used from the structure shown in Figure 1B to the structure shown in Figure 1G , Will not repeat them here.

參閱第5A-5E圖，第5A-5E圖為根據本揭露的一些實施例之形成半導體裝置結構100E的製程各階段的剖面示意圖。在一些實施例，如第5A圖所示，圖案化遮罩218形成於矽基板202上。圖案化遮罩218例如為光阻。圖案化遮罩218可藉由微影製程而形成在矽基板202上。此外，圖案化遮罩218具有開口220，露出一部分的矽基板202的表面S5。 Referring to FIGS. 5A-5E, FIGS. 5A-5E are schematic cross-sectional views of various stages of the process of forming a semiconductor device structure 100E according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 5A, the patterned mask 218 is formed on the silicon substrate 202. The patterned mask 218 is, for example, a photoresist. The patterned mask 218 can be formed on the silicon substrate 202 by a lithography process. In addition, the patterned mask 218 has an opening 220 exposing a part of the surface S5 of the silicon substrate 202.

在一些實施例，如第5B圖所示，執行離子植入製程222，形成圖案化摻雜區224鄰近於表面S5。在一些實施例，使用一種或多種適合的摻雜質植入矽基板202。例如，使用氫、硼、氮或其他元素形成圖案化摻雜區224。在一些實施例，執行多個植入製程以形成圖案化摻雜區224。 In some embodiments, as shown in FIG. 5B, an ion implantation process 222 is performed to form a patterned doped region 224 adjacent to the surface S5. In some embodiments, one or more suitable dopants are used to implant the silicon substrate 202. For example, patterned doped regions 224 are formed using hydrogen, boron, nitrogen, or other elements. In some embodiments, multiple implantation processes are performed to form patterned doped regions 224.

如第5B圖所示，圖案化摻雜區224具有厚度T3。厚度T3可取決於之後欲形成的圖案化矽層的厚度。在一些實施例，厚度T3介於400nm-700nm的範圍間。在一些實施例，圖案化摻雜區224由矽基板202的表面S5延伸至離表面S5相當於厚度T3的距離。在一些實施例，圖案化摻雜區224的摻雜濃度可介於約10¹⁸atoms/cm³至約10²¹atoms/cm³的範圍間。 As shown in FIG. 5B, the patterned doped region 224 has a thickness T3. The thickness T3 may depend on the thickness of the patterned silicon layer to be formed later. In some embodiments, the thickness T3 is in the range of 400nm-700nm. In some embodiments, the patterned doped region 224 extends from the surface S5 of the silicon substrate 202 to a distance corresponding to the thickness T3 from the surface S5. In some embodiments, the doping concentration of the patterned doped region 224 may range from about 10 ¹⁸ atoms/cm ³ to about 10 ²¹ atoms/cm ³ .

如先前所述，圖案化摻雜區224與未被摻雜的區域的界面的Si-Si鍵被破壞掉。因此，形成圖案化摻雜區224有助於之後分離矽基板202中被摻雜的區域與未被摻雜的區域。 As described previously, the Si-Si bond at the interface of the patterned doped region 224 and the undoped region is broken. Therefore, forming the patterned doped region 224 helps to separate the doped region from the undoped region in the silicon substrate 202 later.

在一些實施例，如第5C圖所示，將矽基板202貼合至複合基板102的緩衝層106上。在一些實施例，表面S5與緩衝層106黏合。如第5C圖所示，圖案化摻雜區224及一部分的矽基板202黏合至複合基板102上，並直接接觸複合基板102。 In some embodiments, as shown in FIG. 5C, the silicon substrate 202 is attached to the buffer layer 106 of the composite substrate 102. In some embodiments, the surface S5 is bonded to the buffer layer 106. As shown in FIG. 5C, the patterned doped region 224 and a part of the silicon substrate 202 are bonded to the composite substrate 102 and directly contact the composite substrate 102.

在一些實施例，如第5D圖所示，移除矽基板202，並留下圖案化摻雜區224於複合基板102上，以形成圖案化矽層108d。由於圖案化摻雜區224與未被摻雜的區域的界面的Si-Si鍵被破壞掉，因此可以用物理方式分離圖案化摻雜區224與矽基板202中未被摻雜的區域。 In some embodiments, as shown in FIG. 5D, the silicon substrate 202 is removed, and a patterned doped region 224 is left on the composite substrate 102 to form a patterned silicon layer 108d. Since the Si—Si bond at the interface between the patterned doped region 224 and the undoped region is broken, the patterned doped region 224 and the undoped region in the silicon substrate 202 can be physically separated.

在一些實施例，如第5E圖所示，形成通道層112、障壁層114、閘極電極118、導體層120、介電層122、源/汲極結構124及導線128，以形成半導體裝置結構100E。從第5D圖所示的結構至5E圖所示的結構所實施的製程和使用的材料與從第1B圖所示的結構至1G圖所示的結構所實施的製程和使用的材料相同或相似，在此不再贅述。 In some embodiments, as shown in FIG. 5E, a channel layer 112, a barrier layer 114, a gate electrode 118, a conductor layer 120, a dielectric layer 122, a source/drain structure 124, and a wire 128 are formed to form a semiconductor device structure 100E. The processes and materials used from the structure shown in Figure 5D to the structure shown in Figure 5E are the same as or similar to the processes and materials used from the structure shown in Figure 1B to the structure shown in Figure 1G , Will not repeat them here.

雖然本揭露的實施例及其優點已揭露如上，但應該瞭解的是，任何所屬技術領域中具有通常知識者，在不脫離本揭露之精神和範圍內，當可作更動、替代與潤飾。此外，本揭露之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本揭露一些實施例之揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大抵相同功能或獲得大抵相同結果皆可根據本揭露一些實施例使用。因此，本揭露之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本揭露之保護範圍也包括各個申請專利範圍及實施例的組合。 Although the embodiments and advantages of the present disclosure have been disclosed above, it should be understood that anyone with ordinary knowledge in the technical field can make changes, substitutions, and retouching without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material composition, devices, methods, and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the technical field can implement some implementations from the present disclosure. In the disclosure of the examples, understand the current or future development of processes, machines, manufacturing, material composition, devices, methods and steps, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein. This disclosure uses some embodiments. Therefore, the protection scope of the present disclosure includes the above processes, machines, manufacturing, material composition, devices, methods and steps. In addition, each patent application scope constitutes an individual embodiment, and the protection scope of the present disclosure also includes a combination of each patent application scope and embodiment.

100A‧‧‧半導體裝置結構 100A‧‧‧Semiconductor device structure

102‧‧‧複合基板 102‧‧‧composite substrate

104‧‧‧基底基板 104‧‧‧ Base substrate

106‧‧‧緩衝層 106‧‧‧buffer layer

108a‧‧‧圖案化矽層 108a‧‧‧patterned silicon layer

112‧‧‧通道層 112‧‧‧channel layer

114‧‧‧障壁層 114‧‧‧ Barrier layer

116‧‧‧載子通道 116‧‧‧Carrier channel

118‧‧‧閘極電極 118‧‧‧Gate electrode

120‧‧‧導體層 120‧‧‧Conductor layer

122‧‧‧介電層 122‧‧‧Dielectric layer

124‧‧‧源/汲極結構 124‧‧‧ source/drain structure

128‧‧‧導線 128‧‧‧Wire

A‧‧‧主要裝置區 A‧‧‧Main installation area

B‧‧‧切割道區 B‧‧‧Cutting area

Claims

一種製造半導體裝置結構的方法，包括：提供一基底基板；形成一緩衝層於該基底基板上；形成一圖案化矽層於該緩衝層上，該圖案化矽層具有一開口露出一部分的該緩衝層；依序磊晶成長一圖案化通道層及一圖案化障壁層於該圖案化矽層的一上表面上，其中一載子通道形成於該圖案化通道層與該圖案化障壁層之間的一界面上；以及形成一閘極電極於該圖案化障壁層上。 A method of manufacturing a semiconductor device structure includes: providing a base substrate; forming a buffer layer on the base substrate; forming a patterned silicon layer on the buffer layer, the patterned silicon layer having an opening to expose a portion of the buffer Layer; sequentially epitaxially growing a patterned channel layer and a patterned barrier layer on an upper surface of the patterned silicon layer, wherein a carrier channel is formed between the patterned channel layer and the patterned barrier layer On an interface; and forming a gate electrode on the patterned barrier layer.

如申請專利範圍第1項所述之製造半導體裝置結構的方法，其中該基底基板包括AlN基板或藍寶石基板。 The method for manufacturing a semiconductor device structure as described in item 1 of the patent application range, wherein the base substrate includes an AlN substrate or a sapphire substrate.

如申請專利範圍第1項所述之製造半導體裝置結構的方法，其中該基底基板的楊氏係數大於該圖案化矽層的楊氏係數。 The method for manufacturing a semiconductor device structure as described in item 1 of the patent application range, wherein the Young's coefficient of the base substrate is greater than that of the patterned silicon layer.

如申請專利範圍第1項所述之製造半導體裝置結構的方法，更包括：沉積一絕緣材料至該開口內，以形成貫穿該圖案化障壁層、該圖案化通道層及該圖案化矽層的一隔離元件。 The method for manufacturing a semiconductor device structure as described in item 1 of the scope of the patent application further includes: depositing an insulating material into the opening to form a pattern penetrating the patterned barrier layer, the patterned channel layer and the patterned silicon layer One isolation element.

如申請專利範圍第1項所述之製造半導體裝置結構的方法，更包括：沉積一導電材料至該開口內，以形成貫穿該圖案化障壁層、該圖案化通道層及該圖案化矽層的一導體層。 The method of manufacturing a semiconductor device structure as described in item 1 of the patent scope further includes: depositing a conductive material into the opening to form a pattern that penetrates the patterned barrier layer, the patterned channel layer and the patterned silicon layer One conductor layer.

如申請專利範圍第1項所述之製造半導體裝置結構的方法，其中形成該圖案化矽層包括：形成一包括矽的材料層於該緩衝層上；以及執行一蝕刻製程於該材料層上，以形成該開口及該圖案化矽層。 The method for manufacturing a semiconductor device structure as described in item 1 of the patent scope, wherein forming the patterned silicon layer includes: forming a material layer including silicon on the buffer layer; and performing an etching process on the material layer, To form the opening and the patterned silicon layer.

如申請專利範圍第1項所述之製造半導體裝置結構的方法，其中形成該圖案化矽層包括：提供一矽基板；執行一離子植入製程，形成一圖案化摻雜區於該矽基板內；將該矽基板貼合至該緩衝層；以及移除該矽基板，使該圖案化摻雜區留在該緩衝層上，以形成該圖案化矽層。 The method for manufacturing a semiconductor device structure as described in item 1 of the patent application scope, wherein forming the patterned silicon layer includes: providing a silicon substrate; performing an ion implantation process to form a patterned doped region in the silicon substrate Affixing the silicon substrate to the buffer layer; and removing the silicon substrate so that the patterned doped region remains on the buffer layer to form the patterned silicon layer.

如申請專利範圍第7項所述之製造半導體裝置結構的方法，更包括：形成一圖案化遮罩於該矽基板上，露出該矽基板的一第一表面的一部分；對該矽基板的該部分執行一蝕刻製程，圖案化該第一表面；以及去除該圖案化遮罩，其中該圖案化摻雜區形成在該矽基板的經圖案化的該第一表面內。 The method of manufacturing a semiconductor device structure as described in item 7 of the patent scope further includes: forming a patterned mask on the silicon substrate to expose a portion of a first surface of the silicon substrate; the An etching process is partially performed to pattern the first surface; and the patterned mask is removed, wherein the patterned doped region is formed in the patterned first surface of the silicon substrate.

如申請專利範圍第8項所述之製造半導體裝置結構的方法，更包括：將該矽基板的經圖案化的該第一表面貼合至該緩衝層。 The method for manufacturing a semiconductor device structure as described in item 8 of the scope of the patent application further includes: bonding the patterned first surface of the silicon substrate to the buffer layer.

如申請專利範圍第7項所述之製造半導體裝置結構的方法，更包括：形成一圖案化遮罩於該矽基板上，露出該矽基板的一部分；藉由該離子植入製程，形成該圖案化摻雜區於該矽基板的一第一表面內，並對應該矽基板的該部分；移除該圖案化遮罩；將該矽基板的該第一表面貼合至該緩衝層；以及移除該矽基板，使該矽基板的該圖案化摻雜區留在該緩衝層上。 The method for manufacturing a semiconductor device structure as described in item 7 of the patent application scope further includes: forming a patterned mask on the silicon substrate to expose a part of the silicon substrate; forming the pattern by the ion implantation process A doped region in a first surface of the silicon substrate and corresponding to the portion of the silicon substrate; removing the patterned mask; attaching the first surface of the silicon substrate to the buffer layer; and shifting Except for the silicon substrate, the patterned doped region of the silicon substrate is left on the buffer layer.

一種半導體裝置結構，包括：一基底基板；一緩衝層，設置於該基底基板上；一圖案化矽層，覆蓋一部分的該緩衝層；一通道層，設置於該圖案化矽層的一上表面上；一障壁層，設置於該通道層上，其中一載子通道形成於該通道層與該障壁層之間的一界面上；以及一閘極電極，設置於該障壁層上。 A semiconductor device structure includes: a base substrate; a buffer layer disposed on the base substrate; a patterned silicon layer covering a portion of the buffer layer; and a channel layer disposed on an upper surface of the patterned silicon layer A barrier layer disposed on the channel layer, wherein a carrier channel is formed on an interface between the channel layer and the barrier layer; and a gate electrode is disposed on the barrier layer.

如申請專利範圍第11項所述之半導體裝置結構，其中該基底基板包括AlN基板或藍寶石基板。 The semiconductor device structure as described in item 11 of the patent application range, wherein the base substrate includes an AlN substrate or a sapphire substrate.

如申請專利範圍第11項所述之半導體裝置結構，其中該基底基板的楊氏係數大於該圖案化矽層的楊氏係數。 The semiconductor device structure as described in item 11 of the patent application range, wherein the Young's coefficient of the base substrate is greater than that of the patterned silicon layer.

如申請專利範圍第11項所述之半導體裝置結構，更包括：一隔離元件，貫穿該障壁層、該通道層及該圖案化矽層。 The semiconductor device structure as described in item 11 of the patent application scope further includes: an isolation element penetrating the barrier layer, the channel layer and the patterned silicon layer.

如申請專利範圍第11項所述之半導體裝置結構，更包括：一導體層，貫穿該障壁層、該通道層及該圖案化矽層。 The semiconductor device structure as described in item 11 of the patent application scope further includes: a conductor layer penetrating the barrier layer, the channel layer and the patterned silicon layer.

如申請專利範圍第11項所述之半導體裝置結構，其中該通道層的一厚度介於約5μm至約20μm的範圍間。 The semiconductor device structure as described in item 11 of the patent application range, wherein a thickness of the channel layer ranges from about 5 μm to about 20 μm.

如申請專利範圍第11項所述之半導體裝置結構，其中該圖案化矽層具有一摻雜區。 The semiconductor device structure as described in item 11 of the patent application range, wherein the patterned silicon layer has a doped region.

如申請專利範圍第11項所述之半導體裝置結構，其中該圖案化矽層的該上表面為(111)晶面。 The semiconductor device structure as described in item 11 of the patent application scope, wherein the upper surface of the patterned silicon layer is a (111) crystal plane.