TW202008586A - 穿隧式場效電晶體及其形成方法 - Google Patents

穿隧式場效電晶體及其形成方法 Download PDF

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TW202008586A
TW202008586A TW108101693A TW108101693A TW202008586A TW 202008586 A TW202008586 A TW 202008586A TW 108101693 A TW108101693 A TW 108101693A TW 108101693 A TW108101693 A TW 108101693A TW 202008586 A TW202008586 A TW 202008586A
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layer
layers
semiconductor layer
doped epitaxial
field effect
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朵爾伯斯 吉爾本
瑞姆瓦爾 彼德
麥特西亞斯帕斯拉克
迪亞茲 卡羅司
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台灣積體電路製造股份有限公司
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Abstract

一種裝置包含第一半導體層、第二半導體層以及本質半導體層。第二半導體層位於第一半導體層上。第一半導體層與第二半導體層是相對的導電型態。第二半導體層包含第一側壁以及第二側壁，其實質垂直且大於第一側壁。本質半導體層接觸第二半導體層的第二側壁與第一半導體層。

Description

穿隧式場效電晶體及其形成方法
本揭露是關於穿隧式場效電晶體及其形成方法。
為了追求高裝置密度、高效能以及低成本，半導體產業進展至奈米級科技製程，而三維設計(例如多閘極場效電晶體(multi-gate field effect transistor(FET))，包含鰭式場效電晶體(Fin FET)以及閘極全環場效電晶體(gate-all-around(GAA)FET)的發展面臨來自製程以及設計議題兩者的考驗。場效電晶體(FET)廣泛地使用於積體晶片。場效電晶體包含源極、汲極以及閘極。場效電晶體常需要大的次臨界斜率，例如小的次臨界擺幅(subthreshold swing)，因為大的次臨界斜率(subthreshold slope)有助於增加電流開關比而降低漏電流。
本揭露之部份實施方式提供一種裝置包含第一 半導體層、第二半導體層以及本質半導體層。第二半導體層位於第一半導體層上。第一半導體層與第二半導體層是相對的導電型態。第二半導體層包含第一側壁以及第二側壁，其實質垂直且大於第一側壁。本質半導體層接觸第二半導體層的第二側壁與第一半導體層。
100‧‧‧方法
102~122‧‧‧步驟
210‧‧‧基板
210A‧‧‧第一區域
210B‧‧‧第二區域
220‧‧‧介電層
220O‧‧‧開口
230‧‧‧源極/汲極接觸
300‧‧‧n型穿隧式場效電晶體
300'‧‧‧n型穿隧式場效電 晶體
370‧‧‧填充金屬層
400‧‧‧p型穿隧式場效電晶體
400'‧‧‧p型穿隧式場效電晶體
410、410'‧‧‧第一摻雜磊晶層
410B‧‧‧底部分
410P‧‧‧突出部分
420、420'‧‧‧中間層
420"‧‧‧絕緣層
310、310'‧‧‧第一摻雜磊晶層
310B‧‧‧底部分
310P‧‧‧突出部分
320、320'‧‧‧中間層
320"‧‧‧絕緣層
330、330'‧‧‧第二摻雜磊晶層
340‧‧‧本質半導體層
350‧‧‧閘極介電層
350SP‧‧‧短部分
350LP‧‧‧長部分
360‧‧‧金屬閘極層
430、430'‧‧‧第二摻雜磊晶層
440‧‧‧本質半導體層
450‧‧‧閘極介電層
450SP‧‧‧短部分
450LP‧‧‧長部分
460‧‧‧金屬閘極層
470‧‧‧填充金屬層
500‧‧‧反相器
FS1、FS2‧‧‧鰭式結構
LS1、LS2‧‧‧長邊
SS1、SS2‧‧‧短邊
M1‧‧‧遮罩
DT1、DT2‧‧‧溝槽
從以下詳細敘述並搭配圖式檢閱，可理解本揭露的態樣。應注意到，多種特徵並未以產業上實務標準的比例繪製。事實上，為了清楚討論，多種特徵的尺寸可以任意地增加或減少。
第1A圖與第1B圖為根據本揭露之部分實施方式的穿隧式場效電晶體的形成方法的流程圖。
第2圖至第12B圖繪示根據本揭露之部分實施方式的穿隧式場效電晶體的形成方法的各個階段。
第13圖為根據本揭露之部分實施方式的穿隧式場效電晶體的剖面示意圖。
第14圖為根據本揭露之部分實施方式的積體電路的剖面示意圖。
以下本揭露將提供許多個不同的實施方式或實施例以實現所提供之專利標的之不同特徵。許多元件與設置將以特定實施例在以下說明，以簡化本揭露。當然這些實施 例僅用以示例而不應用以限制本揭露。舉例而言，敘述「第一特徵形成於第二特徵上」包含多種實施方式，其中涵蓋第一特徵與第二特徵直接接觸，以及額外的特徵形成於第一特徵與第二特徵之間而使兩者不直接接觸。此外，於各式各樣的實施例中，本揭露可能會重複標號以及/或標註字母。此重複是為了簡化並清楚說明，而非意圖表明這些討論的各種實施方式以及/或配置之間的關係。
更甚者，空間相對的詞彙，例如「下層的」、「低於」、「下方」、「之下」、「上層的」、「上方」等相關詞彙，於此用以簡單描述元件或特徵與另一元件或特徵的關係，如圖所示。在使用或操作時，除了圖中所繪示的轉向之外，這些空間相對的詞彙涵蓋裝置的不同的轉向。或者，這些裝置可旋轉(旋轉90度或其他角度)，且在此使用的空間相對的描述語可作對應的解讀。
次臨限擺幅(sub-threshold swing；SS)表示電晶體切換電流開關的容易程度，且也是決定電晶體速度的因素。在現有的技術領域中，在室溫下，次臨限擺幅的極限大約為60mV/decade。此極限是因為載子的擴散傳輸機制受到溫度影響。因此，現有的裝置在室溫下開關速度無法超過60mV/decade。
穿隧式場效電晶體(Tunnel field-effect transistor；TFET)經研究能解決以上討論的問題。在穿隧式場效電晶體中，從源極的價帶至通道的導帶的帶對帶穿隧(band-to-band tunneling)主導接面。有鑑於電流機 制由此穿隧決定，電流展現非常低的溫度依賴特性，其主要來自於能隙隨溫度的變化。據此，次臨限擺幅不限於溫度，且能達到相對較低的次臨限擺幅。
第1A圖與第1B圖為根據本揭露之部分實施方式的穿隧式場效電晶體的形成方法100的流程圖。第2圖至圖12B繪示根據本揭露之部分實施方式的穿隧式場效電晶體的形成方法100的各個階段。此描述僅為例示，而不意圖進一步限制後續專利申請範圍中所載的內容。應了解到，可以在第1A圖與第1B圖步驟之前、之中以及之後加入額外的步驟，且對於該方法的另一部份實施方式，以下提到的部分步驟可以被取代或取消。步驟/程序的順序可以被改變。
參照第2圖，方法100開始於步驟102，在基板210的第一區域210A上形成第一摻雜磊晶層310、中間層320和第二摻雜磊晶層330，並且在基板210的第二區域210B上形成第一摻雜磊晶層410、中間層420和第二摻雜磊晶層430。第一區域210A可以用於形成n型裝置，例如n型穿隧式場效電晶體，第二區域210B可以用於形成p型裝置，例如p型穿隧式場效電晶體。
基板210可以是半導體基板，例如塊狀基板、絕緣上半導體(semiconductor-on-insulator；SOI)基板等。基板210可包含晶圓，例如矽晶圓。絕緣上半導體基板通常包含一層半導體材料形成於絕緣層上。絕緣層可例如為埋氧化物層、矽氧化物層等。絕緣層可提供於基板上，例如為矽或玻璃基板上。也可以採用其他基板，例如多層或漸 變基板。於部分實施方式中，基板210的半導體材料可包含矽；鍺；化合物半導體包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦以及/或銻化銦；合金半導體包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP以及/或GaInAsP；或其組合。
於部分實施方式中，第一摻雜磊晶層310與410以及第二摻雜磊晶層330與440由低能隙材料所組成，其可以是低能隙三五族化合物半導體材料。此低能隙材料可具有低於0.75eV的能隙，或例如低於0.5eV。舉例而言，第一摻雜磊晶層310與410以及第二摻雜磊晶層330與440由GaxIn1-xAsySb1-y組成，其中x是位於範圍0至1之間，且y是位於範圍0至1之間。
第一摻雜磊晶層310以及第二摻雜磊晶層330的成分以及/或材料不同。舉例而言，第一摻雜磊晶層310中的x跟y不同於第二摻雜磊晶層330中的x跟y。在進一步的實施方式中，第一摻雜磊晶層310可以是無鋁的InAs，而第二摻雜磊晶層330可以是無鋁的GaSb。在後續階段中，在氧化處理後，此在摻雜磊晶層310與330沒有鋁的配置會降低摻雜磊晶層310與330的氧化。第一與第二摻雜磊晶層310與330是屬於相對的導電型態。在部分實施方式中，第一摻雜磊晶層310是摻雜n型摻雜物，例如但不限於，矽、氧或其組合。第一摻雜磊晶層310的n型雜質濃度可高於大約1018/cm3。第二摻雜磊晶層330是摻雜一p型摻雜物，例如但不限於，鎂、鈣、鋅、鈹、碳或其組合。第二摻雜磊晶 層330的p型雜質濃度可高於大約1018/cm3。第一摻雜磊晶層310以及第二摻雜磊晶層330用於形成n型穿隧式場效電晶體。
第一摻雜磊晶層410以及第二摻雜磊晶層430的成分以及/或材料不同。舉例而言，第一摻雜磊晶層410中的x跟y不同於第二摻雜磊晶層430中的x跟y。在部分實施方式中，第一摻雜磊晶層410可以是實質無鋁的GaSb，而第二摻雜磊晶層430可以是實質無鋁的InAs。在後續階段中，在氧化處理後，此在摻雜磊晶層410與430沒有鋁的配置會降低摻雜磊晶層410與430的氧化。第一與第二摻雜磊晶層410與430是屬於相對的導電型態。在部分實施方式中，第一摻雜磊晶層410是摻雜p型摻雜物，例如但不限於，鎂、鈣、鋅、鈹、碳或其組合。第一摻雜磊晶層410的p型雜質濃度可高於大約1018/cm3。第二摻雜磊晶層430是摻雜一n型摻雜物，例如但不限於，矽、氧或其組合。第二摻雜磊晶層430的n型雜質濃度可高於大約1018/cm3。第一摻雜磊晶層410以及第二摻雜磊晶層430用於形成p型穿隧式場效電晶體。
於部分實施方式中，中間層320與420由含鋁半導體組成。中間層320與420的材料不同於第一摻雜磊晶層310與410以及第二摻雜磊晶層330與430的材料。舉例而言，中間層320與420是AlxGa1-xAsySb1-y，其中x是位於範圍0.1至1之間，且y是位於範圍0至1之間。所選擇的x與y能夠使上層材料與下層材料晶格匹配，例如使層體310與 330晶格匹配，使層體410與430晶格匹配。在進一步的實施方式中，中間層320與420是二元的銻化鋁(AlSb)化合物，其不含鎵和砷。
於部分實施方式中，中間層320與420為非刻意摻雜的(not-intentionally doped；NID)，舉例而言，未刻意設置摻雜物，而是因為製程汙染而摻雜。舉例而言，中間層320與420不含有第一摻雜磊晶層310以及410的摻雜物，或者中間層320與420的摻雜濃度低於第一摻雜磊晶層310以及410的摻雜濃度。
於部分實施方式中，第一摻雜磊晶層310以及410、中間層320與420以及第二摻雜磊晶層330以及430具有相同的晶體結構，其為面心立方(face-centered cubic；FCC)晶體結構，又稱為閃鋅礦(Zinc blende)結構。於部分實施方式中，基板210具有一(001)表面，而第一摻雜磊晶層310以及410、中間層320與420以及第二摻雜磊晶層330以及430在基板210的(001)表面上的長晶方向為[001]。在其他部分實施方式中，基板210具有一(111)表面，而第一摻雜磊晶層310以及410、中間層320與420以及第二摻雜磊晶層330以及430在基板210的(111)表面上的長晶方向為[111]。
於部分實施方式中，第一摻雜磊晶層310以及410、中間層320與420以及第二摻雜磊晶層330以及430由適當的沉積製程而形成，例如化學氣相沉積(chemical vapor deposition；CVD)、低壓化學氣相沉積(low pressure CVD；LPCVD)、常壓化學氣相沉積(atmospheric pressure CVD；APCVD)、超高真空化學氣相沉積(ultrahigh vacuum pressure CVD；UHVCVD)、原子層沉積(atomic layer deposition；ALD)、分子層沉積(molecular layer deposition；MLD)、電漿增強化學氣相沉積法(plasma enhanced CVD；PECVD)、金屬有機化學氣相沉積(metal-organic CVD；MOCVD)、分子束磊晶(molecular beam epitaxy；MBE)、濺鍍沉積(sputter deposition)、相似方法或其組合。第一摻雜磊晶層310以及410與第二摻雜磊晶層330以及430的厚度可大於20奈米，此足夠的厚度能提供低錯位密度(dislocation density)，例如小於108cm-2。中間層320與420的厚度在大約10奈米至大約20奈米的範圍內，在後續階段中，此厚度能使中間層320與420容易被氧化而能提供足夠的隔絕效果。
參照第3圖，方法100進行到步驟104，其中圖案化第一摻雜磊晶層310和410、中間層320和420以及第二摻雜磊晶層330和430，以形成鰭式結構FS1和FS2。在部分實施例中，在第二摻雜磊晶層330和430上方形成圖案化遮罩M1，以定義將要形成穿隧式場效電晶體的位置。進行蝕刻製程以移除未被圖案化遮罩M1覆蓋的第一摻雜磊晶層310和410、中間層320和420、以及第二摻雜磊晶層330和430的部分，進而形成鰭式結構FS1和FS2。
於此，第一摻雜磊晶層310和410的剩餘部分分 別稱為第一摻雜磊晶層310'和410'。第一摻雜磊晶層310'和410'具有底部分310B和410B以及突出部分310P和410P，突出部分310P和410P分別從底部分310B和410B向上突出的。中間層320和420的剩餘部分分別稱為中間層320'和420'。第二摻雜磊晶層330和430的剩餘部分分別稱為第二摻雜磊晶層330'和430'。突出部分310P、中間層320'和第二摻雜磊晶層330'的組合稱為鰭式結構FS1。類似地，突出部分410P、中間層420'和第二摻雜磊晶層430'的組合被稱為鰭式結構FS2。
如圖所示，鰭式結構FS1具有長邊LS1和比長邊LS1短的短邊SS1，鰭式結構FS2具有長邊LS2和比長邊LS2短的短邊SS2。短邊SS1連接相對的長邊LS1，短邊SS2連接相對的長邊LS2。在這種情況下，長邊LS1和短邊SS1也可以稱為側壁。在基板210在其頂部具有(001)切面的部分實施方事中，可以進行圖案化製程，使得鰭式結構FS1的長邊LS1和短邊SS1在不同的晶向上取向。這種不同的晶向可能導致三五族化合物在長邊LS1上的長晶速率不同於三五族化合物在短邊SS1上的長晶速率。舉例而言，鰭式結構FS1的長邊LS1和短邊SS1分別具有[110]和[1-10]方向。舉例而言，在部分實施方式中，長邊LS1沿(110)晶面延伸，短邊SS1沿(1-10)晶面延伸。在部分其他實施方式中，長邊LS1沿(1-10)晶面延伸，短邊SS1沿(110)晶面延伸。類似地，進行圖案化製程，使得鰭式結構FS1的長邊LS2和短邊SS2在不同的晶向上取向，例如[110]和 [1-10]方向。
在基板210在其頂部具有(111)切面的部分實施方式中，可以進行圖案化，使得鰭式結構FS1和FS2在不同的晶向上取向。這種不同的晶向可能導致長邊LS1上的三五族化合物的長晶速率不同於短邊SS1上的長晶速率。舉例而言，鰭式結構FS1的長邊LS1和短邊SS1具有[-110]和[11-2]方向。舉例而言，在部分實施方式中，長邊LS1沿(-110)晶面延伸，短邊SS1沿(11-2)晶面延伸。在部分其他實施方式中，長邊LS1沿(11-2)晶面延伸，短邊SS1沿(-110)晶面延伸。類似地，進行圖案化，使得鰭式結構FS1的長邊LS2和短邊SS2在不同的晶向上取向，例如[-110]和[11-2]方向。
參見第4A圖和第4B圖，方法100進行到步驟106，其中本質半導體層340形成在鰭式結構FS1的相對長邊LS1上，並且本質半導體層440形成在鰭式結構FS2的相對長邊LS2上。第4A圖和第4B圖中所示結構的上視圖，其中省略了一些元件(例如，省略了前述的圖案化遮罩M1和底部分310B和410B)。本質半導體層340和440垂直於基板210的水平表面。如第4B圖所示，本質半導體層340和440分別覆蓋鰭式結構FS1和FS2的長邊LS1和LS2，而本質半導體層340和440露出鰭式結構FS1和FS2的短邊SS1和SS2。
本質半導體層340和440可以由具有閃鋅礦晶體結構的低能隙三五族半導體形成。舉例而言，本質半導體 層340和440可以由GaxIn1-xAsySb1-y組成，其中x在大約0到大約1的範圍內，並且y在從大約0到大約1的範圍內。本質半導體層340和440可以由與穿隧式場效電晶體的汲極層相同的材料製成，例如分別是第一摻雜磊晶層310'和410'。舉例而言，在部分實施方式中，本質半導體層340可以是非刻意摻雜的InAs層，其連接n型穿隧式場效電晶體的n型摻雜InAs層310'和GaSb層330'。在部分實施方式中，本質半導體層440可以是GaSb層，其連接p型穿隧式場效電晶體的GaSb層410'和InAs層430'的。不應以此限制本實施方式的範圍。於此，本質半導體層340和440的厚度可以在1至6奈米的範圍內，例如3奈米。此選擇的本質半導體層340和440的厚度能以擴大主動區並優化穿隧效應。在部分實施方式中，本質半導體層340和440為非刻意摻雜的，舉例而言，本質半導體層340和440內沒有刻意放置的摻雜物，而是因製程污染引起的摻雜。舉例而言，本質半導體層340和440為非刻意摻雜的(NID)半導體層，因此本質半導體層340和440沒有第一摻雜磊晶層310和410以及第二摻雜磊晶層330和430中的摻雜物。或者，本質半導體層340 440和440可以摻雜有p型或n型，並且摻雜濃度低於第一摻雜磊晶層310和410以及第二摻雜晶層330和430的摻雜濃度。舉例而言，本質半導體層340和440的摻雜濃度低於大約1013/cm3。
在部分實施方式中，本質半導體層340和440的形成可以依賴於不同晶面上的不同長晶速率。舉例而言， 在部分實施方式中，本質半導體層在長邊LS1和LS2上的長晶速率不同於其在短邊SS1和SS2上的長晶速率，因而在長邊LS1和LS2上的本質半導體層可以比在短邊SS1和SS2上的本質半導體層更厚。在部分實施方式中，本質半導體層可以不在鰭式結構FS1和FS2的短邊SS1和SS2上生長，而是在鰭式結構FS1和FS2的長邊LS1和LS2上生長。因此，本質半導體層340和440沒有覆蓋鰭式結構FS1和FS2的短邊SS1和SS2，因此鰭式結構FS1和FS2的短邊SS1和SS2外露而有助於隨後的氧化製程。
在部分實施方式中，本質半導體層340和440的形成可以依賴於不同晶面處的不同蝕刻速率。舉例而言，本質半導體層在短邊SS1和SS2上的蝕刻速率與在長邊LS1和LS2上的蝕刻速率不同。舉例而言，鰭式結構FS1和FS2的長邊LS1和LS2上的本質半導體層具有比鰭式結構FS1和FS2的短邊SS1和SS2上的本質半導體層更高的抗蝕刻性，使得短邊SS1和SS2上的本質半導體層可以通過蝕刻製程而移除，而長邊LS1和LS2上的本質半導體層(稱為本質半導體層340和440)保留。
在本質半導體層形成在長邊LS1和LS以及短邊SS1和SS2上的部分其他實施方式中，鰭式結構FS1和FS2以及鰭式結構FS1和FS2的長邊LS1和LS2上的本質半導體層被遮蔽，並進行蝕刻製程以移除本質半導體層的未被遮蔽的部分。因此，移除了本質半導體層的未被遮蔽的部分(例如短邊SS1和SS2上的本質半導體層)，而長邊LS1和 LS2上的本質半導體層(稱為本質半導體層340和440)仍然保留。在部分其他實施方式中，進行數位蝕刻(digital etching)以移除短邊SS1和SS2上的本質半導體層。數位蝕刻是一循環過程，其包括至少一次重複氧化步驟和蝕刻步驟，以移除氧化層。每個蝕刻步驟可以移除例如大約2奈米的厚度。
本質半導體層340和440可以通過沉積本質半導體層並且選擇性地蝕刻本質半導體層來形成，而使本質半導體層340和440露出鰭式結構FS1和FS2的短邊SS1和SS2。在部分實施方式中，本質半導體層340和440可以通過合適的沉積製程形成，例如化學氣相沉積(CVD)、低壓CVD(LPCVD)、常壓CVD(APCVD)、超高真空CVD(UHVCVD)、原子層沉積(ALD)、分子層沉積(MLD)、等離子體增強CVD(PECVD)、金屬有機CVD(MOCVD)、分子束磊晶(MBE)、濺射沉積等或其組合。
第4C圖示出了根據本揭露的部分實施方式的穿隧式場效電晶體的中間結構。在本實施方式中，除了覆蓋鰭式結構FS1的長邊LS1之外，本質半導體層340還可以覆蓋一個短邊SS1，並且露出另一個短邊SS1以便於隨後的氧化處理。類似地，除了覆蓋鰭式結構FS2的長邊LS2之外，本質半導體層440還可以覆蓋一個短邊SS2，並露出另一個短邊SS2以便於隨後的氧化處理。
參考第5圖，方法100進行到步驟108，其中在形成本質半導體層340和440之後進行氧化處理或製程。此 氧化處理可以使用O2、O3或H2O的氣體或氧電漿。藉由氧化處理，氧滲透到中間層320'和420'的外露表面，並且中間層320'和420'被氧化成絕緣層320"和420"。舉例而言，可以氧化含鋁半導體(例如AlSb)，這會形成氧化鋁(AlOx)，其是非晶狀的而不是結晶的。在部分實施方式中，中間層320'和420'具有比層體310'、330'、340、410'、430'和440的氧化速率更高的氧化速率，使得中間層320'和420'被氧化成絕緣體，而層體310'、330'、340、410'、430'和440則沒有。絕緣層320"和420"是具有比含鋁半導體(例如AlSb)更大能隙的絕緣體，因此，相較於含鋁半導體中間層320'和420'，絕緣層320"和420"可以減少斷止狀態電流(off-state current)，進而可抑制穿隧式場效電晶體的漏電流。在氧化之後，可以選擇性地對半導體(例如InAs 310P、GaSb 330'、GaSb 410P和InAs 430')進行表面處理，藉以降低界面陷阱密度(interface trap density；Dit)。
參考第6A圖至第6C圖，方法100進行到步驟110，形成閘極介電層350和450，其分別圍繞鰭式結構FS1和FS2。第6B圖是沿第6A圖的6B-6B線的剖面圖。第6C圖是沿第6A圖的6C-6C線的剖面圖。閘極介電層350和450通過原子層沉積(ALD)、化學氣相沉積(CVD)、金屬有機CVD(MOCVD)、物理氣相沉積(PVD)、熱氧化或其組合形成。閘極介電層350和450例如是二元或三元高介電常數膜，例如HfO、LaO、AlO、ZrO、TiO、Ta2O5、 Y2O3、STO、BTO、BaZrO、HfZrO、HfLaO、HfTaO、HfTiO等或其組合。在部分實施方式中，閘極介電層350和450由相同的材料形成。或者，閘極介電層350和450由不同材料形成。在部分實施方式中，閘極介電層350或450的厚度可以在大約1奈米至大約10奈米的範圍內，例如，大約2奈米。在部分實施方式中，閘極介電層是多層結構，其具有高介電常數的介電層以及其下方的高溫氧化物(high temperature oxide；HTO)層。高溫氧化物層將有助於降低閘極介電質和鰭式結構的半導體之間的界面能態密度(interfacial density of states；Dit)。
於此，由於鰭式結構FS1的短邊SS1沒有被本質半導體層340覆蓋，所形成的圍繞鰭式結構FS1的閘極介電層350可以與短邊SS1接觸。鰭式結構FS2的配置類似於鰭式結構FS1，在此不再重複。
參考第7A圖至第7C圖，方法100進行到步驟112，形成金屬閘極層360，其圍繞鰭式結構FS1和介電層350，並且形成金屬閘極層460，其圍繞鰭式結構FS2和介電層450。第7B圖是沿第7A圖的7B-7B線的剖面圖。第7C圖是沿第7A圖的7C-7C線的剖面圖。在部分實施例中，在第一區域210A中，金屬閘極層360以毯覆方式形成於閘極介電層350上方，以形成n型穿隧式場效電晶體。在第二區域210B中，金屬閘極層460以毯覆方式形成於介電層450上方，以形成p型穿隧式場效電晶體。金屬閘極層360和460可以包括不同的功函數金屬，以分別為n型和p型穿隧式場 效電晶體提供合適的功函數。金屬閘極層360和460的示例材料包括鎢、氮化鈦等或其組合。藉由原子層沉積、濺射或其他製程，可沉積金屬閘極層360和460。在部分實施方式中，金屬閘極層360和460的厚度可以在大約1奈米至大約5奈米的範圍內，例如大約2奈米。
第7D圖是第7A圖中所示結構的上視圖。金屬閘極層360圍繞鰭式結構FS1的長邊LS1和短邊SS1。鰭式結構FS2的配置類似於鰭式結構FS1。舉例而言，金屬閘極層460圍繞鰭式結構FS1的長邊LS2和短邊SS2。在鰭式結構FS1的短邊SS1沒有被本質半導體層340覆蓋的部分實施方式中，閘極介電層350包含短部分350SP，每個短部分350SP具有相對兩側，其分別與鰭式結構FS1的短邊SS1以及金屬閘極層360接觸。相反地，閘極介電層350包含長部分350LP，每個長部分350LP具有相對兩側，其分別與本質半導體層340和金屬閘極層360接觸。類似地，閘極介電層450包括短部分450SP，每個短部分450SP具有相對兩側，其分別與鰭式結構FS1的短邊SS2和金屬閘極層460接觸。相反地，閘極介電層450包括長部分450LP，每個長部分450LP具有相對兩側，其分別與本質半導體層440和金屬閘極層460接觸。
第7E圖示出了根據本揭露的部分實施方式的穿隧式場效電晶體的中間結構。如第7E圖所示，第7E圖所示的實施方式類似於第7D圖所示的實施方式，第7E圖所示的實施方式與第7D圖所示的實施方式差別在於閘極介電層 350和450的短部分350SP和450SP分別與本質半導體層340和440接觸。在所示實施方式中，閘極介電層350的較上部的一個短部分350SP與本質半導體層340接觸，而不與鰭式結構FS1的上部短邊SS1接觸，而閘極介電層350較下部的一個短部分350SP與鰭式結構FS1的下部短邊SS1接觸。類似地，閘極介電層450的較上部的一個短部分450SP與本質半導體層440接觸，而不與鰭式結構FS2的上部短邊SS2接觸，而閘極介電層450的較下部的一個短部分450SP中與鰭式結構FS2的下部短邊SS2接觸。
參考第8圖，方法100進行到步驟114，其中分別在金屬閘極層360和460上形成填充金屬層370和470。填充金屬層370和470可以由例如W、Co、Al、Cu等或其組合形成。在部分實施方適中，填充金屬層370和470由相同的材料形成。或者，填充金屬層370和470可由不同材料形成。
參考第9圖，方法100進行到步驟116，其中進行化學機械研磨(chemical-mechanical polish；CMP)製程以移除在鰭式結構FS1上方的閘極介電層350、金屬閘極層360和填充金屬層370的一部分，並且移除鰭式結構FS2上方的閘極介電層450、金屬閘極層460和填充金屬層470的一部分。進行化學機械研磨製程直到露出第二摻雜磊晶層330'和430'，如第9圖所示。
在部分實施方式中，化學機械研磨製程使填充金屬層370的頂表面與第二摻雜磊晶層330'實質齊平。類似 地，化學機械研磨製程使填充金屬層470的頂表面與第二摻雜磊晶層430'的頂表面實質齊平。
參考第10圖，方法100進行到步驟118，其中溝槽DT1和DT2形成在填充金屬層370和470中。溝槽DT1可以進一步延伸穿過閘極介電層350、金屬閘極層360以及第一摻雜磊晶層310'的底部分310B至基板210。類似地，溝槽DT2可以進一步延伸穿過介電層450、金屬閘極層460和第一摻雜磊晶的410'的底部分410B至基板210。藉由溝槽DT1和DT2的配置，圍繞鰭式結構FS1的金屬閘極層360和填充金屬層370的部分分離於圍繞鰭式結構FS2的金屬閘極層460和填充金屬層470的部分。
溝槽DT1和DT2可以使用合適的蝕刻製程形成，例如濕式蝕刻、乾式蝕刻或其組合。在部分實施方式中，蝕刻製程導致填充金屬層370、金屬閘極層360和閘極介電層350的頂表面低於第二摻雜磊晶層330'的頂表面。類似地，蝕刻製程導致填充金屬層470、金屬閘極層460和閘極介電層450的頂表面低於第二摻雜磊晶層430'的頂表面。也就是說，閘極介電層350和450、金屬閘極層360和460以及填充金屬層370和470被進一步拉回，使得鰭式結構FS1和FS2分別突出於閘極介電層350和450、金屬閘極層360和460以及填充金屬層370和470。
參照第11圖，方法100進行到步驟120，其中溝槽DT1和DT2填充有介電層220，使得分別圍繞鰭式結構FS1和FS2的金屬閘極層360和460是彼此電性隔離的，且 分別圍繞鰭式結構FS1和FS2的填充金屬層370和470是彼此電性隔離的。於此，藉由使用例如化學氣相沉積(CVD)、物理氣相沉積(PVD)、旋塗等或其組合，介電層220填滿至溢出溝槽DT1和DT2。此填滿至溢出溝槽DT1和DT2填充金屬層370和470、金屬閘極層360和460、閘極介電層350和450、第二摻雜磊晶層330'和430'以及第一摻雜磊晶層310'和410'被介電層220覆蓋。
參考第12A圖和第12B圖，方法100進行到步驟122，其中在介電層220中形成源極/汲極接觸230。於此，在介電層220中形成開口220O，以露出鰭式結構FS1和鰭式結構FS2，以導電材料填充開口220O，進而形成源極/汲極接觸230。具體地，開口220O露出第二摻雜磊晶層330'和430'，使得源極/汲極接觸230可與第二摻雜磊晶層330'和430'接觸。於此，開口220O具有與鰭式結構FS1和FS2的尺寸類似的尺寸，使得本質半導體層340和440的頂表面被介電層220覆蓋。可以進行更多的穿隧式場效電晶體製程以形成各種特徵，例如接觸/通孔、層間介電層、內連接金屬層以及鈍化層等等。通過上述步驟，n型穿隧式場效電晶體300和p型穿隧式場效電晶體400可以經由一個整合製程而形成。
n型第一摻雜磊晶層310'和p型第二磊晶層330'可分別稱為n型穿隧式場效電晶體300的n型汲極層和p型源極層。在n型穿隧式場效電晶體300的部分實施方式中，從p型源極層330'到本質半導體層340發生穿隧。於此， 電子從p型源極層330'穿隧到本質半導體層340，然後電流垂直流過至汲極層310'。類似地，p型第一摻雜磊晶層410'和n型第二磊晶層430'可分別稱為p型穿隧式場效電晶體400的p型汲極層和n型源極層。在p型穿隧式場效電晶體400的部分實施方式中，從n型源極層430'到本質半導體層440發生穿隧。在部分實施方式中，本質半導體層340和440的頂表面分別低於源極/汲極接觸230的底表面，使得本質半導體層340和440不接觸具有源極/汲極接觸230，其中本質半導體層340和440與其汲極層(例如，第一摻雜磊晶層310'和410')的材料相同。
在部分實施方式中，由於絕緣層320"和420"的存在，汲極層和源極層之間的漏電流受到抑制，例如當電壓未施加到金屬閘極層360時。換句話說，絕緣層320"和420"有助於減小穿隧式場效電晶體300和400的斷止狀態電流。
第13圖是根據本揭露的部分實施方式的穿隧式場效電晶體的剖面圖。本文描繪了n型穿隧式場效電晶體300'和p型穿隧式場效電晶體400'。在部分實施方式中，第一摻雜磊晶層310'由p型摻雜物摻雜，例如但不限於鎂、鈣、鋅、鈹、碳及其組合。第二摻雜磊晶層330'由n型摻雜物摻雜，例如但不限於矽、氧或其組合。p型第一摻雜磊晶層310'和n型第二磊晶層330'可分別稱為n型穿隧式場效電晶體300'的p型源極層和n型汲極層。
在部分實施方式中，第一摻雜磊晶層410'摻雜 有n型摻雜物，例如但不限於矽、氧或其組合。第二摻雜磊晶層430'由p型摻雜物摻雜，例如但不限於鎂、鈣、鋅、鈹、碳及其組合。n型第一摻雜磊晶層410'和p型第二磊晶層430'可分別稱為p型穿隧式場效電晶體400'的n型源極層和p型汲極層。
如前所述，第一摻雜磊晶層310'和410'以及第二摻雜磊晶層330'和430'由具有閃鋅礦晶體結構的三五族半導體形成。舉例而言，第一摻雜磊晶層310'和410'以及第二摻雜磊晶層330'和430'由GaxIn1-xAsySb1-y組成，其中x在大約0到大約1的範圍內，並且y在大約0到大約1的範圍內。於此，第一摻雜磊晶層310'中的x和y與第二摻雜磊晶層330'中的x和y不同。第一摻雜磊晶層410'中的x和y與第二摻雜磊晶層430'中的x和y不同。在進一步的實施方式中，第一摻雜磊晶層310'可以由GaSb製成，而第二摻雜磊晶層330'可以由InAs製成。在部分實施方式中，第一摻雜磊晶層410'可以由InAs製成，而第二摻雜磊晶層430'可以由GaSb製成。第一摻雜磊晶層310'和410'以及第二摻雜磊晶層330'和430'可以分別具有大於20奈米的厚度。
本質半導體層340和440可以由與穿隧式場效電晶體300'和400'的汲極層相同的材料製成，其中穿隧式場效電晶體300'和400'的汲極層例如為第二摻雜磊晶層330'和430'。具體而言，本質半導體層340和440可以由GaxIn1-xAsySb1-y製成，其中x在大約0至大約1的範圍內，並且y在大約0至大約1的範圍內。舉例而言，本質半導體層 340可以由InAs製成。舉例而言，本質半導體層440可以由GaSb製成。本實施方式的範圍不以此為限。
在本實施方式中，開口220O的尺寸大於鰭式結構FS1和FS2的尺寸，使得本質半導體層340和440的頂表面通過開口220O露出，而源極/汲極接觸230更接觸本質半導體層340和440。本揭露的其他實施方式類似於第12A圖的實施方式，並在此不再重複。
第14圖是根據本揭露的部分實施方式的積體電路的剖面圖。反相器500包括第12A圖中的上述n型穿隧式場效電晶體300和第13圖中的p型穿隧式場效電晶體400'。金屬閘極層360和460互相電性連接，並且n型穿隧式場效電晶體300的汲極層(即第一摻雜磊晶層310')連接到p型穿隧式場效電晶體400'的源極層(即第一摻雜磊晶層410')，以形成反相器500。如上所述，在部分實施方式中，本質半導體層340的頂表面低於源極/汲極接觸230的底表面，使得本質半導體層340不與源極/汲極接觸230接觸。在部分實施方式中，本質半導體層440的頂表面可以與源極/汲極接觸230接觸。
於此，n型穿隧式場效電晶體300和p型穿隧式場效電晶體400'可以通過整合製程形成，從而降低了製程成本。舉例而言，第一摻雜磊晶層310'和410'可以由相同的材料形成，例如InAs，並且摻雜有n型摻雜物。第二摻雜磊晶層330'和430'可以由相同的材料形成，例如GaSb，並且摻雜有p型摻雜物。本質半導體層340'和440'可以由不同 的材料製成。舉例而言，本質半導體層340'和440'可以分別由InAs和GaSb製成。
在部分其他實施方式中，第13圖中的n型穿隧式場效電晶體300'和第12A圖中的p型穿隧式場效電晶體400可以通過整合製程形成，從而降低了製程成本。
基於以上討論，可以看出本揭露提供了多個優點。然而，應該理解，其他實施方式可以提供額外的優點，並且並非所有優點都必須在此揭露，並且並非所有實施方式都需要特別的優點。本揭露的優點之一是藉由採用氧化處理在源極層和汲極層之間形成絕緣層，可以有效地減少漏電流。本揭露的另一個優點是藉由設計具有垂直本質半導體層的穿隧式場效電晶體，可以改善每個晶片面上的導通電流。本揭露的又一個優點是，由於長晶速率和蝕刻速率對不同晶面的依賴性，本質半導體層可以自然地形成在鰭式結構的相對兩側上。
根據本揭露之部分實施方式，裝置包含第一半導體層、第二半導體層以及本質半導體層。第二半導體層位於第一半導體層上。第一半導體層與第二半導體層是相對的導電型態。第二半導體層包含第一側壁以及第二側壁，其實質垂直且大於第一側壁。本質半導體層接觸第二半導體層的第二側壁與第一半導體層。
於部分實施方式中，第一半導體層包含一底部分以及一突出部分。突出部分突出於底部分，且突出部分包含第三側壁與第四側壁，第四側壁實質垂直且大於第三側 壁，其中本質半導體層接觸第四側壁。
於部分實施方式中，第二半導體層的第一側壁實質沒有被本質半導體覆蓋。
於部分實施方式中，第二半導體層的第一側壁與第二側壁之一者實質沿著(110)晶面延伸。
於部分實施方式中，第二半導體層的第一側壁與第二側壁之另一者實質沿著(1-10)晶面延伸。
於部分實施方式中，第二半導體層的第一側壁與第二側壁之一者實質沿著(-110)晶面延伸。
於部分實施方式中，第二半導體層的第一側壁與第二側壁之另一者實質沿著(11-2)晶面延伸。
於部分實施方式中，裝置更包含介電層，位於第一半導體層與第二半導體層之間。介電層包含金屬元素，且第一半導體層、第二半導體層以及本質半導體層是實質沒有介電層的金屬元素。
於部分實施方式中，裝置更包含介電層，位於第一半導體層與第二半導體層之間。介電層包含氧化鋁。
於部分實施方式中，第一半導體層與第二半導體層是由不同的三五族化合物材料組成。
於部分實施方式中，第一半導體層與第二半導體層是的三五族化合物材料具有閃鋅礦晶體結構。
根據本揭露之部分實施方式，裝置包含基板、鰭式結構以及本質半導體層。鰭式結構位於基板上，鰭式結構包含第一半導體層、位於第一半導體層上的介電層、位於 介電層上的第二半導體層。第一半導體層與第二半導體層是相對的導電型態。本質半導體層延伸自第一半導體層越過介電層至第二半導體層。
於部分實施方式中，鰭式結構具有第一側壁以及第二側壁，其實質垂直且大於第一側壁。第一側壁實質沒有被本質半導體層覆蓋。
於部分實施方式中，介電層包含一三族元素，第一半導體層、本質半導體層以及第二半導體層不具有該三族元素。
於部分實施方式中，介電層是該三族元素的氧化物。
於部分實施方式中，裝置更包含源極/汲極接觸，其與第二半導體層以及本質半導體層接觸。
於部分實施方式中，裝置更包含源極/汲極接觸，其與第二半導體層接觸，其中本質半導體層的頂表面低於源極/汲極接觸的底表面。
根據本揭露之部分實施方式，方法包含以下步驟。形成第一型半導體層。在第一型半導體層上，形成一半導體中間層。在半導體中間層上，形成第二型半導體層。蝕刻第一型半導體層、半導體中間層以及第二型半導體層，以形成鰭式結構。進行氧化處理，以氧化半導體中間層。
於部分實施方式中，方法更包含在進行氧化處理之前，在鰭式結構的側壁上，形成本質半導體層。
於部分實施方式中，在氧化處理的過程中，半 導體中間層的氧化速率比第一型半導體層的氧化速率、第二型半導體層的氧化速率以及本質半導體層的氧化速率快。
以上概述多個實施方式之特徵，該技術領域具有通常知識者可較佳地了解本揭露之多個態樣。該技術領域具有通常知識者應了解，可將本揭露作為設計或修飾其他程序或結構的基礎，以實行實施方式中提到的相同的目的以及/或達到相同的好處。該技術領域具有通常知識者也應了解，這些相等的結構並未超出本揭露之精神與範圍，且可以進行各種改變、替換、轉化，在此，本揭露精神與範圍涵蓋這些改變、替換、轉化。
210‧‧‧基板
220‧‧‧介電層
220O‧‧‧開口
230‧‧‧源極/汲極接觸
300‧‧‧n型穿隧式場效電 晶體
310'‧‧‧第一摻雜磊晶層
310B‧‧‧底部分
310P‧‧‧突出部分
320"‧‧‧絕緣層
330'‧‧‧第二摻雜磊晶層
340‧‧‧本質半導體層
350‧‧‧閘極介電層
360‧‧‧金屬閘極層
370‧‧‧填充金屬層
400‧‧‧p型穿隧式場效電 晶體
410'‧‧‧第一摻雜磊晶層
410B‧‧‧底部分
410P‧‧‧突出部分
420"‧‧‧絕緣層
430'‧‧‧第二摻雜磊晶層
440‧‧‧本質半導體層
450‧‧‧閘極介電層
460‧‧‧金屬閘極層
470‧‧‧填充金屬層
FS1、FS2‧‧‧鰭式結構
LS1、LS2‧‧‧長邊

Claims (1)

  1. 一種穿隧式場效電晶體，包含：一第一半導體層；一第二半導體層，位於該第一半導體層上，其中該第一半導體層與該第二半導體層是屬於相對的導電型態，且該第二半導體層包含一第一側壁以及一第二側壁，該第二側壁實質垂直於且大於該第一側壁；以及一本質半導體層，接觸該第二半導體的該第二側壁與該第一半導體層。
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US10505025B1 (en) 2019-12-10
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US20200098898A1 (en) 2020-03-26

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