TW202008531A - 封裝結構 - Google Patents

封裝結構 Download PDF

Info

Publication number
TW202008531A
TW202008531A TW108102529A TW108102529A TW202008531A TW 202008531 A TW202008531 A TW 202008531A TW 108102529 A TW108102529 A TW 108102529A TW 108102529 A TW108102529 A TW 108102529A TW 202008531 A TW202008531 A TW 202008531A
Authority
TW
Taiwan
Prior art keywords
layer
semiconductor die
insulating
conductive
isolation
Prior art date
Application number
TW108102529A
Other languages
English (en)
Inventor
陳憲偉
陳明發
葉松峯
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202008531A publication Critical patent/TW202008531A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/24147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92124—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92224—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一種封裝結構包括至少一個第一半導體晶粒、絕緣密封體、隔離層及重佈線層。所述至少一個第一半導體晶粒具有半導體基板及安置在半導體基板上的導電杆。絕緣密封體部分地密封第一半導體晶粒，其中導電杆具有被絕緣密封體環繞的第一部分及從絕緣密封體凸出的第二部分。隔離層安置在絕緣密封體上且環繞導電杆的第二部分。重佈線層安置在第一半導體晶粒及隔離層上，其中重佈線層電性連接到第一半導體晶粒的所述導電杆。

Description

封裝結構
本發明實施例是有關於一種封裝結構，且特別是有關於一種整合扇出型封裝結構。
半導體器件用於各種電子應用中，例如個人電腦、手機、數位照相機及其他的電子設備。半導體器件通常是通過以下步驟來製作：在半導體基板之上依序沉積絕緣材料層或介電材料層、導電材料層及半導體材料層，並使用光阻來將各種材料層圖案化以在其上形成電路構件及元件。諸多半導體積體電路通常被製造在單個半導體晶圓上。可在晶圓級下對晶圓的晶粒進行處理及封裝，且已開發出各種用於進行晶圓級封裝的技術。
本發明實施例的一種封裝結構，包括至少一個第一半導體晶粒、絕緣密封體、隔離層以及重佈線層。所述至少一個第一半導體晶粒具有半導體基板及安置在所述半導體基板上的導電杆。所述絕緣密封體部分地密封所述第一半導體晶粒，其中所述導電杆具有被所述絕緣密封體環繞的第一部分及從所述絕緣密封體凸出的第二部分。所述隔離層安置在所述絕緣密封體上且環繞所述導電杆的所述第二部分。所述重佈線層安置在所述第一半導體晶粒及所述隔離層上，所述重佈線層電性連接到所述第一半導體晶粒的所述導電杆。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同實施例或實例。下文描述元件和佈置的特定實例以簡化本公開。當然，這些元件和佈置僅為實例且並不意圖為限制性的。舉例來說，在以下描述中，第一特徵形成在第二特徵上方或上可包含其中第一特徵與第二特徵直接接觸地形成的實施例，且還可包含其中額外特徵可形成在第一特徵與第二特徵之間以使得第一特徵與第二特徵可不直接接觸的實施例。另外，本公開可在各種實例中重複附圖標號和/或字母。這種重複是出於簡化和清楚的目的，且本身並不規定所論述的各種實施例和/或配置之間的關係。
另外，為了便於描述，在本文中可使用空間相對術語，如“在…之下”、“在…下方”、“下部”、“在…上方”、“上部”等，以描述如圖式中所說明的一個元件或特徵與另一（一些）元件或特徵的關係。除圖式中所描繪的定向以外，空間相對術語意欲涵蓋器件在使用或操作中的不同定向。裝置可以其它方式定向（旋轉90度或處於其它定向），且本文中所使用的空間相對描述詞同樣可相應地進行解釋。
還可包含其它特徵和過程。舉例來說，可包含測試結構以說明驗證測試3D封裝或3DIC器件。測試結構可包含例如形成於重佈線層中或基板上的測試墊，所述重佈線層或基板允許測試3D封裝或3DIC、使用探針和/或探針卡等等。驗證測試可在中間結構以及最終結構上執行。另外，本文中所公開的結構和方法可以與併入有已知良好晶粒的中間驗證的測試方法結合使用以增加產率並降低成本。
圖1至圖9是根據本文的一些示例性實施例的製作封裝結構的方法的各個階段的示意性剖視圖。參考圖1，設置載體102，載體102上塗布有緩衝層104。在一個實施例中，載體102可以是用於承載半導體晶圓或經重構的晶圓的玻璃載體或任何適合的載體，製作封裝結構的方法會用到所述半導體晶圓或經重構的晶圓。
在一些實施例中，緩衝層104包括脫膠層104A及介電層104B，其中脫膠層104A位於載體102與介電層104B中間。在某些實施例中，脫膠層104A安置在載體102上，且脫膠層104A的材料可以是適合於結合載體102及將載體102從上方的層（例如，介電層104B）或可從安置在脫膠層104A上的任何晶片剝離的任何材料。在一些實施例中，脫膠層104A可包括釋放層（例如，光熱轉換（light-to-heat conversion，“LTHC”）層）或黏合層（例如，紫外線固化型黏合層或熱固化型黏合層）。在一些實施例中，可在脫膠層104A上方形成介電層104B。介電層104B可由介電材料製成，例如苯環丁烷（benzocyclobutene，“BCB”）、聚苯並噁唑（polybenzoxazole，“PBO”）或任何其他適合的聚合物類介電材料。
注意的是，載體102的材料、脫膠層104A的材料及介電層104B的材料並不僅限於所述實施例的說明。在一些替代實施例中，可視情況省略介電層104B；換句話說，可在載體102上僅形成脫膠層104A。在某些實施例中，可在脫膠層104A上直接形成晶粒貼合膜（未示出）以用於貼合到上方的組件。
在設置緩衝層104之後，在緩衝層104上且在載體102之上形成多個貫穿絕緣層孔108，並在緩衝層104上設置多個第一半導體晶粒106A。在一些實施例中，貫穿絕緣層孔108是整合扇出型（integrated fan-out，“InFO”）穿孔。在一個實施例中，形成貫穿絕緣層孔108包括形成具有開口的罩幕圖案（未示出），然後通過電鍍或沉積來形成金屬材料（未示出）以填充所述開口，並移除罩幕圖案以在緩衝層104上形成貫穿絕緣層孔108。罩幕圖案的材料可包括正型光阻或負型光阻。在一個實施例中，貫穿絕緣層孔108的材料可包括金屬材料，例如銅或銅合金等。然而，本發明實施例並不僅限於此。
在替代實施例中，可通過以下操作形成貫穿絕緣層孔108：在緩衝層104上形成晶種層（未示出）；形成具有開口的罩幕圖案，使得暴露出晶種層的一些部分；通過鍍覆來在晶種層的暴露出的部分上形成金屬材料以形成貫穿絕緣層孔108；移除罩幕圖案；且然後移除晶種層的被貫穿絕緣層孔108暴露出的部分。舉例來說，晶種層可以是鈦/銅複合層。為簡潔起見，圖1中僅繪示四個貫穿絕緣層孔108。然而，應注意，貫穿絕緣層孔108的數目並不僅限於此，且可基於要求進行選擇。
如圖1中所示，可將一個或多個第一半導體晶粒106A拾起並放置在緩衝層104上。在某些實施例中，第一半導體晶粒106A具有主動表面AS及與主動表面AS相對的背側表面BS。舉例來說，可通過晶粒貼合膜DF將第一半導體晶粒106A的背側表面BS貼合到緩衝層104。通過使用晶粒貼合膜DF，確保第一半導體晶粒106A與緩衝層104之間更好地黏合。在示例性實施例中，僅說明了兩個第一半導體晶粒106A。然而，本發明實施例並不僅限於此。應注意，可基於產品要求來調整安置在緩衝層104上的第一半導體晶粒106A的數目。
在示例性實施例中，第一半導體晶粒106A中的每一者包括半導體基板106a-1、多個導電接墊106a-2、鈍化層106a-3、多個導電杆106a-4及保護層106a-5。如圖1中所示，所述多個導電接墊106a-2安置在半導體基板106a-1上。鈍化層106a-3形成在半導體基板106a-1之上，且具有部分地暴露出位於半導體基板106a-1上的導電接墊106a-2的開口。半導體基板106a-1可以是塊狀矽基板或絕緣體上矽（silicon-on-insulator，SOI）基板，且還包括形成在半導體基板106a-1中的主動元件（例如，電晶體等）且視情況包括被動元件（例如電阻器、電容器、電感器等）。導電接墊106a-2可以是鋁接墊、銅接墊或其他適合的金屬接墊。鈍化層106a-3可以是氧化矽層、氮化矽層、氮氧化矽層或由任何適合的介電材料形成的介電層。此外，在一些實施例中，在鈍化層106a-3之上視情況形成後鈍化層（未示出）。後鈍化層覆蓋鈍化層106a-3且具有多個接觸開口。後鈍化層的接觸開口部分地暴露出導電接墊106a-2。後鈍化層可以是苯環丁烷（BCB）層、聚醯亞胺層、聚苯並噁唑（PBO）層或由其他適合的聚合物形成的介電層。在一些實施例中，通過鍍覆在導電接墊106a-2上形成導電杆106a-4。在一些實施例中，在鈍化層106a-3上或在後鈍化層上形成保護層106a-5，且保護層106a-5覆蓋導電杆106a-4以保護導電杆106a-4。
在一些實施例中，當將一個以上的第一半導體晶粒106A放置在緩衝層104上時，可將第一半導體晶粒106A排列成陣列，且當第一半導體晶粒106A被排列成陣列時，可將貫穿絕緣層孔108劃分成群組。第一半導體晶粒106A的數目可對應於貫穿絕緣層孔108的群組的數目。在所示的實施例中，可在形成貫穿絕緣層孔108之後，將第一半導體晶粒106A拾起並放置在緩衝層104上。然而，本發明實施例並不僅限於此。在一些替代實施例中，可在形成貫穿絕緣層孔108之前，將第一半導體晶粒106A拾起並放置在緩衝層104上。
在一些實施例中，第一半導體晶粒106A可以從特殊應用積體電路（application-specific integrated circuit，ASIC）晶片、類比晶片（舉例來說，無線射頻晶片）、數位晶片（舉例來說，基頻晶片）、整合被動構件（integrated passive device，IPD）、電壓調節器晶片、感測器晶片、記憶體晶片等中選擇。本發明實施例並不僅限於此。
參考圖2A，在下一步驟中，在載體102上設置模具MD，從而覆蓋第一半導體晶粒106A及所述多個貫穿絕緣層孔108。在一些實施例中，模具MD可包括流道孔HR及貼合到模具MD的內表面的釋放膜RF。流道孔HR位於模具MD的一側上。在一些實施例中，釋放膜RF被按壓到第一半導體晶粒106A上以部分地覆蓋第一半導體晶粒106A。在某些實施例中，釋放膜RF還被按壓到貫穿絕緣層孔108上以部分地覆蓋貫穿絕緣層孔108。圖2B是圖2A中所示結構的俯視圖，其中出於說明目的，省略了模具MD、釋放膜RF及貫穿絕緣層孔108。如圖2B中所示，第一半導體晶粒106A位於緩衝層104上，且在形成絕緣密封體之前暴露出緩衝層104的頂表面。
參考圖3A，將絕緣材料110通過流道孔RH注入到模具MD中，以使得絕緣材料110部分地密封第一半導體晶粒106A及貫穿絕緣層孔108。圖3B是圖3A中所示結構的俯視圖，其中出於說明目的，省略模具MD、釋放膜RF及貫穿絕緣層孔108。如圖3B中所示，絕緣材料110是從模具MD的一側注入並擴散到緩衝層104上以覆蓋緩衝層104。在一些實施例中，絕緣材料110擴散並環繞第一半導體晶粒106A中的每一者。在某些實施例中，絕緣材料110填充第一半導體晶粒106A與鄰近的貫穿絕緣層孔108中間的間隙。由於存在釋放膜RF，因此第一半導體晶粒106A的一些部分及貫穿絕緣層孔108的一些部分未被絕緣材料110覆蓋。通過從模具MD的一側注入絕緣材料110，在後續步驟中形成的絕緣密封體可具有預定的高度。換句話說，不需要進行其他的研磨或平面化步驟即可形成絕緣密封體。因此，可減少在研磨或平面化步驟之後由於存在填充物而在絕緣密封體中產生的模塑凹坑。
在一些實施例中，絕緣材料110包括聚合物（例如，環氧樹脂、酚醛樹脂、含矽樹脂或其他適合的樹脂）、具有低電容率（Dk）及低損耗角正切（Df）性質的介電材料或其他適合的材料。在替代實施例中，絕緣材料110可包括可接受的絕緣密封材料。絕緣材料110可以液體形式或以流動速率比液體慢的其他形式被注入。在一些實施例中，絕緣材料110還可包括無機填充物或無機化合物（例如，二氧化矽、粘土等），可將所述無機填充物或無機化合物添加到絕緣材料110中以將絕緣材料110的熱膨脹係數（coefficient of thermal expansion，CTE）優化。在某些實施例中，無機填充物可以是SiO2、Al2O3、二氧化矽等的介電粒子，且可具有球形形狀。在一些實施例中，可基於要求而使用精細填充物或大的填充物作為填充物粒子。
參考圖4A，在注入絕緣材料110之後，將絕緣材料110固化以形成絕緣密封體110’。然後，可移除模具MD，並剝除釋放膜RF以暴露出第一半導體晶粒106A的一些部分及貫穿絕緣層孔108的一些部分。圖4B是圖4A中所示結構的俯視圖，其中出於說明目的省略貫穿絕緣層孔108。如圖4B中所示，絕緣密封體110’形成為環繞所述第一半導體晶粒106A中的每一者，而暴露出第一半導體晶粒106A的頂表面。此外，如圖4A及圖4B中所示，第一半導體晶粒106A及貫穿絕緣層孔108從絕緣密封體110’凸出。在某些實施例中，導電杆106a-4的第一部分P1被絕緣密封體110’環繞，而導電杆106a-4的第二部分P2從絕緣密封體110’凸出。在一些實施例中，保護層106a-5的一些部分也從絕緣密封體110’凸出。
參考圖5，在下一步驟中，在絕緣密封體110’上形成隔離材料112以覆蓋第一半導體晶粒106A的凸出部分（或暴露出的部分）及貫穿絕緣層孔108的凸出部分（或暴露出的部分）。在一些實施例中，通過適合的製作技術來形成隔離材料112，例如化學氣相沉積（chemical vapor deposition，CVD）、等離子增強化學氣相沉積（plasma-enhanced chemical vapor deposition，PECVD）等。本發明實施例並不僅限於此。在此階段處，第一半導體晶粒106A及貫穿絕緣層孔108受到隔離材料112的良好保護且被隔離材料112覆蓋。在一些實施例中，隔離材料112可包括介電材料，例如聚醯亞胺、聚苯並噁唑（PBO）、苯環丁烷（BCB）等。本發明實施例並不僅限於此。在某些實施例中，隔離材料112可由與絕緣密封體110’不同的材料製成。在一些其他實施例中，隔離材料112可包括與針對絕緣密封體110’列舉的材料類似的材料，但隔離材料112中不含有任何填充物粒子。由於隔離材料112與絕緣密封體110’是在不同的步驟中形成，因此當在絕緣密封體110’之上形成隔離材料112時，隔離材料112與絕緣密封體110’將會存在介面。
參考圖6，在形成隔離材料112之後，部分地移除隔離材料112以暴露出導電杆106a-4及貫穿絕緣層孔108。在一些實施例中，通過平面化步驟對隔離材料112及保護層106a-5進行研磨或拋光。舉例來說，通過機械研磨製程及/或化學機械拋光（chemical mechanical polishing，CMP）製程來執行平面化步驟，直到暴露出導電杆106a-4的頂表面106TSC為止。在一些實施例中，可對貫穿絕緣層孔108進行部分地拋光，以使得貫穿絕緣層孔108的頂表面108TS與導電杆106a-4的頂表面106TSC齊平。換句話說，還可對導電杆106a-4及貫穿絕緣層孔108進行輕微的研磨/拋光。在一些實施例中，絕緣密封體110’的頂表面110TS低於所述多個導電杆106a-4的頂表面106TSC的水準高度。
在所示的實施例中，隔離材料112被拋光以形成隔離層112’。在一些實施例中，隔離層112’的頂表面112TS、貫穿絕緣層孔108的頂表面108TS、導電杆106a-4的頂表面106TSC及經拋光的保護層106a-5的頂表面106TSP彼此共面且齊平。在一些實施例中，在機械研磨或化學機械拋光（CMP）步驟之後，可視情況執行清洗步驟。舉例來說，執行清洗步驟來清洗並移除由平面化步驟產生的殘餘物。然而，本發明實施例並不僅限於此，且可通過任何其他適合的方法來執行平面化步驟。
另外，如圖6中所示，隔離層112’形成在絕緣密封體110’上且環繞導電杆106a-4的第二部分P2，且還環繞保護層106a-5。在一些實施例中，由於在隔離層112’與導電杆106a-4之間定位有保護層106a-5，因此隔離層112’與導電杆106a-4彼此分離。換句話說，隔離層112’不與導電杆106a-4實體接觸。此外，隔離層112’的厚度T1對絕緣密封體110’的厚度T2的比率處於1:6到1:40範圍中。通過將隔離層112’的厚度T1及絕緣密封體110’的厚度T2控制在此範圍中，可確保保護第一半導體晶粒106A，而絕緣密封體110’上的模塑凹坑（如果存在的話）可被隔離層112’有效地覆蓋或隔離。如果隔離層112’的厚度T1太小，則絕緣密封體110’上的模塑凹坑不能被良好地覆蓋及隔離，且仍可能會存在重佈線層（redistribution layer，RDL）塌陷問題。在一些實施例中，隔離層112’的厚度T1處於從1 μm到30 μm範圍中。在某些實施例中，隔離層112’的厚度T1處於從5 μm到20 μm範圍中。在一個示例性實施例中，隔離層112’的厚度T1是約5 μm。
參考圖7，在進行平面化步驟之後，在隔離層112’上、在貫穿絕緣層孔108上且在第一半導體晶粒106A上形成重佈線層114。如圖7中所示，重佈線層114形成在貫穿絕緣層孔108的頂表面108TS上、形成在導電杆106a-4的頂表面106TSC上且形成在隔離層112’的頂表面112TS上。在一些實施例中，隔離層112’將重佈線層114與絕緣密封體110’分離。在一些實施例中，重佈線層114電性連接到貫穿絕緣層孔108，且通過導電杆106a-4電性連接到第一半導體晶粒106A。在某些實施例中，第一半導體晶粒106A通過重佈線層114電性連接到貫穿絕緣層孔108。
在一些實施例中，形成重佈線層114包括依序交替地形成一個或多個介電層114A以及一個或多個金屬層114B。在某些實施例中，金屬層114B夾在數個介電層114A之間。儘管本文中僅說明了兩層金屬層114B及三層介電層114A，然而，本揭露的範圍並不受本發明實施例限制。在其他實施例中，可基於產品要求來調整金屬層114B及介電層114A的數目。在一些實施例中，金屬層114B電性連接到第一半導體晶粒106A的導電杆106a-4。此外，金屬層114B電性連接到貫穿絕緣層孔108。
在某些實施例中，介電層114A的材料可以是聚醯亞胺、聚苯並噁唑（PBO）、苯環丁烷（BCB）、例如氮化矽等氮化物、例如氧化矽等氧化物、磷矽酸鹽玻璃（phosphosilicate glass，PSG）、硼矽酸鹽玻璃（borosilicate glass，BSG）、摻雜硼的磷矽酸鹽玻璃（boron-doped phosphosilicate glass，BPSG）、上述各項的組合等，可使用光阻及/或蝕刻製程來將所述介電層114A的材料圖案化。在一些實施例中，通過適合的製作技術來形成介電層114A，所述技術包括例如旋轉塗布、化學氣相沉積（CVD）、等離子增強化學氣相沉積（PECVD）等。本發明實施例並不僅限於此。
在一些實施例中，金屬層114B的材料可由通過電鍍或沉積形成的導電材料製成，例如鋁、鈦、銅、鎳、鎢及/或其合金，可使用光阻及蝕刻製程來將所述金屬層114B的材料圖案化。在一些實施例中，金屬層114B可以是經圖案化銅層或其他適合的經圖案化金屬層。在本說明通篇，用語“銅”旨在包含實質上純元素銅、含不可避免的雜質的銅、及含微量（例如）的鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁或鋯等元素的銅合金。
在形成重佈線層114之後，可在金屬層114B的最頂層的暴露出的頂表面上安置多個導電接墊114C以與導電球電性連接。在某些實施例中，舉例來說，導電接墊114C是用於安裝球的球下金屬（under-ball metallurgy，UBM）圖案。如圖7中所示，導電接墊114C形成在重佈線層114上且電性連接到重佈線層114。在一些實施例中，導電接墊114C的材料可包括銅、鎳、鈦、鎢或其合金等，且可通過例如電鍍等製程形成。導電接墊114C的數目並不僅限於本發明實施例，且可基於設計佈局而做出選擇。在一些替代實施例中，可省略導電接墊114C。換句話說，在後續步驟中形成的導電球116可直接安置在重佈線層114上。
仍參考圖7，在形成導電接墊114C之後，在導電接墊114C上且在重佈線層114之上安置多個導電球116。在一些實施例中，可通過植球製程或回焊製程來將導電球116安置在導電接墊114C上。在一些實施例中，舉例來說，導電球116是焊球或球柵陣列（ball grid array，BGA）球。在一些實施例中，導電球116通過導電接墊114C連接到重佈線層114。在某些實施例中，導電球116中的一些可通過重佈線層114電性連接到第一半導體晶粒106A。此外，導電球116中的一些可通過重佈線層114電性連接到貫穿絕緣層孔108。導電球116的數目並不僅限於本發明實施例，且可基於導電接墊114C的數目進行指定及選擇。在一些替代實施例中，可視情況在重佈線層114上安置集成被動構件（IPD）（未示出）且所述集成被動構件電性連接到重佈線層114。
參考圖8，在下一步驟中，在形成重佈線層114及導電球116之後，可將圖7中所示的結構上下翻轉並貼合到由框架302支撐的條帶301。隨後，剝離載體102以將形成在載體102上的介電層104B及其他元件與載體102分離。在示例性實施例中，剝離製程包括將光（例如，雷射或紫外線（ultraviolet，UV）光）投射在脫膠層104A（例如，LTHC釋放層）上，以使得可容易地移除載體102。在某些實施例中，還可移除或剝除脫膠層104A以暴露出介電層104B。然後，可將剩餘介電層104B圖案化以形成暴露出貫穿絕緣層孔108的底表面的多個開口（未示出）。所形成的開口的數目對應於貫穿絕緣層孔108的數目。此後，可在貫穿絕緣層孔108的由開口暴露出的底表面上放置多個導電球118。舉例來說，對導電球118執行回焊以與貫穿絕緣層孔108的底表面結合。在形成導電球118之後，完成具有雙側端子的封裝結構PK1。
參考圖9，在一些實施例中，可在封裝結構PK1上堆疊另一封裝結構PK2以形成疊層封裝（package-on-package，PoP）結構。如圖9中所示，封裝結構PK2電性連接到封裝結構PK1的導電球118。在一些實施例中，封裝結構PK2具有基板210、安裝在基板210的一個表面（例如頂表面）上且彼此堆疊的多個半導體晶片220。在一些實施例中，使用結合配線230來提供半導體晶片220與接墊240（例如，結合接墊）之間的電性連接。在一些實施例中，形成絕緣密封體260以密封半導體晶片220及結合配線230來保護這些元件。在一些實施例中，可使用貫穿絕緣層孔（未示出）來提供接墊240與位於基板210的另一表面（例如，底表面）上的導電接墊250（例如，結合接墊）之間的電性連接。在某些實施例中，導電接墊250通過這些貫穿絕緣層孔（未示出）電性連接到半導體晶片220。在一些實施例中，封裝結構PK2的導電接墊250電性連接到封裝結構PK1的導電球118。在一些實施例中，還提供底部填充膠270以填充在導電球118之間的空間中以保護導電球118。在將封裝結構PK2堆疊在封裝結構PK1上且提供這兩者之間的電性連接之後，可製作出疊層封裝結構10A。
圖10A及圖10B是根據本文的一些其他示例性實施例的製作封裝結構的方法的各個階段的示意性剖視圖。圖10A及圖10B中所示的實施例類似於圖1到圖9中所示的實施例，因此使用相同的參考標號來指代相同或相似的部分，且本文中將省略對相同或相似的部分的詳細說明。圖10A到圖10B的實施例與圖1到圖9的實施例之間的差異在於隔離層112’的設計。如圖10A中所示，形成隔離層112’以環繞導電杆106a-4的第二部分P2。此外，在一些實施例中，保護層106a-5的頂表面106TSP低於隔離層112’的頂表面112TS。換句話說，未對隔離層112’執行平面化步驟，且隔離層112’將環繞貫穿絕緣層孔108且位於貫穿絕緣層孔108的頂表面108TS上且位於保護層106a-5的頂表面106TSP上。在後續步驟中，在隔離層112’上形成重佈線層114的第一介電層114A。將第一介電層114A及隔離層112’圖案化以形成開口，所述開口暴露出貫穿絕緣層孔108的頂表面108TS及導電杆106a-4的頂表面106TSC。然後，在開口內形成金屬層114B以電性連接到第一半導體晶粒106A及貫穿絕緣層孔108。
參考圖10B，在一些實施例中，然後可執行圖7至圖9中所述的相同的步驟來形成封裝結構PK1的重佈線層114、導電球116及導電球118。隨後，可在封裝結構PK1之上堆疊相同的封裝結構PK2，且將封裝結構PK2電性連接到封裝結構PK1。在將封裝結構PK2堆疊在封裝結構PK1上且提供這兩者之間的電性連接之後，可製作出疊層封裝結構10B。
圖11A到圖11C是根據本文的一些其他示例性實施例的製作封裝結構的方法的各個階段的示意性剖視圖。圖11A到圖11C中所示的實施例類似於圖1到圖9中所示的實施例，因此使用相同的參考標號來指代相同或相似的部分，且本文中將省略對相同或相似的部分的詳細說明。圖11A到圖11C的實施例與圖1到圖9的實施例之間的差異在於第一半導體晶粒106A的設計。
如圖11A中所示，在一些實施例中，可省略第一半導體晶粒106A的保護層106a-5。如此，在形成絕緣密封體110’期間，絕緣密封體110’將與第一半導體晶粒106A的導電杆106a-4接觸。在某些實施例中，絕緣密封體110’與導電杆106a-4的第一部分P1接觸，而導電杆106a-4的第二部分P2從絕緣密封體110’暴露出。參考圖11B，在下一步驟中，可在絕緣密封體110’之上形成隔離材料（未示出），並可執行平面化步驟以形成隔離層112’。在示例性實施例中，在進行平面化步驟之後，隔離層112’的頂表面112TS、貫穿絕緣層孔108的頂表面108TS及導電杆106a-4的頂表面106TSC彼此共面且齊平。此外，在一些實施例中，隔離層112’環繞且接觸所述多個導電杆106a-4。在某些實施例中，隔離層112’與導電杆106a-4的第二部分P2接觸。參考圖11C，在形成隔離層112’之後，然後可執行圖7到圖9中所述的相同的步驟以形成封裝結構PK1的重佈線層114、導電球116及導電球118。隨後，可在封裝結構PK1之上堆疊相同的封裝結構PK2，且將封裝結構PK2電性連接到封裝結構PK1。在將封裝結構PK2堆疊在封裝結構PK1上且提供這兩者之間的電性連接之後，可製作出疊層封裝結構10C。
圖12A及圖12B是根據本文的一些其他示例性實施例的製作封裝結構的方法的各個階段的示意性剖視圖。圖12A及圖12B中所示的實施例類似於圖11A到圖11C中所示的實施例，因此使用相同的參考標號來指代相同或相似的部分，且本文中將省略對相同或相似的部分的詳細說明。圖12A到12B的實施例與圖11A到圖11C的實施例之間的差異在於隔離層112’的設計。如圖12A中所示，形成隔離層112’以環繞且接觸導電杆106a-4的第二部分P2。此外，在一些實施例中，導電杆106a-4的頂表面106TSC低於隔離層112’的頂表面112TS。換句話說，未對隔離層112’執行平面化步驟，且隔離層112’共形地位於貫穿絕緣層孔108的頂表面108TS上、位於導電杆106a-4的頂表面106TSC上且位於絕緣密封體110’之上。在後續步驟中，在隔離層112’之上形成重佈線層114的第一介電層114A。將第一介電層114A及隔離層112’圖案化以形成開口，所述開口暴露出貫穿絕緣層孔108的頂表面108TS及導電杆106a-4的頂表面106TSC。然後，在開口內形成金屬層114B以電性連接到第一半導體晶粒106A及貫穿絕緣層孔108。
參考圖12B，在一些實施例中，然後可執行圖7到圖9中所述的相同的步驟以形成封裝結構PK1的重佈線層114、導電球116及導電球118。隨後，可在封裝結構PK1之上堆疊相同的封裝結構PK2，且將封裝結構PK2電性連接到封裝結構PK1。在將封裝結構PK2堆疊在封裝結構PK1上且提供這兩者之間的電性連接之後，可製作出疊層封裝結構10D。
圖13A到圖13C是根據本文的一些其他示例性實施例的製作封裝結構的方法的各個階段的示意性剖視圖。圖13A到圖13C中所示的實施例類似於圖1到圖9中所示的實施例，因此使用相同的參考標號來指代相同或相似的部分，其本文中將省略對相同或相似的部分的詳細說明。圖13A到圖13C的實施例與圖1到圖9的實施例之間的差異在於，圖13A到圖13C的實施例中還設置第二半導體晶粒106B。
如圖13A中所示，在第一半導體晶粒106A上堆疊第二半導體晶粒106B以形成堆疊式晶粒。在一些實施例中，第二半導體晶粒106B通過連接元件CE連接到第一半導體晶粒106A。在某些實施例中，連接元件CE可以是提供第一半導體晶粒106A與第二半導體晶粒106B之間的必要連接的導電凸塊或導電接墊，本發明實施例並不僅限於此。在示例性實施例中，第一半導體晶粒106A不具有保護層106a-5，且第二半導體晶粒106B位於第一半導體晶粒106A的半導體基板106a-1上、位於兩個導電杆106a-4中間。在一些實施例中，第二半導體晶粒106B包括第二半導體基板106b-1及安置在第二半導體基板106b-1上的多個第二導電杆106b-2。在一些實施例中，第一半導體晶粒106A的導電杆106a-4及第二半導體晶粒106B的第二導電杆106b-2分別具有被絕緣密封體110’環繞的第一部分P1及從絕緣密封體110’凸出的第二部分P2。在一些實施例中，第二導電杆106b-2的寬度W1小於導電杆106a-4的寬度W2。換句話說，導電杆106a-4的尺寸與第二導電杆106b-2的尺寸是不同的。在一個示例性實施例中，第二導電杆106b-2的寬度W1處於1 μm到10 μm範圍中，而導電杆106a-4的寬度W2處於10 μm到90 μm範圍中。本發明實施例並不僅限於此。
參考圖13B，在下一步驟中，可在絕緣密封體110’之上形成隔離材料（未示出），並可執行平面化步驟以形成隔離層112’。在示例性實施例中，在進行平面化步驟之後，隔離層112’的頂表面112TS、貫穿絕緣層孔108的頂表面108TS、導電杆106a-4的頂表面106TSC及第二導電杆106b-2的頂表面106TSCx彼此共面且齊平。在一些實施例中，形成隔離層112’以環繞且接觸第一半導體晶粒106A的導電杆106a-4，且形成隔離層112’以環繞且接觸第二半導體晶粒106B的第二導電杆106b-2。參考圖13C，在形成隔離層112’之後，然後可執行圖7到圖9所述的相同的步驟以形成封裝結構PK1的重佈線層114、導電球116及導電球118。在一些實施例中，還可在重佈線層114上安置集成被動構件117 （integrated passive device）。隨後，可在封裝結構PK1之上堆疊相同的封裝結構PK2，且將封裝結構PK2電性連接到封裝結構PK1。在將封裝結構PK2堆疊在封裝結構PK1上且提供這兩者之間的電性連接之後，可製作出疊層封裝結構10E。
在上述實施例中，可形成絕緣密封體以直接密封半導體晶粒，而無需進行其他的研磨或平面化步驟。此外，隔離層形成在絕緣密封體與重佈線層中間。因此，可減少在研磨或平面化步驟之後由於存在填充物而在絕緣密封體中產生的模塑凹坑。此外，隔離層將用作為壁障來將絕緣密封體中的模塑凹坑與重佈線層隔離開。如此，當在絕緣密封體之上形成重佈線層（RDL）時，可防止RDL塌陷問題或畸形的RDL圖案。總體來說，在絕緣密封體上形成隔離層將會提供更平坦的表面，從而能夠高效地製作重佈線層，提高RDL圖案的良率。
根據本揭露的一些實施例，提供一種封裝結構，所述封裝結構包括至少一個半導體晶粒、絕緣密封體、隔離層及重佈線層。所述至少一個第一半導體晶粒具有半導體基板及安置在所述半導體基板上的導電杆。所述絕緣密封體部分地密封所述第一半導體晶粒，其中所述導電杆具有被絕緣密封體環繞的第一部分及從所述絕緣密封體凸出的第二部分。所述隔離層安置在所述絕緣密封體上且環繞所述導電杆的所述第二部分。所述重佈線層安置在所述第一半導體晶粒及所述隔離層上，其中所述重佈線層電性連接到所述第一半導體晶粒的所述導電杆。
在一些實施例中，所述隔離層將所述重佈線層與所述絕緣密封體分離。在一些實施例中，所述第一半導體晶粒還包括保護層，所述保護層安置在所述半導體基板上且環繞所述導電杆，所述隔離層環繞所述保護層，且所述保護層的頂表面與所述隔離層的頂表面共面。在一些實施例中，所述第一半導體晶粒還包括保護層，所述保護層安置在所述半導體基板上且環繞所述導電杆，所述隔離層環繞所述保護層，且所述保護層的頂表面低於所述隔離層的頂表面。在一些實施例中，所述隔離層環繞且接觸所述導電杆。在一些實施例中，所述的封裝結構還包括環繞所述第一半導體晶粒的多個貫穿絕緣層孔，其中所述多個貫穿絕緣層孔從所述絕緣密封體凸出，且所述隔離層環繞所述多個貫穿絕緣層孔的所述凸出部分。在一些實施例中，所述的封裝結構還包括堆疊在所述第一半導體晶粒上的第二半導體晶粒，所述第二半導體晶粒包括第二半導體基板及安置在所述第二半導體基板上的第二導電杆，其中所述第二導電杆具有被所述絕緣密封體環繞的第一部分及從所述絕緣密封體凸出的第二部分，且所述隔離層環繞所述第二導電杆的所述第二部分。在一些實施例中，所述第一半導體晶粒的所述導電杆的頂表面與所述第二半導體晶粒的所述第二導電杆的頂表面實質上共面。
根據本揭露的一些其他實施例，提供一種封裝結構，所述封裝結構包括第一半導體晶粒、絕緣密封體、隔離層及重佈線層。所述第一半導體晶粒具有半導體基板及安置在所述半導體基板上的多個導電杆。所述絕緣密封體部分地密封所述第一半導體晶粒，其中所述絕緣密封體的頂表面低於所述多個導電杆的頂表面的水準高度。所述隔離層安置在所述絕緣密封體的頂表面上且環繞所述多個導電杆，其中所述隔離層的頂表面與所述多個導電杆的所述頂表面實質上共面，且所述隔離層的厚度對所述絕緣密封體的厚度的比率處於1:6到1:40範圍中。所述重佈線層安置在所述第一半導體晶粒及所述隔離層上，其中所述重佈線層電性連接到所述第一半導體晶粒的所述多個導電杆。
在一些實施例中，所述隔離層將所述重佈線層與所述絕緣密封體分離。在一些實施例中，所述第一半導體晶粒還包括保護層，所述保護層安置在所述半導體基板上且環繞所述多個導電杆，所述隔離層環繞所述保護層，且所述保護層的頂表面與所述隔離層的所述頂表面共面。在一些實施例中，所述隔離層環繞且接觸所述多個導電杆中的每一者。在一些實施例中，所述多個導電杆的一部分被所述絕緣密封體環繞，且所述多個導電杆的另一部分被所述隔離層環繞。在一些實施例中，所述的封裝結構還包括堆疊在所述第一半導體晶粒上的第二半導體晶粒，所述第二半導體晶粒包括第二半導體基板及安置在所述第二半導體基板上的多個第二導電杆，其中所述絕緣密封體部分地密封所述第二半導體晶粒，且所述隔離層的所述頂表面與所述多個第二導電杆的頂表面共面。
根據本揭露的又一實施例，闡述一種製作封裝結構的方法。所述方法包括以下步驟。將第一半導體晶粒結合在載體上，其中所述第一半導體晶粒包括半導體基板及安置在所述半導體基板上的多個導電杆。形成絕緣密封體以部分地密封所述第一半導體晶粒，其中所述絕緣密封體形成為環繞所述多個導電杆的第一部分，且所述多個導電杆的第二部分從所述絕緣密封體凸出。在所述絕緣密封體上形成隔離層以環繞所述多個導電杆的所述第二部分。在所述第一半導體晶粒及所述隔離層上形成重佈線層，其中所述重佈線層電性連接到所述第一半導體晶粒。
在一些實施例中，成所述絕緣密封體包括：在所述載體上設置模具，使其覆蓋所述第一半導體晶粒，其中所述模具包括流道孔及貼合到所述模具的內表面的釋放膜，且所述釋放膜部分地覆蓋所述第一半導體晶粒；將絕緣材料通過所述流道孔注入到所述模具中，使得所述絕緣材料部分地密封所述第一半導體晶粒；將所述絕緣材料固化以形成所述絕緣密封體；以及移除所述模具並從所述第一半導體晶粒分離所述釋放膜，使得所述絕緣密封體部分地密封所述第一半導體晶粒且暴露出所述第一半導體晶粒的一些部分。在一些實施例中，在所述模具被移除之後，所述隔離層形成為覆蓋所述第一半導體晶粒暴露出的所述部分。在一些實施例中，所述的製作封裝結構的方法還包括將所述絕緣材料通過位於所述模具的一側上的所述流道孔注入到所述模具中，使得所述絕緣材料從所述載體的一側擴散到所述載體的另一側以部分地密封所述第一半導體晶粒。在一些實施例中，所述隔離層形成為接觸所述多個導電杆。在一些實施例中，所述的製作封裝結構的方法還包括在所述第一半導體晶粒上堆疊第二半導體晶粒，所述第二半導體晶粒包括第二半導體基板及安置在所述第二半導體基板上的多個第二導電杆，其中所述絕緣密封體是形成為環繞所述多個第二導電杆的第一部分，且所述多個第二導電杆的第二部分從所述絕緣密封體凸出，且所述隔離層是形成為環繞所述多個第二導電杆的所述第二部分。
上述內容概述了數個實施例的特徵，以使所屬領域的技術人員可更好地理解本發明實施例的各方面。所屬領域的技術人員應瞭解，其可容易地使用本發明實施例作為設計或修改其他製程及結構以實現與本文中所介紹的實施例相同的目的及/或達成相同的優勢的基礎。所屬領域的技術人員還應意識到這些等效構造並不背離本發明實施例的精神及範圍，且其可在不背離本發明實施例的精神及範圍的情況下在本文中做出各種變化、替代及更改。
10A、10B、10C、10D‧‧‧疊層封裝結構 102‧‧‧載體 104‧‧‧緩衝層 104A‧‧‧脫膠層 104B‧‧‧介電層 106A‧‧‧第一半導體晶粒 106a-1‧‧‧半導體基板 106a-2、114C、250‧‧‧導電接墊 106a-3‧‧‧鈍化層 106a-4‧‧‧導電杆 106a-5‧‧‧保護層 106B‧‧‧第二半導體晶粒 106b-1‧‧‧第二半導體基板 106b-2‧‧‧第二導電杆 106TSC‧‧‧導電杆的頂表面 106TSCx‧‧‧第二導電杆的頂表面 106TSP‧‧‧保護層的頂表面 108‧‧‧貫穿絕緣層孔 108TS‧‧‧貫穿絕緣層孔的頂表面 110‧‧‧絕緣材料 110’‧‧‧絕緣密封體 110TS‧‧‧絕緣密封體的頂表面 112‧‧‧隔離材料 112’‧‧‧隔離層 112TS‧‧‧隔離層的頂表面 114‧‧‧重佈線層 114A‧‧‧介電層/第一介電層 114B‧‧‧金屬層 116、118‧‧‧導電球 117‧‧‧集成被動構件 210‧‧‧基板 220‧‧‧半導體晶片 230‧‧‧結合配線 240‧‧‧接墊 260‧‧‧絕緣密封體 270‧‧‧底部填充膠 301‧‧‧條帶 302‧‧‧框架 AS‧‧‧主動表面 BS‧‧‧背側表面 CE‧‧‧連接元件 DF‧‧‧晶粒貼合膜 HR‧‧‧流道孔 MD‧‧‧模具 P1‧‧‧第一部分 P2‧‧‧第二部分 PK1、PK2‧‧‧封裝結構 RF‧‧‧釋放膜 T1‧‧‧隔離層的厚度 T2‧‧‧絕緣密封體的厚度 W1‧‧‧第二導電杆的寬度 W2‧‧‧導電杆的寬度
當結合圖式閱讀時，根據以下詳細描述最好地理解本公開的各方面。應注意，根據行業中的標準慣例，各種特徵未按比例繪製。實際上，為了論述清楚起見，可以任意地增大或減小各種特徵的尺寸。 圖1至圖9是根據本文的一些示例性實施例的製作封裝結構的方法的各個階段的示意性剖視圖。 圖10A及圖10B是根據本文的一些其他示例性實施例的製作封裝結構的方法的各個階段的示意性剖視圖。 圖11A到圖11C是根據本文的一些其他示例性實施例的製作封裝結構的方法的各個階段的示意性剖視圖。 圖12A及圖12B是根據本文的一些其他示例性實施例的製作封裝結構的方法的各個階段的示意性剖視圖。 圖13A到圖13C是根據本文的一些其他示例性實施例的製作封裝結構的方法的各個階段的示意性剖視圖。
10A‧‧‧疊層封裝結構
104B‧‧‧介電層
106A‧‧‧第一半導體晶粒
106a-2、114C、250‧‧‧導電接墊
106a-3‧‧‧鈍化層
106a-4‧‧‧導電杆
106a-5‧‧‧保護層
108‧‧‧貫穿絕緣層孔
110’‧‧‧絕緣密封體
112’‧‧‧隔離層
114‧‧‧重佈線層
114A‧‧‧介電層/第一介電層
114B‧‧‧金屬層
116、118‧‧‧導電球
210‧‧‧基板
220‧‧‧半導體晶片
230‧‧‧結合配線
240‧‧‧接墊
260‧‧‧絕緣密封體
270‧‧‧底部填充膠
DF‧‧‧晶粒貼合膜
PK1、PK2‧‧‧封裝結構

Claims (1)

  1. 一種封裝結構，其特徵在於，包括： 至少一個第一半導體晶粒，具有半導體基板及安置在所述半導體基板上的導電杆； 絕緣密封體，部分地密封所述第一半導體晶粒，其中所述導電杆具有被所述絕緣密封體環繞的第一部分及從所述絕緣密封體凸出的第二部分； 隔離層，安置在所述絕緣密封體上且環繞所述導電杆的所述第二部分；以及 重佈線層，安置在所述第一半導體晶粒及所述隔離層上，所述重佈線層電性連接到所述第一半導體晶粒的所述導電杆。
TW108102529A 2018-07-31 2019-01-23 封裝結構 TW202008531A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862712219P 2018-07-31 2018-07-31
US62/712,219 2018-07-31
US16/199,230 2018-11-26
US16/199,230 US10658333B2 (en) 2018-07-31 2018-11-26 Package structure and method of fabricating the same

Publications (1)

Publication Number Publication Date
TW202008531A true TW202008531A (zh) 2020-02-16

Family

ID=69229820

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108102529A TW202008531A (zh) 2018-07-31 2019-01-23 封裝結構

Country Status (3)

Country Link
US (4) US10658333B2 (zh)
CN (1) CN110783282A (zh)
TW (1) TW202008531A (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10460987B2 (en) * 2017-05-09 2019-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device with integrated antenna and manufacturing method thereof
US10658333B2 (en) * 2018-07-31 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of fabricating the same
KR20210083830A (ko) * 2019-12-27 2021-07-07 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
US11270975B2 (en) 2020-07-21 2022-03-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages including passive devices and methods of forming same
US11798859B2 (en) * 2021-05-11 2023-10-24 Advanced Semiconductor Engineering, Inc. Electronic device package and method of manufacturing the same

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG149710A1 (en) * 2007-07-12 2009-02-27 Micron Technology Inc Interconnects for packaged semiconductor devices and methods for manufacturing such devices
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9412689B2 (en) * 2012-01-24 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packaging structure and method
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US20130307153A1 (en) 2012-05-18 2013-11-21 International Business Machines Corporation Interconnect with titanium-oxide diffusion barrier
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
KR102181013B1 (ko) * 2014-09-05 2020-11-19 삼성전자주식회사 반도체 패키지
US10276541B2 (en) * 2015-06-30 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. 3D package structure and methods of forming same
US10658333B2 (en) * 2018-07-31 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of fabricating the same

Also Published As

Publication number Publication date
US20200043893A1 (en) 2020-02-06
US20200279831A1 (en) 2020-09-03
US20220173070A1 (en) 2022-06-02
US11257787B2 (en) 2022-02-22
US11837578B2 (en) 2023-12-05
US20240047422A1 (en) 2024-02-08
US10658333B2 (en) 2020-05-19
CN110783282A (zh) 2020-02-11

Similar Documents

Publication Publication Date Title
US11502040B2 (en) Package structure and semiconductor pacakge
US11776905B2 (en) Package structure, package-on-package structure and manufacturing method thereof
US11063019B2 (en) Package structure, chip structure and method of fabricating the same
US11837578B2 (en) Package structure
US12015017B2 (en) Package structure, package-on-package structure and method of fabricating the same
US11251119B2 (en) Package structure, package-on-package structure and method of fabricating the same
TWI736229B (zh) 封裝結構、疊層封裝結構及其製作方法
US11101252B2 (en) Package-on-package structure and manufacturing method thereof
US20200203301A1 (en) Electronic assembly, package structure and method of fabricating the same
TWI743996B (zh) 封裝結構及其製作方法
US10879166B2 (en) Package structure having redistribution structure with photosensitive and non-photosensitive dielectric materials and fabricating method thereof
TW202114088A (zh) 封裝結構
US20230282558A1 (en) Package structure and method of fabricating the same
US20230268260A1 (en) Package structure and method of fabricating the same
US20220336364A1 (en) Package structure and method of fabricating the same
TW202310270A (zh) 半導體裝置、封裝結構及其製備方法