TW201944594A - Semiconductor structures and method for fabricating the same - Google Patents
Semiconductor structures and method for fabricating the same Download PDFInfo
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本發明係有關於一種半導體結構,特別是有關於一種具有絕緣核心基板且不須偏壓連接的半導體結構及其製造方法。 The present invention relates to a semiconductor structure, and more particularly, to a semiconductor structure having an insulating core substrate and requiring no bias connection, and a manufacturing method thereof.
氮化鎵(GaN)半導體具備優異的物理特性,例如寬能隙、高崩潰電場、以及相對較高的電子遷移率。在此種半導體上所製作的元件特別適合用於功率電子的領域。研究顯示,氮化鎵鋁(AlGaN)/氮化鎵(GaN)異質結構的三族氮化物半導體是製作高電子遷移率電晶體(HEMT)的極佳材料系統。該結構同時提供了高載子濃度以及高載子遷移率這兩項優越且獨特的性質。 Gallium nitride (GaN) semiconductors have excellent physical properties, such as wide energy gaps, high collapse electric fields, and relatively high electron mobility. An element fabricated on such a semiconductor is particularly suitable for use in the field of power electronics. Studies have shown that a group III nitride semiconductor with an aluminum gallium nitride (AlGaN) / gallium nitride (GaN) heterostructure is an excellent material system for making high electron mobility transistors (HEMT). This structure provides both superior and unique properties of high carrier concentration and high carrier mobility.
對於積體電路的應用,隔離氮化鎵(GaN)元件是必要的。傳統上,藉由離子佈植或淺蝕刻所形成的橫向隔離結構係用來中斷形成高電子遷移率電晶體(HEMT)元件通道的高導電性二維電子氣層(two-dimensional electron gas(2DEG)layer)。然而,由於產生自半導體基板的背偏壓效應(back bias effect),此種隔離結構已不適合用於處於不同偏壓條件(即施加不同電壓於各元件端子)下的多重元件。上述背偏壓效應將影響電晶體的崩潰電壓及電特性。 For integrated circuit applications, isolating gallium nitride (GaN) elements is necessary. Traditionally, a lateral isolation structure formed by ion implantation or shallow etching is used to interrupt the formation of a highly conductive two-dimensional electron gas (2DEG) channel of a high electron mobility transistor (HEMT) device channel. ) layer). However, due to the back bias effect generated from the semiconductor substrate, such an isolation structure is no longer suitable for multiple components under different bias conditions (ie, applying different voltages to the terminals of each component). The aforementioned back bias effect will affect the breakdown voltage and electrical characteristics of the transistor.
因此,開發一種具有簡單、適當的隔離結構且可消除背偏壓效應(back bias effect)的半導體結構是眾所期待的。 Therefore, it is desirable to develop a semiconductor structure having a simple and appropriate isolation structure and which can eliminate the back bias effect.
根據本發明的一實施例,提供一種半導體結構。該半導體結構,包括:一絕緣基板、一工程化層(engineered layer)、一成核層(nucleation layer)、一緩衝層、一第一磊晶層、一第二磊晶層、一隔離結構、一第一閘極、一第一源極、一第一汲極、一第二閘極、一第二源極、以及一第二汲極。該絕緣基板包括一第一區與一第二區。該工程化層包圍該絕緣基板。該成核層形成於該工程化層上。該緩衝層形成於該成核層上。該第一磊晶層形成於該緩衝層上。該第二磊晶層形成於該第一磊晶層上。該隔離結構至少形成於該第二磊晶層、該第一磊晶層、以及該成核層中。該隔離結構位於該第一區與該第二區之間。該第一閘極形成於該第二磊晶層上,並位於該第一區內。該第一源極與該第一汲極形成於該第二磊晶層上,並位於該第一區內。該第一源極與該第一汲極位於該第一閘極的兩側。該第二閘極形成於該第二磊晶層上,並位於該第二區內。該第二源極與該第二汲極形成於該第二磊晶層上,並位於該第二區內。該第二源極與該第二汲極位於該第二閘極的兩側。 According to an embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure includes: an insulating substrate, an engineered layer, a nucleation layer, a buffer layer, a first epitaxial layer, a second epitaxial layer, an isolation structure, A first gate, a first source, a first drain, a second gate, a second source, and a second drain. The insulating substrate includes a first region and a second region. The engineered layer surrounds the insulating substrate. The nucleation layer is formed on the engineered layer. The buffer layer is formed on the nucleation layer. The first epitaxial layer is formed on the buffer layer. The second epitaxial layer is formed on the first epitaxial layer. The isolation structure is formed at least in the second epitaxial layer, the first epitaxial layer, and the nucleation layer. The isolation structure is located between the first region and the second region. The first gate is formed on the second epitaxial layer and is located in the first region. The first source electrode and the first drain electrode are formed on the second epitaxial layer and are located in the first region. The first source electrode and the first drain electrode are located on two sides of the first gate electrode. The second gate is formed on the second epitaxial layer and is located in the second region. The second source electrode and the second drain electrode are formed on the second epitaxial layer and are located in the second region. The second source and the second drain are located on both sides of the second gate.
根據部分實施例,上述絕緣基板的熱膨脹係數(coefficient of thermal expansion,CTE)與上述第一磊晶層的熱膨脹係數相近。 According to some embodiments, the coefficient of thermal expansion (CTE) of the insulating substrate is similar to that of the first epitaxial layer.
根據部分實施例,上述絕緣基板的體電阻率(bulk resistivity)大於106ohm-cm。 According to some embodiments, the bulk resistivity of the insulating substrate is greater than 10 6 ohm-cm.
根據部分實施例,上述絕緣基板的熱傳導率(thermal conductivity)高於矽的熱傳導率。 According to some embodiments, the thermal conductivity of the insulating substrate is higher than the thermal conductivity of silicon.
根據部分實施例,上述絕緣基板包括氮化鋁、多晶碳化矽(polycrystalline silicon carbide)、多晶鑽石(polycrystalline diamond)、或其混合物、或不同多晶材料的混合物、或其他適合的絕緣材料。 According to some embodiments, the above-mentioned insulating substrate includes aluminum nitride, polycrystalline silicon carbide, polycrystalline diamond, or a mixture thereof, or a mixture of different polycrystalline materials, or other suitable insulating materials.
根據部分實施例,上述工程化層包括氮化物、氧化物、氮氧化物、或多晶矽。 According to some embodiments, the engineered layer includes nitride, oxide, oxynitride, or polycrystalline silicon.
根據部分實施例,上述成核層包括矽<111>。 According to some embodiments, the nucleation layer includes silicon <111>.
根據部分實施例,上述成核層為結晶型。 According to some embodiments, the nucleation layer is crystalline.
根據部分實施例,上述成核層的厚度介於0.1微米至5微米。 According to some embodiments, the thickness of the nucleation layer is between 0.1 μm and 5 μm.
根據部分實施例,上述緩衝層包括氮化鎵鋁或氮化鋁。 According to some embodiments, the buffer layer includes aluminum gallium nitride or aluminum nitride.
根據部分實施例,上述第一磊晶層包括氮化鎵。 According to some embodiments, the first epitaxial layer includes gallium nitride.
根據部分實施例,上述第二磊晶層包括氮化鎵鋁。 According to some embodiments, the second epitaxial layer includes aluminum gallium nitride.
根據部分實施例,更包括一第三磊晶層,形成於上述第二磊晶層上。 According to some embodiments, a third epitaxial layer is further formed on the second epitaxial layer.
根據部分實施例,上述第三磊晶層為一P型氮化鎵層。 According to some embodiments, the third epitaxial layer is a P-type GaN layer.
根據部分實施例,上述隔離結構包括一溝槽,填入有一絕緣材料,上述溝槽穿過上述第二磊晶層、上述第一磊 晶層、上述緩衝層、以及上述成核層。 According to some embodiments, the isolation structure includes a trench filled with an insulating material, and the trench passes through the second epitaxial layer, the first epitaxial layer, the buffer layer, and the nucleation layer.
根據部分實施例,上述隔離結構包括一溝槽,填入有一絕緣材料,上述溝槽穿過上述第二磊晶層、上述第一磊晶層、上述緩衝層、上述成核層、以及部分的上述工程化層。 According to some embodiments, the isolation structure includes a trench filled with an insulating material, and the trench passes through the second epitaxial layer, the first epitaxial layer, the buffer layer, the nucleation layer, and part of the The above engineering layer.
根據部分實施例,上述隔離結構包括一第一佈植區與一第二佈植區。 According to some embodiments, the isolation structure includes a first planting area and a second planting area.
根據部分實施例,上述第一佈植區位於上述第二磊晶層與上述第一磊晶層中。 According to some embodiments, the first implanted region is located in the second epitaxial layer and the first epitaxial layer.
根據部分實施例,上述第二佈植區位於上述成核層中。 According to some embodiments, the second implantation region is located in the nucleation layer.
根據部分實施例,上述隔離結構包括一連續佈植區,覆蓋上述第二磊晶層、上述第一磊晶層、上述緩衝層、以及上述成核層。 According to some embodiments, the isolation structure includes a continuous implanted region covering the second epitaxial layer, the first epitaxial layer, the buffer layer, and the nucleation layer.
根據部分實施例,上述第一閘極、上述第一源極、以及上述第一汲極構成一高壓元件。 According to some embodiments, the first gate electrode, the first source electrode, and the first drain electrode constitute a high-voltage element.
根據部分實施例,上述第二閘極、上述第二源極、以及上述第二汲極構成一低壓元件或一高壓元件。 According to some embodiments, the second gate, the second source, and the second drain constitute a low-voltage element or a high-voltage element.
根據本發明的一實施例,提供一種半導體結構的製造方法。該製造方法包括下列步驟。提供一絕緣基板,其具有一工程化層(engineered layer),包圍該絕緣基板。該絕緣基板包括一第一區與一第二區。形成一成核層(nucleation layer)於該工程化層上。形成一緩衝層於該成核層上。形成一第一磊晶層於該緩衝層上。形成一第二磊晶層於該第一磊晶層上。形成一隔離結構至少於該第二磊晶層、該第一磊晶層、以及該成 核層中。該隔離結構位於該第一區與該第二區之間。形成一第一閘極於該第二磊晶層上,並位於該第一區內。形成一第一源極與一第一汲極於該第二磊晶層上,並位於該第一區內。該第一源極與該第一汲極位於該第一閘極的兩側。形成一第二閘極於該第二磊晶層上,並位於該第二區內。形成一第二源極與一第二汲極於該第二磊晶層上,並位於該第二區內。該第二源極與該第二汲極位於該第二閘極的兩側。 According to an embodiment of the present invention, a method for manufacturing a semiconductor structure is provided. The manufacturing method includes the following steps. An insulating substrate is provided, which has an engineered layer surrounding the insulating substrate. The insulating substrate includes a first region and a second region. A nucleation layer is formed on the engineered layer. A buffer layer is formed on the nucleation layer. A first epitaxial layer is formed on the buffer layer. A second epitaxial layer is formed on the first epitaxial layer. An isolation structure is formed at least in the second epitaxial layer, the first epitaxial layer, and the nucleation layer. The isolation structure is located between the first region and the second region. A first gate is formed on the second epitaxial layer and is located in the first region. A first source electrode and a first drain electrode are formed on the second epitaxial layer and are located in the first region. The first source electrode and the first drain electrode are located on two sides of the first gate electrode. A second gate is formed on the second epitaxial layer and is located in the second region. A second source electrode and a second drain electrode are formed on the second epitaxial layer and are located in the second region. The second source and the second drain are located on both sides of the second gate.
根據部分實施例,藉由蝕刻一溝槽穿過上述第二磊晶層、上述第一磊晶層、上述緩衝層、以及上述成核層,並填入一絕緣材料於上述溝槽內,以形成上述隔離結構。 According to some embodiments, a trench is etched through the second epitaxial layer, the first epitaxial layer, the buffer layer, and the nucleation layer, and an insulating material is filled in the trench, so that The above-mentioned isolation structure is formed.
根據部分實施例,藉由蝕刻一溝槽穿過上述第二磊晶層、上述第一磊晶層、上述緩衝層、上述成核層、以及部份的上述工程化層,並填入一絕緣材料於上述溝槽內,以形成上述隔離結構。 According to some embodiments, a trench is etched through the second epitaxial layer, the first epitaxial layer, the buffer layer, the nucleation layer, and a part of the engineered layer by filling an insulating layer. The material is in the trench to form the isolation structure.
根據部分實施例,藉由蝕刻一溝槽穿過上述第二磊晶層、上述第一磊晶層、上述緩衝層、上述成核層、以及上述工程化層,並填入一絕緣材料於上述溝槽內,以形成上述隔離結構。 According to some embodiments, a trench is etched through the second epitaxial layer, the first epitaxial layer, the buffer layer, the nucleation layer, and the engineered layer, and an insulating material is filled in the above Inside the trench to form the aforementioned isolation structure.
根據部分實施例,藉由實施一第一佈植製程於上述第二磊晶層與上述第一磊晶層上,以形成上述隔離結構。 According to some embodiments, a first implantation process is performed on the second epitaxial layer and the first epitaxial layer to form the isolation structure.
根據部分實施例,更包括藉由實施一第二佈植製程於上述成核層上,以形成上述隔離結構。 According to some embodiments, the method further includes forming a second implantation process on the nucleation layer to form the isolation structure.
根據部分實施例,藉由實施一佈植製程於上述第二磊晶層、上述第一磊晶層、上述緩衝層、以及上述成核層上, 以形成上述隔離結構。 According to some embodiments, an isolation process is formed on the second epitaxial layer, the first epitaxial layer, the buffer layer, and the nucleation layer by implementing an implantation process.
在本發明所揭露的半導體結構中,具有以下適當特性(例如,與電晶體材料層相近的熱膨脹係數(CTE)、高體電阻率、高熱傳導率、以及低成本)且進一步被特定工程化層(例如,氧化物、氮化物、氮氧化物、或多晶矽)所包圍的絕緣核心基板(例如氮化鋁)係用來取代傳統的半導體矽基板。在上述半導體結構中,亦形成有簡單的隔離結構,例如填充有絕緣材料的單一溝槽或分離式的佈植區(包括淺佈植區以及深佈植區),以破壞二維電子氣層(2DEG layer)並阻隔半導體成核層,以確保相鄰元件間不會形成電連接。因此,由於核心基板是絕緣體(不發生背偏壓效應),遂不需在基板上形成偏壓連接,且不需在深溝槽中形成複雜又昂貴的導體以連接成核層或基板。本發明確實提供了簡單的製程步驟以及電連接。此外,以不同電壓施加於其端子的多重元件(例如主動元件及/或被動元件)亦可集積在同一晶粒上。 In the semiconductor structure disclosed in the present invention, it has the following appropriate characteristics (for example, a coefficient of thermal expansion (CTE) similar to that of a transistor material layer, a high bulk resistivity, a high thermal conductivity, and a low cost) and is further specifically engineered. An insulating core substrate (for example, aluminum nitride) surrounded by (for example, oxide, nitride, oxynitride, or polycrystalline silicon) is used to replace a conventional semiconductor silicon substrate. In the above semiconductor structure, a simple isolation structure is also formed, such as a single trench filled with insulating material or a separate implanted area (including a shallow implanted area and a deep implanted area) to destroy the two-dimensional electron gas layer (2DEG layer) and block the semiconductor nucleation layer to ensure that no electrical connection is formed between adjacent components. Therefore, since the core substrate is an insulator (no back bias effect occurs), it is not necessary to form a bias connection on the substrate, and it is not necessary to form a complex and expensive conductor in a deep trench to connect the nucleation layer or the substrate. The invention does provide simple process steps and electrical connections. In addition, multiple components (such as active components and / or passive components) that are applied to their terminals with different voltages can also be accumulated on the same die.
為讓本發明之上述目的、特徵及優點能更明顯易懂,下文特舉一較佳實施例,並配合所附的圖式,作詳細說明如下。 In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows.
10‧‧‧半導體結構 10‧‧‧Semiconductor Structure
12‧‧‧絕緣基板 12‧‧‧ insulated substrate
14‧‧‧工程化層 14‧‧‧Engineering layer
16‧‧‧成核層 16‧‧‧nucleation layer
18‧‧‧緩衝層 18‧‧‧ buffer layer
20‧‧‧第一磊晶層 20‧‧‧First epitaxial layer
22‧‧‧第二磊晶層 22‧‧‧Second epitaxial layer
24‧‧‧隔離結構 24‧‧‧Isolated structure
26‧‧‧第一閘極 26‧‧‧First gate
28‧‧‧第一源極 28‧‧‧ the first source
30‧‧‧第一汲極 30‧‧‧ first drain
32‧‧‧第二閘極 32‧‧‧Second gate
34‧‧‧第二源極 34‧‧‧Second Source
36‧‧‧第二汲極 36‧‧‧Second Drain
38‧‧‧絕緣基板的第一區 38‧‧‧ The first area of the insulating substrate
40‧‧‧絕緣基板的第二區 40‧‧‧ The second area of the insulating substrate
42‧‧‧溝槽 42‧‧‧Trench
44‧‧‧絕緣材料 44‧‧‧Insulation material
46‧‧‧成核層的底表面 46‧‧‧ bottom surface of nucleation layer
48‧‧‧工程化層的上表面 48‧‧‧ upper surface of engineered layer
50‧‧‧高壓元件 50‧‧‧High-voltage components
52‧‧‧低壓元件 52‧‧‧Low-voltage components
54‧‧‧工程化層的底表面 54‧‧‧ the bottom surface of the engineered layer
56‧‧‧絕緣基板的上表面 56‧‧‧ Upper surface of insulating substrate
58‧‧‧第一佈植區 58‧‧‧The first planting area
60‧‧‧第二佈植區 60‧‧‧Second planting area
62‧‧‧連續佈植區 62‧‧‧Continuous planting area
64‧‧‧第一佈植製程 64‧‧‧The first planting process
66‧‧‧第二佈植製程 66‧‧‧The second planting process
第1圖係根據本發明的一實施例,一種半導體結構的剖面示意圖;第2圖係根據本發明的一實施例,一種半導體結構的剖面示意圖; 第3圖係根據本發明的一實施例,一種半導體結構的剖面示意圖;第4圖係根據本發明的一實施例,一種半導體結構的剖面示意圖;第5圖係根據本發明的一實施例,一種半導體結構的剖面示意圖;第6A-6H圖係根據本發明的一實施例,一種半導體結構製造方法的剖面示意圖;第7A-7I圖係根據本發明的一實施例,一種半導體結構製造方法的剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention; FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention; and FIG. 3 is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention. A schematic sectional view of a semiconductor structure; FIG. 4 is a schematic sectional view of a semiconductor structure according to an embodiment of the present invention; FIG. 5 is a schematic sectional view of a semiconductor structure according to an embodiment of the present invention; FIGS. 6A-6H FIG. 7A-7I are schematic cross-sectional views of a method for manufacturing a semiconductor structure according to an embodiment of the present invention.
請參閱第1圖,根據本發明的一實施例,提供一種半導體結構10。第1圖為半導體結構10的剖面示意圖。 Referring to FIG. 1, a semiconductor structure 10 is provided according to an embodiment of the present invention. FIG. 1 is a schematic cross-sectional view of the semiconductor structure 10.
如第1圖所示,在本實施例中,半導體結構10包括絕緣基板12、工程化層(engineered layer)14、成核層(nucleation layer)16、緩衝層18、第一磊晶層20、第二磊晶層22、隔離結構24、第一閘極26、第一源極28、第一汲極30、第二閘極32、第二源極34、以及第二汲極36。 As shown in FIG. 1, in this embodiment, the semiconductor structure 10 includes an insulating substrate 12, an engineered layer 14, a nucleation layer 16, a buffer layer 18, a first epitaxial layer 20, The second epitaxial layer 22, the isolation structure 24, the first gate electrode 26, the first source electrode 28, the first drain electrode 30, the second gate electrode 32, the second source electrode 34, and the second drain electrode 36.
當第一閘極26或第二閘極32為金屬時,包括此金屬閘極的元件即為空乏模式常開型元件(depletion mode normally-on device)。而當第一閘極26或第二閘極32由頂部具有金屬的P型氮化鎵層所構成時,包括此P型氮化鎵閘極的元件即為增強模式常關型元件(enhancement mode normally-off device)。 When the first gate electrode 26 or the second gate electrode 32 is metal, the element including the metal gate electrode is a depletion mode normally-on device. When the first gate 26 or the second gate 32 is composed of a P-type GaN layer with a metal on top, an element including the P-type GaN gate is an enhancement mode normally-off element. normally-off device).
如第1圖所示,絕緣基板12包括第一區38與第二區40。工程化層14包圍絕緣基板12。成核層16形成於工程化層14上。緩衝層18形成於成核層16上。第一磊晶層20形成於緩衝層18上。第二磊晶層22形成於第一磊晶層20上。值得注意的是,隔離結構24至少形成於第二磊晶層22、第一磊晶層20、以及成核層16中。隔離結構24位於第一區38與第二區40之間。第一閘極26形成於第二磊晶層22上,並位於第一區38內。第一源極28與第一汲極30形成於第二磊晶層22上,並位於第一區38內。第一源極28與第一汲極30位於第一閘極26的兩側。此外,第二閘極32形成於第二磊晶層22上,並位於第二區40內。第二源極34與第二汲極36形成於第二磊晶層22上,並位於第二區40內。第二源極34與第二汲極36位於第二閘極32的兩側。 As shown in FIG. 1, the insulating substrate 12 includes a first region 38 and a second region 40. The engineering layer 14 surrounds the insulating substrate 12. A nucleation layer 16 is formed on the engineered layer 14. The buffer layer 18 is formed on the nucleation layer 16. The first epitaxial layer 20 is formed on the buffer layer 18. The second epitaxial layer 22 is formed on the first epitaxial layer 20. It is worth noting that the isolation structure 24 is formed at least in the second epitaxial layer 22, the first epitaxial layer 20, and the nucleation layer 16. The isolation structure 24 is located between the first region 38 and the second region 40. The first gate electrode 26 is formed on the second epitaxial layer 22 and is located in the first region 38. The first source electrode 28 and the first drain electrode 30 are formed on the second epitaxial layer 22 and are located in the first region 38. The first source electrode 28 and the first drain electrode 30 are located on both sides of the first gate electrode 26. In addition, the second gate electrode 32 is formed on the second epitaxial layer 22 and is located in the second region 40. The second source electrode 34 and the second drain electrode 36 are formed on the second epitaxial layer 22 and are located in the second region 40. The second source electrode 34 and the second drain electrode 36 are located on both sides of the second gate electrode 32.
根據部分實施例,絕緣基板12的熱膨脹係數(coefficient of thermal expansion,CTE)與第一磊晶層20的熱膨脹係數大致相同或相近。 According to some embodiments, the coefficient of thermal expansion (CTE) of the insulating substrate 12 is substantially the same as or similar to that of the first epitaxial layer 20.
根據部分實施例,絕緣基板12的體電阻率(bulk resistivity)大約大於106ohm-cm。 According to some embodiments, the bulk resistivity of the insulating substrate 12 is greater than about 10 6 ohm-cm.
根據部分實施例,絕緣基板12的熱傳導率(thermal conductivity)大約高於矽的熱傳導率。 According to some embodiments, the thermal conductivity of the insulating substrate 12 is approximately higher than the thermal conductivity of silicon.
根據部分實施例,絕緣基板12可包括氮化鋁、多晶碳化矽(polycrystalline silicon carbide)、多晶鑽石(polycrystalline diamond)、或其混合物、或不同多晶材料的混合物、或其他適合的絕緣材料。 According to some embodiments, the insulating substrate 12 may include aluminum nitride, polycrystalline silicon carbide, polycrystalline diamond, or a mixture thereof, or a mixture of different polycrystalline materials, or other suitable insulating materials. .
根據部分實施例,工程化層14可包括氮化物、氧 化物、氮氧化物、或多晶矽。 According to some embodiments, the engineered layer 14 may include nitride, oxide, oxynitride, or polycrystalline silicon.
根據部分實施例,成核層16可包括矽<111>。 According to some embodiments, the nucleation layer 16 may include silicon <111>.
根據部分實施例,成核層16可為結晶型。 According to some embodiments, the nucleation layer 16 may be crystalline.
根據部分實施例,成核層16的厚度大約介於0.1微米至5微米。 According to some embodiments, the thickness of the nucleation layer 16 is between about 0.1 micrometers and 5 micrometers.
根據部分實施例,成核層16的晶格常數相對接近成長於其上的磊晶層(例如氮化鎵)的晶格常數。 According to some embodiments, the lattice constant of the nucleation layer 16 is relatively close to the lattice constant of an epitaxial layer (eg, gallium nitride) grown thereon.
根據部分實施例,緩衝層18可包括氮化鎵鋁或氮化鋁。 According to some embodiments, the buffer layer 18 may include aluminum gallium nitride or aluminum nitride.
根據部分實施例,第一磊晶層20可包括氮化鎵。 According to some embodiments, the first epitaxial layer 20 may include gallium nitride.
根據部分實施例,第二磊晶層22可包括氮化鎵鋁。 According to some embodiments, the second epitaxial layer 22 may include gallium aluminum nitride.
根據部分實施例,隔離結構24可包括填入有絕緣材料的溝槽或佈植區。 According to some embodiments, the isolation structure 24 may include a trench or an implanted region filled with an insulating material.
在本實施例中,隔離結構24包括溝槽42,填入有絕緣材料44,其穿過第二磊晶層22、第一磊晶層20、緩衝層18、以及成核層16。也就是,隔離結構24從第二磊晶層22延伸至成核層16的底表面46(亦即工程化層14的上表面48)。 In this embodiment, the isolation structure 24 includes a trench 42 filled with an insulating material 44 that passes through the second epitaxial layer 22, the first epitaxial layer 20, the buffer layer 18, and the nucleation layer 16. That is, the isolation structure 24 extends from the second epitaxial layer 22 to the bottom surface 46 of the nucleation layer 16 (ie, the upper surface 48 of the engineered layer 14).
根據部分實施例,填入溝槽42的絕緣材料44可包括氧化物、氮化物與其上的氧化物、或氧化物與其上的多晶矽。 According to some embodiments, the insulating material 44 filling the trench 42 may include an oxide, a nitride and an oxide thereon, or an oxide and polycrystalline silicon thereon.
根據部分實施例,溝槽42可在其中留下“氣隙”或“空隙”,只要溝槽42的頂部是“密封的”,如此,就不會有材料掉落或陷入溝槽42內。 According to some embodiments, the trench 42 may leave an “air gap” or “gap” therein, as long as the top of the trench 42 is “sealed” so that no material will fall or sink into the trench 42.
根據部分實施例,第一閘極26、第一源極28、以及第一汲極30構成高壓元件50。 According to some embodiments, the first gate electrode 26, the first source electrode 28, and the first drain electrode 30 constitute a high-voltage element 50.
根據部分實施例,第二閘極32、第二源極34、以及第二汲極36構成低壓元件52。 According to some embodiments, the second gate electrode 32, the second source electrode 34, and the second drain electrode 36 constitute a low-voltage element 52.
請參閱第2圖,根據本發明的一實施例,提供一種半導體結構10。第2圖為半導體結構10的剖面示意圖。 Referring to FIG. 2, a semiconductor structure 10 is provided according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the semiconductor structure 10.
如第2圖所示,在本實施例中,半導體結構10包括絕緣基板12、工程化層(engineered layer)14、成核層(nucleation 1ayer)16、緩衝層18、第一磊晶層20、第二磊晶層22、隔離結構24、第一閘極26、第一源極28、第一汲極30、第二閘極32、第二源極34、以及第二汲極36。 As shown in FIG. 2, in this embodiment, the semiconductor structure 10 includes an insulating substrate 12, an engineered layer 14, a nucleation layer 16, a buffer layer 18, a first epitaxial layer 20, The second epitaxial layer 22, the isolation structure 24, the first gate electrode 26, the first source electrode 28, the first drain electrode 30, the second gate electrode 32, the second source electrode 34, and the second drain electrode 36.
如第2圖所示,絕緣基板12包括第一區38與第二區40。工程化層14包圍絕緣基板12。成核層16形成於工程化層14上。緩衝層18形成於成核層16上。第一磊晶層20形成於緩衝層18上。第二磊晶層22形成於第一磊晶層20上。值得注意的是,隔離結構24至少形成於第二磊晶層22、第一磊晶層20、以及成核層16中。隔離結構24位於第一區38與第二區40之間。第一閘極26形成於第二磊晶層22上,並位於第一區38內。第一源極28與第一汲極30形成於第二磊晶層22上,並位於第一區38內。第一源極28與第一汲極30位於第一閘極26的兩側。此外,第二閘極32形成於第二磊晶層22上,並位於第二區40內。第二源極34與第二汲極36形成於第二磊晶層22上,並位於第二區40內。第二源極34與第二汲極36位於第二閘極32的兩側。 As shown in FIG. 2, the insulating substrate 12 includes a first region 38 and a second region 40. The engineering layer 14 surrounds the insulating substrate 12. A nucleation layer 16 is formed on the engineered layer 14. The buffer layer 18 is formed on the nucleation layer 16. The first epitaxial layer 20 is formed on the buffer layer 18. The second epitaxial layer 22 is formed on the first epitaxial layer 20. It is worth noting that the isolation structure 24 is formed at least in the second epitaxial layer 22, the first epitaxial layer 20, and the nucleation layer 16. The isolation structure 24 is located between the first region 38 and the second region 40. The first gate electrode 26 is formed on the second epitaxial layer 22 and is located in the first region 38. The first source electrode 28 and the first drain electrode 30 are formed on the second epitaxial layer 22 and are located in the first region 38. The first source electrode 28 and the first drain electrode 30 are located on both sides of the first gate electrode 26. In addition, the second gate electrode 32 is formed on the second epitaxial layer 22 and is located in the second region 40. The second source electrode 34 and the second drain electrode 36 are formed on the second epitaxial layer 22 and are located in the second region 40. The second source electrode 34 and the second drain electrode 36 are located on both sides of the second gate electrode 32.
根據部分實施例,絕緣基板12的熱膨脹係數 (coefficient of thermal expansion,CTE)與第一磊晶層20的熱膨脹係數大致相同或相近。 According to some embodiments, the coefficient of thermal expansion (CTE) of the insulating substrate 12 is substantially the same as or similar to that of the first epitaxial layer 20.
根據部分實施例,絕緣基板12的體電阻率(bulk resistivity)大約大於106ohm-cm。 According to some embodiments, the bulk resistivity of the insulating substrate 12 is greater than about 10 6 ohm-cm.
根據部分實施例,絕緣基板12的熱傳導率(thermal conductivity)大約高於矽的熱傳導率。 According to some embodiments, the thermal conductivity of the insulating substrate 12 is approximately higher than the thermal conductivity of silicon.
根據部分實施例,絕緣基板12可包括氮化鋁、多晶碳化矽(polycrystalline silicon carbide)、多晶鑽石(polycrystalline diamond)、或其混合物、或不同多晶材料的混合物、或其他適合的絕緣材料。 According to some embodiments, the insulating substrate 12 may include aluminum nitride, polycrystalline silicon carbide, polycrystalline diamond, or a mixture thereof, or a mixture of different polycrystalline materials, or other suitable insulating materials. .
根據部分實施例,工程化層14可包括氮化物、氧化物、氮氧化物、或多晶矽。 According to some embodiments, the engineered layer 14 may include nitride, oxide, oxynitride, or polycrystalline silicon.
根據部分實施例,成核層16可包括矽<111>。 According to some embodiments, the nucleation layer 16 may include silicon <111>.
根據部分實施例,成核層16可為結晶型。 According to some embodiments, the nucleation layer 16 may be crystalline.
根據部分實施例,成核層16的厚度大約介於0.1微米至5微米。 According to some embodiments, the thickness of the nucleation layer 16 is between about 0.1 micrometers and 5 micrometers.
根據部分實施例,成核層16的晶格常數相對接近成長於其上的磊晶層(例如氮化鎵)的晶格常數。 According to some embodiments, the lattice constant of the nucleation layer 16 is relatively close to the lattice constant of an epitaxial layer (eg, gallium nitride) grown thereon.
根據部分實施例,緩衝層18可包括氮化鎵鋁或氮化鋁。 According to some embodiments, the buffer layer 18 may include aluminum gallium nitride or aluminum nitride.
根據部分實施例,第一磊晶層20可包括氮化鎵。 According to some embodiments, the first epitaxial layer 20 may include gallium nitride.
根據部分實施例,第二磊晶層22可包括氮化鎵鋁。 According to some embodiments, the second epitaxial layer 22 may include gallium aluminum nitride.
根據部分實施例,隔離結構24可包括填入有絕緣 材料的溝槽或佈植區。 According to some embodiments, the isolation structure 24 may include a trench or an implanted region filled with an insulating material.
在本實施例中,隔離結構24包括溝槽42,填入有絕緣材料44,其穿過第二磊晶層22、第一磊晶層20、緩衝層18、成核層16、以及部分的工程化層14。也就是,隔離結構24從第二磊晶層22延伸至工程化層14中的任一處。 In this embodiment, the isolation structure 24 includes a trench 42 filled with an insulating material 44 that passes through the second epitaxial layer 22, the first epitaxial layer 20, the buffer layer 18, the nucleation layer 16, and a portion Engineering layer 14. That is, the isolation structure 24 extends from the second epitaxial layer 22 to any of the engineered layers 14.
根據部分實施例,填入溝槽42的絕緣材料44可包括氧化物、氮化物與其上的氧化物、或氧化物與其上的多晶矽。 According to some embodiments, the insulating material 44 filling the trench 42 may include an oxide, a nitride and an oxide thereon, or an oxide and polycrystalline silicon thereon.
根據部分實施例,溝槽42可在其中留下“氣隙”或“空隙”,只要溝槽42的頂部是“密封的”,如此,就不會有材料掉落或陷入溝槽42內。 According to some embodiments, the trench 42 may leave an “air gap” or “gap” therein, as long as the top of the trench 42 is “sealed” so that no material will fall or sink into the trench 42.
根據部分實施例,第一閘極26、第一源極28、以及第一汲極30構成高壓元件50。 According to some embodiments, the first gate electrode 26, the first source electrode 28, and the first drain electrode 30 constitute a high-voltage element 50.
根據部分實施例,第二閘極32、第二源極34、以及第二汲極36構成低壓元件52。 According to some embodiments, the second gate electrode 32, the second source electrode 34, and the second drain electrode 36 constitute a low-voltage element 52.
請參閱第3圖,根據本發明的一實施例,提供一種半導體結構10。第3圖為半導體結構10的剖面示意圖。 Referring to FIG. 3, a semiconductor structure 10 is provided according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of the semiconductor structure 10.
如第3圖所示,在本實施例中,半導體結構10包括絕緣基板12、工程化層(engineered layer)14、成核層(nucleation layer)16、緩衝層18、第一磊晶層20、第二磊晶層22、隔離結構24、第一閘極26、第一源極28、第一汲極30、第二閘極32、第二源極34、以及第二汲極36。 As shown in FIG. 3, in this embodiment, the semiconductor structure 10 includes an insulating substrate 12, an engineered layer 14, a nucleation layer 16, a buffer layer 18, a first epitaxial layer 20, The second epitaxial layer 22, the isolation structure 24, the first gate electrode 26, the first source electrode 28, the first drain electrode 30, the second gate electrode 32, the second source electrode 34, and the second drain electrode 36.
如第3圖所示,絕緣基板12包括第一區38與第二區40。工程化層14包圍絕緣基板12。成核層16形成於工程化層14 上。緩衝層18形成於成核層16上。第一磊晶層20形成於緩衝層18上。第二磊晶層22形成於第一磊晶層20上。值得注意的是,隔離結構24至少形成於第二磊晶層22、第一磊晶層20、以及成核層16中。隔離結構24位於第一區38與第二區40之間。第一閘極26形成於第二磊晶層22上,並位於第一區38內。第一源極28與第一汲極30形成於第二磊晶層22上,並位於第一區38內。第一源極28與第一汲極30位於第一閘極26的兩側。此外,第二閘極32形成於第二磊晶層22上,並位於第二區40內。第二源極34與第二汲極36形成於第二磊晶層22上,並位於第二區40內。第二源極34與第二汲極36位於第二閘極32的兩側。 As shown in FIG. 3, the insulating substrate 12 includes a first region 38 and a second region 40. The engineering layer 14 surrounds the insulating substrate 12. A nucleation layer 16 is formed on the engineered layer 14. The buffer layer 18 is formed on the nucleation layer 16. The first epitaxial layer 20 is formed on the buffer layer 18. The second epitaxial layer 22 is formed on the first epitaxial layer 20. It is worth noting that the isolation structure 24 is formed at least in the second epitaxial layer 22, the first epitaxial layer 20, and the nucleation layer 16. The isolation structure 24 is located between the first region 38 and the second region 40. The first gate electrode 26 is formed on the second epitaxial layer 22 and is located in the first region 38. The first source electrode 28 and the first drain electrode 30 are formed on the second epitaxial layer 22 and are located in the first region 38. The first source electrode 28 and the first drain electrode 30 are located on both sides of the first gate electrode 26. In addition, the second gate electrode 32 is formed on the second epitaxial layer 22 and is located in the second region 40. The second source electrode 34 and the second drain electrode 36 are formed on the second epitaxial layer 22 and are located in the second region 40. The second source electrode 34 and the second drain electrode 36 are located on both sides of the second gate electrode 32.
根據部分實施例,絕緣基板12的熱膨脹係數(coefficient of thermal expansion,CTE)與第一磊晶層20的熱膨脹係數大致相同或相近。 According to some embodiments, the coefficient of thermal expansion (CTE) of the insulating substrate 12 is substantially the same as or similar to that of the first epitaxial layer 20.
根據部分實施例,絕緣基板12的體電阻率(bulk resistivity)大約大於106ohm-cm。 According to some embodiments, the bulk resistivity of the insulating substrate 12 is greater than about 10 6 ohm-cm.
根據部分實施例,絕緣基板12的熱傳導率(thermal conductivity)大約高於矽的熱傳導率。 According to some embodiments, the thermal conductivity of the insulating substrate 12 is approximately higher than the thermal conductivity of silicon.
根據部分實施例,絕緣基板12可包括氮化鋁、多晶碳化矽(polycrystalline silicon carbide)、多晶鑽石(polycrystalline diamond)、或其混合物、或不同多晶材料的混合物、或其他適合的絕緣材料。 According to some embodiments, the insulating substrate 12 may include aluminum nitride, polycrystalline silicon carbide, polycrystalline diamond, or a mixture thereof, or a mixture of different polycrystalline materials, or other suitable insulating materials. .
根據部分實施例,工程化層14可包括氮化物、氧化物、氮氧化物、或多晶矽。 According to some embodiments, the engineered layer 14 may include nitride, oxide, oxynitride, or polycrystalline silicon.
根據部分實施例,成核層16可包括矽<111>。 According to some embodiments, the nucleation layer 16 may include silicon <111>.
根據部分實施例,成核層16可為結晶型。 According to some embodiments, the nucleation layer 16 may be crystalline.
根據部分實施例,成核層16的厚度大約介於0.1微米至5微米。 According to some embodiments, the thickness of the nucleation layer 16 is between about 0.1 micrometers and 5 micrometers.
根據部分實施例,成核層16的晶格常數相對接近成長於其上的磊晶層(例如氮化鎵)的晶格常數。 According to some embodiments, the lattice constant of the nucleation layer 16 is relatively close to the lattice constant of an epitaxial layer (eg, gallium nitride) grown thereon.
根據部分實施例,緩衝層18可包括氮化鎵鋁或氮化鋁。 According to some embodiments, the buffer layer 18 may include aluminum gallium nitride or aluminum nitride.
根據部分實施例,第一磊晶層20可包括氮化鎵。 According to some embodiments, the first epitaxial layer 20 may include gallium nitride.
根據部分實施例,第二磊晶層22可包括氮化鎵鋁。 According to some embodiments, the second epitaxial layer 22 may include gallium aluminum nitride.
根據部分實施例,隔離結構24可包括填入有絕緣材料的溝槽或佈植區。 According to some embodiments, the isolation structure 24 may include a trench or an implanted region filled with an insulating material.
在本實施例中,隔離結構24包括溝槽42,填入有絕緣材料44,其穿過第二磊晶層22、第一磊晶層20、緩衝層18、成核層16、以及工程化層14。也就是,隔離結構24從第二磊晶層22延伸至工程化層14的底表面54(亦即絕緣基板12的上表面56)。 In this embodiment, the isolation structure 24 includes a trench 42 filled with an insulating material 44 that passes through the second epitaxial layer 22, the first epitaxial layer 20, the buffer layer 18, the nucleation layer 16, and the engineering Layer 14. That is, the isolation structure 24 extends from the second epitaxial layer 22 to the bottom surface 54 of the engineering layer 14 (ie, the upper surface 56 of the insulating substrate 12).
根據部分實施例,填入溝槽42的絕緣材料44可包括氧化物、氮化物與其上的氧化物、或氧化物與其上的多晶矽。 According to some embodiments, the insulating material 44 filling the trench 42 may include an oxide, a nitride and an oxide thereon, or an oxide and polycrystalline silicon thereon.
根據部分實施例,溝槽42可在其中留下“氣隙”或“空隙”,只要溝槽42的頂部是“密封的”,如此,就不會有材料掉落或陷入溝槽42內。 According to some embodiments, the trench 42 may leave an “air gap” or “gap” therein, as long as the top of the trench 42 is “sealed” so that no material will fall or sink into the trench 42.
根據部分實施例,第一閘極26、第一源極28、以 及第一汲極30構成高壓元件50。 According to some embodiments, the first gate electrode 26, the first source electrode 28, and the first drain electrode 30 constitute a high-voltage element 50.
根據部分實施例,第二閘極32、第二源極34、以及第二汲極36構成低壓元件52。 According to some embodiments, the second gate electrode 32, the second source electrode 34, and the second drain electrode 36 constitute a low-voltage element 52.
請參閱第4圖,根據本發明的一實施例,提供一種半導體結構10。第4圖為半導體結構10的剖面示意圖。 Referring to FIG. 4, a semiconductor structure 10 is provided according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of the semiconductor structure 10.
如第4圖所示,在本實施例中,半導體結構10包括絕緣基板12、工程化層(engineered layer)14、成核層(nucleation layer)16、緩衝層18、第一磊晶層20、第二磊晶層22、隔離結構24、第一閘極26、第一源極28、第一汲極30、第二閘極32、第二源極34、以及第二汲極36。 As shown in FIG. 4, in this embodiment, the semiconductor structure 10 includes an insulating substrate 12, an engineered layer 14, a nucleation layer 16, a buffer layer 18, a first epitaxial layer 20, The second epitaxial layer 22, the isolation structure 24, the first gate electrode 26, the first source electrode 28, the first drain electrode 30, the second gate electrode 32, the second source electrode 34, and the second drain electrode 36.
如第4圖所示,絕緣基板12包括第一區38與第二區40。工程化層14包圍絕緣基板12。成核層16形成於工程化層14上。緩衝層18形成於成核層16上。第一磊晶層20形成於緩衝層18上。第二磊晶層22形成於第一磊晶層20上。值得注意的是,隔離結構24至少形成於第二磊晶層22、第一磊晶層20、以及成核層16中。隔離結構24位於第一區38與第二區40之間。第一閘極26形成於第二磊晶層22上,並位於第一區38內。第一源極28與第一汲極30形成於第二磊晶層22上,並位於第一區38內。第一源極28與第一汲極30位於第一閘極26的兩側。此外,第二閘極32形成於第二磊晶層22上,並位於第二區40內。第二源極34與第二汲極36形成於第二磊晶層22上,並位於第二區40內。第二源極34與第二汲極36位於第二閘極32的兩側。 As shown in FIG. 4, the insulating substrate 12 includes a first region 38 and a second region 40. The engineering layer 14 surrounds the insulating substrate 12. A nucleation layer 16 is formed on the engineered layer 14. The buffer layer 18 is formed on the nucleation layer 16. The first epitaxial layer 20 is formed on the buffer layer 18. The second epitaxial layer 22 is formed on the first epitaxial layer 20. It is worth noting that the isolation structure 24 is formed at least in the second epitaxial layer 22, the first epitaxial layer 20, and the nucleation layer 16. The isolation structure 24 is located between the first region 38 and the second region 40. The first gate electrode 26 is formed on the second epitaxial layer 22 and is located in the first region 38. The first source electrode 28 and the first drain electrode 30 are formed on the second epitaxial layer 22 and are located in the first region 38. The first source electrode 28 and the first drain electrode 30 are located on both sides of the first gate electrode 26. In addition, the second gate electrode 32 is formed on the second epitaxial layer 22 and is located in the second region 40. The second source electrode 34 and the second drain electrode 36 are formed on the second epitaxial layer 22 and are located in the second region 40. The second source electrode 34 and the second drain electrode 36 are located on both sides of the second gate electrode 32.
根據部分實施例,絕緣基板12的熱膨脹係數(coefficient of thermal expansion,CTE)與第一磊晶層20的熱膨 脹係數大致相同或相近。 According to some embodiments, the coefficient of thermal expansion (CTE) of the insulating substrate 12 is substantially the same as or similar to that of the first epitaxial layer 20.
根據部分實施例,絕緣基板12的體電阻率(bulk resistivity)大約大於106ohm-cm。 According to some embodiments, the bulk resistivity of the insulating substrate 12 is greater than about 10 6 ohm-cm.
根據部分實施例,絕緣基板12的熱傳導率(thermal conductivity)大約高於矽的熱傳導率。 According to some embodiments, the thermal conductivity of the insulating substrate 12 is approximately higher than the thermal conductivity of silicon.
根據部分實施例,絕緣基板12可包括氮化鋁、多晶碳化矽(polycrystalline silicon carbide)、多晶鑽石(polycrystalline diamond)、或其混合物、或不同多晶材料的混合物、或其他適合的絕緣材料。 According to some embodiments, the insulating substrate 12 may include aluminum nitride, polycrystalline silicon carbide, polycrystalline diamond, or a mixture thereof, or a mixture of different polycrystalline materials, or other suitable insulating materials. .
根據部分實施例,工程化層14可包括氮化物、氧化物、氮氧化物、或多晶矽。 According to some embodiments, the engineered layer 14 may include nitride, oxide, oxynitride, or polycrystalline silicon.
根據部分實施例,成核層16可包括矽<111>。 According to some embodiments, the nucleation layer 16 may include silicon <111>.
根據部分實施例,成核層16可為結晶型。 According to some embodiments, the nucleation layer 16 may be crystalline.
根據部分實施例,成核層16的厚度大約介於0.1微米至5微米。 According to some embodiments, the thickness of the nucleation layer 16 is between about 0.1 micrometers and 5 micrometers.
根據部分實施例,成核層16的晶格常數相對接近成長於其上的磊晶層(例如氮化鎵)的晶格常數。 According to some embodiments, the lattice constant of the nucleation layer 16 is relatively close to the lattice constant of an epitaxial layer (eg, gallium nitride) grown thereon.
根據部分實施例,緩衝層18可包括氮化鎵鋁或氮化鋁。 According to some embodiments, the buffer layer 18 may include aluminum gallium nitride or aluminum nitride.
根據部分實施例,第一磊晶層20可包括氮化鎵。 According to some embodiments, the first epitaxial layer 20 may include gallium nitride.
根據部分實施例,第二磊晶層22可包括氮化鎵鋁。 According to some embodiments, the second epitaxial layer 22 may include gallium aluminum nitride.
根據部分實施例,隔離結構24可包括填入有絕緣材料的溝槽或佈植區。 According to some embodiments, the isolation structure 24 may include a trench or an implanted region filled with an insulating material.
在本實施例中,隔離結構24包括第一佈植區58與第二佈植區60。值得注意的是,第一佈植區58(亦即淺佈植區)位於第二磊晶層22與第一磊晶層20中。第二佈植區60(亦即深佈植區)位於成核層16中。 In this embodiment, the isolation structure 24 includes a first planting area 58 and a second planting area 60. It is worth noting that the first implantation region 58 (ie, the shallow implantation region) is located in the second epitaxial layer 22 and the first epitaxial layer 20. A second implantation area 60 (ie, a deep implantation area) is located in the nucleation layer 16.
根據部分實施例,第一佈植區58與第二佈植區60可包括氧或氮。 According to some embodiments, the first and second implantation areas 58 and 60 may include oxygen or nitrogen.
根據部分實施例,第一閘極26、第一源極28、以及第一汲極30構成高壓元件50。 According to some embodiments, the first gate electrode 26, the first source electrode 28, and the first drain electrode 30 constitute a high-voltage element 50.
根據部分實施例,第二閘極32、第二源極34、以及第二汲極36構成低壓元件52。 According to some embodiments, the second gate electrode 32, the second source electrode 34, and the second drain electrode 36 constitute a low-voltage element 52.
請參閱第5圖,根據本發明的一實施例,提供一種半導體結構10。第5圖為半導體結構10的剖面示意圖。 Referring to FIG. 5, a semiconductor structure 10 is provided according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of the semiconductor structure 10.
如第5圖所示,在本實施例中,半導體結構10包括絕緣基板12、工程化層(engineered layer)14、成核層(nucleation layer)16、緩衝層18、第一磊晶層20、第二磊晶層22、隔離結構24、第一閘極26、第一源極28、第一汲極30、第二閘極32、第二源極34、以及第二汲極36。 As shown in FIG. 5, in this embodiment, the semiconductor structure 10 includes an insulating substrate 12, an engineered layer 14, a nucleation layer 16, a buffer layer 18, a first epitaxial layer 20, The second epitaxial layer 22, the isolation structure 24, the first gate electrode 26, the first source electrode 28, the first drain electrode 30, the second gate electrode 32, the second source electrode 34, and the second drain electrode 36.
如第5圖所示,絕緣基板12包括第一區38與第二區40。工程化層14包圍絕緣基板12。成核層16形成於工程化層14上。緩衝層18形成於成核層16上。第一磊晶層20形成於緩衝層18上。第二磊晶層22形成於第一磊晶層20上。值得注意的是,隔離結構24至少形成於第二磊晶層22、第一磊晶層20、以及成核層16中。隔離結構24位於第一區38與第二區40之間。第一閘極26形成於第二磊晶層22上,並位於第一區38內。第一源極28 與第一汲極30形成於第二磊晶層22上,並位於第一區38內。第一源極28與第一汲極30位於第一閘極26的兩側。此外,第二閘極32形成於第二磊晶層22上,並位於第二區40內。第二源極34與第二汲極36形成於第二磊晶層22上,並位於第二區40內。第二源極34與第二汲極36位於第二閘極32的兩側。 As shown in FIG. 5, the insulating substrate 12 includes a first region 38 and a second region 40. The engineering layer 14 surrounds the insulating substrate 12. A nucleation layer 16 is formed on the engineered layer 14. The buffer layer 18 is formed on the nucleation layer 16. The first epitaxial layer 20 is formed on the buffer layer 18. The second epitaxial layer 22 is formed on the first epitaxial layer 20. It is worth noting that the isolation structure 24 is formed at least in the second epitaxial layer 22, the first epitaxial layer 20, and the nucleation layer 16. The isolation structure 24 is located between the first region 38 and the second region 40. The first gate electrode 26 is formed on the second epitaxial layer 22 and is located in the first region 38. The first source electrode 28 and the first drain electrode 30 are formed on the second epitaxial layer 22 and are located in the first region 38. The first source electrode 28 and the first drain electrode 30 are located on both sides of the first gate electrode 26. In addition, the second gate electrode 32 is formed on the second epitaxial layer 22 and is located in the second region 40. The second source electrode 34 and the second drain electrode 36 are formed on the second epitaxial layer 22 and are located in the second region 40. The second source electrode 34 and the second drain electrode 36 are located on both sides of the second gate electrode 32.
根據部分實施例,絕緣基板12的熱膨脹係數(coefficient of thermal expansion,CTE)與第一磊晶層20的熱膨脹係數大致相同或相近。 According to some embodiments, the coefficient of thermal expansion (CTE) of the insulating substrate 12 is substantially the same as or similar to that of the first epitaxial layer 20.
根據部分實施例,絕緣基板12的體電阻率(bulk resistivity)大約大於106ohm-cm。 According to some embodiments, the bulk resistivity of the insulating substrate 12 is greater than about 10 6 ohm-cm.
根據部分實施例,絕緣基板12的熱傳導率(thermal conductivity)大約高於矽的熱傳導率。 According to some embodiments, the thermal conductivity of the insulating substrate 12 is approximately higher than the thermal conductivity of silicon.
根據部分實施例,絕緣基板12可包括氮化鋁、多晶碳化矽(polycrystalline silicon carbide)、多晶鑽石(polycrystalline diamond)、或其混合物、或不同多晶材料的混合物、或其他適合的絕緣材料。 According to some embodiments, the insulating substrate 12 may include aluminum nitride, polycrystalline silicon carbide, polycrystalline diamond, or a mixture thereof, or a mixture of different polycrystalline materials, or other suitable insulating materials. .
根據部分實施例,工程化層14可包括氮化物、氧化物、氮氧化物、或多晶矽。 According to some embodiments, the engineered layer 14 may include nitride, oxide, oxynitride, or polycrystalline silicon.
根據部分實施例,成核層16可包括矽<111>。 According to some embodiments, the nucleation layer 16 may include silicon <111>.
根據部分實施例,成核層16可為結晶型。 According to some embodiments, the nucleation layer 16 may be crystalline.
根據部分實施例,成核層16的厚度大約介於0.1微米至5微米。 According to some embodiments, the thickness of the nucleation layer 16 is between about 0.1 micrometers and 5 micrometers.
根據部分實施例,成核層16的晶格常數相對接近成長於其上的磊晶層(例如氮化鎵)的晶格常數。 According to some embodiments, the lattice constant of the nucleation layer 16 is relatively close to the lattice constant of an epitaxial layer (eg, gallium nitride) grown thereon.
根據部分實施例,緩衝層18可包括氮化鎵鋁或氮化鋁。 According to some embodiments, the buffer layer 18 may include aluminum gallium nitride or aluminum nitride.
根據部分實施例,第一磊晶層20可包括氮化鎵。 According to some embodiments, the first epitaxial layer 20 may include gallium nitride.
根據部分實施例,第二磊晶層22可包括氮化鎵鋁。 According to some embodiments, the second epitaxial layer 22 may include gallium aluminum nitride.
根據部分實施例,隔離結構24可包括填入有絕緣材料的溝槽或佈植區。 According to some embodiments, the isolation structure 24 may include a trench or an implanted region filled with an insulating material.
在本實施例中,隔離結構24包括連續佈植區62,其覆蓋第二磊晶層22、第一磊晶層20、緩衝層18、以及成核層16。 In this embodiment, the isolation structure 24 includes a continuous implantation region 62 that covers the second epitaxial layer 22, the first epitaxial layer 20, the buffer layer 18, and the nucleation layer 16.
根據部分實施例,連續佈植區62可包括氧或氮。 According to some embodiments, the continuous implantation area 62 may include oxygen or nitrogen.
根據部分實施例,第一閘極26、第一源極28、以及第一汲極30構成高壓元件50。 According to some embodiments, the first gate electrode 26, the first source electrode 28, and the first drain electrode 30 constitute a high-voltage element 50.
根據部分實施例,第二閘極32、第二源極34、以及第二汲極36構成低壓元件52。 According to some embodiments, the second gate electrode 32, the second source electrode 34, and the second drain electrode 36 constitute a low-voltage element 52.
請參閱第6A-6H圖,根據本發明的一實施例,提供一種半導體結構10的製造方法。第6A-6H圖為半導體結構10製造方法的剖面示意圖。 Please refer to FIGS. 6A-6H. According to an embodiment of the present invention, a method for manufacturing a semiconductor structure 10 is provided. 6A-6H are schematic cross-sectional views of a method for manufacturing the semiconductor structure 10.
如第6A圖所示,提供絕緣基板12,其具有工程化層(engineered layer)14,包圍絕緣基板12。絕緣基板12包括第一區38與第二區40。 As shown in FIG. 6A, an insulating substrate 12 is provided, which has an engineered layer 14 surrounding the insulating substrate 12. The insulating substrate 12 includes a first region 38 and a second region 40.
根據部分實施例,絕緣基板12的熱膨脹係數(coefficient of thermal expansion,CTE)與第一磊晶層20的熱膨脹係數大致相同或相近。 According to some embodiments, the coefficient of thermal expansion (CTE) of the insulating substrate 12 is substantially the same as or similar to that of the first epitaxial layer 20.
根據部分實施例,絕緣基板12的體電阻率(bulk resistivity)大約大於106ohm-cm。 According to some embodiments, the bulk resistivity of the insulating substrate 12 is greater than about 10 6 ohm-cm.
根據部分實施例,絕緣基板12的熱傳導率(thermal conductivity)大約高於矽的熱傳導率。 According to some embodiments, the thermal conductivity of the insulating substrate 12 is approximately higher than the thermal conductivity of silicon.
根據部分實施例,絕緣基板12可包括氮化鋁、多晶碳化矽(polycrystalline silicon carbide)、多晶鑽石(polycrystalline diamond)、或其混合物、或不同多晶材料的混合物、或其他適合的絕緣材料。 According to some embodiments, the insulating substrate 12 may include aluminum nitride, polycrystalline silicon carbide, polycrystalline diamond, or a mixture thereof, or a mixture of different polycrystalline materials, or other suitable insulating materials. .
根據部分實施例,工程化層14可包括氮化物、氧化物、氮氧化物、或多晶矽。 According to some embodiments, the engineered layer 14 may include nitride, oxide, oxynitride, or polycrystalline silicon.
之後,如第6B圖所示,藉由適當的沉積製程形成成核層(nucleation layer)16於工程化層14上。 Thereafter, as shown in FIG. 6B, a nucleation layer 16 is formed on the engineering layer 14 by an appropriate deposition process.
根據部分實施例,成核層16可包括矽<111>。 According to some embodiments, the nucleation layer 16 may include silicon <111>.
根據部分實施例,成核層16可為結晶型。 According to some embodiments, the nucleation layer 16 may be crystalline.
根據部分實施例,成核層16的厚度大約介於0.1微米至5微米。 According to some embodiments, the thickness of the nucleation layer 16 is between about 0.1 micrometers and 5 micrometers.
根據部分實施例,成核層16的晶格常數相對接近成長於其上的磊晶層(例如氮化鎵)的晶格常數。 According to some embodiments, the lattice constant of the nucleation layer 16 is relatively close to the lattice constant of an epitaxial layer (eg, gallium nitride) grown thereon.
如下進一步說明成核層16的製備。對<111>矽晶圓的表面實施氫佈植(hydrogen implantation)至距離晶圓表面約0.3微米至約5微米的深度。利用晶圓接合技術將晶圓的佈植側附接至工程化層14。對晶圓進行回火並實施切割製程以破壞矽<111>晶圓的氫佈植界面,而於工程化層14上留下薄矽層(例如,成核層16)。 The preparation of the nucleation layer 16 is further explained as follows. Hydrogen implantation is performed on the surface of the <111> silicon wafer to a depth of about 0.3 microns to about 5 microns from the wafer surface. The implanted side of the wafer is attached to the engineered layer 14 using wafer bonding technology. Tempering the wafer and performing a dicing process to destroy the hydrogen implant interface of the silicon <111> wafer, leaving a thin silicon layer (eg, nucleation layer 16) on the engineered layer 14.
之後,如第6C圖所示,藉由適當的磊晶製程形成緩衝層18於成核層16上。 Thereafter, as shown in FIG. 6C, a buffer layer 18 is formed on the nucleation layer 16 by an appropriate epitaxial process.
根據部分實施例,緩衝層18可包括氮化鎵鋁或氮化鋁。 According to some embodiments, the buffer layer 18 may include aluminum gallium nitride or aluminum nitride.
之後,如第6D圖所示,藉由適當的磊晶製程形成第一磊晶層20於緩衝層18上。 Thereafter, as shown in FIG. 6D, a first epitaxial layer 20 is formed on the buffer layer 18 by an appropriate epitaxial process.
根據部分實施例,第一磊晶層20可包括氮化鎵。 According to some embodiments, the first epitaxial layer 20 may include gallium nitride.
之後,如第6E圖所示,藉由適當的磊晶製程形成第二磊晶層22於第一磊晶層20上。 Thereafter, as shown in FIG. 6E, a second epitaxial layer 22 is formed on the first epitaxial layer 20 by an appropriate epitaxial process.
根據部分實施例,第二磊晶層22可包括氮化鎵鋁。 According to some embodiments, the second epitaxial layer 22 may include gallium aluminum nitride.
根據部分實施例,可對第二磊晶層22與第一磊晶層20進一步實施氧佈植或氮佈植,以在其中形成佈植區(未圖示)。 According to some embodiments, the second epitaxial layer 22 and the first epitaxial layer 20 may be further subjected to oxygen implantation or nitrogen implantation to form an implantation region (not shown) therein.
之後,如第6F圖所示,形成作為罩幕的圖案化光阻層(未圖示)於第二磊晶層22上,以定義後續形成的隔離結構。 Thereafter, as shown in FIG. 6F, a patterned photoresist layer (not shown) as a mask is formed on the second epitaxial layer 22 to define a subsequent isolation structure.
之後,利用上述罩幕對第二磊晶層22、第一磊晶層20、緩衝層18、以及成核層16進行蝕刻,以形成溝槽42。之後,填入絕緣材料44於溝槽42中並進行平坦化步驟,以形成隔離結構24。隔離結構24位於第一區38與第二區40之間。 After that, the second epitaxial layer 22, the first epitaxial layer 20, the buffer layer 18, and the nucleation layer 16 are etched by using the mask to form a trench 42. Then, the insulating material 44 is filled in the trenches 42 and a planarization step is performed to form the isolation structure 24. The isolation structure 24 is located between the first region 38 and the second region 40.
根據部分實施例,填入溝槽42的絕緣材料44可包括氧化物、氮化物與其上的氧化物、或氧化物與其上的多晶矽。 According to some embodiments, the insulating material 44 filling the trench 42 may include an oxide, a nitride and an oxide thereon, or an oxide and polycrystalline silicon thereon.
根據部分實施例,溝槽42可在其中留下“氣隙”或“空隙”,只要溝槽42的頂部是“密封的”,如此,就不會有材料掉落或陷入溝槽42內。 According to some embodiments, the trench 42 may leave an “air gap” or “gap” therein, as long as the top of the trench 42 is “sealed” so that no material will fall or sink into the trench 42.
根據部分實施例,於填入絕緣材料44至溝槽42之前,形成氮化物材料於溝槽42的側壁與底部,以形成襯墊(未圖示)。 According to some embodiments, before filling the insulating material 44 to the trench 42, a nitride material is formed on the sidewall and the bottom of the trench 42 to form a gasket (not shown).
根據部分實施例,可藉由蝕刻溝槽42穿過第二磊晶層22、第一磊晶層20、緩衝層18、成核層16、以及部份的工程化層14,並填入絕緣材料44於溝槽42內,以形成隔離結構24,如第2圖所示。 According to some embodiments, the second epitaxial layer 22, the first epitaxial layer 20, the buffer layer 18, the nucleation layer 16, and a part of the engineered layer 14 may be etched through the trench 42 and filled with insulation. The material 44 is in the trench 42 to form the isolation structure 24, as shown in FIG. 2.
根據部分實施例,可藉由蝕刻溝槽42穿過第二磊晶層22、第一磊晶層20、緩衝層18、成核層16、以及工程化層14,並填入絕緣材料44於溝槽42內,以形成隔離結構24,如第3圖所示。 According to some embodiments, the second epitaxial layer 22, the first epitaxial layer 20, the buffer layer 18, the nucleation layer 16, and the engineered layer 14 can be penetrated by etching the trench 42 and filled with an insulating material 44 in Within the trench 42, an isolation structure 24 is formed, as shown in FIG. 3.
之後,如第6G圖所示,形成第一閘極26於第二磊晶層22上,並位於第一區38內。形成第一源極28與第一汲極30於第二磊晶層22上,並位於第一區38內。第一源極28與第一汲極30位於第一閘極26的兩側。 Thereafter, as shown in FIG. 6G, a first gate electrode 26 is formed on the second epitaxial layer 22 and is located in the first region 38. A first source electrode 28 and a first drain electrode 30 are formed on the second epitaxial layer 22 and are located in the first region 38. The first source electrode 28 and the first drain electrode 30 are located on both sides of the first gate electrode 26.
根據部分實施例,第一閘極26、第一源極28、以及第一汲極30構成高壓元件50。 According to some embodiments, the first gate electrode 26, the first source electrode 28, and the first drain electrode 30 constitute a high-voltage element 50.
之後,如第6H圖所示,形成第二閘極32於第二磊晶層22上,並位於第二區40內。形成第二源極34與第二汲極36於第二磊晶層22上,並位於第二區40內。第二源極34與第二汲極36位於第二閘極32的兩側。 Thereafter, as shown in FIG. 6H, a second gate electrode 32 is formed on the second epitaxial layer 22 and is located in the second region 40. A second source electrode 34 and a second drain electrode 36 are formed on the second epitaxial layer 22 and are located in the second region 40. The second source electrode 34 and the second drain electrode 36 are located on both sides of the second gate electrode 32.
根據部分實施例,第二閘極32、第二源極34、以及第二汲極36構成低壓元件52。 According to some embodiments, the second gate electrode 32, the second source electrode 34, and the second drain electrode 36 constitute a low-voltage element 52.
至此,完成本實施例半導體結構10的製作。 So far, the fabrication of the semiconductor structure 10 of this embodiment is completed.
之後,實施後續的適當製程,例如鈍化製程、場板形成以及電力互連。 After that, appropriate subsequent processes such as passivation, field plate formation, and power interconnection are implemented.
請參閱第7A-7I圖,根據本發明的一實施例,提供一種半導體結構10的製造方法。第7A-7I圖為半導體結構10製造方法的剖面示意圖。 Please refer to FIGS. 7A-7I. According to an embodiment of the present invention, a method for manufacturing a semiconductor structure 10 is provided. 7A-7I are schematic cross-sectional views of a method for manufacturing the semiconductor structure 10.
如第7A圖所示,提供絕緣基板12,其具有工程化層(engineered layer)14,包圍絕緣基板12。絕緣基板12包括第一區38與第二區40。 As shown in FIG. 7A, an insulating substrate 12 is provided, which has an engineered layer 14 surrounding the insulating substrate 12. The insulating substrate 12 includes a first region 38 and a second region 40.
根據部分實施例,絕緣基板12的熱膨脹係數(coefficient of thermal expansion,CTE)與第一磊晶層20的熱膨脹係數大致相同或相近。 According to some embodiments, the coefficient of thermal expansion (CTE) of the insulating substrate 12 is substantially the same as or similar to that of the first epitaxial layer 20.
根據部分實施例,絕緣基板12的體電阻率(bulk resistivity)大約大於106ohm-cm。 According to some embodiments, the bulk resistivity of the insulating substrate 12 is greater than about 10 6 ohm-cm.
根據部分實施例,絕緣基板12的熱傳導率(thermal conductivity)大約高於矽的熱傳導率。 According to some embodiments, the thermal conductivity of the insulating substrate 12 is approximately higher than the thermal conductivity of silicon.
根據部分實施例,絕緣基板12可包括氮化鋁、多晶碳化矽(polycrystalline silicon carbide)、多晶鑽石(polycrystalline diamond)、或其混合物、或不同多晶材料的混合物、或其他適合的絕緣材料。 According to some embodiments, the insulating substrate 12 may include aluminum nitride, polycrystalline silicon carbide, polycrystalline diamond, or a mixture thereof, or a mixture of different polycrystalline materials, or other suitable insulating materials. .
根據部分實施例,工程化層14可包括氮化物、氧化物、氮氧化物、或多晶矽。 According to some embodiments, the engineered layer 14 may include nitride, oxide, oxynitride, or polycrystalline silicon.
之後,如第7B圖所示,藉由適當的沉積製程形成成核層(nucleation layer)16於工程化層14上。 Thereafter, as shown in FIG. 7B, a nucleation layer 16 is formed on the engineering layer 14 by an appropriate deposition process.
根據部分實施例,成核層16可包括矽<111>。 According to some embodiments, the nucleation layer 16 may include silicon <111>.
根據部分實施例,成核層16可為結晶型。 According to some embodiments, the nucleation layer 16 may be crystalline.
根據部分實施例,成核層16的厚度大約介於0.1微米至5微米。 According to some embodiments, the thickness of the nucleation layer 16 is between about 0.1 micrometers and 5 micrometers.
根據部分實施例,成核層16的晶格常數相對接近成長於其上的磊晶層(例如氮化鎵)的晶格常數。 According to some embodiments, the lattice constant of the nucleation layer 16 is relatively close to the lattice constant of an epitaxial layer (eg, gallium nitride) grown thereon.
之後,如第7C圖所示,藉由適當的磊晶製程形成緩衝層18於成核層16上。 Thereafter, as shown in FIG. 7C, a buffer layer 18 is formed on the nucleation layer 16 by an appropriate epitaxial process.
根據部分實施例,緩衝層18可包括氮化鎵鋁或氮化鋁。 According to some embodiments, the buffer layer 18 may include aluminum gallium nitride or aluminum nitride.
之後,如第7D圖所示,藉由適當的磊晶製程形成第一磊晶層20於緩衝層18上。 Then, as shown in FIG. 7D, a first epitaxial layer 20 is formed on the buffer layer 18 by an appropriate epitaxial process.
根據部分實施例,第一磊晶層20可包括氮化鎵。 According to some embodiments, the first epitaxial layer 20 may include gallium nitride.
之後,如第7E圖所示,藉由適當的磊晶製程形成第二磊晶層22於第一磊晶層20上。 Thereafter, as shown in FIG. 7E, a second epitaxial layer 22 is formed on the first epitaxial layer 20 by an appropriate epitaxial process.
根據部分實施例,第二磊晶層22可包括氮化鎵鋁。 According to some embodiments, the second epitaxial layer 22 may include gallium aluminum nitride.
之後,如第7F圖所示,形成作為罩幕的圖案化光阻層(未圖示)於第二磊晶層22上,以定義後續形成的隔離結構。 Thereafter, as shown in FIG. 7F, a patterned photoresist layer (not shown) as a mask is formed on the second epitaxial layer 22 to define a subsequent isolation structure.
之後,對第二磊晶層22與第一磊晶層20實施第一佈植製程64,以於其中形成第一佈植區58(亦即淺佈植區)。第 一佈植區58位於第一區38與第二區40之間。 Thereafter, a first implantation process 64 is performed on the second epitaxial layer 22 and the first epitaxial layer 20 to form a first implantation region 58 (ie, a shallow implantation region) therein. The first planting area 58 is located between the first area 38 and the second area 40.
根據部分實施例,第一佈植製程64可為氧佈植或氮佈植。 According to some embodiments, the first implantation process 64 may be an oxygen implantation or a nitrogen implantation.
之後,如第7G圖所示,對成核層16實施第二佈植製程66,以於其中形成第二佈植區60(亦即深佈植區)。第二佈植區60位於第一區38與第二區40之間。 Thereafter, as shown in FIG. 7G, a second implantation process 66 is performed on the nucleation layer 16 to form a second implantation region 60 (ie, a deep implantation region) therein. The second planting area 60 is located between the first area 38 and the second area 40.
根據部分實施例,第二佈植製程66可為氧佈植或氮佈植。 According to some embodiments, the second implantation process 66 may be an oxygen implantation or a nitrogen implantation.
在本實施例中,第一佈植區58與第二佈植區60構成隔離結構24。 In this embodiment, the first planting area 58 and the second planting area 60 constitute an isolation structure 24.
在本實施例中,藉由調整第一佈植製程64與第二佈植製程66的強度,分別形成位於較淺區域的第一佈植區58以及較深區域的第二佈植區60,以達到破壞二維電子氣層(two-dimensional electron gas(2DEG)layer)及阻隔成核層16的目的。 In this embodiment, by adjusting the strengths of the first and second implantation processes 64 and 66, the first and second implantation regions 58 and 60 in the shallower regions are respectively formed. In order to achieve the purpose of destroying the two-dimensional electron gas layer (2DEG) layer and blocking the nucleation layer 16.
根據部分實施例,於形成作為罩幕的圖案化光阻層(未圖示)於第二磊晶層22上之後,可對第二磊晶層22、第一磊晶層20、緩衝層18、以及成核層16實施例如氧佈植(oxygen implantation)或氮佈植(nitrogen implantation)的佈植製程,以於其中形成連續佈植區62(亦即隔離結構),如第5圖所示。連續佈植區62位於第一區38與第二區40之間。 According to some embodiments, after forming a patterned photoresist layer (not shown) as a mask on the second epitaxial layer 22, the second epitaxial layer 22, the first epitaxial layer 20, and the buffer layer 18 may be formed. And the nucleation layer 16 implements an implantation process such as oxygen implantation or nitrogen implantation to form a continuous implantation region 62 (ie, an isolation structure) therein, as shown in FIG. 5 . The continuous implantation area 62 is located between the first area 38 and the second area 40.
之後,如第7H圖所示,形成第一閘極26於第二磊晶層22上,並位於第一區38內。形成第一源極28與第一汲極30於第二磊晶層22上,並位於第一區38內。第一源極28與第一汲 極30位於第一閘極26的兩側。 Thereafter, as shown in FIG. 7H, a first gate electrode 26 is formed on the second epitaxial layer 22 and is located in the first region 38. A first source electrode 28 and a first drain electrode 30 are formed on the second epitaxial layer 22 and are located in the first region 38. The first source electrode 28 and the first drain electrode 30 are located on both sides of the first gate electrode 26.
根據部分實施例,第一閘極26、第一源極28、以及第一汲極30構成高壓元件50。 According to some embodiments, the first gate electrode 26, the first source electrode 28, and the first drain electrode 30 constitute a high-voltage element 50.
之後,如第7I圖所示,形成第二閘極32於第二磊晶層22上,並位於第二區40內。形成第二源極34與第二汲極36於第二磊晶層22上,並位於第二區40內。第二源極34與第二汲極36位於第二閘極32的兩側。 Thereafter, as shown in FIG. 7I, a second gate electrode 32 is formed on the second epitaxial layer 22 and is located in the second region 40. A second source electrode 34 and a second drain electrode 36 are formed on the second epitaxial layer 22 and are located in the second region 40. The second source electrode 34 and the second drain electrode 36 are located on both sides of the second gate electrode 32.
根據部分實施例,第二閘極32、第二源極34、以及第二汲極36構成低壓元件52。 According to some embodiments, the second gate electrode 32, the second source electrode 34, and the second drain electrode 36 constitute a low-voltage element 52.
至此,完成本實施例半導體結構10的製作。 So far, the fabrication of the semiconductor structure 10 of this embodiment is completed.
之後,實施後續的適當製程,例如鈍化製程、場板形成以及電力互連。 After that, appropriate subsequent processes such as passivation, field plate formation, and power interconnection are implemented.
在本發明所揭露的半導體結構中,具有以下適當特性(例如,與電晶體材料層相近的熱膨脹係數(CTE)、高體電阻率、高熱傳導率、以及低成本)且進一步被特定工程化層(例如,氧化物、氮化物、氮氧化物、或多晶矽)所包圍的絕緣核心基板(例如氮化鋁)係用來取代傳統的半導體矽基板。在上述半導體結構中,亦形成有簡單的隔離結構,例如填充有絕緣材料的單一溝槽或分離式的佈植區(包括淺佈植區以及深佈植區),以破壞二維電子氣層(2DEG layer)並阻隔半導體成核層,以確保相鄰元件間不會形成電連接。因此,由於核心基板是絕緣體(不發生背偏壓效應),遂不需在基板上形成偏壓連接,且不需在深溝槽中形成複雜又昂貴的導體以連接成核層或基板。本發明確實提供了簡單的製程步驟以及電連接。此外,以不同電壓 施加於其端子的多重元件(例如主動元件及/或被動元件)亦可集積在同一晶粒上。 In the semiconductor structure disclosed in the present invention, it has the following appropriate characteristics (for example, a coefficient of thermal expansion (CTE) similar to that of a transistor material layer, a high bulk resistivity, a high thermal conductivity, and a low cost) and is further specifically engineered. An insulating core substrate (for example, aluminum nitride) surrounded by (for example, oxide, nitride, oxynitride, or polycrystalline silicon) is used to replace a conventional semiconductor silicon substrate. In the above semiconductor structure, a simple isolation structure is also formed, such as a single trench filled with insulating material or a separate implanted area (including a shallow implanted area and a deep implanted area) to destroy the two-dimensional electron gas layer (2DEG layer) and block the semiconductor nucleation layer to ensure that no electrical connection is formed between adjacent components. Therefore, since the core substrate is an insulator (no back bias effect occurs), it is not necessary to form a bias connection on the substrate, and it is not necessary to form a complex and expensive conductor in a deep trench to connect the nucleation layer or the substrate. The invention does provide simple process steps and electrical connections. In addition, multiple components (such as active and / or passive components) that are applied to their terminals with different voltages can also be accumulated on the same die.
雖然本發明已以數個較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作任意之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make any changes without departing from the spirit and scope of the present invention. And retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application.
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US11588036B2 (en) | 2020-11-11 | 2023-02-21 | Vanguard International Semiconductor Corporation | High-efficiency packaged chip structure and electronic device including the same |
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