TW201944467A - Semiconductor devices and methods for forming the same - Google Patents
Semiconductor devices and methods for forming the same Download PDFInfo
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本發明實施例係有關於半導體技術，特別為有關於***式閘極(split-gate)溝槽功率金屬氧化物半導體場效電晶體(trench power metal oxide semiconductor field effect transistor，trench power MOSFET)及其製造方法。 Embodiments of the present invention relate to semiconductor technology, and in particular, to a split-gate trench power metal oxide semiconductor field effect transistor (trench power MOSFET) and a trench power MOSFET. Production method.
高壓元件技術應用於高電壓與高功率的積體電路，傳統的功率電晶體為了達到高耐壓及高電流，驅動電流的流動由平面方向發展為垂直方向。目前發展出具有溝槽式閘極(trench gate)的金屬氧化物半導體場效電晶體(MOSFET)，能夠有效地降低導通電阻，且具有較大電流處理能力。 High-voltage component technology is applied to integrated circuits with high voltage and high power. In order to achieve high withstand voltage and high current, traditional power transistors have driven the flow of driving current from a planar direction to a vertical direction. At present, metal oxide semiconductor field effect transistors (MOSFETs) having trench gates have been developed, which can effectively reduce the on-resistance and have a large current processing capability.
近年來，更研發出***式閘極(split-gate)溝槽結構。***式閘極溝槽功率金屬氧化物半導體場效電晶體主要包括在閘極溝槽中的上下設置的兩個電極，其中一個電極作為閘極電極，主要控制著金屬氧化物半導體場效電晶體的電流通道的形成，另一個電極則作為遮罩電極，位於閘極電極的正下方，例如可以降低汲極電極與閘極電極之間的寄生電容。然而，在製造***式閘極溝槽結構時，容易產生逆向閘極漏電(IGSSR leakage)。 In recent years, a split-gate trench structure has been developed. The split gate trench power metal oxide semiconductor field effect transistor mainly includes two electrodes provided above and below the gate trench. One of the electrodes is used as a gate electrode and mainly controls the metal oxide semiconductor field effect transistor. In the formation of a current channel, the other electrode is used as a shield electrode and is located directly below the gate electrode, for example, the parasitic capacitance between the drain electrode and the gate electrode can be reduced. However, when manufacturing a split gate trench structure, reverse gate leakage (IGSSR leakage) is likely to occur.
因此，有必要尋求***式閘極溝槽功率金屬氧化物半導體場效電晶體及其製造方法，其能夠解決或改善上述的問題。 Therefore, it is necessary to find a split gate trench power metal oxide semiconductor field effect transistor and a method for manufacturing the same, which can solve or improve the above problems.
本發明的一些實施例提供半導體裝置的製造方法，包括：提供具有第一導電型的基底；在基底上形成具有第一導電型的磊晶層；在磊晶層中形成溝槽；在溝槽中和磊晶層的頂表面上形成第一絕緣層；在第一絕緣層上依序形成遮罩電極和遮罩層；使用遮罩層移除第一絕緣層的一部分，其中在移除第一絕緣層的此部分之後，第一絕緣層的頂表面高於遮罩電極的頂表面；移除遮罩層；在第一絕緣層和遮罩電極上形成第二絕緣層；在第二絕緣層上形成閘極電極；在磊晶層中形成具有第二導電型的井區，第二導電型不同於第一導電型；以及在井區上形成具有第一導電型的重摻雜區。 Some embodiments of the present invention provide a method for manufacturing a semiconductor device, including: providing a substrate having a first conductivity type; forming an epitaxial layer having a first conductivity type on the substrate; forming a trench in the epitaxial layer; A first insulating layer is formed on the top surface of the neutralization epitaxial layer; a mask electrode and a mask layer are sequentially formed on the first insulating layer; a portion of the first insulating layer is removed using the mask layer, where the first After this part of an insulating layer, the top surface of the first insulating layer is higher than the top surface of the mask electrode; removing the mask layer; forming a second insulating layer on the first insulating layer and the mask electrode; A gate electrode is formed on the layer; a well region having a second conductivity type is formed in the epitaxial layer; the second conductivity type is different from the first conductivity type; and a heavily doped region having the first conductivity type is formed on the well region.
本發明的一些實施例提供半導體裝置，包括：基底，具有第一導電型；磊晶層，具有第一導電型，設置於基底上，且磊晶層內具有溝槽；井區，設置於磊晶層上，且具有不同於第一導電型的第二導電型；重摻雜區，設置於井區上，且具有第一導電型；遮罩電極，設置於溝槽中，其中遮罩電極透過第一絕緣層與磊晶層隔開，且第一絕緣層的頂表面高於遮罩電極的頂表面；以及閘極電極，設置於溝槽中且位於遮罩電極上方，其中閘極電極透過第二絕緣層與磊晶層和遮罩電極隔開。 Some embodiments of the present invention provide a semiconductor device including: a substrate having a first conductivity type; an epitaxial layer having a first conductivity type, disposed on the substrate, and having trenches in the epitaxial layer; and a well region, disposed in the On the crystal layer and having a second conductivity type different from the first conductivity type; a heavily doped region disposed on the well region and having the first conductivity type; a mask electrode disposed in the trench, wherein the mask electrode It is separated from the epitaxial layer by the first insulating layer, and the top surface of the first insulating layer is higher than the top surface of the mask electrode; and the gate electrode is disposed in the trench and located above the mask electrode, wherein the gate electrode The second insulating layer is separated from the epitaxial layer and the mask electrode.
100‧‧‧半導體裝置 100‧‧‧ semiconductor device
101‧‧‧基底 101‧‧‧ substrate
102‧‧‧磊晶層 102‧‧‧Epitaxial layer
103‧‧‧圖案化遮罩 103‧‧‧patterned mask
103a‧‧‧開口 103a‧‧‧ opening
104‧‧‧溝槽 104‧‧‧Groove
105、105’‧‧‧第一絕緣層 105、105’‧‧‧first insulation layer
106‧‧‧遮罩電極 106‧‧‧Mask electrode
107‧‧‧遮罩材料層 107‧‧‧Mask material layer
107’‧‧‧遮罩層 107’‧‧‧Mask layer
108‧‧‧第二絕緣層 108‧‧‧Second insulation layer
109‧‧‧閘極電極 109‧‧‧Gate electrode
110‧‧‧第三絕緣層 110‧‧‧third insulating layer
111‧‧‧井區 111‧‧‧well area
112‧‧‧重摻雜區 112‧‧‧Heavy doped region
113‧‧‧第一金屬層 113‧‧‧first metal layer
T1、T2、T3、T4‧‧‧厚度 T1, T2, T3, T4‧‧‧thickness
第1A-1L圖顯示依據本發明的一些實施例之半導體裝置的製造方法在各階段的剖面示意圖。 1A-1L are schematic cross-sectional views of various stages of a method for manufacturing a semiconductor device according to some embodiments of the present invention.
以下說明本發明實施例之半導體裝置及其製造方法。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。再者，在本發明實施例之圖式及說明內容中係使用相同的標號來表示相同或相似的部件。 Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described. However, it can be easily understood that the embodiments of the present invention provide many suitable inventive concepts and can be implemented in a wide variety of specific backgrounds. The specific embodiments disclosed are only used to illustrate that the present invention is made and used in a specific method, and are not intended to limit the scope of the present invention. Moreover, in the drawings and the description of the embodiments of the present invention, the same reference numerals are used to represent the same or similar components.
請參照第1A-1L圖，其顯示出依據本發明的一些實施例之形成第1L圖所示之半導體裝置100的製造方法在各階段的剖面示意圖。可在第1A-1L圖所述的階段之前、期間、及/或之後提供額外的操作。在不同的實施例中，可移動、刪除或置換前述的一些操作。可加入額外的部件到半導體裝置。在不同的實施例中，可移動、刪除或置換以下所述的一些部件。 Please refer to FIGS. 1A-1L, which are schematic cross-sectional views at various stages of a manufacturing method of forming the semiconductor device 100 shown in FIG. 1L according to some embodiments of the present invention. Additional operations may be provided before, during, and / or after the stages described in Figures 1A-1L. In different embodiments, some of the foregoing operations may be moved, deleted, or replaced. Additional components can be added to the semiconductor device. In different embodiments, some of the components described below can be moved, deleted, or replaced.
依據一些實施例，如第1A圖所示，提供具有第一導電型的基底101，且做為半導體裝置100的汲極(Drain，D)。在一些實施例中，基底101可由矽或其他半導體材料製成，或者，基底101可包含其他元素半導體材料，例如鍺(Ge)。在一些實施例中，基底101可由化合物半導體製成，例如碳化矽、氮化鎵、砷化鎵、砷化銦或磷化銦。在一些實施例中，基底101由合金半導體製成，例如矽鍺、碳化矽鍺、磷化砷鎵或磷化銦鎵。一些實施例中，基底101包含絕緣層上覆矽 (silicon-on-insulator，SOI)基底或其他合適的基底。在本實施例中，第一導電型為n型，但並不限定於此。在一些其他實施例中，第一導電型也可為p型。 According to some embodiments, as shown in FIG. 1A, a substrate 101 having a first conductivity type is provided and used as a drain (Drain, D) of the semiconductor device 100. In some embodiments, the substrate 101 may be made of silicon or other semiconductor materials, or the substrate 101 may include other elemental semiconductor materials, such as germanium (Ge). In some embodiments, the substrate 101 may be made of a compound semiconductor, such as silicon carbide, gallium nitride, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 101 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or indium gallium phosphide. In some embodiments, the substrate 101 includes a silicon-on-insulator (SOI) substrate or other suitable substrates. In this embodiment, the first conductivity type is an n-type, but it is not limited thereto. In some other embodiments, the first conductivity type may also be a p-type.
隨後，依據一些實施例，進行磊晶成長(epitaxial growth)製程，在基底101上形成磊晶層102，半導體基底101和磊晶層102具有相同的導電型，例如第一導電型。在本實施例中，磊晶層102為n型。在一些實施例中，磊晶成長製程可為金屬有機物化學氣相沉積法(metal organic chemical vapor deposition，MOCVD)、電漿增強化學氣相沉積法(plasma-enhanced CVD，PECVD)、分子束磊晶法(molecular beam epitaxy，MBE)、氫化物氣相磊晶法(hydride vapour phase epitaxy，HVPE)、液相磊晶法(liquid phase epitaxy，LPE)、氯化物氣相磊晶法(Cl-VPE)、其他合適的製程方法或前述之組合。 Subsequently, according to some embodiments, an epitaxial growth process is performed to form an epitaxial layer 102 on the substrate 101. The semiconductor substrate 101 and the epitaxial layer 102 have the same conductivity type, such as a first conductivity type. In this embodiment, the epitaxial layer 102 is n-type. In some embodiments, the epitaxial growth process may be metal organic chemical vapor deposition (MOCVD), plasma-enhanced CVD (PECVD), molecular beam epitaxy Method (molecular beam epitaxy (MBE), hydride vapour phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE) , Other suitable process methods or a combination of the foregoing.
接著，依據一些實施例，如第1B圖所示，透過微影圖案化製程在磊晶層102上形成圖案化遮罩103，圖案化遮罩103具有開口103a。在本實施例中，圖案化遮罩103的材料可為光阻材料。在一些其他實施例中，圖案化遮罩103的材料可為由氧化物層和氮化物層所組成的硬遮罩(hard mask)。在一些實施例中，微影圖案化製程包含光阻塗佈(例如，自旋塗佈)、軟烤、遮罩對準、曝光、曝光後烤、光阻顯影、清洗及乾燥(例如，硬烤)、其他合適製程或前述之組合。 Next, according to some embodiments, as shown in FIG. 1B, a patterned mask 103 is formed on the epitaxial layer 102 through a lithographic patterning process, and the patterned mask 103 has an opening 103 a. In this embodiment, a material of the patterned mask 103 may be a photoresist material. In some other embodiments, the material of the patterned mask 103 may be a hard mask composed of an oxide layer and a nitride layer. In some embodiments, the lithographic patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying (e.g., hard coating). Baking), other suitable processes or a combination of the foregoing.
依據一些實施例，如第1C圖所示，在形成圖案化遮罩103之後，經由圖案化遮罩103的開口103a對磊晶層102實 施蝕刻製程，以在磊晶層102中形成溝槽104。在一些實施例中，蝕刻製程可為乾蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程、其他合適的製程或前述之組合。在形成溝槽104之後，移除圖案化遮罩103。應理解的是，第1C圖所示之溝槽104尺寸、形狀、及位置僅為例示，而非用以限制本發明實施例。 According to some embodiments, as shown in FIG. 1C, after the patterned mask 103 is formed, the epitaxial layer 102 is etched through the opening 103 a of the patterned mask 103 to form a trench 104 in the epitaxial layer 102. . In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof. After the trench 104 is formed, the patterned mask 103 is removed. It should be understood that the size, shape, and position of the trench 104 shown in FIG. 1C are merely examples, and are not intended to limit the embodiments of the present invention.
依據一些實施例，如第1D圖所示，透過氧化製程在溝槽104中和磊晶層102的頂表面上形成第一絕緣層105，並對第一絕緣層105實施退火製程，以增加第一絕緣層105的緻密度。在一些實施例中，第一絕緣層105具有均勻的厚度T1。在一些實施例中，厚度T1在50nm至500nm的範圍內。可根據半導體裝置的元件尺寸及設計需要而調整第一絕緣層105的厚度T1。在一些實施例中，第一絕緣層105可為氧化矽、氧化鍺、其它合適的半導體氧化物材料或前述之組合。在一些實施例中，氧化製程可為熱氧化法、自由基氧化法或其他合適的製程。在一些實施例中，退火製程可為快速熱退火(rapid thermal annealing，RTA)製程。 According to some embodiments, as shown in FIG. 1D, a first insulating layer 105 is formed in the trench 104 and the top surface of the epitaxial layer 102 through an oxidation process, and an annealing process is performed on the first insulating layer 105 to increase the first The density of an insulating layer 105. In some embodiments, the first insulating layer 105 has a uniform thickness T1. In some embodiments, the thickness T1 is in a range of 50 nm to 500 nm. The thickness T1 of the first insulating layer 105 can be adjusted according to the element size and design requirements of the semiconductor device. In some embodiments, the first insulating layer 105 may be silicon oxide, germanium oxide, other suitable semiconductor oxide materials, or a combination thereof. In some embodiments, the oxidation process may be a thermal oxidation process, a radical oxidation process, or other suitable processes. In some embodiments, the annealing process may be a rapid thermal annealing (RTA) process.
依據一些實施例，如第1E圖所示，透過沉積製程、微影圖案化製程及蝕刻製程在溝槽104中的第一絕緣層105上形成遮罩電極106。在本實施例中，遮罩電極106填入溝槽104的下部而未填滿溝槽104，且第一絕緣層105圍繞遮罩電極106。在一些實施例中，遮罩電極106具有均勻的厚度T2。在一些實施例中，厚度T2在500nm至5000nm的範圍內。可根據半導體裝置的元件尺寸及設計需要而調整遮罩電極106的厚度T2。 在一些實施例中，遮罩電極106之材料可為一或多層結構，且由非晶矽、多晶矽、一或多種金屬、金屬氮化物、金屬矽化物、導電金屬氧化物或前述之組合所形成。明確而言，前述金屬可包括但不限於鉬(Mo)、鎢(W)、鈦(Ti)、鉭(Ta)、鉑(Pt)或鉿(Hf)。上述金屬氮化物可包括但不限於氮化鉬(MoN)、氮化鎢(WN)、氮化鈦(TiN)以及氮化鉭(TaN)。前述金屬矽化物可包括但不限於矽化鎢(WSix)。前述導電金屬氧化物可包括但不限於釕金屬氧化物(RuO2)以及銦錫金屬氧化物(indium tin oxide，ITO)。在一些實施例中，沉積製程可為物理氣相沈積(physical vapor deposition，PVD)製程、化學氣相沈積(CVD)製程、其他合適的製程或前述之組合。在一些實施例中，微影圖案化製程包含光阻塗佈(例如，自旋塗佈)、軟烤、遮罩對準、曝光、曝光後烤、光阻顯影、清洗及乾燥(例如，硬烤)、其他合適的製程或前述之組合。在一些實施例中，蝕刻製程可為乾蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程、其他合適的製程或前述之組合。 According to some embodiments, as shown in FIG. 1E, a mask electrode 106 is formed on the first insulating layer 105 in the trench 104 through a deposition process, a lithographic patterning process, and an etching process. In this embodiment, the mask electrode 106 fills the lower portion of the trench 104 without filling the trench 104, and the first insulating layer 105 surrounds the mask electrode 106. In some embodiments, the mask electrode 106 has a uniform thickness T2. In some embodiments, the thickness T2 is in a range of 500 nm to 5000 nm. The thickness T2 of the mask electrode 106 can be adjusted according to the element size and design requirements of the semiconductor device. In some embodiments, the material of the mask electrode 106 may be one or more layers, and is formed of amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, or combinations thereof. . Specifically, the foregoing metals may include, but are not limited to, molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), or hafnium (Hf). The metal nitride may include, but is not limited to, molybdenum nitride (MoN), tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN). The aforementioned metal silicide may include, but is not limited to, tungsten silicide (WSi x ). The foregoing conductive metal oxide may include, but is not limited to, ruthenium metal oxide (RuO 2 ) and indium tin oxide (ITO). In some embodiments, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination thereof. In some embodiments, the lithographic patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying (e.g., hard coating). Baking), other suitable processes or a combination of the foregoing. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof.
接著，依據一些實施例，如第1F圖所示，在第一絕緣層105和遮罩電極106上形成遮罩材料層107。在一些實施例中，遮罩材料層107填滿溝槽104的餘留部分。在一些實施例中，遮罩材料層107的材料相同於圖案化遮罩103的材料。在一些其他實施例中，遮罩材料層107的材料不同於圖案化遮罩103的材料。在一些實施例中，透過沉積製程或塗佈製程形成遮罩材料層107。 Next, according to some embodiments, as shown in FIG. 1F, a mask material layer 107 is formed on the first insulating layer 105 and the mask electrode 106. In some embodiments, the mask material layer 107 fills the remaining portion of the trench 104. In some embodiments, the material of the mask material layer 107 is the same as the material of the patterned mask 103. In some other embodiments, the material of the mask material layer 107 is different from the material of the patterned mask 103. In some embodiments, the masking material layer 107 is formed by a deposition process or a coating process.
依據一些實施例，如第1G圖所示，移除遮罩材料 層107的一部分以形成遮罩層107’，並在遮罩層107’上保留溝槽104的一餘留空間。在一些實施例中，第一絕緣層105圍繞遮罩層107’。在一些實施例中，遮罩層107’具有均勻的厚度T3。在一些實施例中，厚度T3在50nm至500nm的範圍內。可根據半導體裝置的元件尺寸及設計需要而調整遮罩層107’的厚度T3。在一些實施例中，遮罩層107’的厚度T3小於遮罩電極106的厚度T2。 According to some embodiments, as shown in FIG. 1G, a part of the masking material layer 107 is removed to form a masking layer 107 ', and a remaining space of the trench 104 is left on the masking layer 107'. In some embodiments, the first insulating layer 105 surrounds the mask layer 107 '. In some embodiments, the mask layer 107 'has a uniform thickness T3. In some embodiments, the thickness T3 is in a range of 50 nm to 500 nm. The thickness T3 of the mask layer 107 'can be adjusted according to the element size and design requirements of the semiconductor device. In some embodiments, the thickness T3 of the mask layer 107 'is smaller than the thickness T2 of the mask electrode 106.
接著，依據一些實施例，如第1H圖所示，以遮罩層107’作為遮罩移除第一絕緣層105的一部分，保留第一絕緣層105’。在本實施例中，第一絕緣層105’的頂表面高於遮罩電極106的頂表面，且第一絕緣層105’的頂表面低於遮罩層107’的頂表面。在一些實施例中，第一絕緣層105’也具有均勻的厚度T1。在一些實施例中，在移除製程中，移除第一絕緣層105在磊晶層102的頂表面上的部分以及第一絕緣層105在溝槽104中的上部部分，以暴露出溝槽104中的磊晶層102的一部分。在本實施例中，在形成第一絕緣層105’之後，移除遮罩層107’。 Then, according to some embodiments, as shown in FIG. 1H, a part of the first insulating layer 105 is removed using the mask layer 107 'as a mask, and the first insulating layer 105' is retained. In this embodiment, the top surface of the first insulating layer 105 'is higher than the top surface of the mask electrode 106, and the top surface of the first insulating layer 105' is lower than the top surface of the mask layer 107 '. In some embodiments, the first insulating layer 105 'also has a uniform thickness T1. In some embodiments, during the removal process, a portion of the first insulating layer 105 on the top surface of the epitaxial layer 102 and an upper portion of the first insulating layer 105 in the trench 104 are removed to expose the trench. Part of the epitaxial layer 102 in 104. In this embodiment, after the first insulating layer 105 'is formed, the mask layer 107' is removed.
依據一些實施例，如第1I圖所示，透過沉積製程在磊晶層102、第一絕緣層105’和遮罩電極106上形成第二絕緣層108。在一些實施例中，第二絕緣層108具有均勻的厚度T4。在一些實施例中，厚度T4在10nm至200nm的範圍內。可根據半導體裝置的元件尺寸及設計需要而調整第二絕緣層108的厚度T4。在一些實施例中，第一絕緣層105’(或第一絕緣層105)的厚度T1大於第二絕緣層108的厚度T4。在本實施例中，第二絕緣層108在第一絕緣層105’和遮罩電極106上方形成階梯狀上表 面，且第二絕緣層108在第一絕緣層105’上的第一部分高於第二絕緣層108在遮罩電極106上的第二部分。在一些其他實施例中，第二絕緣層108在第一絕緣層105’和遮罩電極106上方形成U形上表面。在一些實施例中，第二絕緣層108可為氧化矽、氧化鉿、氧化鋯、氧化鋁、二氧化鋁鉿合金、二氧化矽鉿、氮氧化矽鉿、氧化鉭鉿、氧化鈦鉿、氧化鋯鉿、其它合適的高介電常數(high-k)介電材料或前述之組合。。在一些實施例中，第二絕緣層108的材料不同於第一絕緣層105’的材料。在一些其他實施例中，第二絕緣層108的材料相同於第一絕緣層105’的材料。在本實施例中，沉積製程為順應性沉積製程，且可為物理氣相沈積(PVD)製程、化學氣相沈積(CVD)製程、其他合適的製程或前述之組合。 According to some embodiments, as shown in FIG. 11I, a second insulating layer 108 is formed on the epitaxial layer 102, the first insulating layer 105 ', and the mask electrode 106 through a deposition process. In some embodiments, the second insulating layer 108 has a uniform thickness T4. In some embodiments, the thickness T4 is in a range of 10 nm to 200 nm. The thickness T4 of the second insulating layer 108 can be adjusted according to the element size and design requirements of the semiconductor device. In some embodiments, the thickness T1 of the first insulating layer 105 '(or the first insulating layer 105) is greater than the thickness T4 of the second insulating layer 108. In this embodiment, the second insulating layer 108 forms a stepped upper surface above the first insulating layer 105 'and the mask electrode 106, and the first portion of the second insulating layer 108 on the first insulating layer 105' is higher than the first portion A second portion of the two insulating layers 108 on the mask electrode 106. In some other embodiments, the second insulating layer 108 forms a U-shaped upper surface over the first insulating layer 105 'and the shield electrode 106. In some embodiments, the second insulating layer 108 may be silicon oxide, hafnium oxide, zirconia, alumina, alumina alumina alloy, silicon dioxide, silicon oxynitride, tantalum oxide, titanium oxide, oxide Zirconium hafnium, other suitable high-k dielectric materials, or a combination of the foregoing. . In some embodiments, the material of the second insulating layer 108 is different from the material of the first insulating layer 105 '. In some other embodiments, the material of the second insulating layer 108 is the same as the material of the first insulating layer 105 '. In this embodiment, the deposition process is a compliant deposition process, and may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination thereof.
依據一些實施例，如第1J圖所示，透過沉積製程、微影圖案化製程及蝕刻製程在溝槽104中的第二絕緣層108上形成閘極電極109。在一些實施例中，閘極電極109的材料相同於遮罩電極106的材料。在一些其他實施例中，閘極電極109的材料不同於遮罩電極106的材料。在一些實施例中，沉積製程可為物理氣相沈積(PVD)製程、化學氣相沈積(CVD)製程、其他合適的製程或前述之組合。在一些實施例中，微影圖案化製程包含光阻塗佈(例如，自旋塗佈)、軟烤、遮罩對準、曝光、曝光後烤、光阻顯影、清洗及乾燥(例如，硬烤)、其他合適的製程或前述之組合。在一些實施例中，蝕刻製程可為乾蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程、其他合適的製程或前述之組合。 According to some embodiments, as shown in FIG. 1J, a gate electrode 109 is formed on the second insulating layer 108 in the trench 104 through a deposition process, a lithography patterning process, and an etching process. In some embodiments, the material of the gate electrode 109 is the same as that of the mask electrode 106. In some other embodiments, the material of the gate electrode 109 is different from the material of the shield electrode 106. In some embodiments, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination thereof. In some embodiments, the lithographic patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying (e.g., hard coating). Baking), other suitable processes or a combination of the foregoing. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof.
透過遮罩層107’的設置，在移除第一絕緣層105的一部分的期間，可避免過度移除第一絕緣層105，即可避免第一絕緣層105底切(undercut)的現象。也就是說，透過遮罩層107’的設置，在移除第一絕緣層105的一部分之後，第一絕緣層105的餘留部分的頂表面可高於遮罩電極106的頂表面。因此，在沉積第二絕緣層108之後，第二絕緣層108在第一絕緣層105’和遮罩電極106上方形成的輪廓較不易發生逆向閘極漏電(IGSSR leakage)。此外，第二絕緣層108在第一絕緣層105’和遮罩電極106上方形成的輪廓也可降低閘極-汲極間電荷(Qgd)，進一步提升半導體裝置的效能。 By providing the mask layer 107 ', during the removal of a part of the first insulating layer 105, excessive removal of the first insulating layer 105 can be avoided, and an undercut of the first insulating layer 105 can be avoided. That is, through the disposition of the mask layer 107 ', the top surface of the remaining portion of the first insulation layer 105 may be higher than the top surface of the mask electrode 106 after a portion of the first insulation layer 105 is removed. Therefore, after the second insulating layer 108 is deposited, the contour formed by the second insulating layer 108 above the first insulating layer 105 'and the shield electrode 106 is less likely to cause reverse gate leakage (IGSSR leakage). In addition, the contour of the second insulating layer 108 over the first insulating layer 105 'and the shield electrode 106 can also reduce the gate-drain charge (Qgd) and further improve the performance of the semiconductor device.
依據一些實施例，如第1J圖所示，透過沉積製程、微影圖案化製程及蝕刻製程在閘極電極109上形成第三絕緣層110。在一些實施例中，第三絕緣層110的材料不同於第二絕緣層108的材料。在一些其他實施例中，第三絕緣層110的材料相同於第二絕緣層108的材料。在一些實施例中，沉積製程可為物理氣相沈積(PVD)製程、化學氣相沈積(CVD)製程、其他合適的製程或前述之組合。在一些實施例中，微影圖案化製程包含光阻塗佈(例如，自旋塗佈)、軟烤、遮罩對準、曝光、曝光後烤、光阻顯影、清洗及乾燥(例如，硬烤)、其他合適的製程或前述之組合。在一些實施例中，蝕刻製程可為乾蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程、其他合適的製程或前述之組合。 According to some embodiments, as shown in FIG. 1J, a third insulating layer 110 is formed on the gate electrode 109 through a deposition process, a lithographic patterning process, and an etching process. In some embodiments, a material of the third insulating layer 110 is different from a material of the second insulating layer 108. In some other embodiments, the material of the third insulating layer 110 is the same as that of the second insulating layer 108. In some embodiments, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination thereof. In some embodiments, the lithographic patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying (e.g., hard coating) Baking), other suitable processes or a combination of the foregoing. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof.
接著，依據一些實施例，如第1K圖所示，透過摻雜製程(例如，離子佈植製程)在磊晶層102中形成井區111，再 透過另一摻雜製程(例如，離子佈植製程)在井區111中形成重摻雜區112。依據一些實施例，井區111係做為半導體裝置100的通道區，重摻雜區112係做為半導體裝置100的源極(Source，S)。在本實施例中，井區111和重摻雜區112圍繞溝槽104。在本實施例中，井區111具有不同於基底101的第二導電型，而重摻雜區112具有相同於基底101的第一導電型。在本實施例中，第二導電型為p型，但並不限定於此。在一些其他實施例中，第二導電型也可為n型。在一些實施例中，重摻雜區112的摻雜濃度大於基底101和磊晶層102。 Then, according to some embodiments, as shown in FIG. 1K, a well region 111 is formed in the epitaxial layer 102 through a doping process (for example, an ion implantation process), and then another doping process (for example, an ion implantation process) is formed. (Process) A heavily doped region 112 is formed in the well region 111. According to some embodiments, the well region 111 is used as a channel region of the semiconductor device 100, and the heavily doped region 112 is used as a source (S) of the semiconductor device 100. In this embodiment, the well region 111 and the heavily doped region 112 surround the trench 104. In this embodiment, the well region 111 has a second conductivity type different from that of the substrate 101, and the heavily doped region 112 has a first conductivity type that is the same as the substrate 101. In this embodiment, the second conductivity type is a p-type, but it is not limited to this. In some other embodiments, the second conductivity type may also be an n-type. In some embodiments, the doping concentration of the heavily doped region 112 is greater than that of the substrate 101 and the epitaxial layer 102.
依據一些實施例，如第1L圖所示，透過沉積製程在第二絕緣層108和第三絕緣層110上形成第一金屬層113，第一金屬層113穿透第二絕緣層108以電性連接至重摻雜區112。在一些實施例中，第一金屬層113可為銀、銅、金、鉑、鎢、釙或其他合適的導電材料。在一些實施例中，沉積製程可為物理氣相沈積(PVD)製程、化學氣相沈積(CVD)製程、其他合適的製程或前述之組合。 According to some embodiments, as shown in FIG. 1L, a first metal layer 113 is formed on the second insulating layer 108 and the third insulating layer 110 through a deposition process, and the first metal layer 113 penetrates the second insulating layer 108 to electrically Connected to the heavily doped region 112. In some embodiments, the first metal layer 113 may be silver, copper, gold, platinum, tungsten, rhenium, or other suitable conductive materials. In some embodiments, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination thereof.
在一些實施例中，更透過沉積製程在第三絕緣層110上形成第二金屬層(未顯示)，第二金屬層穿透第三絕緣層110、閘極電極109和第二絕緣層108以電性連接至閘極電極109和遮罩電極106。在一些實施例中，第二金屬層可為銀、銅、金、鉑、鎢、釙或其他合適的導電材料。在一些實施例中，沉積製程可為物理氣相沈積(PVD)製程、化學氣相沈積(CVD)製程、其他合適的製程或前述之組合。在形成第一金屬層113和第二金屬層之後，完成半導體裝置100的製程。 In some embodiments, a second metal layer (not shown) is formed on the third insulating layer 110 through a deposition process. The second metal layer penetrates the third insulating layer 110, the gate electrode 109, and the second insulating layer 108 to It is electrically connected to the gate electrode 109 and the shield electrode 106. In some embodiments, the second metal layer may be silver, copper, gold, platinum, tungsten, rhenium, or other suitable conductive materials. In some embodiments, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination thereof. After the first metal layer 113 and the second metal layer are formed, the process of the semiconductor device 100 is completed.
依據本發明的一些實施例，透過遮罩層的設置，在移除第一絕緣層的一部分的期間，可避免過度移除第一絕緣層，即可避免第一絕緣層底切的現象。也就是說，透過遮罩層的設置，在移除第一絕緣層的一部分之後，第一絕緣層的餘留部分的頂表面可高於遮罩電極的頂表面。因此，在沉積第二絕緣層之後，第二絕緣層在第一絕緣層和遮罩電極上方形成的輪廓較不易發生逆向閘極漏電。此外，第二絕緣層在第一絕緣層和遮罩電極上方形成的輪廓也可降低閘極-汲極間電荷，進一步提升半導體裝置的效能。 According to some embodiments of the present invention, during the removal of a part of the first insulating layer through the disposition of the mask layer, excessive removal of the first insulating layer can be avoided, and the phenomenon of undercutting of the first insulating layer can be avoided. That is, through the arrangement of the mask layer, after removing a part of the first insulating layer, the top surface of the remaining portion of the first insulating layer may be higher than the top surface of the mask electrode. Therefore, after the second insulating layer is deposited, the contour formed by the second insulating layer above the first insulating layer and the shield electrode is less likely to cause reverse gate leakage. In addition, the contour of the second insulating layer formed over the first insulating layer and the shield electrode can also reduce the gate-drain charge, further improving the performance of the semiconductor device.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可更動與組合上述各種實施例。 Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can change and combine the above various implementations without departing from the spirit and scope of the present invention. example.
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