TW201926353A

TW201926353A - Method of calibrating timing of reading/writing data of memory module and system thereof

Info

Publication number: TW201926353A
Application number: TW106142201A
Authority: TW
Inventors: 楊宗和
Original assignee: 旺宏電子股份有限公司
Priority date: 2017-12-01
Filing date: 2017-12-01
Publication date: 2019-07-01

Abstract

The present invention provides a method of calibrating timing of reading/writing data of memory module, wherein the timing is in an entire cycle of a pulse and is divided into n calibration timings, and the method comprises the following steps of: providing a clock, wherein the clock has a plurality of pulses having the cycle; transmitting n commands at the n calibration timings respectively, wherein the n commands are corresponded with n testing data; receiving n response data in response to transmitting the n commands; comparing the n testing data and the n response data to obtain n comparison results of a first desire result or a second non-desire result; and indentifying a comparison result sequence having a longest-subsequent m first desire results, and deciding a related calibration timing corresponding with a pth comparison result to be the best calibration timing, wherein when m is odd number, p is (m+1)/2; and when m is even number, p is m/2 or 1+(m/2).

Description

校正記憶體模組之讀/寫資料的時序的方法及其系統Method and system for correcting timing of reading/writing data of memory module

本發明是關於一種校正記憶體模組之讀/寫資料的時序的方法及其系統，特別是關於一種使用軟體的方式來校正記憶體模組之讀/寫資料的時序的方法及其系統。The present invention relates to a method and system for correcting the timing of reading/writing data of a memory module, and more particularly to a method and system for correcting the timing of reading/writing data of a memory module by using a software.

在記憶體模組的資料的讀取或寫入的過程中，通常會需要時脈訊號來觸發。該時脈訊號通常包含複數週期性的脈波，每個脈波又包括上升緣與下降緣，當時序來到上升緣或下降緣時，資料便會從記憶體模組讀取出來，或是寫入記憶體模組，但在此上升緣或下降緣的時間點若資料有變化時，則資料的讀取或寫入就會產生錯誤，或是無法讀取或寫入。因此在資料的讀取或寫入時，時脈訊號的上升緣與下降緣都必須與資料改變的時間錯開一個適當的時間間隔，以確保資料讀寫的正確性。In the process of reading or writing data of the memory module, a clock signal is usually required to trigger. The clock signal usually includes a plurality of periodic pulse waves, and each pulse wave includes a rising edge and a falling edge. When the timing comes to the rising edge or the falling edge, the data is read from the memory module, or Write to the memory module, but if the data changes at the time of the rising edge or the falling edge, the reading or writing of the data will cause an error or cannot be read or written. Therefore, when reading or writing data, the rising edge and falling edge of the clock signal must be offset from the data change time by an appropriate time interval to ensure the correct reading and writing of the data.

請參閱第一圖，其為習知資料取樣的示意圖，橫軸方向代表時間，縱軸方向代表電壓。在第一圖中，電源電壓為VCCQ，接地電壓為VSS，VIH為使邏輯準位為高邏輯準位的輸入最小電壓，VIL為使邏輯準位為低邏輯準位的輸入最大電壓，VT代表VCCQ與VSS的中間電壓，在VT與VIH之間的電壓以及在VT與VIL之間的電壓所形成的邏輯準位則無效。Please refer to the first figure, which is a schematic diagram of sampling of conventional data. The horizontal axis represents time and the vertical axis represents voltage. In the first figure, the power supply voltage is VCCQ, the ground voltage is VSS, VIH is the input minimum voltage that makes the logic level high logic level, and VIL is the input maximum voltage that makes the logic level low logic level, VT stands for The intermediate voltage of VCCQ and VSS, the voltage between VT and VIH and the logic level formed between the voltage between VT and VIL are invalid.

在第一圖中，時脈訊號CK1具有一周期，並包含至少一脈波PL1，每一脈波PL1具有上升緣RIS1與下降緣FL1。輸入的指令CMD或資料訊號DAT[7-0]，在從電壓VCCQ轉換成電壓VSS或從電壓VSS轉換成電壓VCCQ的過程中(也就是資料訊號從1到0或從0到1)，電壓VIH/VIL與上升緣RIS1的中間電壓VT之間會間隔一設定時間(setup time)TS1與一保持時間(hold time)TH1，在該設定時間TS1與該保持時間TH1的時段內為一有效視窗，由上升緣RIS1所取樣到的資料是有效的。否則在該有效是衝的時段外則可能取樣到無效的邏輯準位，使得取樣到的是無效的資料或是錯誤的資料。In the first figure, the clock signal CK1 has a period and includes at least one pulse wave PL1, and each pulse wave PL1 has a rising edge RIS1 and a falling edge FL1. The input command CMD or the data signal DAT[7-0] is converted from the voltage VCCQ to the voltage VSS or the voltage VSS to the voltage VCCQ (that is, the data signal is from 1 to 0 or from 0 to 1). A set time TS1 and a hold time TH1 are separated between the VIH/VIL and the intermediate voltage VT of the rising edge RIS1, and are an effective window during the set time TS1 and the holding time TH1. The data sampled by the rising edge RIS1 is valid. Otherwise, the invalid logic level may be sampled outside the period when the validity is rushed, so that the sampled data is invalid data or erroneous data.

一般而言，時脈訊號CK1的相位偏移會受到實際物理特性的影響、例如，在系統的匯流排上的承載時脈訊號CK1的導線長度、以及承載指令訊號CMD或資料訊號DAT的導線長度不同時，則時脈訊號CK1的上升緣RIS1與下降緣FL1與資料改變的時間就會與預定的時脈相位有所偏差。再者，時脈訊號CK1的驅動能力的強弱、電路的充電或放電能力也會影響到上升緣RIS1與下降緣FL1的時間延遲。雖然工程師可在模組整合成系統的階段藉由加掛電阻器與電容器在承載時脈訊號CK1的導線上，而可調整上升緣RIS1與下降緣FL1的時間延遲，然而若要依據不同廠商或型號的複雜物理特性與硬體電路來分別調校出適合的時序的時脈，以系統的角度來看，並不是十分有效率且又有效的做法，特別是不同廠商的系統處理單元與不同廠商的記憶體模組進行整合時。In general, the phase offset of the clock signal CK1 is affected by the actual physical characteristics, for example, the length of the wire carrying the clock signal CK1 on the bus bar of the system, and the length of the wire carrying the command signal CMD or the data signal DAT. At the same time, the rising edge RIS1 of the clock signal CK1 and the falling edge FL1 and the time when the data is changed may deviate from the predetermined clock phase. Furthermore, the driving ability of the clock signal CK1 and the charging or discharging capability of the circuit also affect the time delay of the rising edge RIS1 and the falling edge FL1. Although the engineer can adjust the time delay of the rising edge RIS1 and the falling edge FL1 by adding a resistor and a capacitor on the wire carrying the clock signal CK1 during the integration of the module into the system, however, depending on different manufacturers or The complex physical characteristics of the model and the hardware circuit to adjust the timing of the appropriate timing, from a system point of view, is not very efficient and effective, especially system processing units and different manufacturers from different manufacturers. When the memory module is integrated.

通常系統廠商，例如機上盒、手機內建記憶體模組等、在開發產品時會考量產品的功能、成本等需求，而在設計開發階段就會選擇不同的廠商的系統處理單元與不同廠商的記憶體模組來搭配，因此若能提供一種方法與系統，能夠將這些不同的廠商的系統處理單元與不同廠商的記憶體模組調校後，所得到的對於時脈的調校參數儲存起來，以提供日後下游的系統廠商快速地導入其產品中，將是十分令人期待的。Usually system manufacturers, such as set-top boxes, mobile phone built-in memory modules, etc., will consider the functions and costs of the products when developing products, and select different manufacturers' system processing units and different manufacturers in the design and development stage. The memory module is matched, so if a method and system can be provided, the system processing unit of these different manufacturers can be adjusted with the memory modules of different manufacturers, and the obtained tuning parameters for the clock are stored. It will be very exciting to provide system vendors that will be introduced downstream in the future.

有鑒於此，期待有一種校正記憶體模組之讀/寫資料的時序的方法及其系統，不論在何種不同廠商的系統處理單元與不同廠商的記憶體模組進行整合時，啟動引導程式都能夠在整合之系統啟動時，藉由調整時序參數來調整時脈的相位，以達到最佳化的資料取樣之校正時序，並將這些時序參數儲存起來，每一時序參數分別對應到特定的系統處理單元與特定的記憶體模組，這些參數便可提供系統整合的廠商來快速導入其產品，而無須在整合整個系統時再去針對不同的電路結構作調校。In view of this, it is expected that there is a method and system for correcting the timing of reading/writing data of a memory module, and starting the boot program regardless of the integration of the system processing units of different manufacturers with the memory modules of different manufacturers. The phase of the clock can be adjusted by adjusting the timing parameters when the integrated system is started to achieve the optimized timing of the data sampling, and the timing parameters are stored, and each timing parameter corresponds to a specific one. The system processing unit and the specific memory module, these parameters can provide system integration manufacturers to quickly import their products without having to adjust the different circuit structures when integrating the whole system.

本發明的構想是提供一種校正記憶體模組之讀/寫資料的時序的啟動引導程式、方法及其系統，啟動引導程式包含控制時脈的相位之時序參數，時脈具有一周期，並包括多個脈波，啟動引導程式改變時序參數，使得系統的處理單元輸出的該時脈的相位產生改變，在該周期內，相位的偏移可使用最小單位逐漸地偏移來進行，脈波先從原始的相位開始，系統的處理單元發送原始相位的脈波以及一指令至記憶體模組，記憶體模組因應該原始相位的脈波與該指令而回傳一回應資料至該系統處理單元，該系統處理單元接收並比對該回應資料是否與該指令所指示的測試資料相同，以驗證資料的取樣(寫入)是否成功，然後將第一比對結果儲存起來。該啟動引導程式接續調整時序參數而使得系統的處理單元輸出的該時脈的相位產生一或多個單位的偏移，並重覆上述的操作來比對回傳資料是否與該指令所指示的測試資料相同，然後將第二比對結果儲存起來，重覆這樣的操作直到該脈波的相位偏移經過一個周期為止，並將這些比對結果儲存到記憶單元來進行分析。該系統處理單元分析這些比對結果，找出在這些比對結果中，持續資料取樣成功維持最多的一連串比對結果，若在此一連串的比對結果的數目為單數，則取中間排序的比對結果所對應的時序參數，其所代表的時脈相位為一最佳校正時序。若為偶數，則將該一連串的比對結果的數目直接除以2，或是該一連串的比對結果的數目除以2後加1，再取經過運算的比對結果之數目所對應的時序參數，其所代表的時脈相位為一最佳校正時序。The idea of the present invention is to provide a booting program, method and system for correcting the timing of reading/writing data of a memory module. The booting program includes timing parameters for controlling the phase of the clock, the clock has a period, and includes a plurality of pulse waves, starting the boot program to change the timing parameters, so that the phase of the clock outputted by the processing unit of the system changes, in which the phase offset can be gradually shifted by using a minimum unit, the pulse wave first Starting from the original phase, the processing unit of the system sends the pulse of the original phase and an instruction to the memory module, and the memory module returns a response data to the processing unit of the system according to the pulse of the original phase and the instruction. The system processing unit receives and compares the response data to the test data indicated by the instruction to verify whether the sampling (writing) of the data is successful, and then stores the first comparison result. The booting program further adjusts the timing parameter such that the phase of the clock output by the processing unit of the system generates one or more unit offsets, and repeats the above operation to compare whether the returned data is related to the test indicated by the instruction. The data is the same, then the second alignment result is stored, and the operation is repeated until the phase shift of the pulse wave passes through one cycle, and the comparison results are stored in the memory unit for analysis. The system processing unit analyzes the comparison results and finds a series of comparison results in which the continuous data sampling is successfully maintained among the comparison results. If the number of comparison results in this series is singular, the ratio of the intermediate order is taken. For the timing parameters corresponding to the result, the clock phase represented by it is an optimal correction timing. If it is an even number, the number of the series of comparison results is directly divided by 2, or the number of the series of comparison results is divided by 2, then 1 is added, and then the timing corresponding to the number of comparison results of the operation is taken. The parameter, which represents the clock phase, is an optimal correction timing.

依據上述構想，本發明提供一種校正讀/寫資料的時序的系統，包含一啟動導引程式、一主控單元、以及一記憶體模組。該啟動導引程式具有一指令與一時序參數，該主控單元傳送該指令並依據該時序參數產生一時脈，其中該時脈根據該時序參數的不同而具有n個相位，該指令對應一測試資料。該記憶體模組藉由一系統匯流排電連接於該主控單元，該主控單元分別調整該時脈至該n個相位，該記憶體模組分別在該時脈的n個相位下接收該指令並分別產生n個回應資料，且將該n個回應資料回傳至該主控單元，其中該主控單元藉由比對該測試資料與該n個回應資料以分別產生n個暫存值，該n個暫存值形成一序列，該主控單元找出在該序列中代表連續驗證成功的一最長子序列，從該最長子序列中找出在中間順序的一特定暫存值，並以該特定暫存值所對應的該時序參數所代表的時脈相位做為一最佳校正時序。In accordance with the above concept, the present invention provides a system for correcting the timing of read/write data, comprising a boot guide, a master unit, and a memory module. The startup boot program has an instruction and a timing parameter, and the main control unit transmits the instruction and generates a clock according to the timing parameter, wherein the clock has n phases according to the timing parameter, and the instruction corresponds to a test data. The memory module is electrically connected to the main control unit by a system bus, and the main control unit respectively adjusts the clock to the n phases, and the memory module respectively receives n phases of the clock. The instruction generates n response data respectively, and returns the n response data to the main control unit, wherein the main control unit generates n temporary storage values by comparing the test data with the n response data respectively. And the n temporary storage values form a sequence, the master unit finds a longest subsequence representing the success of the continuous verification in the sequence, and finds a specific temporary storage value in the intermediate order from the longest subsequence, and The clock phase represented by the timing parameter corresponding to the specific temporary storage value is used as an optimal correction timing.

依據上述構想，本發明提供一種校正一記憶體模組之讀/寫資料的時序的方法，包含下列步驟：產生一指令與一時序參數；傳送該指令並依據該時序參數產生一時脈，其中該時脈根據該時序參數的不同而具有n個相位，該指令對應一測試資料；分別調整該時脈至該n個相位，該記憶體模組分別在該時脈的n個相位下接收該指令，並分別產生n個回應資料；比對該測試資料與該n個回應資料以產生n個暫存值，該n個暫存值形成一序列;以及找出在該序列中代表連續驗證成功的一最長子序列，從該最長子序列找出在中間順序的一特定暫存值，並以該特定暫存值所對應的該時序參數所代表的時脈相位做為一最佳校正時序。According to the above concept, the present invention provides a method for correcting the timing of reading/writing data of a memory module, comprising the steps of: generating an instruction and a timing parameter; transmitting the instruction and generating a clock according to the timing parameter, wherein the The clock has n phases according to the timing parameter, the command corresponds to a test data; the clock is respectively adjusted to the n phases, and the memory module receives the command in n phases of the clock respectively And generating n response data respectively; comparing the test data with the n response data to generate n temporary storage values, the n temporary storage values form a sequence; and finding out that the continuous verification succeeds in the sequence A longest subsequence is obtained from the longest subsequence to find a specific temporary storage value in the intermediate sequence, and the clock phase represented by the timing parameter corresponding to the specific temporary storage value is used as an optimal correction timing.

依據上述構想，本發明提供一種校正讀/寫資料的一時序的方法，包含下列步驟：提供一時脈，其中該時脈具有分別含n個相位之n個脈波，其中該n個相位分別對應n個時序參數，且該n個時序參數分別對應n個校正時序;在該時脈之該n個相位下分別傳送n個指令，其中該n個指令對應n個測試資料；因應所傳送的該n個指令而分別接收n個回應資料；比對該n個測試資料與該n個回應資料以獲得屬於第一所欲或第二非所欲結果之n個比較結果，其中該n個比較結果分別對應該n個時序參數及該n個校正時序；以及找出具有最長連續m個第一所欲結果之一比較結果序列，並決定以一第p個比較結果對應的校正時序為一最佳校正時序，其中當m為奇數時，p為(m+1)/2，而當m為偶數時，p為m/2或1+(m/2)。In accordance with the above concept, the present invention provides a method of correcting a timing of read/write data, comprising the steps of: providing a clock, wherein the clock has n pulses each having n phases, wherein the n phases respectively correspond n timing parameters, and the n timing parameters respectively correspond to n correction timings; respectively, n instructions are transmitted under the n phases of the clock, wherein the n instructions correspond to n test data; n instructions respectively receiving n response data; comparing the n test data and the n response data to obtain n comparison results belonging to the first desired or second undesired result, wherein the n comparison results Corresponding to n timing parameters and the n correction timings respectively; and finding a comparison result sequence having one of the longest consecutive m first desired results, and determining the correction timing corresponding to a p-th comparison result as the best The timing is corrected, where p is (m+1)/2 when m is an odd number, and p is m/2 or 1+(m/2) when m is an even number.

依據上述構想，本發明提供一種校正讀/寫資料的一時序的方法，其中該時序在一脈波之一完整週期內，區分成n個校正時序，該方法包含下列步驟：提供一時脈，其中該時脈具有複數個具該週期之脈波；分別於該n個校正時序，傳送n個指令，其中該n個指令對應n個測試資料；因應所傳送的該n個指令，而分別接收n個回應資料；比對該n個測試資料與該n個回應資料以獲得屬於第一所欲或第二非所欲結果之n個比較結果；以及找出具有最長連續m個第一所欲結果之一比較結果序列，並決定以一第p個比較結果所對應之一該相關校正時序為一最佳校正時序，其中當m為奇數時，p為(m+1)/2，而當m為偶數時，p為m/2或1+(m/2)。In accordance with the above concept, the present invention provides a method of correcting a timing of read/write data, wherein the timing is divided into n correction timings in one complete cycle of a pulse wave, the method comprising the steps of: providing a clock, wherein The clock has a plurality of pulse waves having the cycle; respectively, n instructions are transmitted in the n correction timings, wherein the n instructions correspond to n test data; respectively, corresponding to the n instructions transmitted, respectively receiving n Response data; comparing the n test data with the n response data to obtain n comparison results belonging to the first desired or second undesired result; and finding the longest continuous m first desired results One compares the result sequence and determines that the correlation correction timing is one of the optimal correction timings corresponding to one of the pth comparison results, wherein when m is an odd number, p is (m+1)/2, and when m When it is an even number, p is m/2 or 1+(m/2).

本發明可使不同廠商或型號(規格)的主控單元與不同廠商或型號(規格)的記憶體體模組整合時，將每種組合的最佳化校正時序的相對應時序參數儲存起來，在日後系統啟動時可直接偵測型號並直接套用相對應的最佳時序參數，以加快整合的流程。同時，本發明的調校方法可更精準地找出恰當的時脈的資料取樣點，而使資料的讀寫在經過時脈的調校後不僅更快速，也更加穩定無錯誤。請參閱下文與圖式來對本發明進一步的了解。The invention can store the corresponding timing parameters of the optimized correction timing of each combination when the main control unit of different manufacturers or models (specifications) is integrated with the memory modules of different manufacturers or models (specifications), In the future, the system can directly detect the model and directly apply the corresponding optimal timing parameters to speed up the integration process. At the same time, the calibration method of the present invention can more accurately find the data sampling points of the appropriate clock, and the reading and writing of the data is not only faster but also more stable and error-free after the adjustment of the clock. Please refer to the following figures and drawings for further understanding of the present invention.

本發明提供下列較佳實施例來說明本發明的精神，為了更簡潔表述本發明而省略了部分元件，而在各實施例之間可互相組合形成新的實施例，且在較佳實施例中的具體形狀、結構、裝置以及參數值並非用來限制本創作，凡熟知此技藝者當可做出更動或潤飾，其皆在本發明的範圍內。The present invention is provided to illustrate the spirit of the present invention. For the sake of brevity of the present invention, some of the elements are omitted, and the embodiments may be combined with each other to form a new embodiment, and in the preferred embodiment. The specific shapes, structures, devices, and parameter values are not intended to limit the present invention, and those skilled in the art can make modifications or refinements, which are within the scope of the present invention.

請同時參閱第二圖與第三圖，第二圖為本發明較佳實施例校正一記憶體模組103之讀寫資料的時序的示意圖。第三圖為本發明較佳實施例校正讀/寫資料的時序的系統10的示意圖。該系統10包含一啟動引導程式101、一主控單元102、以及一記憶體模組103。啟動引導程式101可儲存於非揮發性記憶體中，在步驟S100開始時，系統10啟動時，引導程式101會載入該主控單元102，該主控單元102會根據啟動引導程式101來執行該系統10開機的運作。該記憶體模組103包含記憶體控制單元1031以及複數記憶體胞元1032，且其類型包含固態硬碟(SSD)、嵌入式多媒體記憶卡(eMMC)、或其他具有記憶體控制器1031與複數記憶體胞元1032整合在一起的模組等等，例如micro SD卡與讀卡機的結合。記憶體控制單元1031與複數記憶體胞元1032之間藉由一以記憶體匯流排1033電連接並相互溝通訊息，主控單元102與記憶體模組103之間藉由一系統匯流排104電連接並相互溝通訊息。Please refer to the second and third figures. The second figure is a schematic diagram for correcting the timing of reading and writing data of a memory module 103 according to a preferred embodiment of the present invention. The third diagram is a schematic diagram of a system 10 for correcting the timing of read/write data in accordance with a preferred embodiment of the present invention. The system 10 includes an activation boot program 101, a main control unit 102, and a memory module 103. The booting program 101 can be stored in the non-volatile memory. At the beginning of step S100, when the system 10 is started, the booting program 101 loads the main control unit 102, and the main control unit 102 executes according to the booting program 101. The system 10 is powered on. The memory module 103 includes a memory control unit 1031 and a plurality of memory cells 1032, and the type thereof includes a solid state drive (SSD), an embedded multimedia memory card (eMMC), or the like, and has a memory controller 1031 and a plurality of The modules in which the memory cells 1032 are integrated, and the like, such as a combination of a micro SD card and a card reader. The memory control unit 1031 and the plurality of memory cells 1032 are electrically connected and communicate with each other by a memory bus 1033. The main control unit 102 and the memory module 103 are electrically connected by a system bus 104. Connect and communicate with each other.

請同時參考第二圖與第三圖，該記憶體模組103以eMMC為例，在步驟S101中，在系統10啟動時，主控單元102傳送指令CMD 8至記憶體模組103，以讀取記憶體模組103的種類，指令CMD 8是用來讀取eMMC的暫存器中的值，記憶體模組103的記憶體控制單元1031會因應所接收到的指令CMD 8，而透過系統匯流排104回傳包含該記憶體模組103當前可支持的各參數與狀態的資訊至該主控單元102。在步驟S102中，主控單元102接收來自記憶體控制單元1031的該些資訊，以判斷該記憶體模組是否支持一第一操作模式，例如HS200的操作模式，也就是時脈的頻率是運作在200MHz的頻率。需要注意的是，所有的時脈都由主控單元102提供，也由主控單元102來調控，因此從主控單元102發出的時脈與資料的相對應的取樣時間點可較容易掌控，而從記憶體模組103回傳的資料所需的時脈也是由主控單元102來提供，故從記憶體模組103回傳的資料與來自主控單元102的時脈的取樣時間點需要調校，以獲取最佳的資料讀寫時序，最大限度來避免資料的讀寫錯誤。Referring to the second and third figures, the memory module 103 takes the eMMC as an example. In step S101, when the system 10 is started, the main control unit 102 transmits the command CMD 8 to the memory module 103 to read. Taking the type of the memory module 103, the command CMD 8 is used to read the value in the register of the eMMC, and the memory control unit 1031 of the memory module 103 transmits the system according to the received command CMD 8. The bus bar 104 returns information including the parameters and states currently supported by the memory module 103 to the main control unit 102. In step S102, the main control unit 102 receives the information from the memory control unit 1031 to determine whether the memory module supports a first operation mode, such as the operation mode of the HS200, that is, the frequency of the clock is operated. At a frequency of 200MHz. It should be noted that all the clocks are provided by the main control unit 102, and are also controlled by the main control unit 102. Therefore, the clocks sent from the main control unit 102 and the corresponding sampling time points of the data can be easily controlled. The clock required for the data returned from the memory module 103 is also provided by the main control unit 102, so the data returned from the memory module 103 and the sampling time point of the clock from the main control unit 102 are required. Tuning to get the best data read and write timing, to avoid reading and writing errors.

在第二圖與第三圖中，在步驟S104中，若步驟S102的判斷為否，則流程進入步驟S103，結束此調校流程；若步驟S102的判斷為是，則該主控單元102傳送指令CMD 6至該記憶體模組103，以設定系統匯流排104以及記憶體匯流排1033的寬度為4位元或是8位元，然後流程進入步驟S105。在步驟S105中，主控單元102發送指令CMD 8至該記憶體模組103，以讀取該記憶體模組103的驅動強度參數。在步驟S106中，該主控單元102發送指令CMD 6至該記憶體模組103，以設定該記憶體模組103在第一操作模式，並設定其驅動強度的值。例如設定該記憶體模組103在HS200的操作模式，並設定在HS200的操作模式下的驅動強度。在步驟S107中，該主控單元102判斷該記憶體模組103是否忙碌中，若忙碌，則重覆檢查該記憶體模組103是否忙碌；若不忙碌，則進入步驟S108。在步驟S108中，主控單元102發送指令CMD 13至該記憶體模組103，使該記憶體模組103回報自身的狀態，若該記憶體模組103的狀態有錯誤的情況發生，則進入步驟S103，結束此調校流程；若該記憶體模組103的狀態沒有錯誤的情況發生，則進入步驟S109。In the second and third figures, in step S104, if the determination in step S102 is no, the flow proceeds to step S103, and the calibration process is ended; if the determination in step S102 is YES, the main control unit 102 transmits The CMD 6 is instructed to the memory module 103 to set the width of the system bus bar 104 and the memory bus bar 1033 to be 4-bit or 8-bit, and the flow proceeds to step S105. In step S105, the main control unit 102 sends the command CMD 8 to the memory module 103 to read the driving strength parameter of the memory module 103. In step S106, the main control unit 102 sends the command CMD 6 to the memory module 103 to set the memory module 103 in the first operation mode and set the value of the driving strength. For example, the operation mode of the memory module 103 in the HS 200 is set, and the driving strength in the operation mode of the HS 200 is set. In step S107, the main control unit 102 determines whether the memory module 103 is busy. If it is busy, it repeatedly checks whether the memory module 103 is busy. If it is not busy, it proceeds to step S108. In step S108, the main control unit 102 sends the command CMD 13 to the memory module 103, so that the memory module 103 returns its own state, and if the state of the memory module 103 is wrong, it enters In step S103, the calibration process is ended. If the state of the memory module 103 is not erroneous, the process proceeds to step S109.

在步驟S109中，主控單元102可改變操作模式從該第一操作模式至一第二操作模式，例如當第一操作模式的時脈為200MHz時，改變時脈的頻率使其小於200MHz，由於頻率變小，上升緣與下降緣的密度也不會太高，資料讀寫的錯誤也比較不容易發生，但讀寫的速率會降低。在步驟S110中，主控單元102可進一步導入調校的程序，例如發送一調校指令CMD 21至該記憶體模組103，以調校時脈的取樣時間點，請詳見後文的說明。在步驟S111中，若在步驟S110中的調校程序尚未完畢，則回到步驟S110中繼續調校；若在步驟S110中的調校程序已經完畢，則進入步驟S112，第一操作模式或第二操作模式的選擇已經完成，該系統10可在該第一操作模式或該第二操作模式下運行。值得注意的是，若在步驟S110進一步的調校的過程中，發生資料讀寫錯誤或逾時，則該主控單元102可降低時脈的頻率；在步驟S110進一步的調校的過程中能完成最佳化的時序取樣點，則可提升時脈的頻率，例如提升至400MHz，也就是可在dual rate HS400的操作模式下運行，同時兼顧資料讀寫的正確性與速率，請詳見後文說明。In step S109, the main control unit 102 can change the operation mode from the first operation mode to a second operation mode, for example, when the clock of the first operation mode is 200 MHz, the frequency of the clock is changed to be less than 200 MHz, The frequency becomes smaller, the density of the rising edge and the falling edge are not too high, and errors in reading and writing data are less likely to occur, but the rate of reading and writing is reduced. In step S110, the main control unit 102 can further import the calibration program, for example, send a calibration command CMD 21 to the memory module 103 to adjust the sampling time point of the clock, please refer to the following description. . In step S111, if the calibration procedure in step S110 has not been completed, then return to step S110 to continue the calibration; if the calibration procedure in step S110 has been completed, proceed to step S112, the first operation mode or the first The selection of the two modes of operation has been completed and the system 10 can operate in either the first mode of operation or the second mode of operation. It should be noted that, if a data read/write error or timeout occurs during the further adjustment in step S110, the main control unit 102 can reduce the frequency of the clock; in the process of further adjusting in step S110, Completing the optimized timing sampling point can increase the frequency of the clock, for example, to 400MHz, that is, it can be operated in the operating mode of the dual rate HS400, while taking into account the correctness and rate of data reading and writing, please see later. Description.

請參閱下列表1以及第四圖，表1為本發明較佳實施例的時序參數對照時脈的相位之對照表，第四圖為本發明較佳實施例的時脈CK2的相位依據時序參數來調整的示意圖，時脈CK2具有一週期T2並包含複數脈波PL2，每一脈波PL2包含上升緣RIS2與下降緣FL2。表1中的SELCLK_SAMPLE(後文以時序參數CT來表示)代表主控單元102的暫存器中的第0到第2個位元，其為二進制一共3個位元，可用來粗調控時脈CK2的相位之偏移，所以粗調一共有2^3=8種步階之相位可以偏移。表1中的SAMPLE_CLK_TUNING(後文以時序參數FT來表示，粗調與微調所形成的時序參數以CTFT來表示)代表主控單元102的暫存器中的第6到第7個位元，其為二進制一共2個位元，可用來微調控時脈CK2的相位之偏移，所以在粗調中還可細分成微調一共有2^2=4種步階之相位可以偏移。所以以此較佳實施例來說，粗調與微調在一週期T2內一共有8×4=32種步階之相位可以偏移。而粗調偏移一個相位單位為360度÷8=45度，微調偏移一個相位單位為45度÷4=11.25度。表1 Please refer to the following Table 1 and the fourth figure. Table 1 is a comparison table of timing parameters of clocks according to a preferred embodiment of the present invention, and FIG. 4 is a timing chart of phase of clock CK2 according to a preferred embodiment of the present invention. For the adjustment diagram, the clock CK2 has a period T2 and includes a plurality of pulse waves PL2, and each pulse wave PL2 includes a rising edge RIS2 and a falling edge FL2. SELCLK_SAMPLE in Table 1 (hereinafter referred to as timing parameter CT) represents the 0th to 2nd bits in the register of the main control unit 102, which is a total of 3 bits in binary, which can be used to coarsely control the clock. The phase shift of CK2, so the coarse adjustment has a total of 2^3 = 8 steps of phase can be offset. SAMPLE_CLK_TUNING in Table 1 (hereinafter referred to as timing parameter FT, the timing parameters formed by coarse tuning and fine tuning are represented by CTFT) represents the 6th to 7th bits in the register of the main control unit 102, A total of 2 bits for the binary can be used to fine-tune the phase shift of the clock CK2, so it can be subdivided into fine-tuning in the coarse adjustment. A total of 2^2=4 steps can be offset. Therefore, in the preferred embodiment, the coarse and fine adjustments can be offset by a total of 8 x 4 = 32 steps in a period T2. The coarse adjustment offset has a phase unit of 360 degrees ÷ 8 = 45 degrees, and the fine adjustment offset has a phase unit of 45 degrees ÷ 4 = 11.25 degrees. Table 1

請同時參閱表1、第三圖、以及第四圖，本發明較佳實施例校正讀/寫資料的時序的系統10包含一啟動引導程式101、一主控單元102、以及一記憶體模組103。該啟動導引程式101具有一指令CMD 21與一時序參數CT, FT。該主控單元102傳送該指令CMD 21並依據該時序參數CT, FT產生一時脈CK2，其中該時脈CK2根據該時序參數CT, FT的不同而具有n個相位(如第四圖所示)，該指令CMD 21對應一測試資料(未顯示)。該記憶體模組103藉由一系統匯流排104電連接於該主控單元102，該主控單元102分別調整該時脈CK2至該n個相位，該記憶體模組103分別在該時脈的n個相位下接收該指令CMD 21並分別產生n個回應資料RS1~RSn，且將該n個回應資料RS1~RSn回傳至該主控單元102。Referring to Table 1, FIG. 3, and FIG. 4 simultaneously, the system 10 for correcting the timing of reading/writing data includes a booting program 101, a main control unit 102, and a memory module. 103. The bootstrapping program 101 has an instruction CMD 21 and a timing parameter CT, FT. The main control unit 102 transmits the command CMD 21 and generates a clock CK2 according to the timing parameter CT, wherein the clock CK2 has n phases according to the timing parameter CT, FT (as shown in the fourth figure). The instruction CMD 21 corresponds to a test data (not shown). The memory module 103 is electrically connected to the main control unit 102 by a system bus bar 104. The main control unit 102 respectively adjusts the clock CK2 to the n phases, and the memory module 103 is respectively at the clock. The command CMD 21 is received in the n phases and n response data RS1~RSn are respectively generated, and the n response data RS1~RSn are transmitted back to the main control unit 102.

請參閱第五圖，其為本發明較佳實施例驗證資料的讀寫的示意圖。請同時參考表1、以及第三圖~第五圖，其中該主控單元102藉由比對該測試資料與該n個回應資料RS1~RSn以分別產生n個暫存值，在本發明較佳實施例中，因為粗調與微調一共有5個位元可以設定，所以共有2^5=32個不同的時序參數用來嘗試，也就一共有32個暫存值產生。該n個暫存值形成一序列SQ1，該主控單元102找出在該序列SQ1中代表連續驗證成功的一最長子序列sq11，從該最長子序列sq11中找出在中間順序的一特定暫存值，並以該特定暫存值所對應的該時序參數所代表的時脈相位做為一最佳校正時序。Please refer to the fifth figure, which is a schematic diagram of reading and writing of verification data according to a preferred embodiment of the present invention. Please refer to Table 1, and the third to fifth figures, wherein the main control unit 102 generates n temporary storage values by comparing the test data with the n response data RS1~RSn, which is preferred in the present invention. In the embodiment, since a total of 5 bits can be set for the coarse adjustment and the fine adjustment, a total of 2^5=32 different timing parameters are used for the attempt, and a total of 32 temporary values are generated. The n temporary storage values form a sequence SQ1, and the main control unit 102 finds a longest subsequence sq11 representing the success of the continuous verification in the sequence SQ1, and finds a specific temporary in the intermediate order from the longest subsequence sq11 The value is stored, and the clock phase represented by the timing parameter corresponding to the specific temporary storage value is used as an optimal correction timing.

請同時參閱表1、第三圖、第四圖、以及第五圖，例如在本發明較佳實施例中，在第四圖中的上升緣RIS2與下降緣FL2會隨著時脈CK2的相位的偏移而改變其取樣的時間點，時脈CK2的相位偏移可以步階的方式持續直到完成一個周期T2為止，每偏移一個步階的相位，主控單元102就開始傳送指令CMD 21與第一時序參數CTFT1到記憶體模組103，例如第一時序參數CTFT1包含粗調加上微調的位元值為00000，則時脈CK2的偏移相位為0度，也就是時脈CK2的相位不偏移，記憶體模組103的記憶體控制單元1031因應指令CMD 21與第一時序參數CTFT1而回傳回應資料RS1至主控單元102，主控單元102比對指令CMD 21所代表的第一測試資料與回應資料RS1，當兩者一致，則表示在時脈CK2的偏移相位為0度時，指令CMD 21成功被記憶體模組103接收，且回應資料RS1也成功被讀取。主控單元102產生暫存值1並將其儲存至第一個暫存器中，代表在時脈CK2的偏移相位為0度時不會有資料讀寫錯誤發生。Please refer to Table 1, FIG. 3, FIG. 4, and FIG. 5 at the same time. For example, in the preferred embodiment of the present invention, the rising edge RIS2 and the falling edge FL2 in the fourth figure will follow the phase of the clock CK2. The offset of the time point at which the sampling is changed, the phase shift of the clock CK2 can be continued in steps until the completion of one period T2, and each time the phase of one step is shifted, the main control unit 102 starts transmitting the command CMD 21 And the first timing parameter CTFT1 to the memory module 103, for example, the first timing parameter CTFT1 includes a coarse adjustment plus a fine adjustment of a bit value of 00000, and the offset phase of the clock CK2 is 0 degrees, that is, the clock. The phase of the CK2 is not offset, and the memory control unit 1031 of the memory module 103 returns the response data RS1 to the main control unit 102 in response to the command CMD 21 and the first timing parameter CTFT1, and the main control unit 102 compares the command CMD 21 The first test data and the response data RS1 are represented. When the two are consistent, it indicates that when the offset phase of the clock CK2 is 0 degrees, the command CMD 21 is successfully received by the memory module 103, and the response data RS1 is also successful. Was read. The main control unit 102 generates the temporary value 1 and stores it in the first register, indicating that no data read/write error occurs when the offset phase of the clock CK2 is 0 degrees.

接續下來，主控單元102就開始傳送指令CMD 21與第二時序參數CTFT2到記憶體模組103，例如第二時序參數CTFT2包含粗調加上微調的位元值為00001，則時脈CK2的偏移相位為11.25度，記憶體模組103的記憶體控制單元1031因應指令CMD 21與第二時序參數CTFT2而回傳回應資料RS2至主控單元102，主控單元102比對指令CMD 21所代表的第二測試資料與回應資料RS2，當兩者一致，則表示在時脈CK2的偏移相位為11.25度時，指令CMD 21成功被記憶體模組103接收，且回應資料RS2也成功被讀取。主控單元102產生暫存值1並將其儲存至第二個暫存器中，代表在時脈CK2的偏移相位為11.25度時不會有資料讀寫錯誤發生。In the following, the main control unit 102 starts to transmit the command CMD 21 and the second timing parameter CTFT2 to the memory module 103. For example, the second timing parameter CTFT2 includes the coarse adjustment plus the fine adjustment bit value of 0001, then the clock CK2 The offset phase is 11.25 degrees, and the memory control unit 1031 of the memory module 103 returns the response data RS2 to the main control unit 102 in response to the command CMD 21 and the second timing parameter CTFT2, and the main control unit 102 compares the command CMD 21 The second test data and the response data RS2 are represented. When the two are consistent, it indicates that when the offset phase of the clock CK2 is 11.25 degrees, the command CMD 21 is successfully received by the memory module 103, and the response data RS2 is successfully succeeded. Read. The main control unit 102 generates a temporary value of 1 and stores it in the second temporary register, indicating that no data read/write error occurs when the offset phase of the clock CK2 is 11.25 degrees.

接續下來，類似的動作重複進行，當主控單元102比對指令CMD 21所代表的第七個測試資料與回應資料RS7，兩者不一致時，主控單元102產生暫存值0並將其儲存至第七個暫存器中，代表在時脈CK2的偏移相位為11.25×7=78.75度時，資料讀寫錯誤發生。In the following, the similar action is repeated. When the main control unit 102 compares the seventh test data and the response data RS7 represented by the command CMD 21, the main control unit 102 generates a temporary value of 0 and stores it. In the seventh register, the data read and write error occurs when the offset phase of the clock CK2 is 11.25×7=78.75 degrees.

接續下來，類似的動作重複進行，直到主控單元102比對指令CMD 21所代表的第n-1個測試資料與回應資料RSn-1，產生暫存值1並將其儲存至第n-1個暫存器中、主控單元102比對指令CMD 21所代表的第n個測試資料與回應資料RSn，產生暫存值1並將其儲存至第n個暫存器中，而完成了整個校正的程序，相位偏移至下一個周期T2所得到的資料驗證或比對的結果將會與上一個周期T2所得到的資料驗證或比對的結果相同，因相位偏移此無須再繼續。In the following, the similar action is repeated until the main control unit 102 compares the n-1th test data and the response data RSn-1 represented by the command CMD 21, and generates a temporary value of 1 and stores it to the n-1th. In the temporary register, the main control unit 102 compares the nth test data and the response data RSn represented by the instruction CMD 21, generates a temporary value 1 and stores it in the nth temporary register, and completes the whole The corrected program, the phase offset to the next period T2, the data verification or comparison result will be the same as the data verification or comparison result obtained in the previous period T2, because the phase offset does not need to continue.

在第五圖中，因為資料驗證或比對的結果是周期性的重復出現，所以第30~32次的資料驗證或比對的結果之後，接續將會是第1~6次的資料驗證或比對的結果。在本發明較佳實施例中，第30~32次的資料驗證或比對的結果，以及第1~6次的資料驗證或比對的結果，兩者形成了第一個連續傳輸成功的最長子序列sq11，在此最長子序列sq11中一共有9個暫存值，主控單元102找出中間順序的暫存值，也就是最長子序列sq11中的第5個暫存值，以該第五個暫存值所對應到的時序參數所代表的時脈相位做為一最佳校正時序，即以第二個步階的偏移的相位11.25×2=22.5度作為最佳校正時序。In the fifth picture, because the data verification or comparison results are periodically repeated, after the 30th to 32nd data verification or comparison results, the connection will be the first to sixth data verification or The result of the comparison. In the preferred embodiment of the present invention, the 30th to 32nd data verification or comparison results, and the 1st to 6th data verification or comparison results, the two form the longest success of the first continuous transmission. The subsequence sq11 has a total of 9 temporary storage values in the longest subsequence sq11, and the main control unit 102 finds the intermediate order temporary storage value, that is, the fifth temporary storage value in the longest subsequence sq11, The clock phase represented by the timing parameters corresponding to the five temporary values is used as an optimal correction timing, that is, the phase of the offset of the second step is 11.25×2=22.5 degrees as the optimal correction timing.

以上的時脈之調校可在第二圖的步驟S110中來完成，若最長子序列sq11中的暫存值的數量為偶數，則可將偶數數量直接除以2，或是將偶數數量除以2後加1，再取經過運算的比對結果之數目所對應的時序參數，其所代表的時脈相位為一最佳校正時序。若調校過程順利，則可提升時脈CK2的頻率，例如可提升到400MHz的操作模式HS400，也就是上升緣RIS2與下降緣FL2都會對資料取樣的兩倍取樣速率的動作，這相對於在操作模式HS200之下僅統一在上升緣RIS2對資料取樣，或統一在下降緣FL2對資料取樣的情況下，都展現出更快的資料讀寫速率；反之，若調校過程不順利，則主控單元102需降低時脈CK2的頻率後，例如從200MHz調降至133MHz，然後再重新調校一次。藉由本發明，該最佳校正時序可使該n個回應資料RS1~RSn與該上升緣RIS2之間具有確保資料能被讀寫的一起始時間間隔TS1(套用到第一圖中)，且使該n個回應資料RS1~RSn與該下降緣FL2之間具有確保資料能被讀寫的一保持時間間隔TH1(套用到第一圖中)。The adjustment of the above clock can be completed in step S110 of the second figure. If the number of temporary values in the longest subsequence sq11 is even, the number of even numbers can be directly divided by 2, or the number of even numbers can be divided. After adding 2 to 2, and taking the timing parameter corresponding to the number of comparison results of the operation, the clock phase represented by it is an optimal correction timing. If the tuning process is smooth, the frequency of the clock CK2 can be increased, for example, the operating mode HS400 can be upgraded to 400 MHz, that is, the rising edge RIS2 and the falling edge FL2 both have twice the sampling rate of the data sampling action, which is relative to Under the operating mode HS200, only the data is sampled at the rising edge RIS2, or the data is sampled at the falling edge FL2, which shows a faster data reading and writing rate; otherwise, if the tuning process is not smooth, the main The control unit 102 needs to lower the frequency of the clock CK2, for example, from 200MHz to 133MHz, and then re-adjust it once. According to the present invention, the optimal correction timing can have a start time interval TS1 (applied to the first picture) between the n response data RS1~RSn and the rising edge RIS2 to ensure that the data can be read and written, and There is a hold time interval TH1 (applied to the first figure) between the n response data RS1~RSn and the falling edge FL2 to ensure that the data can be read and written.

在本案較佳實施例中，若主控單元102發送指令CMD 21到記憶體模組103，而記憶體模組103並未順利接收指令CMD 21，即逾時而主控單元102未收到記憶體模組103回傳的回應資料RS1~RSn，則主控單元102可對此種一連串逾時而未收到回傳的回應資料RS1~RSn的狀況採取降頻的措施，降低時脈CK2的頻率後重新再調校一次，或是在第一次完整調校過後，記錄並分析這些比對結果，然後再決定是否對時脈CK2降頻。In the preferred embodiment of the present invention, if the main control unit 102 sends the command CMD 21 to the memory module 103, and the memory module 103 does not successfully receive the command CMD 21, that is, the timeout period and the main control unit 102 does not receive the memory. The response data RS1~RSn returned by the body module 103 can be used by the main control unit 102 to reduce the frequency of the response data RS1~RSn that has not received the return message, and reduce the clock CK2. After the frequency is re-tuned again, or after the first complete calibration, record and analyze the comparison results before deciding whether to downgrade the clock CK2.

請參閱第六圖，其為本發明另一較佳實施例驗證資料的讀寫的示意圖。總序列SQ2包含資料連續取樣成功的第一子序列sq21與第二子序列sq22，兩個子序列sq21, sq22中，連續驗證資料成功的數目都是9，則主控單元102選取第一子序列sq21，再找出第一子序列sq21中在其中間排序位置所對應到的時序參數。Please refer to a sixth figure, which is a schematic diagram of reading and writing of verification data according to another preferred embodiment of the present invention. The total sequence SQ2 includes the first subsequence sq21 and the second subsequence sq22 in which the data is continuously sampled successfully. In the two subsequences sq21, sq22, the number of consecutive verification data successes is 9, and the main control unit 102 selects the first subsequence. Sq21, and then find the timing parameters corresponding to the position in the middle of the first subsequence sq21.

在第六圖中，當第一子序列sq21在時脈偏移至某個相位而遇到讀或寫資料的驗證失敗時，則第一子序列sq21的長度小於第二子序列sq22，主控單元102可選擇第二子序列sq22來分析，找出第二子序列sq22中在其中間排序位置所對應到的時序參數，例如第17個時序參數為10001，其對應到第17個步階的相位偏移=11.25×17=191.25度，將時脈CK2的相位偏移(或延遲)191.25度後，將其作為最佳校正時序。若兩個子序列sq21, sq22中都出現資料驗證失敗，則該主控單元102可降低時脈CK2的頻率。不同廠商或型號(規格)的主控單元102，可在與不同廠商或型號(規格)的記憶體體模組103整合時，將每種組合的最佳化校正時序的相對應時序參數儲存起來，在日後系統10啟動時可直接偵測型號並直接套用相對應的最佳時序參數，以加快整合的流程，這對下游整合晶片的系統廠商頗有助益。另一方式是根據系統廠商所組合的主控單元102與記憶體模組103，可直接把時序參數提供給他們，系統廠商載選定晶片的組合後，將所提供的時序參數直接寫入啟動導引程式101中不再變更，因為消費者使用的是整合後的系統，不會任意對主控單元102或記憶體模組103做更換。In the sixth figure, when the first subsequence sq21 fails to verify the read or write data when the clock is shifted to a certain phase, the length of the first subsequence sq21 is smaller than the second subsequence sq22, and the main control The unit 102 may select the second subsequence sq22 for analysis to find the timing parameter corresponding to the position in the middle of the second subsequence sq22, for example, the 17th timing parameter is 10001, which corresponds to the 17th step. The phase shift = 11.25 × 17 = 191.25 degrees, and the phase of the clock CK2 is shifted (or delayed) by 191.25 degrees, which is taken as the optimum correction timing. If data verification fails in both subsequences sq21, sq22, the main control unit 102 can reduce the frequency of the clock CK2. The main control unit 102 of different manufacturers or models (specifications) can store the corresponding timing parameters of the optimized correction timing of each combination when integrating with the memory module 103 of different manufacturers or models (specifications). In the future, when the system 10 starts, it can directly detect the model and directly apply the corresponding optimal timing parameters to speed up the integration process, which is helpful for the system vendors that integrate the chips downstream. Another way is that according to the combination of the main control unit 102 and the memory module 103 of the system manufacturer, the timing parameters can be directly provided to them. After the system manufacturer loads the combination of the selected wafers, the provided timing parameters are directly written into the startup guide. The program 101 is no longer changed because the consumer uses the integrated system and does not arbitrarily replace the main control unit 102 or the memory module 103.

請參閱第七圖，其為本發明另一較佳實施例驗證資料的讀寫的示意圖。總序列SQ3包含資料連續取樣成功的第一子序列sq31、第二子序列sq32、以及第三子序列sq33，三個子序列sq31, sq32, sq33中，最長的連續驗證資料成功的數目都是3，因為連續驗證成功的數目太低，資料讀寫不正常，此頻率下的時脈CK2對資料讀寫的穩定性有所影響，所以主控單元102會分析此情況而將時脈CK2的頻率降低，然後整個重新再調校一次。Please refer to the seventh figure, which is a schematic diagram of reading and writing of verification data according to another preferred embodiment of the present invention. The total sequence SQ3 contains the first subsequence sq31, the second subsequence sq32, and the third subsequence sq33, and the three consecutive subsequences sq31, sq32, sq33, the longest consecutive verification data is 3, Because the number of consecutive verification successes is too low, data reading and writing is not normal, the clock CK2 at this frequency has an impact on the stability of data reading and writing, so the main control unit 102 will analyze this situation and reduce the frequency of the clock CK2. And then re-adjust the whole time.

相反地，若是如第五圖中相對較為順利的調校過程，則可提高時脈CK2的頻率，因為頻率的提高，上升緣RIS2與下降緣FL2在時間間隔上變的更密集，因此本發明的調校方法可更精準地找出恰當的時脈CK2的資料取樣點，而使資料的讀寫不僅更快速，也更加穩定無錯誤。甚至於若當時脈CK2的頻率已經提高，例如提高至400MHz之後，仍存在較長的連續驗證資料讀寫成功的序列時，則時脈CK2的頻率可繼續往上提升。Conversely, if the calibration process is relatively smooth as in the fifth figure, the frequency of the clock CK2 can be increased, and since the frequency is increased, the rising edge RIS2 and the falling edge FL2 become denser in time interval, and thus the present invention The calibration method can more accurately find the appropriate sampling point of the clock CK2, so that the reading and writing of the data is not only faster, but also more stable and error-free. Even if the frequency of the current pulse CK2 has been increased, for example, after increasing to 400 MHz, there is still a long sequence of consecutive verification data reading and writing success, then the frequency of the clock CK2 can continue to rise.

請參閱第八圖，其為本發明另一較佳實施例校正讀/寫資料的一時序的方法的示意圖，包含下列步驟。步驟S201，提供一時脈，其中該時脈具有分別含n個相位之n個脈波，其中該n個相位分別對應n個時序參數，且該n個時序參數分別對應n個校正時序。步驟S202，在該時脈之該n個相位下分別傳送n個指令，其中該n個指令對應n個測試資料。步驟S203，因應所傳送的該n個指令而分別接收n個回應資料。步驟S204，比對該n個測試資料與該n個回應資料以獲得屬於第一所欲或第二非所欲結果之n個比較結果，其中該n個比較結果分別對應該n個時序參數及該n個校正時序。步驟S205，找出具有最長連續m個第一所欲結果之一比較結果序列，並決定以一第p個比較結果對應的校正時序為一最佳校正時序，其中當m為奇數時，p為(m+1)/2，而當m為偶數時，p為m/2或1+(m/2)。Please refer to the eighth figure, which is a schematic diagram of a method for correcting a sequence of read/write data according to another preferred embodiment of the present invention, including the following steps. Step S201, providing a clock, wherein the clock has n pulse waves respectively containing n phases, wherein the n phases respectively correspond to n timing parameters, and the n timing parameters respectively correspond to n correction timings. Step S202, transmitting n instructions respectively in the n phases of the clock, wherein the n instructions correspond to n test data. Step S203, receiving n response data respectively according to the n instructions transmitted. Step S204, comparing the n test data and the n response data to obtain n comparison results belonging to the first desired or the second undesired result, wherein the n comparison results respectively correspond to n timing parameters and The n correction timings. Step S205, finding a comparison result sequence having one of the longest consecutive m first desired results, and determining a correction timing corresponding to a p-th comparison result as an optimal correction timing, wherein when m is an odd number, p is (m+1)/2, and when m is an even number, p is m/2 or 1+(m/2).

在第八圖中，該第一所欲結果為第n個測試資料與第n個回應資料驗證成功之結果，該第二非所欲結果為第n個測試資料與第n個回應資料驗證失敗的結果。請同時參閱第六圖~第八圖，當該比較結果序列重覆出現時，則選擇第一次先出現的比較結果序列來計算p；當該比較結果序列的m小於一門檻值時，則降低該時脈CK2的頻率後重新進行校正。請同時參閱第第一圖、第四圖、與第五圖，該時脈CK2具有周期T2，並包含該n個脈波，每一脈波包含一上升緣與RIS2一下降緣FL2，該最佳校正時序使該n個回應資料RS1~RSn與該上升緣RIS2之間具有確保資料能被讀寫的一起始時間間隔TS1(將第四圖的上升緣RIS2套用至第一圖的上升緣RIS1)，且使該n個回應資料RS1~RSn與該下降緣FL2之間具有確保資料能被讀寫的一保持時間間隔TH1(將第四圖的下降緣FL2套用至第一圖的下降緣FL2)。該上升緣RIS2與該下降緣FL2隨著該時脈CK2的相位之偏移而延遲對相對應的回應資料RS1~RSn的取樣時間。該時序參數CTFT包含x個二進制的位元，其中2^x=n。該時脈CK2的相位的偏移以步階的方式來進行，直到相位偏移達到該週期T2為止。該n個比較結果表示該n個回應資料RS1~RSn之驗證狀態。In the eighth figure, the first desired result is the result of successful verification of the nth test data and the nth response data, and the second undesired result is the nth test data and the nth response data verification failure. the result of. Please refer to the sixth to eighth pictures at the same time. When the comparison result sequence is repeated, the first comparison result sequence appears first to calculate p; when the comparison result sequence m is less than a threshold value, then The frequency of the clock CK2 is lowered and the correction is performed again. Please refer to FIG. 1 , FIG. 4 , and FIG. 5 simultaneously. The clock CK2 has a period T2 and includes the n pulse waves, and each pulse wave includes a rising edge and a falling edge FL2 of the RIS2. The correction timing is such that a start time interval TS1 is ensured between the n response data RS1~RSn and the rising edge RIS2 to ensure that the data can be read and written (the rising edge RIS2 of the fourth figure is applied to the rising edge RIS1 of the first figure) And having a hold time interval TH1 between the n response data RS1~RSn and the falling edge FL2 to ensure that the data can be read and written (the falling edge FL2 of the fourth figure is applied to the falling edge FL2 of the first figure) ). The rising edge RIS2 and the falling edge FL2 delay the sampling time of the corresponding response data RS1 to RSn as the phase of the clock CK2 shifts. The timing parameter CTFT contains x binary bits, where 2^x=n. The phase shift of the clock CK2 is performed in steps until the phase shift reaches the period T2. The n comparison results indicate the verification status of the n response data RS1~RSn.

請參閱第九圖，其為本發明另一較佳實施例校正讀/寫資料的一時序的方法的示意圖，其中該時序在一脈波之一完整週期內，區分成n個校正時序，該方法包含下列步驟。步驟S301，提供一時脈CK2，其中該時脈CK2具有複數個具該週期T2之脈波P2。步驟S302，分別於該n個校正時序，傳送n個指令，其中該n個指令對應n個測試資料。步驟S303，因應所傳送的該n個指令，而分別接收n個回應資料。步驟S304，比對該n個測試資料與該n個回應資料以獲得屬於第一所欲或第二非所欲結果之n個比較結果。步驟S305，找出具有最長連續m個第一所欲結果之一比較結果序列，並決定以一第p個比較結果所對應之一該相關校正時序為一最佳校正時序，其中當m為奇數時，p為(m+1)/2，而當m為偶數時，p為m/2或1+(m/2)。Please refer to a ninth figure, which is a schematic diagram of a method for correcting a timing of reading/writing data according to another preferred embodiment of the present invention, wherein the timing is divided into n correction timings in one complete period of a pulse wave, The method consists of the following steps. In step S301, a clock CK2 is provided, wherein the clock CK2 has a plurality of pulse waves P2 having the period T2. Step S302, transmitting n instructions respectively for the n correction timings, wherein the n instructions correspond to n test data. Step S303, receiving n response data respectively according to the n instructions transmitted. Step S304, comparing the n test data with the n response data to obtain n comparison results belonging to the first desired or the second undesired result. Step S305, finding a comparison result sequence having one of the longest consecutive m first desired results, and determining that the correlation correction timing is one of the optimal correction timings corresponding to one of the pth comparison results, wherein when m is an odd number When p is (m+1)/2, and when m is even, p is m/2 or 1+(m/2).

本發明的附圖是以舉例說明的方式，來介紹本發明各種不同的實施例，並供瞭解如何實現本發明。本發明實施例提供了充足的內容，以供本領域的技術人員來實施本發明所揭示的實施例，或實施依本發明所揭示的內容所衍生的實施例。須注意的是，該些實施例彼此間並不互斥，且部分實施例可與其他一個或多個實施例作適當結合，以形成新的實施例，亦即本發明的實施並不局限於本發明所揭示的實施例。The drawings of the present invention are intended to be illustrative of various embodiments of the present invention The embodiments of the present invention provide sufficient content for those skilled in the art to implement the embodiments disclosed herein, or to implement embodiments derived from the disclosure of the present invention. It should be noted that the embodiments are not mutually exclusive, and some embodiments may be combined with other one or more embodiments to form a new embodiment, that is, the implementation of the present invention is not limited thereto. Embodiments of the present disclosure.

綜上所述，本發明提供一種校正記憶體模組之讀/寫資料的時序的啟動引導程式、方法及其系統，啟動引導程式包含控制時脈的相位之時序參數，時脈具有一周期，並包括多個脈波，啟動引導程式改變時序參數，使得主控單元輸出的該時脈的相位產生改變，直到相位的偏移達到一個周期為止。主控單元發送一指令及不同相位偏移的時脈至記憶體模組，記憶體模組因應該原始相位的脈波與該指令而回傳一回應資料至該主控單元，該主控單元接收並比對該回應資料是否與該指令所指示的測試資料相同，以驗證資料的取樣(寫入)是否成功，然後將每一個比對結果儲存起來並進行分析，找出具有最長連續m個第一所欲結果之一比較結果序列，並決定以一第p個比較結果所對應之一該相關校正時序為一最佳校正時序，其中當m為奇數時，p為(m+1)/2，而當m為偶數時，p為m/2或1+(m/2)。不同廠商或型號(規格)的主控單元，可在與不同廠商或型號(規格)的記憶體體模組整合時，將每種組合的最佳化校正時序的相對應時序參數儲存起來，在日後系統啟動時可直接偵測型號並直接套用相對應的最佳時序參數，以加快整合的流程。同時，本發明的調校方法可更精準地找出恰當的時脈的資料取樣點，而使資料的讀寫在經過時脈的調校後不僅更快速，也更加穩定無錯誤。In summary, the present invention provides a booting program, method, and system for correcting the timing of reading/writing data of a memory module. The booting program includes timing parameters for controlling the phase of the clock, and the clock has a period. And including a plurality of pulse waves, the boot program is changed to change the timing parameters, so that the phase of the clock output by the main control unit is changed until the phase offset reaches one cycle. The main control unit sends a command and a clock with different phase offsets to the memory module, and the memory module returns a response data to the main control unit according to the original phase pulse wave and the instruction, the main control unit Receiving and comparing whether the response data is the same as the test data indicated by the instruction, to verify whether the sampling (writing) of the data is successful, and then storing and analyzing each comparison result to find the longest continuous m One of the first desired results compares the result sequence, and determines that the correlation correction timing is one of the optimal correction timings corresponding to one of the pth comparison results, wherein when m is an odd number, p is (m+1)/ 2, and when m is an even number, p is m/2 or 1+(m/2). The main control unit of different manufacturers or models (specifications) can store the corresponding timing parameters of the optimized correction timing of each combination when integrating with the memory modules of different manufacturers or models (specifications). In the future, the system can directly detect the model and directly apply the corresponding optimal timing parameters to speed up the integration process. At the same time, the calibration method of the present invention can more accurately find the data sampling points of the appropriate clock, and the reading and writing of the data is not only faster but also more stable and error-free after the adjustment of the clock.

是以，縱使本案已由上述之實施例所詳細敘述而可由本領域技術人員任施匠思而為諸般修飾，然皆不脫如權利要求書所欲保護者。Therefore, even if the present invention has been described in detail by the above-described embodiments, it can be modified by those skilled in the art without departing from the scope of the appended claims.

10‧‧‧系統10‧‧‧System

101‧‧‧啟動導引程式101‧‧‧Starting the boot program

103‧‧‧記憶體模組103‧‧‧ memory module

102‧‧‧主控單元102‧‧‧Master unit

104‧‧‧系統匯流排104‧‧‧System Bus

1031‧‧‧記憶體控制單元1031‧‧‧Memory Control Unit

1033‧‧‧記憶體匯流排1033‧‧‧Memory bus

1032‧‧‧複數記憶體胞元1032‧‧‧Multiple memory cells

CK1, CK2‧‧‧時脈CK1, CK2‧‧‧ clock

PL1, PL2‧‧‧脈波PL1, PL2‧‧‧ pulse

RIS1, RIS2‧‧‧上升緣RIS1, RIS2‧‧‧ rising edge

FL1, FL2‧‧‧下降緣FL1, FL2‧‧‧ falling edge

T1, T2‧‧‧週期T1, T2‧‧ cycle

TS1‧‧‧設定時間TS1‧‧‧Set time

CTFT1‧‧‧第一時序參數CTFT1‧‧‧ first timing parameter

TH1‧‧‧保持時間TH1‧‧‧ Hold time

CTFT2‧‧‧第二時序參數CTFT2‧‧‧Second timing parameters

CTFT7‧‧‧第七時序參數CTFT7‧‧‧ seventh timing parameter

CTFTn-1‧‧‧第n-1時序參數CTFTn-1‧‧‧ n-1 timing parameters

CTFTn‧‧‧第n時序參數CTFTn‧‧‧nth timing parameters

RS1~RSn‧‧‧n個回應資料RS1~RSn‧‧‧n response data

CMD 8, CMD 6, CMD 21‧‧‧指令CMD 8, CMD 6, CMD 21‧‧‧ directive

SQ1, SQ2‧‧‧序列SQ1, SQ2‧‧‧ sequence

Sq11, sq21, sq22, sq31, sq32, sq33‧‧‧子序列 Sq11, sq21, sq22, sq31, sq32, sq33‧‧‧ subsequence

第一圖：習知資料取樣的示意圖，第二圖：本發明較佳實施例校正一記憶體模組之讀寫資料的時序的示意圖。第三圖：本發明較佳實施例校正讀/寫資料的時序的系統的示意圖。第四圖：本發明較佳實施例的時脈的相位依據時序參數來調整的示意圖，第五圖：本發明較佳實施例驗證資料的讀寫的示意圖。第六圖：本發明另一較佳實施例驗證資料的讀寫的示意圖。第七圖：本發明另一較佳實施例驗證資料的讀寫的示意圖。第八圖：本發明另一較佳實施例校正讀/寫資料的一時序的方法的示意圖。第九圖：本發明另一較佳實施例校正讀/寫資料的一時序的方法的示意圖。First: Schematic diagram of conventional data sampling, and second diagram: a schematic diagram of timing for correcting read and write data of a memory module in accordance with a preferred embodiment of the present invention. Third FIGURE: A schematic diagram of a system for correcting the timing of read/write data in accordance with a preferred embodiment of the present invention. FIG. 4 is a schematic diagram of the phase of the clock according to the preferred embodiment of the present invention adjusted according to timing parameters. FIG. 5 is a schematic diagram of reading and writing of the verification data according to the preferred embodiment of the present invention. Figure 6 is a schematic diagram of the reading and writing of verification data in another preferred embodiment of the present invention. Figure 7 is a schematic diagram of the reading and writing of the verification data according to another preferred embodiment of the present invention. Figure 8 is a schematic illustration of a method of correcting a sequence of read/write data in accordance with another preferred embodiment of the present invention. Figure 9 is a schematic illustration of a method of correcting a timing of read/write data in accordance with another preferred embodiment of the present invention.

Claims

一種校正讀/寫資料的時序的系統，包含：一啟動導引程式，具有一指令與一時序參數；一主控單元，傳送該指令並依據該時序參數產生一時脈，其中該時脈根據該時序參數的不同而具有n個相位，該指令對應一測試資料；以及一記憶體模組，藉由一系統匯流排電連接於該主控單元，該主控單元分別調整該時脈至該n個相位，該記憶體模組分別在該時脈的n個相位下接收該指令並分別產生n個回應資料，且將該n個回應資料回傳至該主控單元，其中該主控單元藉由比對該測試資料與該n個回應資料以分別產生n個暫存值，該n個暫存值形成一序列，該主控單元找出在該序列中代表連續驗證成功的一最長子序列，從該最長子序列中找出在中間排序，並以該該中間排序所對應的該時序參數所代表的時脈相位做為一最佳校正時序。A system for correcting the timing of reading/writing data, comprising: a start boot program having an instruction and a timing parameter; a master unit transmitting the command and generating a clock according to the timing parameter, wherein the clock is according to the The timing parameter has n phases, the command corresponds to a test data; and a memory module is electrically connected to the main control unit by a system bus, and the main control unit respectively adjusts the clock to the n Phases, the memory module receives the instruction in n phases of the clock and respectively generates n response data, and returns the n response data to the main control unit, wherein the main control unit borrows Comparing the test data with the n response data to generate n temporary storage values respectively, the n temporary storage values form a sequence, and the main control unit finds a longest subsequence representing the success of the continuous verification in the sequence, The intermediate sequence is found from the longest subsequence, and the clock phase represented by the timing parameter corresponding to the intermediate order is used as an optimal correction timing.

如申請專利範圍第1項所述的系統，其中：該時脈具有一周期，並包含複數脈波，每一脈波包含一上升緣與一下降緣，該最佳校正時序使該n個回應資料與該上升緣之間具有確保資料能被讀寫的一起始時間間隔(setup time)，且使該n個回應資料與該下降緣之間具有確保資料能被讀寫的一保持時間間隔(hold time)；該上升緣與該下降緣隨著該時脈的相位之偏移而延遲對相對應的回應資料的取樣時間；該時序參數包含x個二進制的位元，其中2^x=n；該主控單元以步階的方式來偏移該時脈的相位，直到相位偏移達到該週期為止；以及該n個暫存值表示該n個回應資料之驗證狀態。The system of claim 1, wherein: the clock has a period and includes a plurality of pulse waves, each pulse wave including a rising edge and a falling edge, and the optimal correction timing causes the n responses There is a starting time interval between the data and the rising edge to ensure that the data can be read and written, and a holding time interval between the n response data and the falling edge to ensure that the data can be read and written ( Hold time); the rising edge and the falling edge delay the sampling time of the corresponding response data according to the phase shift of the clock; the timing parameter includes x binary bits, where 2^x=n The master unit shifts the phase of the clock in steps to the phase offset until the phase offset reaches the period; and the n temporary values represent the verification status of the n response data.

如申請專利範圍第1項所述的系統，其中：該記憶體模組包含：一記憶體控制單元；以及複數記憶體胞元，藉由一記憶體匯流排與該記憶體控制單元電連接，該記憶體控制單元接收該指令而回傳該n個回應資料；該主控單元與該記憶體模組各具有不同的型號與規格，兩者互相組合經時序校正後，產生一組最佳化時序參數，該主控單元將該組最佳化時序參數儲存以供後續直接套用；以及該記憶體模組的種類包含一固態硬碟(SSD)、一崁入式多媒體記憶卡(eMMC)、或具有該記憶體控制器與該複數記憶體胞元整合在一起的模組。The system of claim 1, wherein: the memory module comprises: a memory control unit; and a plurality of memory cells electrically connected to the memory control unit by a memory bus, The memory control unit receives the instruction and returns the n response data; the main control unit and the memory module each have different models and specifications, and the two are combined with each other to generate a set of optimizations after timing correction. Timing parameters, the main control unit stores the set of optimized timing parameters for subsequent direct application; and the type of the memory module includes a solid state drive (SSD), an intrusive multimedia memory card (eMMC), Or a module having the memory controller integrated with the complex memory cell.

一種校正一記憶體模組之讀/寫資料的時序的方法，包含下列步驟：產生一指令與一時序參數；傳送該指令並依據該時序參數產生一時脈，其中該時脈根據該時序參數的不同而具有n個相位，該指令對應一測試資料；分別調整該時脈至該n個相位，該記憶體模組分別在該時脈的n個相位下接收該指令，並分別產生n個回應資料；比對該測試資料與該n個回應資料以產生n個暫存值，該n個暫存值形成一序列;以及找出在該序列中代表連續驗證成功的一最長子序列，從該最長子序列找出一中間排序，並以該中間排序所對應的該時序參數所代表的時脈相位做為一最佳校正時序。A method for correcting a timing of reading/writing data of a memory module, comprising the steps of: generating an instruction and a timing parameter; transmitting the instruction and generating a clock according to the timing parameter, wherein the clock is based on the timing parameter Differently having n phases, the command corresponds to a test data; respectively adjusting the clock to the n phases, the memory module respectively receiving the instruction in n phases of the clock, and respectively generating n responses Data; comparing the test data with the n response data to generate n temporary values, the n temporary values form a sequence; and finding a longest subsequence representing the success of the continuous verification in the sequence, from The longest subsequence finds an intermediate order, and the clock phase represented by the timing parameter corresponding to the intermediate order is used as an optimal correction timing.

如申請專利範圍第4項所述的方法，其中：該時脈具有一周期，並包含複數脈波，每一脈波包含一上升緣與一下降緣，該最佳校正時序使該n個回應資料與該上升緣之間具有確保資料能被讀寫的一起始時間間隔(setup time)，且使該n個回應資料與該下降緣之間具有確保資料能被讀寫的一保持時間間隔(hold time)；該上升緣與該下降緣隨著該時脈的相位之偏移而延遲對相對應的回應資料的取樣時間；該時序參數包含x個二進制的位元，其中2^x=n；該時脈的相位的偏移以步階的方式來進行，直到相位偏移達到該週期為止；以及該n個暫存值表示該n個回應資料之驗證狀態。The method of claim 4, wherein: the clock has a period and includes a plurality of pulse waves, each pulse wave including a rising edge and a falling edge, and the optimal correction timing causes the n responses There is a starting time interval between the data and the rising edge to ensure that the data can be read and written, and a holding time interval between the n response data and the falling edge to ensure that the data can be read and written ( Hold time); the rising edge and the falling edge delay the sampling time of the corresponding response data according to the phase shift of the clock; the timing parameter includes x binary bits, where 2^x=n The phase offset of the clock is performed in steps until the phase offset reaches the period; and the n temporary values represent the verification status of the n response data.

如申請專利範圍第4項所述的方法，更包含：當該序列中具有相同連續驗證成功次數的子序列時，且該次數為奇數時，從第一個連續驗證成功的子序列找出一中間排序，並儲存該中間排序所對應到的時序參數，當該次數為偶數時，將該次數除以2或將該次數除以2後加1而得到一序數，儲存該序數所對應的時序參數；以及當該序列中具有相同連續驗證成功次數的子序列時，且該次數低於一門檻值時，降低該時脈的頻率後重新進行校正。The method of claim 4, further comprising: when the subsequence having the same consecutive number of successful verification times in the sequence, and the number of times is an odd number, finding a subsequence from the first consecutive successful verification Sorting in the middle, and storing the timing parameter corresponding to the intermediate sorting. When the number of times is even, divide the number by 2 or divide the number by 2 and add 1 to obtain an ordinal number, and store the timing corresponding to the ordinal number. The parameter; and when the subsequence has the same number of consecutive successful verification times in the sequence, and the number is lower than a threshold, the frequency of the clock is decreased and the correction is performed again.

一種校正讀/寫資料的一時序的方法，包含下列步驟：提供一時脈，其中該時脈具有分別含n個相位之n個脈波，其中該n個相位分別對應n個時序參數，且該n個時序參數分別對應n個校正時序; 在該時脈之該n個相位下分別傳送n個指令，其中該n個指令對應n個測試資料；因應所傳送的該n個指令而分別接收n個回應資料；比對該n個測試資料與該n個回應資料以獲得屬於第一所欲或第二非所欲結果之n個比較結果，其中該n個比較結果分別對應該n個時序參數及該n個校正時序；以及找出具有最長連續m個第一所欲結果之一比較結果序列，並決定以一第p個比較結果對應的校正時序為一最佳校正時序，其中當m為奇數時，p為(m+1)/2，而當m為偶數時，p為m/2或1+(m/2)。A method for correcting a timing of reading/writing data, comprising the steps of: providing a clock, wherein the clock has n pulses respectively having n phases, wherein the n phases respectively correspond to n timing parameters, and the n timing parameters respectively correspond to n correction timings; respectively, n instructions are respectively transmitted in the n phases of the clock, wherein the n instructions correspond to n test data; respectively, receiving n instructions corresponding to the transmitted n instructions Response data; comparing the n test data with the n response data to obtain n comparison results belonging to the first desired or second undesired result, wherein the n comparison results respectively correspond to n timing parameters And the n correction timings; and finding a comparison result sequence having one of the longest consecutive m first desired results, and determining a correction timing corresponding to a p-th comparison result as an optimal correction timing, wherein when m is In the case of an odd number, p is (m+1)/2, and when m is an even number, p is m/2 or 1+(m/2).

如申請專利範圍第7項所述的方法，其中：該第一所欲結果為第n個測試資料與第n個回應資料驗證成功之結果，該第二非所欲結果為第n個測試資料與第n個回應資料驗證失敗的結果；當該比較結果序列重覆出現時，則選擇第一次先出現的比較結果序列來計算p；當該比較結果序列的m小於一門檻值時，則降低該時脈的頻率後重新進行校正；該時脈具有一周期，並包含該n個脈波，每一脈波包含一上升緣與一下降緣，該最佳校正時序使該n個回應資料與該上升緣之間具有確保資料能被讀寫的一起始時間間隔(setup time)，且使該n個回應資料與該下降緣之間具有確保資料能被讀寫的一保持時間間隔(hold time)；該上升緣與該下降緣隨著該時脈的相位之偏移而延遲對相對應的回應資料的取樣時間；該時序參數包含x個二進制的位元，其中2^x=n；該時脈的相位的偏移以步階的方式來進行，直到相位偏移達到該週期為止；以及該n個比較結果表示該n個回應資料之驗證狀態。The method of claim 7, wherein: the first desired result is a result of successful verification of the nth test data and the nth response data, and the second undesired result is the nth test data. And the result of the verification of the nth response data failure; when the comparison result sequence is repeated, the first comparison result sequence first appears to calculate p; when the comparison result sequence m is less than a threshold value, then Re-correcting after reducing the frequency of the clock; the clock has a period and includes the n pulses, each pulse wave includes a rising edge and a falling edge, and the optimal correction timing makes the n response data Between the rising edge and a starting time interval for ensuring that the data can be read and written, and a holding time interval between the n response data and the falling edge to ensure that the data can be read and written (hold) The rising edge and the falling edge delay the sampling time of the corresponding response data with the phase shift of the clock; the timing parameter includes x binary bits, where 2^x=n; The phase shift of the clock is The step is performed until the phase offset reaches the period; and the n comparison results indicate the verification status of the n response data.

一種校正讀/寫資料的一時序的方法，其中該時序在一脈波之一完整週期內，區分成n個校正時序，該方法包含下列步驟：提供一時脈，其中該時脈具有複數個具該週期之脈波；分別於該n個校正時序，傳送n個指令，其中該n個指令對應n個測試資料；因應所傳送的該n個指令，而分別接收n個回應資料；比對該n個測試資料與該n個回應資料以獲得屬於第一所欲或第二非所欲結果之n個比較結果；以及找出具有最長連續m個第一所欲結果之一比較結果序列，並決定以一第p個比較結果所對應之一該相關校正時序為一最佳校正時序，其中當m為奇數時，p為(m+1)/2，而當m為偶數時，p為m/2或1+(m/2)。A method of correcting a timing of reading/writing data, wherein the timing is divided into n correction timings in one complete cycle of a pulse wave, the method comprising the steps of: providing a clock, wherein the clock has a plurality of a pulse of the cycle; transmitting n instructions respectively for the n correction timings, wherein the n instructions correspond to n test data; respectively, receiving n response data according to the n instructions transmitted; n test data and the n response data to obtain n comparison results belonging to the first desired or second undesired result; and finding a comparison result sequence having one of the longest consecutive m first desired results, and Determining, by one of the p-th comparison results, the correlation correction timing is an optimal correction timing, wherein when m is an odd number, p is (m+1)/2, and when m is an even number, p is m /2 or 1+(m/2).

如申請專利範圍第0項所述的方法，其中：該第一所欲結果為第n個測試資料與第n個回應資料驗證成功之結果，該第二非所欲結果為第n個測試資料與第n個回應資料驗證失敗的結果；當該比較結果序列重覆出現時，則選擇第一次先出現的比較結果序列來計算p；當該比較結果序列的m小於一門檻值時，則降低該時脈的頻率後重新進行校正；當在該時脈校正的過程中未出現時脈降頻時，則在該時脈校正完之後提升該時脈的頻率，然後再重新校正；該相關校正時序與一時序參數相關，該時序參數被存在於一啟動程式碼中以供後續套用，而該啟動程式碼儲存於一非揮發性記憶體中；該時脈包含n個脈波，每一脈波包含一上升緣與一下降緣，該最佳校正時序使該n個回應資料與該上升緣之間具有確保資料能被讀寫的一起始時間間隔(setup time)，且使該n個回應資料與該下降緣之間具有確保資料能被讀寫的一保持時間間隔(hold time)；該上升緣與該下降緣隨著該時脈的相位之偏移而延遲對相對應的回應資料的取樣時間；該時序參數包含x個二進制的位元，其中2^x=n；該時脈的相位的偏移以步階的方式來進行，直到相位偏移達到該週期為止；以及該n個暫存值表示該n個回應資料的讀取已經驗證成功或驗證失敗。The method of claim 0, wherein: the first desired result is a result of successful verification of the nth test data and the nth response data, and the second undesired result is the nth test data And the result of the verification of the nth response data failure; when the comparison result sequence is repeated, the first comparison result sequence first appears to calculate p; when the comparison result sequence m is less than a threshold value, then Re-correcting after reducing the frequency of the clock; when the clock-down is not occurring during the clock correction, the frequency of the clock is raised after the clock is corrected, and then re-corrected; The correction timing is related to a timing parameter, which is stored in a startup code for subsequent application, and the startup code is stored in a non-volatile memory; the clock includes n pulses, each The pulse wave includes a rising edge and a falling edge, and the optimal correction timing has a starting time interval between the n response data and the rising edge to ensure that the data can be read and written, and the n times Response data Between the falling edge and a holding time interval for ensuring that the data can be read and written; the rising edge and the falling edge delay sampling of the corresponding response data along with the phase shift of the clock Time; the timing parameter includes x binary bits, where 2^x=n; the phase offset of the clock is performed in steps until the phase offset reaches the period; and the n temporary The stored value indicates that the reading of the n response data has been verified successfully or the verification failed.