TW201921835A - Motor driving apparatus - Google Patents
Motor driving apparatusInfo
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- TW201921835A TW201921835A TW108100184A TW108100184A TW201921835A TW 201921835 A TW201921835 A TW 201921835A TW 108100184 A TW108100184 A TW 108100184A TW 108100184 A TW108100184 A TW 108100184A TW 201921835 A TW201921835 A TW 201921835A
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- drive circuit
- motor drive
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- Control Of Motors That Do Not Use Commutators (AREA)
- Control Of Direct Current Motors (AREA)
Abstract
Description
本發明係關於一種馬達驅動裝置。The present invention relates to a motor driving device.
近年來隨著個人電腦或工作站之高速化,CPU(Central Processing Unit:中央處理單元)或DSP(Digital Signal Processor,數位信號處理器)等之運算處理用LSI(Large Scale Integrated Circuit:大型積體電路)之動作速度係呈現上升趨勢。如此之LSI係隨著其動作速度即時脈頻率變高而發熱量亦將變大。來自LSI之發熱存在有導致LSI本身熱爆衝,或對周圍之電路造成影響之問題。因此,以LSI為代表之發熱體之適當熱冷卻成為極為重要之技術。 於眾多電子機器中,為了冷卻LSI,而採用藉由冷卻風扇之氣冷式之冷卻方法。該方法係例如對向於LSI之表面而配置冷卻風扇,將冷空氣吹送至LSI表面。於如此之藉由冷卻風扇之LSI之冷卻時,監視LSI附近之溫度,根據其溫度而變化風扇之旋轉藉此調整冷卻之程度。 圖1係本發明人等研討之具備風扇馬達之驅動積體電路(Integrated Circuit)之冷卻裝置之電路圖。另,不能將圖1之任意構成認定為已知技術。 冷卻裝置2r包含風扇馬達6、及驅動風扇馬達6之驅動裝置9r。驅動裝置9r係以驅動積體電路200r與其周邊零件而構成。驅動裝置9r之構成零件係搭載於共通之印刷基板上。 風扇馬達6係無刷DC馬達。霍爾感測器8係為了檢測轉子之位置而設置於風扇馬達6之附近。驅動積體電路200r之1號引腳及16號引腳之接地端子(GND)係接地。對於3號引腳之電源端子(VCC),經由逆流防止用之二極體D1而輸入電源電壓VDD 。驅動段230之輸出係經由2號引腳(OUT2)、15號引腳(OUT1)而與風扇馬達6連接。另,於本說明書中,引腳之編號係便於方便者,與引腳之佈局等無關。 霍爾偏壓電路204係產生霍爾偏壓電壓VHB ,且經由10號引腳之霍爾偏壓端子(HB)而供給至霍爾感測器8。對於9號引腳、11號引腳之霍爾輸入端子(H+、H-),輸入霍爾感測器8產生之霍爾信號H+、H-。霍爾比較器202係比較霍爾信號H- 、H+ ,且產生顯示轉子位置之脈衝信號S1,並輸出至控制邏輯電路208。控制邏輯電路208與該脈衝信號S1同步進行換相控制。 基準電壓源214係產生經特定之電壓位準穩定化之基準電壓VREF 。基準電壓VREF 係經由12號引腳之基準電壓端子(REF)而輸出至外部。 於6號引腳之振盪器端子(OSC),外置電容器C1。振盪器220係藉由將電容器C1進行充放電,而產生三角波之振盪器電壓VOSC 。 於4號引腳之最低轉速設定端子(MIN),輸入指示風扇馬達6之最低轉速之電壓VMIN 。MIN端子之電壓VMIN 係藉由將基準電壓VREF 利用電阻R11、R12進行分壓而產生。 PWM比較器216對MIN端子之電壓VMIN 與振盪器電壓VOSC 進行比較。PWM比較器216之輸出S2具有根據MIN端子之電壓VMIN 之占空比。 PWM比較器218係將5號引腳之轉速控制端子(TH)之電壓VTH 與振盪器電壓VOSC 進行比較。PWM比較器218之輸出S3具有根據TH端子之電壓VTH 之占空比。 於PWM輸入,給予具有根據風扇馬達6之目標轉速之占空比(輸入占空比)之輸入PWM信號。輸入PWM信號以變流器10反轉之後,以RC濾波器12平滑化而輸入至TH端子。 控制邏輯電路208將PWM比較器216及218之輸出脈衝S2、S3邏輯合成,產生脈衝信號S4。脈衝信號S4之占空比係PWM比較器216與218之輸出脈衝S2、S3之占空比中之較大者。 驅動段230包含霍爾放大器232、234。霍爾放大器232將霍爾信號H+、H-之差值以第1極性放大,且自OUT2端子輸出。霍爾放大器234將霍爾信號H+、H-之差值以第2極性放大,且自OUT15端子輸出。霍爾放大器232、234之各者具有推拉形式之輸出段。霍爾放大器232、234各者之輸出段係根據來自控制邏輯電路208之脈衝信號S4而進行切換。OUT1端子、OUT2端子之輸出電壓係根據霍爾比較器202之輸出S1而交互地成為主動(換相控制)。又,主動之一者之輸出電壓係具有放大霍爾信號而獲得之包絡線,又以根據PWM比較器218(或216)之輸出脈衝S3(或S2)之占空比,切換開啟狀態與高阻抗狀態。 鎖定保護電路240係檢測風扇馬達6之鎖定狀態。TSD電路242係檢測過熱狀態。信號輸出電路244係產生顯示異常之警報信號,且自8號引腳之警報端子(AL)輸出。又信號輸出電路244係產生具有根據風扇馬達6之轉速之週期之FG(Frequency Generator:頻率發生器)信號,且自7號引腳之FG端子輸出。 圖2係圖1之驅動積體電路200r之動作波形圖。本說明書中之波形圖或時序圖之縱軸及橫軸係為容易理解而適當放大、縮小者,又,所示之各波形亦為容易理解而簡化、誇張或強調。圖2係為了擴大顯示相對於霍爾信號H+、H-之週期充分短之時間尺度,故霍爾信號H+、H-係實質性地顯示為固定之電壓位準。輸出OUT1具有根據VMIN 與VTH 中較低者與振盪器電壓VOSC 之比較結果之占空比。藉此,輸入PWM信號之占空比越大,則風扇馬達6之扭矩(轉速)越增大。又,最小扭矩即最低轉速可根據MIN端子之電壓VMIN 而設定。 [先前技術文獻] [專利文獻] [專利文獻1]日本特開2005-224100號公報 [專利文獻2]日本特開2004-166429號公報 [專利文獻3]日本特開2009-296839號公報In recent years, with the increase in the speed of personal computers and workstations, LSIs (Large Scale Integrated Circuits) such as CPUs (Central Processing Units) or DSPs (Digital Signal Processors) The speed of movement is on the rise. In such an LSI system, as the speed of the operation is increased, the amount of heat generated will increase. The heat generated from the LSI has a problem that causes the LSI itself to burst or cause influence on surrounding circuits. Therefore, proper thermal cooling of a heating element represented by LSI has become an extremely important technology. In many electronic devices, in order to cool the LSI, an air-cooled cooling method by a cooling fan is employed. In this method, for example, a cooling fan is disposed on the surface of the LSI, and cold air is blown onto the surface of the LSI. When cooling by the LSI of the cooling fan, the temperature in the vicinity of the LSI is monitored, and the degree of cooling is adjusted by changing the rotation of the fan depending on the temperature. Fig. 1 is a circuit diagram of a cooling device including a drive integrated circuit of a fan motor, which has been studied by the inventors of the present invention. In addition, any configuration of FIG. 1 cannot be considered as a known technique. The cooling device 2r includes a fan motor 6 and a driving device 9r that drives the fan motor 6. The drive device 9r is configured to drive the integrated circuit 200r and its peripheral components. The components of the drive unit 9r are mounted on a common printed circuit board. The fan motor 6 is a brushless DC motor. The Hall sensor 8 is provided in the vicinity of the fan motor 6 in order to detect the position of the rotor. The ground terminal (GND) of the No. 1 pin and the 16th pin of the drive integrated circuit 200r is grounded. For the power supply terminal (VCC) of the pin No. 3, the power supply voltage V DD is input via the counter current prevention diode D1. The output of the driving section 230 is connected to the fan motor 6 via the 2nd pin (OUT2) and the 15th pin (OUT1). In addition, in the present specification, the number of the pin is convenient for the user, regardless of the layout of the pin or the like. The Hall bias circuit 204 generates a Hall bias voltage V HB and supplies it to the Hall sensor 8 via a Hall bias terminal (HB) of a 10 pin. For the Hall input terminals (H+, H-) of the 9th pin and the 11th pin, the Hall signals H+, H- generated by the Hall sensor 8 are input. The Hall comparator 202 compares the Hall signals H - , H + and generates a pulse signal S1 showing the rotor position and outputs it to the control logic circuit 208. The control logic circuit 208 performs commutation control in synchronization with the pulse signal S1. The reference voltage source 214 is a reference voltage V REF that is stabilized by a particular voltage level. The reference voltage V REF is output to the outside via the reference voltage terminal (REF) of the 12th pin. On the 6th pin of the oscillator terminal (OSC), the external capacitor C1. The oscillator 220 generates a triangular wave oscillator voltage V OSC by charging and discharging the capacitor C1. At the lowest speed setting terminal (MIN) of pin 4, input the voltage V MIN indicating the minimum speed of the fan motor 6. The voltage V MIN of the MIN terminal is generated by dividing the reference voltage V REF by the resistors R11 and R12. The PWM comparator 216 compares the voltage V MIN of the MIN terminal with the oscillator voltage V OSC . The output S2 of the PWM comparator 216 has a duty cycle according to the voltage VMIN of the MIN terminal. The PWM comparator 218 compares the voltage V TH of the speed control terminal (TH) of the pin 5 with the oscillator voltage V OSC . The output S3 of the PWM comparator 218 has a duty cycle according to the voltage VTH of the TH terminal. At the PWM input, an input PWM signal having a duty cycle (input duty cycle) according to the target rotational speed of the fan motor 6 is given. The input PWM signal is inverted by the converter 10, smoothed by the RC filter 12, and input to the TH terminal. Control logic circuit 208 logically combines the output pulses S2, S3 of PWM comparators 216 and 218 to produce pulse signal S4. The duty cycle of the pulse signal S4 is the greater of the duty cycles of the output pulses S2, S3 of the PWM comparators 216 and 218. Drive section 230 includes Hall amplifiers 232, 234. The Hall amplifier 232 amplifies the difference between the Hall signals H+ and H- with the first polarity and outputs it from the OUT2 terminal. The Hall amplifier 234 amplifies the difference between the Hall signals H+ and H- with the second polarity and outputs it from the OUT15 terminal. Each of the Hall amplifiers 232, 234 has an output section in a push-pull form. The output segments of each of the Hall amplifiers 232, 234 are switched in accordance with the pulse signal S4 from the control logic circuit 208. The output voltages of the OUT1 terminal and the OUT2 terminal are interactively active (commutation control) in accordance with the output S1 of the Hall comparator 202. Moreover, the output voltage of one of the active ones has an envelope obtained by amplifying the Hall signal, and is switched on and off according to the duty ratio of the output pulse S3 (or S2) of the PWM comparator 218 (or 216). Impedance state. The lock protection circuit 240 detects the locked state of the fan motor 6. The TSD circuit 242 detects an overheat condition. The signal output circuit 244 generates an alarm signal for displaying an abnormality and outputs it from the alarm terminal (AL) of the pin No. 8. Further, the signal output circuit 244 generates an FG (Frequency Generator) signal having a period according to the number of revolutions of the fan motor 6, and outputs it from the FG terminal of the No. 7 pin. Fig. 2 is a waveform diagram showing the operation of the driving integrated circuit 200r of Fig. 1. The vertical axis and the horizontal axis of the waveform diagram or the timing chart in the present specification are appropriately enlarged and reduced for easy understanding, and the waveforms shown are also simplified, exaggerated or emphasized for easy understanding. 2 is a time scale in which the period of the Hall signals H+ and H- is sufficiently short, so that the Hall signals H+ and H- are substantially displayed as fixed voltage levels. The output OUT1 has a duty ratio based on a comparison between the lower of V MIN and V TH and the oscillator voltage V OSC . Thereby, the larger the duty ratio of the input PWM signal is, the more the torque (rotation speed) of the fan motor 6 is increased. Further, the minimum torque, that is, the minimum rotation speed, can be set according to the voltage V MIN of the MIN terminal. [PRIOR ART DOCUMENT] [Patent Document 1] JP-A-2005-224100 (Patent Document 2) JP-A-2004-166429 (Patent Document 3) JP-A-2009-296839
[發明欲解決之問題] 本發明人等針對圖1之驅動積體電路200r進行研討,其結果獲知以下課題。 課題1. 圖3(a)~(c)係顯示圖1之驅動裝置9r中之輸入占空比、TH端子之電壓VTH 、輸出OUT1(OUT2)之輸出占空比、及轉速之關係之圖。如圖3(a)所示,TH端子之電壓VTH 係相對輸入PWM信號之輸入占空比而線形變化,且因此如圖3(b)所示,輸出OUT1、OUT2之占空比(輸出占空比)亦相對於輸入占空比而線形變化。 於圖3(c)中,顯示輸入占空比與風扇馬達6之轉速之關係。於圖3(c)中,顯示假定無負載、無損失之情形之理想特性(i)。現實之實際特性(i)係因馬達線圈之發熱、軸承之摩擦損失、伴隨轉子旋轉之風損、馬達之各種零件之發熱之影響,故與理想特性(i)相比而變低,且轉速越高,其影響越顯著。隨著轉速增加,相對於輸入占空比之轉速被壓縮本身係無法避免。 課題2. 於專利文獻3(日本特開2009-296839號公報)中,揭示有相關技術。於該文獻中,讀取PWM信號,進行補償運算而求得補償信號,且自補償信號加減補償值進行運算,並基於獲得之補償後之PWM信號而控制風扇之轉速。 然而驅動積體電路係與各種風扇馬達組合使用。圖3(c)所示之風扇馬達之旋轉特性係根據風扇馬達6之種類、葉片形狀或大小、風扇馬達6或驅動積體電路200r之散熱性而變化。因此,每個驅動積體電路200r若可相對其使用狀況而設定最佳之修正特性則將更方便。 本發明之某態樣係鑒於課題1而完成者,其例示性之目的之一係提供相對於控制輸入之轉速之線形性獲得改善之馬達驅動裝置。又,本發明之另一態樣係鑒於課題2而完成者,其例示性之目的之一係提供對於使用狀況而設定最佳之修正特性,且可改善相對於轉速控制信號之轉速之線形性的馬達驅動裝置。 [解決問題之技術手段] 1. 本發明之某態樣係關於對風扇馬達進行PWM(Pulse Width Modulation:脈衝寬度調變)驅動之馬達驅動裝置。馬達驅動裝置包含:轉速控制端子,其接受指示轉速之類比之控制電壓;第1振盪器端子,其於第1平台中,於其自身與對接地間,並聯連接電容器及放電電阻;充電電阻及第1開關,其串聯設置於將其電壓穩定化之基準電壓線與第1振盪器端子之間;切換電路,其於第1振盪器端子中產生之振盪器電壓達到上側臨限值時,關斷第1開關,且於振盪器電壓降低至下側臨限值時,接通第1開關;PWM比較器,其將轉速控制端子之電壓與振盪器電壓進行比較,且產生控制脈衝;輸出電路,其至少基於控制脈衝而驅動風扇馬達。 振盪器電壓之坡度並非為直線,而根據CR時間常數而變化。藉此,可改善轉速控制端子之電壓與輸出占空比之線形。此外,可藉由充電電流與放電電阻而規定充電、放電斜率,乃至振盪器電壓之頻率。 於某態樣中,馬達驅動裝置亦可進而包含第2振盪器端子。於第1平台中,充電電阻係外置於第2振盪器端子與第1振盪器端子之間,第1開關亦可設置於第2振盪器端子與基準電壓源之輸出之間。 於某態樣中,切換電路包含:第1電阻、第2電阻、第3電阻,其等依序串聯連接於基準電壓源之輸出與接地之間;第2開關,其與第3電阻並聯設置;及比較器,其將第1電阻和第2電阻之連接點之電壓,與振盪器電壓進行比較;且亦可根據比較器之輸出而控制第1開關及第2開關之接通、斷開。 於某態樣中,馬達驅動裝置進而包含:第1電流源,其於賦能狀態中對振盪器端子供給之特定之充電電流;及第2電流源,其於賦能狀態中自振盪器端子匯入特定之放電電流;且第1電流源、第2電流源之至少一者,亦可構成為可藉由切換電路而控制接通、斷開。切換電路亦可為可切換第1模式與第2模式,該第1模式係將第1電流源及第2電流源設為禁能狀態,而控制第1開關之接通、斷開;該第2模式係斷開第1開關,且將第1電流源及第2電流源設為賦能狀態而控制第1電流源及第2電流源之至少一者之接通、斷開。 於將第1電流源、第2電流源設為賦能狀態之第2模式中,可將振盪器電壓之坡度之斜率作為直線,並可於以往之平台中使用。 於某態樣中,馬達驅動裝置亦可進而包含:第1電流源,其於賦能狀態中對振盪器端子供給特定之充電電流;及第2電流源,其於賦能狀態中可控制接通、斷開;且於接通期間自振盪器端子匯入特定之放電電流。切換電路亦可切換第1模式與第2模式,該第1模式係將第1電流源及第2電流源設為禁能狀態,而控制第1開關之接通、斷開;第2模式係將第1開關斷開,而控制第2電流源之接通、斷開。 於某態樣中,切換電路包含:第1電阻、第2電阻、第3電阻,其等依序串聯連接於基準電壓源之輸出與接地之間;第2開關,其與第3電阻並聯設置;及比較器,其將第1電阻和第2電阻之連接點之電壓,與振盪器電壓進行比較;且(i)於第1模式中,根據比較器之輸出,控制第1開關及第2開關之接通、斷開,(ii)於第2模式中,亦可根據比較器之輸出而控制第2電流源及第2開關之接通、斷開。 於某態樣中,馬達驅動裝置亦可進而包含接收指示第1模式與第2模式之選擇信號之選擇器端子。 於某態樣中,馬達驅動裝置亦可於一個半導體基板一體積體化。 「一體積體化」係指包含電路之構成要件全部形成於半導體基板上之情形、及電路之主要構成要件一體積體化之情形,且亦可為了電路常數之調節用,而將一部分之電阻或電容器設置於半導體基板之外部。 藉由將電路作為1個積體電路而積體化,可削減電路面積,且可均一地保持電路元件之特性。 對於轉速控制端子,亦可經由濾波器而輸入輸入脈衝調變信號。 本發明之另一態樣係關於冷卻裝置。冷卻裝置包含風扇馬達、驅動風扇馬達之上述任一馬達驅動裝置。 本發明之另一態樣係關於對風扇馬達進行PWM(Pulse Width Modulation:脈衝寬度調變)驅動之馬達驅動積體電路(Integrated Circuit)。馬達驅動積體電路包含:轉速控制端子,其接受指示轉速之類比之控制電壓;第1振盪器端子,其於第1平台中,於其自身與對接地間並聯連接電容器及放電電阻;第2振盪器端子,其於第1平台中,於其自身與第1振盪器端子之間外置充電電阻;第1開關,其設於將其電壓穩定化之基準電壓線與第1振盪器端子之間;切換電路,其於第1振盪器端子中產生之振盪器電壓達到上側臨限值時,關斷第1開關,於振盪器電壓降低至下側臨限值時,接通第1開關;PWM比較器,其將轉速控制端子之電壓與振盪器電壓進行比較而產生控制脈衝;輸出電路,其至少基於控制脈衝而驅動風扇馬達。 某態樣之馬達驅動積體電路進而包含:第1電流源,其於啟用狀態中,對振盪器端子供給特定之充電電流;第2電流源,其於啟用狀態中自振盪器端子匯入特定之放電電流。切換電路亦可為可切換(i)第1模式,其將第1電流源及第2電流源作為停用狀態而控制第1開關之接通、斷開;(ii)第2模式,其斷開第1開關,且將第1電流源、第2電流源作為啟用狀態而控制第2電流源之接通、斷開。 2. 本發明之另一態樣係關於對風扇馬達進行PWM(Pulse Width Modulation:脈衝寬度調變)驅動之馬達驅動電路。馬達驅動電路包含:轉速控制輸入部,其輸入指示風扇馬達之轉速之轉速控制信號;第1設定輸入部,其輸入指示第1參數α之第1資訊;數位脈衝寬度調變器,其定義有向下凸出彎曲之修正函數y=f(x),且基於第1參數α可變更修正函數f(x)之彎曲程度,並產生具有與轉速控制信號及修正函數f(x)相應之輸出占空比之控制脈衝;輸出電路,其至少基於控制脈衝而驅動風扇馬達。 根據該態樣,藉由根據所使用之狀況而賦予第1參數α可設定最佳之修正特性,且可改善相對於轉速控制信號之轉速之線形性。 將對應於轉速控制信號之最小值之值設為x0 ,將對應於轉速控制信號之最大值之值設為x100 時,對應於y=ax之直線,亦可以滿足f(x0 )=ax0 、f(x100 )=ax100 之方式定義修正函數y=f(x)。 第1資訊亦可作為類比電壓而輸入至第1設定輸入部。 第1資訊亦可作為數位資料而輸入至第1設定輸入部。第1設定輸入部亦可包含保持第1資訊之第1記憶體。 第1設定輸入部亦可包含接收數位資料之第1資訊之I2 C(Inter IC)匯流排介面電路。 於某態樣中,馬達驅動電路亦可進而包含輸入指示第2參數β之第2資訊之第2設定輸入部。第2參數β亦可規定a。 本發明之另一態樣亦關於馬達驅動電路。馬達驅動電路包含:轉速控制端子,其接受指示風扇馬達之轉速之轉速控制信號;輸入電路,其將轉速控制信號變換為輸入數位值x;第1設定端子,其接受指示第1參數α之第1資訊;占空運算部,其將對應於轉速控制信號之最小值之輸入數位值設為x0 ,將對應於轉速控制信號之最大值之輸入數位值設為x100 時,對應於y=ax之直線,而定義滿足f(x0 )=ax0 、f(x100 )=ax100 之向下凸出彎曲之修正函數y=f(x),且基於第1參數α而可變更修正函數f(x)之彎曲程度,並運算對應於輸入數位值x之占空指令值y;數位脈衝寬度調變器,其產生具有對應於占空指令值y之輸出占空比之控制脈衝;輸出電路,其至少基於控制脈衝而驅動上述風扇馬達。 根據該態樣,藉由根據所使用之狀況而賦予第1參數α可設定最佳之修正特性,且可改善相對於轉速控制信號之轉速之線形性。 於某態樣中,將ax與f(x)之差為最大之輸入數位值設為xc 時,第1參數α亦可規定axc 與f(xc )之差值。 於某態樣中,xc 亦可設定為對應於輸入占空比為33~66%之範圍之值。xc 亦可設定為對應於輸入占空比50%之值。 於某態樣中,第1資訊係作為類比電壓而輸入至第1設定端子,馬達驅動電路亦可進而包含將第1設定端子之類比電壓變換為數位之第1參數α之第1A/D轉換器。 於某態樣中,亦可進而包含接受指示第2參數β之第2資訊之第2設定端子。第2參數β亦可規定a。 於某態樣中,將第2資訊作為類比電壓而輸入至第2設定端子,馬達驅動電路亦可進而包含將第2設定端子之類比電壓變換為數位之第2參數β之第2A/D轉換器。 於某態樣中,第1資訊係作為位數資料而輸入至第1設定端子,馬達驅動電路亦可進而包含:接收輸入至第1設定端子之數位資料,且取得第1參數α之介面電路;及保持第1參數α之第1記憶體。 於某態樣中,第2資訊係作為位數資料而輸入至第2設定端子,馬達驅動電路亦可進而包含:接收輸入至第2設定端子之數位資料,且取得第2參數β之介面電路;及保持第2參數β之第2記憶體。 於某態樣中,進而包含接受指示第3參數γ之第3資訊之第3設定端子。占空運算部亦可將第3參數γ作為下限而對占空指令值y進行箝位。 於某態樣中,亦可於轉速控制端子,輸入作為轉速控制信號而具有輸入占空比之輸入脈衝調變信號。輸入電路亦可包含接受輸入脈衝調變信號,且根據輸入占空比變換為輸入數位值x之占空/數位轉換器。 馬達驅動電路亦可於一個半導體基板一體積體化。 「一體積體化」係指包含電路之構成全部要件形成於半導體基板上之情形,或電路之主要構成要件一體積體化之情形,且亦可為電路常數之調節用而將一部分之電阻或電容器設置於半導體基板之外部。藉由將電路作為1個積體電路而積體化,可削減電路面積,且可均一地保持電路元件之特性。 本發明之另一態樣係關於冷卻裝置。冷卻裝置包含風扇馬達、與驅動風扇馬達之上述之馬達驅動積體電路。 本發明之另一態樣係關於電子機器。電子機器亦可包含處理器、與冷卻處理器之上述冷卻裝置。 另,將以上構成要素之任意組合或本發明之構成要素或表現在方法、裝置、系統等之間相互轉換者亦可有效作為本發明之態樣。 [發明之效果] 根據本發明之某態樣,可改善相對於控制輸入之轉速之線形性。[Problems to be Solved by the Invention] The inventors of the present invention have studied the driving integrated circuit 200r of Fig. 1, and as a result, the following problems have been known. Problem 1. Fig. 3 (a) to (c) show the relationship between the input duty ratio in the driving device 9r of Fig. 1, the voltage V TH of the TH terminal, the output duty ratio of the output OUT1 (OUT2), and the number of revolutions. Figure. As shown in FIG. 3(a), the voltage V TH of the TH terminal changes linearly with respect to the input duty ratio of the input PWM signal, and thus the duty ratios of the outputs OUT1 and OUT2 are output as shown in FIG. 3(b). The duty cycle) also varies linearly with respect to the input duty cycle. In Fig. 3(c), the relationship between the input duty ratio and the rotational speed of the fan motor 6 is shown. In Fig. 3(c), the ideal characteristic (i) of assuming no load and no loss is shown. The actual characteristics of reality (i) are caused by the heat generation of the motor coil, the friction loss of the bearing, the wind loss accompanying the rotation of the rotor, and the heat generation of various parts of the motor, so that it is lower than the ideal characteristic (i), and the rotation speed is low. The higher the impact, the more significant the impact. As the rotational speed increases, the rotational speed relative to the input duty cycle is inherently unavoidable. A related art is disclosed in Patent Document 3 (JP-A-2009-296839). In this document, the PWM signal is read, a compensation operation is performed to obtain a compensation signal, and the compensation signal is added and subtracted from the compensation signal for calculation, and the rotational speed of the fan is controlled based on the obtained PWM signal. However, the drive integrated circuit is used in combination with various fan motors. The rotation characteristics of the fan motor shown in Fig. 3(c) vary depending on the type of the fan motor 6, the shape or size of the blade, the heat dissipation of the fan motor 6 or the drive integrated circuit 200r. Therefore, it is more convenient for each of the driving integrated circuits 200r to set an optimum correction characteristic with respect to its use condition. One aspect of the present invention has been accomplished in view of the subject matter 1, and one of its exemplary objects is to provide a motor drive device that is improved in linearity with respect to a rotational speed of a control input. Further, another aspect of the present invention has been made in view of the problem 2, and an exemplary object thereof is to provide an optimum correction characteristic for use conditions and to improve linearity with respect to a rotational speed control signal. Motor drive unit. [Technical means for solving the problem] 1. A certain aspect of the present invention relates to a motor drive device that performs PWM (Pulse Width Modulation) driving on a fan motor. The motor driving device includes: a rotation speed control terminal that receives an analog voltage indicating an analog speed; and a first oscillator terminal that is connected in parallel with the capacitor and the discharge resistor between the self and the ground in the first platform; the charging resistor and The first switch is provided in series between the reference voltage line for stabilizing the voltage and the first oscillator terminal, and the switching circuit is configured to turn off the oscillator voltage generated in the first oscillator terminal when the upper threshold is reached. The first switch is turned off, and the first switch is turned on when the oscillator voltage is lowered to the lower threshold; the PWM comparator compares the voltage of the speed control terminal with the oscillator voltage, and generates a control pulse; the output circuit It drives the fan motor based at least on the control pulse. The slope of the oscillator voltage is not a straight line, but varies according to the CR time constant. Thereby, the line shape of the voltage of the rotation speed control terminal and the output duty ratio can be improved. In addition, the charging and discharging slopes, and even the frequency of the oscillator voltage, can be specified by the charging current and the discharging resistance. In some aspects, the motor drive device may further include a second oscillator terminal. In the first platform, the charging resistor is externally disposed between the second oscillator terminal and the first oscillator terminal, and the first switch may be disposed between the second oscillator terminal and the output of the reference voltage source. In a certain aspect, the switching circuit includes: a first resistor, a second resistor, and a third resistor, which are sequentially connected in series between the output of the reference voltage source and the ground; and the second switch is disposed in parallel with the third resistor. And a comparator that compares the voltage of the connection point between the first resistor and the second resistor with the oscillator voltage; and controls the on and off of the first switch and the second switch according to the output of the comparator . In one aspect, the motor driving device further includes: a first current source that supplies a specific charging current to the oscillator terminal in the energizing state; and a second current source that is in the energizing state from the oscillator terminal A specific discharge current is introduced; and at least one of the first current source and the second current source may be configured to be controlled to be turned on or off by a switching circuit. The switching circuit may switch between the first mode and the second mode, and the first mode sets the first current source and the second current source to be disabled, and controls the first switch to be turned on and off; In the second mode, the first switch is turned off, and the first current source and the second current source are set to be energized, and at least one of the first current source and the second current source is controlled to be turned on and off. In the second mode in which the first current source and the second current source are in the energized state, the slope of the slope of the oscillator voltage can be used as a straight line, and can be used in a conventional platform. In a certain aspect, the motor driving device may further include: a first current source that supplies a specific charging current to the oscillator terminal in the energizing state; and a second current source that is controllable in the energizing state On and off; and a specific discharge current is drawn from the oscillator terminal during the turn-on. The switching circuit can also switch between the first mode and the second mode, wherein the first current source and the second current source are disabled, and the first switch is turned on and off; the second mode is The first switch is turned off, and the second current source is turned on and off. In a certain aspect, the switching circuit includes: a first resistor, a second resistor, and a third resistor, which are sequentially connected in series between the output of the reference voltage source and the ground; and the second switch is disposed in parallel with the third resistor. And a comparator that compares a voltage at a connection point between the first resistor and the second resistor with an oscillator voltage; and (i) in the first mode, controls the first switch and the second according to an output of the comparator The switch is turned on and off, and (ii) in the second mode, the second current source and the second switch can be turned on and off according to the output of the comparator. In one aspect, the motor driving device may further include a selector terminal that receives a selection signal indicating the first mode and the second mode. In a certain aspect, the motor driving device can also be bulked on one semiconductor substrate. "One volumetric" refers to a situation in which all the constituent elements of the circuit are formed on the semiconductor substrate, and the main constituent elements of the circuit are bulkified, and a part of the resistor may be used for the adjustment of the circuit constant. Or the capacitor is disposed outside the semiconductor substrate. By integrating the circuit as one integrated circuit, the circuit area can be reduced, and the characteristics of the circuit elements can be uniformly maintained. For the speed control terminal, an input pulse modulation signal can also be input via a filter. Another aspect of the invention pertains to a cooling device. The cooling device includes a fan motor and any of the above-described motor driving devices that drive the fan motor. Another aspect of the present invention relates to a motor-driven integrated circuit that performs PWM (Pulse Width Modulation) driving on a fan motor. The motor drive integrated circuit includes: a rotation speed control terminal that receives an analog voltage indicating an analog speed; and a first oscillator terminal that is connected in parallel with the capacitor and the discharge resistor between the ground and the ground in the first platform; The oscillator terminal is externally provided with a charging resistor between the first oscillator terminal and the first oscillator terminal, and the first switch is provided between the reference voltage line for stabilizing the voltage and the first oscillator terminal. a switching circuit that turns off the first switch when the oscillator voltage generated in the first oscillator terminal reaches the upper threshold, and turns on the first switch when the oscillator voltage drops to the lower threshold; A PWM comparator that compares a voltage of the speed control terminal with an oscillator voltage to generate a control pulse; and an output circuit that drives the fan motor based on at least the control pulse. The motor-driven integrated circuit of a certain aspect further includes: a first current source that supplies a specific charging current to the oscillator terminal in an enabled state; and a second current source that imports a specific one from the oscillator terminal in an enabled state The discharge current. The switching circuit may be switchable (i) first mode, which controls the first switch to be turned on and off by using the first current source and the second current source as a deactivated state; (ii) the second mode is broken. The first switch is turned on, and the first current source and the second current source are turned on, and the second current source is turned on and off. 2. Another aspect of the present invention relates to a motor drive circuit that performs PWM (Pulse Width Modulation) driving on a fan motor. The motor drive circuit includes a rotation speed control input unit that inputs a rotation speed control signal indicating a rotation speed of the fan motor, a first setting input unit that inputs a first information indicating the first parameter α, and a digital pulse width modulator defined by The bending correction function y=f(x) is convex downward, and the degree of bending of the correction function f(x) can be changed based on the first parameter α, and an output having a rotation speed control signal and a correction function f(x) is generated. a duty cycle control pulse; an output circuit that drives the fan motor based at least on the control pulse. According to this aspect, the optimum correction characteristic can be set by giving the first parameter α in accordance with the state of use, and the linearity with respect to the rotational speed of the rotational speed control signal can be improved. The value corresponding to the minimum value of the rotation speed control signal is set to x 0 , and when the value corresponding to the maximum value of the rotation speed control signal is set to x 100 , the line corresponding to y=ax can also satisfy f(x 0 )= The correction function y=f(x) is defined by the way ax 0 and f(x 100 )=ax 100 . The first information can also be input to the first setting input unit as an analog voltage. The first information can also be input to the first setting input unit as digital data. The first setting input unit may include a first memory that holds the first information. The first setting input unit may further include an I 2 C (Inter IC) bus interface circuit that receives the first information of the digital data. In a certain aspect, the motor drive circuit may further include a second setting input unit that inputs the second information indicating the second parameter β. The second parameter β can also specify a. Another aspect of the invention also relates to a motor drive circuit. The motor drive circuit includes: a rotation speed control terminal that receives a rotation speed control signal indicating a rotation speed of the fan motor; an input circuit that converts the rotation speed control signal into an input digit value x; and a first setting terminal that receives the indication of the first parameter α 1 information; a duty calculation unit that sets an input digit value corresponding to a minimum value of the rotation speed control signal to x 0 and an input digit value corresponding to a maximum value of the rotation speed control signal to x 100 , corresponding to y= A straight line of ax, and a correction function y=f(x) that satisfies the downward convex curvature of f(x 0 )=ax 0 and f(x 100 )=ax 100 , and can be modified based on the first parameter α a degree of bending of the function f(x), and computing a duty command value y corresponding to the input digit value x; a digital pulse width modulator that generates a control pulse having an output duty ratio corresponding to the duty command value y; An output circuit that drives the fan motor based on at least a control pulse. According to this aspect, the optimum correction characteristic can be set by giving the first parameter α in accordance with the state of use, and the linearity with respect to the rotational speed of the rotational speed control signal can be improved. In a certain aspect, when the input digit value where the difference between ax and f(x) is the maximum is x c , the first parameter α may also specify the difference between ax c and f(x c ). In a certain aspect, x c can also be set to a value corresponding to an input duty ratio of 33 to 66%. x c can also be set to a value corresponding to 50% of the input duty cycle. In a certain aspect, the first information is input to the first set terminal as an analog voltage, and the motor drive circuit may further include a first A/D conversion of the first parameter α that converts the analog voltage of the first set terminal into a digital one. Device. In a certain aspect, the second setting terminal that receives the second information indicating the second parameter β may be further included. The second parameter β can also specify a. In a certain aspect, the second information is input to the second setting terminal as an analog voltage, and the motor driving circuit may further include a second A/D conversion of the second parameter β for converting the analog voltage of the second setting terminal into a digital value. Device. In a certain aspect, the first information is input to the first setting terminal as the bit data, and the motor driving circuit may further include: a interface circuit that receives the digital data input to the first setting terminal and obtains the first parameter α And maintaining the first memory of the first parameter α. In a certain aspect, the second information is input to the second setting terminal as the bit data, and the motor driving circuit may further include: a interface circuit that receives the digital data input to the second setting terminal and obtains the second parameter β And the second memory that holds the second parameter β. In another aspect, the third setting terminal that receives the third information indicating the third parameter γ is further included. The duty calculation unit may clamp the duty command value y by using the third parameter γ as a lower limit. In a certain aspect, an input pulse modulation signal having an input duty ratio as a rotation speed control signal may be input to the rotation speed control terminal. The input circuit can also include a duty/digital converter that accepts an input pulse modulation signal and converts to an input digital value x according to the input duty cycle. The motor drive circuit can also be bulked on one semiconductor substrate. "One volume" refers to the case where all the components of the circuit are formed on the semiconductor substrate, or the main constituent elements of the circuit are bulked, and may also be used for the adjustment of the circuit constants. The capacitor is disposed outside the semiconductor substrate. By integrating the circuit as one integrated circuit, the circuit area can be reduced, and the characteristics of the circuit elements can be uniformly maintained. Another aspect of the invention pertains to a cooling device. The cooling device includes a fan motor and the above-described motor drive integrated circuit that drives the fan motor. Another aspect of the invention pertains to electronic machines. The electronic device can also include a processor, and the aforementioned cooling device of the cooling processor. Further, any combination of the above constituent elements or constituent elements of the present invention or a method of conversion between methods, apparatuses, systems, and the like can be effectively used as the aspect of the present invention. [Effects of the Invention] According to an aspect of the present invention, the linearity with respect to the rotational speed of the control input can be improved.
(第1實施形態) 圖4係顯示包含第1實施形態之驅動積體電路200a之冷卻裝置2a之構成之電路圖。冷卻裝置2a係搭載於例如桌上型或是膝上型之電腦、工作站、遊戲機器、視頻機器、影像機器等,且冷卻CPU(Central Processing Unit,中央處理單元)、GPU(Graphics Processing Unit:圖形處理單元)、電源裝置等之冷卻對象(未圖示)。冷卻裝置2a係包含對向於冷卻對象而設置之風扇馬達6與驅動風扇馬達6之驅動裝置9a。 驅動裝置9a係以實施形態之驅動積體電路200a與其周邊零件而構成。以下,針對驅動裝置9a之構成,以與圖1之驅動裝置9之不同點為中心進行說明。驅動積體電路200a係於一個半導體基板上積體化之功能積體電路。 於轉速控制端子(TH),輸入指示風扇馬達6之轉速之類比之控制電壓VTH 。於該平台中對於TH端子,經由變流器10及RC濾波器12輸入具有輸入占空比之輸入脈衝調變信號PWM。於其他平台中,亦可對TH端子輸入由熱敏電阻等產生之類比電壓。 對於6號引腳之第1振盪器端子(OSC),於其自身OSC與對接地間並聯外置電容器C21及放電電阻R22。於13號引腳之第2振盪器端子(OSCH)與OSC端子之間,外置充電電阻R21。 驅動積體電路200a係代替圖1之振盪器220而包含切換電路250、及第1開關252。如參照圖1所說明,基準電壓源214係產生基準電壓VREF 。基準電壓線254與基準電壓源214之輸出連接,且使其電壓穩定化。經由基準電壓線254,向驅動積體電路200a之內部之各區塊供給基準電壓VREF 。 第1開關252係設置於基準電壓線254與OSCH端子之間。即,第1開關252及充電電阻R21係串聯設置於基準電壓線254與OSC端子之間。 切換電路250係於產生於OSC端子之振盪器電壓VOSC 達到特定之上側臨限值VH (例如3.5V)時,關斷第1開關252,且於振盪器電壓VOSC 降低至下側臨限值VL (例如1.5V)時,接通第1開關252。 PWM比較器218將TH端子之電壓VTH 與振盪器電壓VOSC 進行比較,且產生控制脈衝S3。 控制邏輯電路208及驅動段230係至少構成基於控制脈衝S8而驅動風扇馬達6之輸出電路260。關於控制邏輯電路208、驅動段230係如參照圖1所說明。 本發明係作為圖4之方塊圖或電路圖而掌握,或係涉及自上述說明導出之各種裝置、電路者,並不限定於特定之構成。以下,並非為了縮小本發明之範圍,而為了幫助發明之本質或電路動作之理解,又使其等明確化而對更具體之構成例進行說明。 圖5係顯示切換電路250之構成例之電路圖。第1電阻R31、第2電阻R32、及第3電阻R33係依序串聯連接於基準電壓線254與接地之間。第2開關256係N通道MOSFET(Metal Oxide Semiconductor Field Effect Transistor:金屬氧化物半導體場效電晶體),且與第3電阻R33並聯設置。第2開關256亦可為NPN型雙極電晶體。 比較器258係將第1電阻R31與第2電阻R32之連接點N1之電壓VN1 與振盪器電壓VOSC 進行比較。第1開關252及第2開關256係根據比較器258之輸出S5互補地控制接通、斷開。 具體而言,比較器258之輸出S5於VN1 >VOSC 時為高位準、於VN1 >VOSC 時為低位準。於輸出S5為高位準時,第1開關252斷開,第2開關256接通,而成為放電狀態。 於放電狀態中,電容器C21係經由放電電阻R22而放電,因此成為振盪器電壓VOSC 之下降坡度之區間。因於放電狀態中第2開關256接通,故第3電阻R33短路,且VN1 =VREF ×R32/(R31+R32),其係相當於下側臨限值VL 。 於輸出S5為低位準時,第1開關252接通,第2開關256斷開,而成為充電狀態。於充電狀態中電容器C21經由充電電阻R21充電,因此成為振盪器電壓VOSC 之上升坡度之區間。因於充電狀態中第2開關256斷開,故VN1 =VREF ×(R32+R33)/(R31+R32+R33),其係相當於上側臨限值VH 。 另,切換電路250係掌握為磁滯比較器。因此,切換電路250除圖5之構成以外,亦可使用已知之磁滯比較器而構成。或亦可對於VH 、VL 之各者準備獨立之比較器。 以上係驅動積體電路200a之構成。接著,說明其動作。 圖6係圖4之驅動裝置9a之動作波形圖。OSC端子之振盪器電壓VOSC 係於第1開關252接通之充電期間,經由充電電阻R21充電,且以較大斜率增大。於振盪器電壓VOSC 達到上側臨限值VH 時,關斷第1開關252,且電容器C21經由放電電阻R22而緩緩地充電。接著,於振盪器電壓VOSC 降低至下側臨限值VL 時,接通第1開關252。藉由重複該動作,振盪器電壓VOSC 係如圖6所示,成為具有非線性之上升坡度、下降坡度之鋸齒波形。 於將電壓VTH 與非線形之鋸齒波形進行比較時,其結果所獲得之控制脈衝S3之占空比係相對於電壓VTH 之電壓位準,呈非線形變化。圖7(a)係顯示圖1之振盪器電壓VOSC ’與圖4之振盪器電壓VOSC 之波形圖。此處,為容易理解而方便地將圖1之振盪器電壓VOSC ’之上升坡度與圖4之振盪器電壓VOSC 之上升坡度之斜率重合。圖7(b)係顯示TH端子之電壓VTH 與控制脈衝S3之占空比之關係之圖。(i)係顯示圖4之驅動積體電路200a之特性,(ii)係顯示圖1之驅動積體電路200r之特性。由圖7(b)可明瞭,於圖4之驅動積體電路200a中,控制脈衝S3相對於電壓VTH 非線形地弓形地變化。藉由該弓形之特性(稱為修正特性),可修正輸入占空比與轉速之關係,且可接近圖3(c)之目標特性(iii)。 圖8係顯示改變充電電阻R21、放電電阻R22之組合時之控制特性之圖。此處設為C21=100pF。 (i)R21=10kΩ、R22=100kΩ (ii)R21=10kΩ、R22=10kΩ (iii)R21=10kΩ、R22=100kΩ//470kΩ 100kΩ//470kΩ係100kΩ與470kΩ之並聯連接。於該例中,(i)之組合最接近目標特性。 圖3(c)所示之實際特性係根據風扇馬達6之種類、葉片之形狀或大小、及風扇6或驅動積體電路200之散熱性而變化。根據實施形態之驅動積體電路200a,如圖8所示,因可根據充電電阻R21、放電電阻R22之組合,而變化控制特性之曲線,故根據實際特性,選擇最適之組合,藉此可接近目標特性。 如此,根據實施形態之驅動積體電路200a,可改善相對於控制輸入VTH (即PWM輸入信號之占空比)之轉速之線形性。 (第2實施形態) 圖9係第2實施形態之驅動積體電路200b之電路圖。驅動積體電路200b係除圖4之驅動積體電路200a以外,進而包含第1電流源CS1、第2電流源CS2、及邏輯閘259。 第1電流源CS1、第2電流源CS2係可切換啟用、停用而構成。第1電源流CS1係於啟用狀態中,對OSC端子供給特定量之充電電流IC1 。第2電流源CS2係於啟用狀態中,自OSC端子匯入特定量之放電電流IC2 。 又,除了啟用、停用之切換,第1電流源CS1、第2電流源CS2之至少一者係藉由切換電路250而可控制接通、斷開而構成。於圖9中,僅第2電流源CS2根據比較器258之輸出S5而可控制接通、斷開。 驅動積體電路200b具有用以設定振盪器模式之選擇器端子(SELO)。SELO端子係輸入高位準或低位準之電壓。第1電流源CS1、第2電流源CS2係於SELO端子之電壓為第1位準(例如高位準)時啟用,於SELO端子之電壓為第2位準(例如低位準)時停用。除設置SELO端子以外,亦可經由I2 C匯流排等之介面,輸入用以設定模式之信號。或亦可將非揮發性記憶體內建於驅動積體電路200b,且根據非揮發性記憶體之資料而選擇模式。 邏輯閘259係為了斷開第1開關252而設置。邏輯閘259係於SELO端子為第1位準(高位準)時,將第1開關252固定為斷開。又,邏輯閘259於SELO端子為第2位準(低位準)時,使比較器258之輸出S5通過,且切換第1開關252之接通、斷開。另,此處為了容易理解,雖將邏輯閘259以OR閘之符號顯示,但實際之構成並未限定於OR閘,亦可為具有相同功能之其他構成。 以上為驅動積體電路200b之構成。 驅動積體電路200b係根據所使用之平台,可切換第1模式、第2模式而使用。第1模式係因將低位準輸入至SELO端子而被選擇。於第1模式中,第1電流源CS1、第2電流源CS2係停用,且與第1實施形態相同地動作。 第2模式係因將高位準輸入至SELO端子而被選擇。於第2模式中,第1開關252係固定為斷開,且第1電流源CS1、第2電流源CS2為啟用。於選擇第2模式之平台中,無須充電電阻R21、放電電阻R22。接著,根據比較器258之輸出S5,於第2電流源CS2接通時,電容器C21以IC2 -IC1 放電,於第2電流源CS2斷開時,電容器C21以IC1 充電。於第2模式中,振盪器電壓VOSC 成為三角波。因此,可進行與圖1之驅動積體電路200r相同之動作。於第2模式中,因無須充電電阻R21、放電電阻R22,故可減少電路零件。 (用途) 最後,說明冷卻裝置2之用途。圖10係包含冷卻裝置2之PC之立體圖。PC500包含框體205、CPU504、主機板506、散熱片508、及複數個冷卻裝置2。 CPU504安裝於主機板506上。散熱片508密接於CPU504之上表面。冷卻裝置2_1與散熱片508對向設置,且向散熱片508吹送空氣。冷卻裝置2_2設置於框體502之背面,且將外部空氣送入至框體502內部。 冷卻裝置2除圖10之PC500外,並可搭載於工作站、筆記型PC、電視機、及冰箱等各種電子機器。 以上已針對第1及第2實施形態進行說明。本技藝者當可理解該實施形態係為例示,該等之各構成要素或各處理程序之組合可有各種變化例,且此等變化例亦在本發明範圍內。以下,針對與第1、第2實施形態相關之變化例進行說明。 (第1變化例) 構成驅動積體電路200之元件亦可全部一體積體化,又亦可分成其他積體電路而構成,進而亦可其一部分以分立零件而構成。將哪部分積體化係根據成本或佔有面積、及用途等決定即可。相反地,於實施形態中外置於驅動積體電路200之電路元件之一部分亦可積體化於驅動積體電路200。圖11(a)~(c)係第1變化例之驅動積體電路200之電路圖。於圖11(a)中,電容器C21係積體化於驅動積體電路200。藉此,無須外置之電容器而可減低成本及安裝面積。 於圖11(b)中,充電電阻R21係積體化於驅動積體電路200。藉此,因減少1個外置之電阻而可減低成本及安裝面積。又,因無須OSCH端子,故亦存在可減低驅動積體電路200之晶片大小之情形。 於圖11(c)中,充電電阻R21、放電電阻R22之二者係積體化於驅動積體電路200。藉此,因減少1個外置之電阻而可減低成本及安裝面積。又,因無須OSCH端子,故亦存在可減低驅動積體電路200之晶片大小之情形。於圖11(c)中,期望將充電電阻R21、放電電阻R22之至少一者,較佳為兩者作為可變電阻。藉此,可對每個平台微調修正特性。 (第2變化例) 於實施形態中,雖採用R21<R22而說明振盪器電壓VOSC 之下降坡度較長之情形,但亦可採用R21>R22而使上升坡度之時間變長。該情形,將控制脈衝S3之邏輯反轉,或將TH端子之電壓VTH 之極性反轉即可。 (第3變化例) 於實施形態中,雖就驅動對象之風扇馬達為單相驅動馬達之情形進行說明,但本發明並不限定於此,亦可利用於其他馬達之驅動。 (第4變化例) 驅動段230之構成、驅動方式並未限定於實施形態所說明。於實施形態中,雖根據霍爾信號H+、H-而使OUT1端子、OUT2端子之輸出電壓之振幅(包絡線)變化,但亦可將振幅作為一定。 (第5變化例) 於實施形態中說明之各信號之極性、邏輯位準係例示,亦可適當反轉。 (第3實施形態) 圖12係顯示包含第3實施形態之驅動積體電路200之冷卻裝置2之構成之電路圖。冷卻裝置2係搭載於例如如圖10所示,桌上型、或膝上型之電腦、工作站、遊戲機器、視頻機器及影像機器等,且冷卻CPU(Central Processing Unit,中央處理單元)、GPU(Graphics Processing Unit:圖形處理單元)、電源裝置等之冷卻對象。冷卻裝置2包含:與冷卻對象對向而設置之風扇馬達6與驅動風扇馬達6之驅動裝置9。 驅動裝置9係以第3實施形態之驅動積體電路200與其周邊零件而構成。驅動裝置9之構成零件係搭載於共通之印刷基板上。於圖12中,關於驅動積體電路200,僅顯示本發明之關連部分,省略無關之構成。 風扇馬達6係無刷DC馬達。霍爾感測器8係為了檢測轉子之位置而設置於風扇馬達6之附近。驅動積體電路200係於一個半導體基板上積體化之功能積體電路。 對於驅動積體電路200之5號引腳之轉速控制端子(PWM),自外部輸入指示風扇馬達6之轉速之轉速控制信號SIN 。驅動積體電路200係根據轉速控制信號SIN 而PWM(Pulse Width Modulation:脈衝寬度調變)驅動風扇馬達6。 於本實施形態中,於5號引腳之轉速控制端子(PWM),輸入作為轉速控制信號SIN 而具有輸入占空比DIN 之輸入脈衝調變信號(輸入PWM信號)SPWM 。輸入電路201係接受輸入脈衝調變信號SPWM ,並根據輸入占空比DIN 產生輸入數位值x。輸入電路201亦可以數位濾波器而構成,亦可以類比濾波器與A/D轉換器之組合而構成。亦可將PWM端子與輸入電路201稱為轉速控制輸入部。 驅動積體電路200之16號引腳之接地端子(GND)係接地。對於10號引腳之電源端子(VCC),經由逆流防止用之二極體D1而輸入電源電壓VDD 。驅動段230之輸出係經由9號引腳(OUT1)、7號引腳(OUT2)而與風扇馬達6連接。另,於本說明書中,引腳之編號係便於方便者,與引腳之佈局等無關。 對於2號引腳、3號引腳之霍爾輸入端子(H-、H+),輸入霍爾感測器8產生之霍爾信號H-、H+。霍爾比較器202比較霍爾信號H+、H-,且產生顯示轉子位置之脈衝信號S1,並輸出至控制邏輯電路100。控制邏輯電路100與該脈衝信號S1同步進行換相控制。 基準電壓源214產生經特定之電壓位準穩定化之基準電壓VREF 。基準電壓VREF 經由11號引腳之基準電壓端子(REF)輸出至外部。基準電壓VREF 作為霍爾偏壓信號VHB 而供給至霍爾感測器8。 對於13號引腳之第1設定端子(ADJ),輸入指示第1參數α之第1資訊。於本實施形態中,第1資訊係作為類比電壓VADJ 而給予至ADJ端子。例如於驅動積體電路200中外置電阻R11、R12,且藉由將基準電壓VREF 分壓而產生類比電壓VADJ 。該情形,根據電阻R11、R12之分壓比,可設定第1參數α。第1A/D轉換器270係將ADJ端子之類比電壓VADJ 變換為數位之第1參數α。亦可將ADJ端子與第1A/D轉換器270稱為第1設定輸入部。 對於15號引腳之第2設定端子(SLOPE),輸入指示第2參數β之第2資訊。於本實施形態中,第2資訊係作為類比電壓VSLOPE 而給予至SLOPE端子。例如於驅動積體電路200中外置電阻R21、R22,且藉由將基準電壓VREF 分壓,而產生類比電壓VSLOPE 。該情形,根據電阻R21、R22之分壓比,可設定第2參數β。第2A/D轉換器272係將SLOPE端子之類比電壓VSLOPE 變換為數位之第2參數β。亦可將SLOPE端子與第2A/D轉換器272稱為第2設定輸入部。 對於12號引腳之第3設定端子(MIN),輸入指示第3參數γ之第3資訊。於本實施形態中,第3資訊係作為類比電壓VMIN 而給予至MIN端子。例如於驅動積體電路200中外置電阻R31、R32,且藉由將基準電壓VREF 分壓,而產生類比電壓VMIN 。該情形,根據電阻R31、R32之分壓比,可設定第3參數γ。第3A/D轉換器274係將MIN端子之類比電壓VMIN 變換為數位之第3參數γ。亦可將MIN端子與第3A/D轉換器274稱為第3設定輸入部。 控制邏輯電路100係基於輸入數位值x、第1參數α、第2參數β、第3參數γ而運算輸出占空比DOUT 。然後,產生具有運算之輸出占空比DOUT 之控制脈衝。控制邏輯電路100將霍爾比較器202之輸出S1與控制脈衝合成,且產生驅動信號S5。 驅動段209包含預驅動器210及H橋接電路212。預驅動器210係根據驅動信號S5而驅動H橋接電路212。藉此,與霍爾比較器202之輸出S1同期,且輸出OUT1、OUT2交互地成為主動(換相控制),主動之輸出係根據控制脈衝而切換(PWM驅動)。另,驅動段209亦可具有圖1之驅動段230之構成。 8號引腳之RNF端子係與H橋接電路212之下側端子連接。於RNF端子與外部之接地之間***電流檢測用電阻RNF 。於電阻RNF 中,產生與流向風扇馬達6之電流成比例之檢測電壓VNF 。檢測電壓VNF 輸入至6號引腳之電流檢測端子(CS)。電流箝位比較器206將檢測電壓VNF 與特定之電壓VCL 進行比較。電壓VCL 係規定流向風扇馬達6之電流之上限。於電流箝位比較器206之輸出(電流限制信號)S6生效(高位準)時,控制邏輯電路100為了停止向風扇馬達6之通電而使驅動信號S5之邏輯值變化。 TSD電路242檢測過熱狀態。信號輸出電路244產生具有根據風扇馬達6之轉速之週期的FG(Frequency Generator:頻率發生器)信號,且自1號引腳之FG端子輸出。 以上為驅動積體電路200之整體構成。接著,說明其內部構成。 圖13係顯示圖12之驅動積體電路200之構成之方塊圖。另,於圖13中,僅顯示用以產生驅動信號S5之構成,其他構成係適宜省略。 控制邏輯電路100包含占空運算部108、數位脈衝調變器110、及輸出邏輯部112。控制邏輯電路100亦可以硬體邏輯構成,且亦可以處理器與軟體之組合而構成。 占空運算部108保持修正函數f(x),且使用修正函數運算占空指令值y=f(x)。圖14係顯示修正函數f(x)之圖。橫軸顯示為x,縱軸顯示為y。將對應於轉速控制信號SPWM 之最小值(即占空比0%)之輸入數位值設為x0 ,將對應於轉速控制信號SPWM 之最大值(即占空比為100%)之輸入數位值設為x100 。於本實施形態中,輸入數位值x為6位元,因此x0 =0,x100 =64。 於圖14中顯示y=ax之直線。此處設為a=1。修正函數f(x)係滿足f(x0 )=ax0 、f(x100 )=ax100 ,且向下凸出彎曲。該弓形之修正函數f(x)亦可使用自邏輯解析導出之曲線,亦可自擬合而求得圖3(c)之壓縮特性且藉由逆運算壓縮特性而求得,亦可使用近似該等者。修正函數y=f(x)係基於第1參數α而可變更彎曲之程度。 此處針對各種參數進行說明。將ax與f(x)之差為最大之輸入數位值設為xc 。於圖14中,xc 係對應於輸入占空比DIN =50%之值(即32)。第1參數α係規定axc 與f(x)之差值Δ。又,第2參數β係規定y=ax之斜率a。又,占空運算部108將第3參數γ設為下限而將占空指令值y進行箝位。即第3參數γ規定輸出占空比DOUT 之最低值,換而言之風扇馬達6之最低轉速。於圖14中顯示γ=0之例。 圖15(a)、(b)係說明占空運算部108之輸入輸出特性之參數依存性之圖。圖15(a)係變更第2參數β時之輸入輸出特性。(i)~(iii)係分別顯示a=1、0.5、1.33時之特性。圖15(b)係變更第3參數γ時之輸入輸出特性。 返回至圖13。數位脈衝調變器110產生具有根據占空指令值y之輸出占空比DOUT 的控制脈衝S4。數位脈衝調變器110可使用數位計數器而構成。 輸出電路120至少基於控制脈衝S4而驅動風扇馬達6。輸出電路120具備控制邏輯電路100之輸出邏輯部112、驅動段209、霍爾比較器202、及電流箝位比較器206。 輸出邏輯部112係基於來自霍爾比較器202之脈衝信號S1、來自電流箝位比較器206之電流限制信號S6及控制脈衝S4,而產生驅動信號S5。輸出邏輯部112使用已知技術即可。 以上為驅動積體電路200之構成。接著,說明其動作。 圖16(a)係顯示驅動積體電路200之輸入占空比DIN 與輸出占空比DOUT 之關係之圖,圖16(b)係顯示輸入占空比DIN 與風扇馬達6之轉速之關係之圖。(i)係顯示目標特性,(ii)係顯示不使用修正函數f(x)而基於y=ax運算輸出占空比時之特性,(iii)係顯示圖12之驅動積體電路200之特性。 如此,根據第3實施形態之驅動積體電路200,可將實際之旋轉特性(iii)接近目標特性(i),且可改善相對於轉速控制信號SPWM 之轉速之線形性。 尤其於第3實施形態之驅動積體電路200中,根據給予至AJD端子之第1資訊VADJ 而可調節修正函數f(x)之彎曲程度。因此,根據驅動對象之風扇馬達6之種類或特性、風扇之形狀、及冷卻裝置2所使用之環境,藉由使修正之曲線變化而可於各種狀況下實現較高之線形性。 又,可根據給予至SLOPE端子之第2資訊VSLOPE ,調節修正函數f(x)之斜率,且可根據給予至MIN端子之第3資訊VMIN 而設定最低轉速。 本技藝者當可理解第3實施形態亦為例示,其等之各構成要素或各處理程序之組合可有各種變化例,且此等變化例亦在本發明之範圍內。以下,針對與第3實施形態關連之變化例進行說明。 (第1變化例) 圖17(a)係第1變化例之驅動積體電路200a之方塊圖。於該變化例中,顯示第1參數α之第1資訊係作為數位資料而輸入至ADJ端子。介面電路280係接收輸入至ADJ端子之數位資料,且取得第1參數α。第1記憶體282保持第1參數α。同樣地,顯示第2參數β之第2資訊、顯示第3參數γ之第3資訊亦作為數位資料而輸入至SLOPE端子、MIN端子。介面電路280自數位資料取得第2參數β、第3參數γ,且存儲於第2記憶體284、第3記憶體286。例如介面電路280亦可為I2 C匯流排之接收機。另,於各數位資料以分時多重而傳送之情形,ADJ端子、SLOPE端子、MIN端子係可共通化。又,記憶體282、284、286可為非揮發性記憶體,亦可為揮發性記憶體。 (第2變化例) 於實施形態中,相對於PWM端子,雖輸入脈衝寬度調變之轉速控制信號SPWM ,但本發明並未限定於此。圖17(b)係第2變化例之驅動積體電路200b之方塊圖。驅動積體電路200b係改變PWM端子而包含接受類比電壓VTH 之轉速控制信號SIN 之TH端子。又作為輸入電路201,包含將TH端子之電壓變換為輸入數位值x之A/D轉換器288。 (第3變化例) 於實施形態中,雖將圖14之xc 設為對應於DIN =50%之值,但本發明並未限定於此,亦可設定為對應於DIN =30~66%之範圍之值。或,亦可為可自外部輸入設定xc 之第4參數。 (第4變化例) 於實施形態中,第2參數β、第3參數γ雖可自外部設定,但亦可該等之一者或全部係於驅動積體電路200中預先規定。該情形,可減少端子之數量及外置之電阻之個數。 (第5變化例) 於實施形態中,雖針對驅動對象之風扇馬達為單相驅動馬達之情形進行說明,但本發明並不限定於此,亦可使用於其他二相或三相馬達之驅動。 (第6變化例) 實施形態係說明霍爾感測器8為外置於驅動積體電路200之情形,但霍爾感測器8亦可內建於霍爾。或本發明省略霍爾感測器8且可使用於基於反電動勢而檢測轉子位置之無感測器驅動。(First Embodiment) Fig. 4 is a circuit diagram showing a configuration of a cooling device 2a including a drive integrated circuit 200a according to the first embodiment. The cooling device 2a is mounted on, for example, a desktop or laptop computer, a workstation, a game machine, a video device, a video device, etc., and cools a CPU (Central Processing Unit), a GPU (Graphics Processing Unit: graphics). Cooling target (not shown) such as processing unit) and power supply unit. The cooling device 2a includes a fan motor 6 that is provided to cool the object and a drive device 9a that drives the fan motor 6. The drive unit 9a is configured by driving the integrated circuit 200a and its peripheral components in an embodiment. Hereinafter, the configuration of the drive device 9a will be described focusing on differences from the drive device 9 of Fig. 1. The drive integrated circuit 200a is a functional integrated circuit integrated on one semiconductor substrate. At the speed control terminal (TH), an analog voltage V TH indicating the speed of the fan motor 6 is input. In the platform, an input pulse modulation signal PWM having an input duty ratio is input to the TH terminal via the converter 10 and the RC filter 12. In other platforms, an analog voltage generated by a thermistor or the like can also be input to the TH terminal. For the first oscillator terminal (OSC) of pin 6, the external capacitor C21 and the discharge resistor R22 are connected in parallel between the own OSC and the ground. An external charging resistor R21 is provided between the second oscillator terminal (OSCH) of the pin 13 and the OSC terminal. The drive integrated circuit 200a includes a switching circuit 250 and a first switch 252 instead of the oscillator 220 of FIG. As explained with reference to Figure 1, the reference voltage source 214 generates a reference voltage V REF . The reference voltage line 254 is coupled to the output of the reference voltage source 214 and stabilizes its voltage. The reference voltage V REF is supplied to each block inside the driving integrated circuit 200a via the reference voltage line 254. The first switch 252 is provided between the reference voltage line 254 and the OSCH terminal. That is, the first switch 252 and the charging resistor R21 are provided in series between the reference voltage line 254 and the OSC terminal. The switching circuit 250 turns off the first switch 252 when the oscillator voltage V OSC generated at the OSC terminal reaches a specific upper side threshold value V H (for example, 3.5 V), and lowers the oscillator voltage V OSC to the lower side. When the limit value V L (for example, 1.5 V) is reached, the first switch 252 is turned on. The PWM comparator 218 compares the voltage V TH and TH V OSC terminal voltage of the oscillator, and generates a control pulse S3. The control logic circuit 208 and the drive section 230 constitute at least an output circuit 260 that drives the fan motor 6 based on the control pulse S8. The control logic circuit 208 and the drive section 230 are as described with reference to FIG. The present invention is known as a block diagram or a circuit diagram of FIG. 4, or is related to various devices and circuits derived from the above description, and is not limited to a specific configuration. In the following, in order to reduce the scope of the present invention, a more specific configuration example will be described in order to facilitate the understanding of the nature of the invention or the understanding of the operation of the circuit. FIG. 5 is a circuit diagram showing a configuration example of the switching circuit 250. The first resistor R31, the second resistor R32, and the third resistor R33 are connected in series between the reference voltage line 254 and the ground. The second switch 256 is an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and is provided in parallel with the third resistor R33. The second switch 256 can also be an NPN type bipolar transistor. The comparator 258 compares the voltage V N1 of the connection point N1 between the first resistor R31 and the second resistor R32 with the oscillator voltage V OSC . The first switch 252 and the second switch 256 are complementarily controlled to be turned on and off in accordance with the output S5 of the comparator 258. Specifically, the comparator output to S5 258 V N1> V OSC at a high level when at V N1> when V OSC is low level. When the output S5 is at the high level, the first switch 252 is turned off, and the second switch 256 is turned on to be in a discharged state. In the discharge state, the capacitor C21 is discharged via the discharge resistor R22, and thus becomes a section of the falling slope of the oscillator voltage V OSC . Since the second switch 256 is turned on in the discharge state, the third resistor R33 is short-circuited, and V N1 = V REF × R32 / (R31 + R32), which corresponds to the lower threshold V L . When the output S5 is at the low level, the first switch 252 is turned on, and the second switch 256 is turned off to be in a charged state. In the charged state, the capacitor C21 is charged via the charging resistor R21, and thus becomes a section of the rising slope of the oscillator voltage V OSC . Since the second switch 256 is turned off in the state of charge, V N1 = V REF × (R32 + R33) / (R31 + R32 + R33), which corresponds to the upper threshold V H . Further, the switching circuit 250 is grasped as a hysteresis comparator. Therefore, the switching circuit 250 can be constructed using a known hysteresis comparator in addition to the configuration of FIG. Alternatively, an independent comparator can be prepared for each of V H and V L . The above is the configuration of the integrated circuit 200a. Next, the operation will be described. Fig. 6 is a waveform diagram showing the operation of the driving device 9a of Fig. 4. The oscillator voltage V OSC of the OSC terminal is charged by the charging resistor R21 during the charging period in which the first switch 252 is turned on, and is increased with a large slope. When the oscillator voltage V OSC reaches the upper threshold value V H , the first switch 252 is turned off, and the capacitor C21 is gradually charged via the discharge resistor R22. Next, when the oscillator voltage V OSC is lowered to the lower threshold V L , the first switch 252 is turned on. By repeating this operation, the oscillator voltage V OSC is a sawtooth waveform having a nonlinear rising slope and a falling gradient as shown in FIG. 6 . When the voltage V TH is compared with the non-linear sawtooth waveform, the duty cycle of the control pulse S3 obtained as a result is a nonlinear change with respect to the voltage level of the voltage V TH . FIG. 7 (a) a view showing the oscillator voltage V OSC 'waveform diagram of the voltage V OSC of the oscillator 4 of FIG. 1 of. Here, the slope of the rising slope of the oscillator voltage V OSC ' of FIG. 1 and the slope of the rising slope of the oscillator voltage V OSC of FIG. 4 are conveniently coincident for easy understanding. Fig. 7(b) is a view showing the relationship between the voltage V TH of the TH terminal and the duty ratio of the control pulse S3. (i) shows the characteristics of the driving integrated circuit 200a of Fig. 4, and (ii) shows the characteristics of the driving integrated circuit 200r of Fig. 1. As is apparent from Fig. 7(b), in the driving integrated circuit 200a of Fig. 4, the control pulse S3 changes linearly arcuately with respect to the voltage VTH . By the characteristic of the bow (referred to as the correction characteristic), the relationship between the input duty ratio and the rotational speed can be corrected, and the target characteristic (iii) of Fig. 3(c) can be approximated. Fig. 8 is a view showing control characteristics when the combination of the charging resistor R21 and the discharge resistor R22 is changed. This is set to C21=100pF. (i) R21 = 10 kΩ, R22 = 100 kΩ (ii) R21 = 10 kΩ, R22 = 10 kΩ (iii) R21 = 10 kΩ, R22 = 100 kΩ / / 470 kΩ 100 kΩ / / 470 kΩ is a parallel connection of 100 kΩ and 470 kΩ. In this example, the combination of (i) is closest to the target characteristic. The actual characteristics shown in FIG. 3(c) vary depending on the type of the fan motor 6, the shape or size of the blade, and the heat dissipation of the fan 6 or the drive integrated circuit 200. According to the drive integrated circuit 200a of the embodiment, as shown in FIG. 8, since the curve of the control characteristic can be changed according to the combination of the charging resistor R21 and the discharge resistor R22, the optimum combination can be selected according to the actual characteristics, thereby being accessible. Target characteristics. As described above, according to the driving integrated circuit 200a of the embodiment, the linearity of the rotational speed with respect to the control input VTH (i.e., the duty ratio of the PWM input signal) can be improved. (Second Embodiment) Fig. 9 is a circuit diagram of a drive integrated circuit 200b according to a second embodiment. The drive integrated circuit 200b includes a first current source CS1, a second current source CS2, and a logic gate 259 in addition to the drive integrated circuit 200a of FIG. The first current source CS1 and the second current source CS2 are configured to be switched between activation and deactivation. The first power supply stream CS1 is in an enabled state, and supplies a specific amount of charging current I C1 to the OSC terminal. The second current source CS2 is in an enabled state, and a specific amount of discharge current I C2 is supplied from the OSC terminal. Further, in addition to switching between activation and deactivation, at least one of the first current source CS1 and the second current source CS2 is configured to be controlled to be turned on and off by the switching circuit 250. In FIG. 9, only the second current source CS2 can be controlled to be turned on and off in accordance with the output S5 of the comparator 258. The drive integrated circuit 200b has a selector terminal (SELO) for setting an oscillator mode. The SELO terminal is a voltage that inputs a high or low level. The first current source CS1 and the second current source CS2 are activated when the voltage of the SELO terminal is at the first level (for example, a high level), and are disabled when the voltage of the SELO terminal is at the second level (for example, a low level). In addition to the SELO terminal, a signal for setting the mode can be input via an interface such as an I 2 C bus. Alternatively, the non-volatile memory may be built in the driving integrated circuit 200b, and the mode is selected based on the data of the non-volatile memory. The logic gate 259 is provided to open the first switch 252. The logic gate 259 is fixed to the first switch 252 when the SELO terminal is at the first level (high level). Further, when the SELO terminal is at the second level (low level), the logic gate 259 passes the output S5 of the comparator 258, and switches the first switch 252 on and off. Here, for the sake of easy understanding, the logic gate 259 is shown by the symbol of the OR gate, but the actual configuration is not limited to the OR gate, and may be another configuration having the same function. The above is the configuration of the drive integrated circuit 200b. The drive integrated circuit 200b can be used by switching between the first mode and the second mode depending on the platform used. The first mode is selected by inputting a low level to the SELO terminal. In the first mode, the first current source CS1 and the second current source CS2 are deactivated, and operate in the same manner as in the first embodiment. The second mode is selected by inputting a high level to the SELO terminal. In the second mode, the first switch 252 is fixedly turned off, and the first current source CS1 and the second current source CS2 are activated. In the platform in which the second mode is selected, the charging resistor R21 and the discharging resistor R22 are not required. Next, according to the output S5 of the comparator 258, when the second current source CS2 is turned on, the capacitor C21 is discharged at I C2 - I C1 , and when the second current source CS2 is turned off, the capacitor C 21 is charged at I C1 . In the second mode, the oscillator voltage V OSC becomes a triangular wave. Therefore, the same operation as that of the driving integrated circuit 200r of Fig. 1 can be performed. In the second mode, since the charging resistor R21 and the discharging resistor R22 are not required, the circuit components can be reduced. (Use) Finally, the use of the cooling device 2 will be explained. Figure 10 is a perspective view of a PC including a cooling device 2. The PC 500 includes a housing 205, a CPU 504, a motherboard 506, a heat sink 508, and a plurality of cooling devices 2. The CPU 504 is mounted on the motherboard 506. The heat sink 508 is in close contact with the upper surface of the CPU 504. The cooling device 2_1 is disposed opposite to the heat sink 508, and blows air to the heat sink 508. The cooling device 2_2 is disposed on the back surface of the casing 502, and sends outside air to the inside of the casing 502. The cooling device 2 can be mounted on various electronic devices such as a workstation, a notebook PC, a television, and a refrigerator, in addition to the PC 500 of FIG. The first and second embodiments have been described above. It will be understood by those skilled in the art that the embodiments are exemplified, and various combinations of the various components or combinations of the various processing procedures are possible, and such variations are also within the scope of the invention. Hereinafter, a modification related to the first and second embodiments will be described. (First Modification) The components constituting the drive integrated circuit 200 may be entirely bulky or may be divided into other integrated circuits, or a part thereof may be formed as discrete components. Which part of the integrated system is determined according to the cost, the occupied area, the use, and the like. Conversely, a portion of the circuit elements externally mounted to the drive integrated circuit 200 in the embodiment may be integrated into the drive integrated circuit 200. 11(a) to 11(c) are circuit diagrams of the drive integrated circuit 200 of the first modification. In FIG. 11(a), the capacitor C21 is integrated in the drive integrated circuit 200. Thereby, there is no need for an external capacitor to reduce the cost and the installation area. In FIG. 11(b), the charging resistor R21 is integrated in the driving integrated circuit 200. Thereby, the cost and the mounting area can be reduced by reducing one external resistor. Further, since the OSCH terminal is not required, there is a case where the wafer size of the drive integrated circuit 200 can be reduced. In FIG. 11(c), both of the charging resistor R21 and the discharging resistor R22 are integrated in the driving integrated circuit 200. Thereby, the cost and the mounting area can be reduced by reducing one external resistor. Further, since the OSCH terminal is not required, there is a case where the wafer size of the drive integrated circuit 200 can be reduced. In FIG. 11(c), it is desirable that at least one of the charging resistor R21 and the discharge resistor R22 is preferably a variable resistor. In this way, the correction characteristics can be fine-tuned for each platform. (Second Modification) In the embodiment, R21 < R22 is used to describe a case where the gradient of the oscillator voltage V OSC is long. However, R21 > R22 may be used to increase the time of the rising gradient. In this case, the logic of the control pulse S3 may be inverted or the polarity of the voltage V TH of the TH terminal may be inverted. (Third Modification) In the embodiment, the case where the fan motor to be driven is a single-phase drive motor will be described. However, the present invention is not limited thereto, and may be used for driving other motors. (Fourth Modification) The configuration and driving method of the driving segment 230 are not limited to the embodiments. In the embodiment, the amplitude (envelope) of the output voltages of the OUT1 terminal and the OUT2 terminal is changed according to the Hall signals H+ and H-, but the amplitude may be constant. (Fifth Modification) The polarity and logical level of each signal described in the embodiment are exemplified, and may be appropriately inverted. (Third Embodiment) Fig. 12 is a circuit diagram showing a configuration of a cooling device 2 including a drive integrated circuit 200 according to a third embodiment. The cooling device 2 is mounted on, for example, a desktop or laptop computer, a workstation, a game device, a video device, a video device, and the like as shown in FIG. 10, and cools a CPU (Central Processing Unit) and a GPU. (Graphics Processing Unit), cooling device such as power supply unit. The cooling device 2 includes a fan motor 6 that is disposed opposite to the cooling target and a driving device 9 that drives the fan motor 6. The drive unit 9 is configured by driving the integrated circuit 200 and its peripheral components in the third embodiment. The components of the drive unit 9 are mounted on a common printed circuit board. In Fig. 12, with respect to the drive integrated circuit 200, only the related portions of the present invention are shown, and the irrelevant configuration is omitted. The fan motor 6 is a brushless DC motor. The Hall sensor 8 is provided in the vicinity of the fan motor 6 in order to detect the position of the rotor. The drive integrated circuit 200 is a functional integrated circuit that is integrated on one semiconductor substrate. For the rotation speed control terminal (PWM) of the No. 5 pin of the integrated circuit 200, a rotation speed control signal S IN indicating the rotation speed of the fan motor 6 is input from the outside. The drive integrated circuit 200 drives the fan motor 6 by PWM (Pulse Width Modulation) in accordance with the rotation speed control signal S IN . In the present embodiment, an input pulse modulation signal (input PWM signal) S PWM having an input duty ratio D IN as a rotation speed control signal S IN is input to the rotation speed control terminal (PWM) of the No. 5 pin. The input circuit 201 receives the input pulse modulation signal S PWM and generates an input digital value x based on the input duty ratio D IN . The input circuit 201 may be configured by a digital filter, or may be configured by a combination of an analog filter and an A/D converter. The PWM terminal and the input circuit 201 may also be referred to as a rotational speed control input unit. The ground terminal (GND) of the 16th pin of the driving integrated circuit 200 is grounded. The power supply voltage V DD is input to the power supply terminal (VCC) of the pin 10 via the counter current prevention diode D1. The output of the driving section 230 is connected to the fan motor 6 via pin 9 (OUT1) and pin 7 (OUT2). In addition, in the present specification, the number of the pin is convenient for the user, regardless of the layout of the pin or the like. For the Hall input terminals (H-, H+) of pins 2 and 3, the Hall signals H-, H+ generated by the Hall sensor 8 are input. The Hall comparator 202 compares the Hall signals H+, H-, and generates a pulse signal S1 indicating the rotor position, and outputs it to the control logic circuit 100. The control logic circuit 100 performs commutation control in synchronization with the pulse signal S1. The reference voltage source 214 produces a reference voltage V REF that is stabilized by a particular voltage level. The reference voltage V REF is output to the outside via the reference voltage terminal (REF) of the 11th pin. The reference voltage V REF is supplied to the Hall sensor 8 as a Hall bias signal V HB . For the first setting terminal (ADJ) of the 13th pin, the first information indicating the first parameter α is input. In the present embodiment, the first information is supplied to the ADJ terminal as the analog voltage V ADJ . For example, the external resistors R11 and R12 in the integrated circuit 200 are driven, and the analog voltage V ADJ is generated by dividing the reference voltage V REF . In this case, the first parameter α can be set based on the voltage division ratio of the resistors R11 and R12. The first A/D converter 270 converts the analog voltage V ADJ of the ADJ terminal into a first parameter α of a digital digit. The ADJ terminal and the first A/D converter 270 may also be referred to as a first setting input unit. For the second setting terminal (SLOPE) of the 15th pin, the second information indicating the second parameter β is input. In the present embodiment, the second information is supplied to the SLOPE terminal as the analog voltage V SLOPE . For example, the external resistors R21 and R22 in the integrated circuit 200 are driven, and the analog voltage V SLOPE is generated by dividing the reference voltage V REF . In this case, the second parameter β can be set based on the voltage division ratio of the resistors R21 and R22. The second A/D converter 272 converts the analog voltage V SLOPE of the SLOPE terminal into the second parameter β of the digit. The SLOPE terminal and the second A/D converter 272 may also be referred to as a second setting input unit. For the third setting terminal (MIN) of the 12th pin, the third information indicating the third parameter γ is input. In the present embodiment, the third information is supplied to the MIN terminal as the analog voltage V MIN . For example, the external resistors R31 and R32 in the integrated circuit 200 are driven, and the analog voltage V MIN is generated by dividing the reference voltage V REF . In this case, the third parameter γ can be set based on the voltage division ratio of the resistors R31 and R32. The third A/D converter 274 converts the analog voltage V MIN such as the MIN terminal into the third parameter γ of the digit. The MIN terminal and the third A/D converter 274 may also be referred to as a third setting input unit. The control logic circuit 100 calculates the output duty ratio D OUT based on the input digit value x, the first parameter α, the second parameter β, and the third parameter γ. Then, a control pulse having an operational output duty ratio D OUT is generated. The control logic circuit 100 synthesizes the output S1 of the Hall comparator 202 with the control pulse and generates a drive signal S5. Drive segment 209 includes pre-driver 210 and H-bridge circuit 212. The pre-driver 210 drives the H-bridge circuit 212 in accordance with the drive signal S5. Thereby, the output S1 is synchronized with the output S1 of the Hall comparator 202, and the outputs OUT1 and OUT2 are alternately active (commutation control), and the active output is switched (PWM drive) according to the control pulse. In addition, the driving segment 209 can also have the configuration of the driving segment 230 of FIG. The RNF terminal of the No. 8 pin is connected to the lower terminal of the H-bridge circuit 212. A current detecting resistor R NF is inserted between the RNF terminal and the external ground. In the resistor R NF , a detection voltage V NF which is proportional to the current flowing to the fan motor 6 is generated. The detection voltage V NF is input to the current detection terminal (CS) of pin 6. Current clamp comparator 206 compares detection voltage V NF to a particular voltage V CL . The voltage V CL defines the upper limit of the current flowing to the fan motor 6. When the output (current limit signal) S6 of the current clamp comparator 206 is active (high level), the control logic circuit 100 changes the logic value of the drive signal S5 in order to stop energization to the fan motor 6. The TSD circuit 242 detects an overheated state. The signal output circuit 244 generates an FG (Frequency Generator) signal having a period according to the number of revolutions of the fan motor 6, and is output from the FG terminal of the pin No. 1. The above is the overall configuration of the drive integrated circuit 200. Next, the internal structure will be described. Figure 13 is a block diagram showing the construction of the driving integrated circuit 200 of Figure 12 . In addition, in FIG. 13, only the structure for generating the drive signal S5 is shown, and other structures are suitably abbreviate|omitted. The control logic circuit 100 includes a duty calculation unit 108, a digital pulse modulator 110, and an output logic unit 112. The control logic circuit 100 can also be constructed by hardware logic, and can also be configured by a combination of a processor and a software. The duty calculation unit 108 holds the correction function f(x) and calculates the duty command value y=f(x) using the correction function. Figure 14 is a diagram showing the correction function f(x). The horizontal axis is displayed as x and the vertical axis is displayed as y. Setting the input digit value corresponding to the minimum value of the speed control signal S PWM (ie, the duty ratio 0%) to x 0 will correspond to the input of the maximum value of the speed control signal S PWM (ie, the duty ratio is 100%). The digit value is set to x 100 . In the present embodiment, the input digit value x is 6 bits, so x 0 =0 and x 100 = 64. A straight line of y=ax is shown in FIG. This is set to a=1. The correction function f(x) satisfies f(x 0 )=ax 0 , f(x 100 )=ax 100 , and is convexly curved downward. The bow correction function f(x) can also be derived from a curve derived from logic analysis, or can be obtained by self-fitting to obtain the compression characteristic of FIG. 3(c) and obtained by inversely calculating the compression characteristic, and an approximation can also be used. Those who are. The correction function y=f(x) is based on the first parameter α and the degree of bending can be changed. The various parameters are described here. The input digit value with the largest difference between ax and f(x) is set to x c . In Fig. 14, x c corresponds to the value of the input duty ratio D IN = 50% (i.e., 32). The first parameter α specifies the difference Δ between ax c and f(x). Further, the second parameter β defines the slope a of y=ax. Further, the duty calculation unit 108 clamps the duty command value y by setting the third parameter γ to the lower limit. That is, the third parameter γ defines the lowest value of the output duty ratio D OUT , in other words, the lowest rotational speed of the fan motor 6. An example of γ = 0 is shown in FIG. 15(a) and 15(b) are diagrams showing the parameter dependence of the input/output characteristics of the duty calculation unit 108. Fig. 15 (a) shows the input/output characteristics when the second parameter β is changed. (i) to (iii) show the characteristics of a = 1, 0.5, and 1.33, respectively. Fig. 15 (b) shows the input/output characteristics when the third parameter γ is changed. Return to Figure 13. The digital pulse modulator 110 generates a control pulse S4 having an output duty ratio D OUT according to the duty command value y. The digital pulse modulator 110 can be constructed using a digital counter. The output circuit 120 drives the fan motor 6 based on at least the control pulse S4. The output circuit 120 includes an output logic unit 112 of the control logic circuit 100, a drive section 209, a Hall comparator 202, and a current clamp comparator 206. The output logic unit 112 generates a drive signal S5 based on the pulse signal S1 from the Hall comparator 202, the current limit signal S6 from the current clamp comparator 206, and the control pulse S4. The output logic unit 112 may use a known technique. The above is the configuration of the drive integrated circuit 200. Next, the operation will be described. Fig. 16(a) is a view showing the relationship between the input duty ratio D IN of the driving integrated circuit 200 and the output duty ratio D OUT , and Fig. 16 (b) showing the input duty ratio D IN and the rotational speed of the fan motor 6. The map of the relationship. (i) shows the target characteristics, (ii) shows the characteristics when the output duty ratio is calculated based on y=ax without using the correction function f(x), and (iii) shows the characteristics of the drive integrated circuit 200 of FIG. . As described above, according to the drive integrated circuit 200 of the third embodiment, the actual rotational characteristic (iii) can be brought close to the target characteristic (i), and the linearity with respect to the rotational speed of the rotational speed control signal S PWM can be improved. In particular, in the drive integrated circuit 200 of the third embodiment, the degree of bending of the correction function f(x) can be adjusted in accordance with the first information V ADJ given to the AJD terminal. Therefore, depending on the type or characteristics of the fan motor 6 to be driven, the shape of the fan, and the environment in which the cooling device 2 is used, it is possible to achieve high linearity under various conditions by changing the correction curve. Further, the slope of the correction function f(x) can be adjusted based on the second information VSLOPE given to the SLOPE terminal, and the minimum number of revolutions can be set based on the third information VMIN given to the MIN terminal. It will be understood by those skilled in the art that the third embodiment is also exemplified, and various combinations of the components or the respective processing procedures may be variously modified, and such modifications are also within the scope of the invention. Hereinafter, a modification example related to the third embodiment will be described. (First Modification) Fig. 17 (a) is a block diagram of a drive integrated circuit 200a according to a first modification. In this modification, the first information indicating the first parameter α is input to the ADJ terminal as digital data. The interface circuit 280 receives the digital data input to the ADJ terminal and obtains the first parameter α. The first memory 282 holds the first parameter α. Similarly, the second information indicating the second parameter β and the third information indicating the third parameter γ are also input to the SLOPE terminal and the MIN terminal as digital data. The interface circuit 280 acquires the second parameter β and the third parameter γ from the digital data, and stores them in the second memory 284 and the third memory 286. For example, the interface circuit 280 can also be a receiver of an I 2 C bus. In addition, in the case where each digital data is transmitted in multiple time divisions, the ADJ terminal, the SLOPE terminal, and the MIN terminal can be commonly used. Moreover, the memories 282, 284, and 286 may be non-volatile memory or volatile memory. (Second Modification) In the embodiment, the rotation speed control signal S PWM whose pulse width is modulated is input to the PWM terminal, but the present invention is not limited thereto. Fig. 17 (b) is a block diagram of the drive integrated circuit 200b of the second modification. The drive integrated circuit 200b is a TH terminal that changes the PWM terminal and includes a rotational speed control signal S IN that receives the analog voltage V TH . Further, as the input circuit 201, an A/D converter 288 that converts the voltage of the TH terminal into an input digital value x is included. (Third Modification) In the embodiment, x c of Fig. 14 is set to a value corresponding to D IN = 50%, but the present invention is not limited thereto, and may be set to correspond to D IN = 30 ~. The value of the range of 66%. Alternatively , the fourth parameter of x c can be input from the outside. (Fourth Modification) In the embodiment, the second parameter β and the third parameter γ may be externally set, but one or all of them may be predetermined in the drive integrated circuit 200. In this case, the number of terminals and the number of external resistors can be reduced. (Fifth Modification) In the embodiment, the case where the fan motor to be driven is a single-phase drive motor will be described. However, the present invention is not limited thereto, and may be used for driving other two-phase or three-phase motors. . (Sixth Modification) In the embodiment, the Hall sensor 8 is externally mounted to the integrated circuit 200, but the Hall sensor 8 may be built in the Hall. Or the present invention omits the Hall sensor 8 and can be used for sensorless drive for detecting rotor position based on back electromotive force.
2‧‧‧冷卻裝置2‧‧‧Cooling device
2-1‧‧‧冷卻裝置2-1‧‧‧Cooling device
2-2‧‧‧冷卻裝置2-2‧‧‧Cooling device
2a‧‧‧冷卻裝置2a‧‧‧Cooling device
2r‧‧‧冷卻裝置2r‧‧‧Cooling device
6‧‧‧風扇馬達6‧‧‧Fan motor
8‧‧‧霍爾感測器8‧‧‧ Hall sensor
9‧‧‧驅動裝置9‧‧‧ drive
9a‧‧‧驅動裝置9a‧‧‧ drive unit
9r‧‧‧驅動裝置9r‧‧‧ drive unit
10‧‧‧變流器10‧‧‧Converter
12‧‧‧RC濾波器12‧‧‧RC filter
100‧‧‧控制邏輯電路100‧‧‧Control logic
108‧‧‧占空運算部108‧‧‧Occupy Operations Department
110‧‧‧數位脈衝調變器110‧‧‧Digital Pulse Modulator
112‧‧‧輸出邏輯部112‧‧‧Output logic
120‧‧‧輸出電路120‧‧‧Output circuit
200‧‧‧驅動積體電路200‧‧‧Drive integrated circuit
200a‧‧‧驅動積體電路200a‧‧‧Drive integrated circuit
200b‧‧‧驅動積體電路200b‧‧‧Drive integrated circuit
200r‧‧‧驅動積體電路200r‧‧‧Drive integrated circuit
201‧‧‧輸入電路201‧‧‧Input circuit
202‧‧‧霍爾比較器202‧‧‧Hall Comparator
204‧‧‧霍爾偏壓電路204‧‧‧Hall bias circuit
206‧‧‧電流箝位比較器206‧‧‧Current Clamp Comparator
208‧‧‧控制邏輯電路208‧‧‧Control logic
209‧‧‧驅動段209‧‧‧Drive segment
210‧‧‧預驅動器210‧‧‧Pre-driver
212‧‧‧H橋接電路212‧‧‧H bridge circuit
214‧‧‧基準電壓源214‧‧‧reference voltage source
216‧‧‧PWM比較器216‧‧‧PWM comparator
218‧‧‧PWM比較器218‧‧‧PWM comparator
220‧‧‧振盪器220‧‧‧Oscillator
230‧‧‧驅動段230‧‧‧Drive segment
232‧‧‧霍爾放大器232‧‧‧Hall Amplifier
234‧‧‧霍爾放大器234‧‧‧ Hall amplifier
240‧‧‧鎖定保護電路240‧‧‧Lock protection circuit
242‧‧‧TSD電路242‧‧‧TSD circuit
244‧‧‧信號輸出電路244‧‧‧Signal output circuit
250‧‧‧切換電路250‧‧‧Switching circuit
252‧‧‧第1開關252‧‧‧1st switch
254‧‧‧基準電壓線254‧‧‧reference voltage line
256‧‧‧第2開關256‧‧‧2nd switch
258‧‧‧比較器258‧‧‧ comparator
259‧‧‧邏輯閘259‧‧‧Logic gate
260‧‧‧輸出電路260‧‧‧Output circuit
270‧‧‧第1A/D轉換器270‧‧‧1A/D converter
272‧‧‧第2A/D轉換器272‧‧‧2A/D converter
274‧‧‧第3A/D轉換器274‧‧‧3A/D converter
280‧‧‧介面電路280‧‧‧Interface circuit
282‧‧‧第1記憶體282‧‧‧1st memory
284‧‧‧第2記憶體284‧‧‧2nd memory
286‧‧‧第3記憶體286‧‧‧3rd memory
288‧‧‧A/D轉換器288‧‧‧A/D converter
500‧‧‧PC500‧‧‧PC
502‧‧‧框體502‧‧‧ frame
504‧‧‧CPU504‧‧‧CPU
506‧‧‧主機板506‧‧‧ motherboard
508‧‧‧散熱片508‧‧‧ Heatsink
AL‧‧‧警報端子AL‧‧‧Alarm Terminal
ADJ‧‧‧第1設定端子ADJ‧‧‧1st setting terminal
C1‧‧‧電容器C1‧‧‧ capacitor
C21‧‧‧電容器C21‧‧‧ capacitor
CS‧‧‧電流檢測端子CS‧‧‧current detection terminal
CS1‧‧‧第1電流源CS1‧‧‧1st current source
CS2‧‧‧第2電流源CS2‧‧‧2nd current source
D1‧‧‧二極體D1‧‧‧ diode
DOUT‧‧‧輸出占空比D OUT ‧‧‧output duty cycle
DIN‧‧‧輸入占空比D IN ‧‧‧ input duty cycle
FG‧‧‧端子 FG‧‧‧ terminal
GND‧‧‧接地端子 GND‧‧‧ Grounding terminal
H+‧‧‧霍爾輸入端子 H+‧‧‧ Hall input terminal
H-‧‧‧霍爾輸入端子 H-‧‧‧ Hall input terminal
HB‧‧‧霍爾偏壓端子 HB‧‧‧ Hall bias terminal
IC1‧‧‧充電電流I C1 ‧‧‧Charging current
IC2‧‧‧放電電流I C2 ‧‧‧discharge current
MIN‧‧‧最低轉速設定端子 MIN‧‧‧minimum speed setting terminal
N1‧‧‧連接點 N1‧‧‧ connection point
OSC‧‧‧振盪器端子 OSC‧‧‧Oscillator terminal
OSCH‧‧‧第2振盪器端子 OSCH‧‧‧2nd oscillator terminal
OUT1‧‧‧端子 OUT1‧‧‧ terminal
OUT2‧‧‧端子 OUT2‧‧‧ terminal
PWM‧‧‧輸入脈衝調變信號 PWM‧‧‧ input pulse modulation signal
R11‧‧‧電阻 R11‧‧‧ resistance
R12‧‧‧電阻 R12‧‧‧ resistance
R21‧‧‧充電電阻 R21‧‧‧Charging resistor
R22‧‧‧放電電阻 R22‧‧‧Discharge resistor
R31‧‧‧第1電阻 R31‧‧‧1st resistor
R32‧‧‧第2電阻 R32‧‧‧2nd resistor
R33‧‧‧第3電阻 R33‧‧‧3rd resistor
REF‧‧‧基準電壓端子 REF‧‧‧reference voltage terminal
RNF‧‧‧端子 RNF‧‧‧ terminal
RNF‧‧‧電流檢測用電阻R NF ‧‧‧Resistance for current detection
S1‧‧‧脈衝信號 S1‧‧‧ pulse signal
S2‧‧‧脈衝信號 S2‧‧‧ pulse signal
S3‧‧‧脈衝信號 S3‧‧‧ pulse signal
S4‧‧‧脈衝信號 S4‧‧‧ pulse signal
S5‧‧‧驅動信號 S5‧‧‧ drive signal
S6‧‧‧電流限制信號 S6‧‧‧ current limit signal
SELO‧‧‧選擇器端子 SELO‧‧‧ selector terminal
SIN‧‧‧轉速控制信號S IN ‧‧‧Speed control signal
SLOPE‧‧‧第2設定端子 SLOPE‧‧‧2nd setting terminal
SPWM‧‧‧輸入脈衝調變信號S PWM ‧‧‧ input pulse modulation signal
VADJ‧‧‧類比電壓V ADJ ‧‧‧ analog voltage
VCC‧‧‧電源端子 VCC‧‧‧ power terminal
VCL‧‧‧電壓V CL ‧‧‧ voltage
VDD‧‧‧電源電壓V DD ‧‧‧Power supply voltage
VH‧‧‧上側臨限值V H ‧‧‧ upper threshold
VHB‧‧‧霍爾偏壓電壓V HB ‧‧‧Hall bias voltage
VL‧‧‧下側臨限值V L ‧‧‧ lower threshold
VMIN‧‧‧最低轉速之電壓V MIN ‧‧‧ minimum speed voltage
VN1‧‧‧電壓V N1 ‧‧‧ voltage
VOSC‧‧‧振盪器電壓V OSC ‧‧‧Oscillator voltage
VOSC '‧‧‧振盪器電壓V OSC ' ‧‧‧Oscillator voltage
VREF‧‧‧基準電壓V REF ‧ ‧ reference voltage
VSLOPE‧‧‧類比電壓V SLOPE ‧‧‧ analog voltage
VTH‧‧‧控制電壓V TH ‧‧‧ control voltage
x‧‧‧輸入數位值 x‧‧‧Input digit value
y‧‧‧占空指令值 Y‧‧‧ duty command value
α‧‧‧第1參數 Α‧‧‧1st parameter
β‧‧‧第2參數 Β‧‧‧2nd parameter
γ‧‧‧第3參數 Γ‧‧‧3rd parameter
圖1係包含本發明人等研討之風扇馬達之驅動積體電路(Integrated Circuit)之冷卻裝置之電路圖。 圖2係圖1之驅動積體電路之動作波形圖。 圖3(a)~(c)係顯示圖1之驅動裝置中之輸入占空比、TH端子之電壓、輸出OUT1(OUT2)之輸出占空比、及轉速之關係之圖。 圖4係顯示包含第1實施形態之驅動積體電路之冷卻裝置之構成之電路圖。 圖5係顯示切換電路之構成例之電路圖。' 圖6係圖4之驅動裝置之動作波形圖。 圖7(a)係顯示圖1之振盪器電壓VOSC ' 與圖4之振盪器電壓VOSC 之波形圖,圖7(b)係顯示TH端子之電壓與控制脈衝之占空比之關係之圖。 圖8係顯示改變充電電阻、放電電阻之組合時之控制特性之圖。 圖9係第2實施形態之驅動積體電路之電路圖。 圖10係具備冷卻裝置之PC之立體圖。 圖11(a)~(c)係第1變化例之驅動積體電路之電路圖。 圖12係顯示包含第3實施形態之驅動積體電路之冷卻裝置之構成之電路圖。 圖13係顯示圖12之驅動積體電路之構成之方塊圖。 圖14係顯示修正函數f(x)之圖。 圖15(a)、(b)係說明占空運算部之輸入輸出特性之參數依存性之圖。 圖16(a)係顯示驅動積體電路之輸入占空比DIN 與輸出占空比DOUT 之關係之圖,圖16(b)係顯示輸入占空比DIN 與風扇馬達之轉速之關係之圖。 圖17(a)係第1變化例之驅動積體電路之方塊圖,圖17(b)係第2變化例之驅動積體電路之方塊圖。Fig. 1 is a circuit diagram of a cooling device including a drive integrated circuit of a fan motor studied by the inventors of the present invention. FIG. 2 is an operation waveform diagram of the driving integrated circuit of FIG. 1. FIG. 3(a) to 3(c) are diagrams showing the relationship between the input duty ratio, the voltage of the TH terminal, the output duty ratio of the output OUT1 (OUT2), and the number of revolutions in the driving device of Fig. 1. Fig. 4 is a circuit diagram showing a configuration of a cooling device including the drive integrated circuit of the first embodiment. Fig. 5 is a circuit diagram showing a configuration example of a switching circuit. 'Operation waveform diagram of the drive apparatus of FIG. 4 FIG. 6 lines. FIG. 7 (a) based oscillators FIG waveform diagram showing a voltage V OSC 'in FIG. 4 of the oscillator of the voltage V OSC, FIG. 7 (b) shows the relationship-based duty ratio of the control voltage terminal TH of pulses Figure. Fig. 8 is a view showing control characteristics when a combination of a charging resistor and a discharge resistor is changed. Fig. 9 is a circuit diagram of a drive integrated circuit of the second embodiment. Fig. 10 is a perspective view of a PC equipped with a cooling device. 11(a) to 11(c) are circuit diagrams of a drive integrated circuit of a first modification. Fig. 12 is a circuit diagram showing a configuration of a cooling device including the drive integrated circuit of the third embodiment. Figure 13 is a block diagram showing the construction of the driving integrated circuit of Figure 12. Figure 14 is a diagram showing the correction function f(x). 15(a) and 15(b) are diagrams showing the parameter dependence of the input/output characteristics of the duty calculation unit. Fig. 16(a) is a diagram showing the relationship between the input duty ratio D IN of the driving integrated circuit and the output duty ratio D OUT , and Fig. 16 (b) shows the relationship between the input duty ratio D IN and the rotational speed of the fan motor. Picture. Fig. 17 (a) is a block diagram of a drive integrated circuit of a first modification, and Fig. 17 (b) is a block diagram of a drive integrated circuit of a second modification.
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TWI681620B (en) * | 2018-05-18 | 2020-01-01 | 茂達電子股份有限公司 | Motor driving circuit |
JP7249740B2 (en) * | 2018-07-12 | 2023-03-31 | ミネベアミツミ株式会社 | MOTOR DRIVE DEVICE, MOTOR SYSTEM, FAN MOTOR AND MOTOR DRIVING METHOD |
JP2021029063A (en) * | 2019-08-09 | 2021-02-25 | ミネベアミツミ株式会社 | Pwm signal control device, motor drive control device, pwm signal measurement method, and motor drive control method |
JP7498632B2 (en) | 2020-09-23 | 2024-06-12 | ミネベアミツミ株式会社 | MOTOR CONTROL CIRCUIT, MOTOR DRIVE CONTROL DEVICE, MOTOR UNIT, AND MOTOR CONTROL METHOD |
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CN116264396A (en) * | 2021-12-15 | 2023-06-16 | 新疆金风科技股份有限公司 | Wind generating set, control method and control device of wind power converter |
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