TW201919214A - 影像感測裝置 - Google Patents

影像感測裝置 Download PDF

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TW201919214A
TW201919214A TW107108470A TW107108470A TW201919214A TW 201919214 A TW201919214 A TW 201919214A TW 107108470 A TW107108470 A TW 107108470A TW 107108470 A TW107108470 A TW 107108470A TW 201919214 A TW201919214 A TW 201919214A
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semiconductor substrate
layer
radiation sensing
isolation
trench isolation
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魏嘉余
林彥良
李國政
黃薰瑩
陳信吉
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台灣積體電路製造股份有限公司
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Abstract

一種影像感測裝置，包含半導體基材、輻射感測元件、元件層和溝渠隔離。半導體基材具有前側表面和與前側表面相對的背側表面。輻射感測元件設置於半導體基材的光感測區中且從半導體基材的前側表面延伸出，此輻射感測元件包含帶隙能量小於1.77電子伏特的半導體材料。元件層位於半導體基材的前側表面及輻射感測元件上。溝渠隔離設置於半導體基材的隔離區中且從半導體基材的背側表面延伸出。

Description

影像感測裝置
本揭露是有關於一種影像感測裝置。
影像感測裝置，例如互補式金屬氧化物半導體(complementary metal-oxide semiconductor；CMOS)影像感測器(CMOS image sensor；CIS)、主動像素感測器(active-pixel sensor；APS)、被動像素感測器(passive-pixel sensor)和電荷耦合元件(charge-coupled device；CCD)感測器等，已被廣泛使用在各種電子產品上，例如數位相機、智慧型手機、平板電腦、車用錄影器和其他應用。由於小型化的趨勢，影像感測裝置中的電子元件和在影像感測裝置的每一像素單元中的電子元件之間的距離變得愈來愈小。如何在影像感測裝置的像素尺寸縮小後提升其光吸收效率，已成為相關產業的一大課題。
本揭露提出一種影像感測裝置，此影像感測裝置包含半導體基材、輻射感測元件、元件層和溝渠隔離。半導體基材具有前側表面和與前側表面相對的背側表面。輻射 感測元件設置於半導體基材的光感測區中且從半導體基材的前側表面延伸出，此輻射感測元件包含半導體材料，此半導體材料具有小於1.77電子伏特的帶隙(band gap)能量。元件層位於半導體基材的前側表面及輻射感測元件的上方。溝渠隔離設置於半導體基材的隔離區中且從半導體基材的背側表面延伸出。
100、200‧‧‧影像感測裝置
100A‧‧‧像素區域
100B‧‧‧邏輯區域
102‧‧‧像素單元
200B、200G、200R‧‧‧像素區域
202、302‧‧‧半導體基材
202B、302B‧‧‧背側表面
202F、302F‧‧‧前側表面
104I、202I、302I‧‧‧隔離區
104P、202P、302P‧‧‧光感測區
204、306‧‧‧淺溝渠隔離
206A、310A‧‧‧輻射感測元件
206B、310B‧‧‧釘扎元件
208、312‧‧‧元件層
210、314‧‧‧承載基材
212、316‧‧‧深溝渠隔離
214、318‧‧‧金屬格柵
216、320‧‧‧介電層
218、322‧‧‧彩色濾光層
220、324‧‧‧微透鏡層
304A‧‧‧淺溝渠
308‧‧‧凹陷
A‧‧‧範圍
D304B、D308‧‧‧深度
T202、T206A、T214、T216、T302、T310A、T318、T320、TDTI‧‧‧厚度
W206A、W304B、W308、W310A、WDTI‧‧‧寬度
為了更完整了解實施例及其優點，現參照結合所附圖式所做之下列描述，其中：〔圖1A〕為依據本揭露之一些實施例之影像感測裝置的俯視示意圖；〔圖1B〕為〔圖1A〕之影像感測裝置的部分放大圖；〔圖2〕為依據本揭露之一些實施例之影像感測裝置的剖面示意圖；以及〔圖3A〕至〔圖3J〕為依據本揭露之一些實施例之形成影像感測裝置之各種中間階段的剖面示意圖。
後續說明書提供許多不同實施例或範例，用以達成本揭露的不同特徵。後續描述的元件及配置的特定範例，係用來簡要說明本揭露。當然，這些只是範例，並非用來限制本揭露。舉例而言，在後續說明中，第一特徵形成於第二特徵上，可能包括的實施例為第一特徵及第二特徵形成 直接接觸，以及可能包括的實施例為額外的特徵可能形成介於第一及第二特徵之間，使得第一及第二特徵可能非直接接觸。
本文所使用的用語係用來描述特定的實施例，而非用來限定所附之請求項。舉例來說，除非特別限定，否則單數形式的用語「一」或「該」亦可代表複數形式。此外，本揭露可能會在各範例中重複參考數字及/或文字。這樣的重複係基於簡化與清楚之目的，以其本身而言並非用以指定所討論之各實施方式及/或配置之間的關係。
另外，在此可能會使用空間相對用語，例如「上方(over)」、「上(on)」等等，以方便說明如圖式所繪示之一元件或一特徵與另一(另一些)元件或特徵之關係。除了在圖式中所繪示之方向外，這些空間相對用詞意欲含括元件在使用或操作中的不同方位。設備可能以不同方式定位(旋轉90度或在其他方位上)，因此可利用同樣的方式來解釋在此所使用之空間相對描述符號。
本揭露之實施例是有關於具有增強紅外線輻射(例如近紅外線輻射)吸收能力的影像感測裝置。一般來說，相較於具有間接帶隙的半導體材料，具有直接帶隙的半導體材料可吸收更多低光子能量的入射光或入射輻射。在影像感測裝置中，輻射感測元件是由具有直接帶隙和低帶隙能量的半導體材料形成。在矽基材中的鍺元件吸收入射光的例子中，鍺元件的間接帶隙在退火製程中產生的於二維上拉伸張 力(biaxial tensile stress)下轉換為直接帶隙。如此一來，可增強紅外線輻射的吸收效率。
圖1A為依據本揭露之一些實施例之影像感測裝置100的俯視示意圖。影像感測裝置100為背照式(back-side illuminated；BSI)或前照式(front-side illuminated；FSI)互補式金屬氧化物半導體影像感測器。影像感測裝置100具有像素區域100A和圍繞像素區域100A的邏輯區域100B。像素區域100A包含像素單元102，其回應入射至像素單元102之入射光而產生電荷。在一些實施例中，如圖1A所示，像素單元102排列為多行和多列的矩陣。一些電路係位於像素區域100A中，用以傳送由像素單元102產生的電荷至邏輯區域100B。其他電路係位於邏輯區域100B中，以處理來自像素區域100A的輸出訊號。在本揭露中，像素單元102A的數量可以是例如百萬個。然而，在影像感測裝置100中像素單元102的數量可依不同的應用而變化。
請一併參照圖1B，圖1B為圖1A所示之像素區域100A的範圍A的放大圖。如圖1B所示，在像素區域100A的範圍A內有光感測區104P和隔離區104I。光感測區104P用以感測入射光。隔離區104I係配置為格柵圖案，用以隔絕光感測區104P之間的串擾(crosstalk)。每一光感測區104P和圍繞對應至之光感測區104P之隔離區104I的部分構成像素單元102。
圖2為依據本揭露之一些實施例之影像感測裝置200的剖面示意圖。影像感測裝置200可以是圖1A之影像感測裝置100或其他相似的影像感測裝置。影像感測裝置200可以是背照式互補式金屬氧化物半導體影像感測器，其金屬走線設置在基材的前側，且其輻射感測元件設置在基材的背側。然而，本揭露之實施例不限於是背照式互補式金屬氧化物半導體影像感測器。舉例而言，影像感測裝置200可以是前照式互補式金屬氧化物半導體影像感測器，其金屬走線設置在基材的表面中的輻射感測元件上方。為簡化說明，圖2僅繪示影像感測裝置200的三個像素區域200R、200G、200B，但本揭露之實施例不限於此。在一些實施例中，像素區域200R、200G、200B分別為紅色、綠色和藍色像素區域。其他像素區域200R、200G、200B的組合也可應用在不同的實施例。
在圖2中，影像感測裝置200的半導體基材202包含用以感測入射光的光感測區202P和用以隔離光感測區202P之間的串擾的隔離區202I。在影像感測裝置200為圖1A之影像感測裝置100的實施例中，光感測區202P對應至光感測區104P，而隔離區202I對應至隔離區104I。半導體基材202可以是矽基材。舉例而言，在一些示範實例中，半導體基材202包含摻雜或未摻雜的塊狀矽(例如p型、n型或其組合)。其他合適的材料亦可用於形成影像感測裝置200。舉例而言，半導體基材202可包含例如鍺、石英、藍寶石、玻璃或其他合適的材料。或者，半導體基材202可以 是絕緣物上半導體(semiconductor-on-insulator；SOI)基材的主動層。在一些實施例中，半導體基材202的厚度T202為約1.5微米至約8微米。在一些實施例中，半導體基材202的厚度T202為約6微米。
淺溝渠隔離(shallow trench isolation；STI)204係設置在半導體基材202的隔離區202I中且在半導體基材202的前側表面202F。淺溝渠隔離204包含隔離材料，例如氧化矽、二氧化矽、摻碳的二氧化矽(carbon doped silicon dioxide)、摻鎳的二氧化矽(nitrogen doped silicon dioxide)、摻鍺的二氧化矽(germanium doped silicon dioxide)、摻磷的二氧化矽(phosphorus doped silicon dioxide)、可流動氧化物(flowable oxide)、上述組合，和/或其他合適的材料。在一些實施例中，淺溝渠隔離204設置為格柵圖案。
輻射感測元件206A係分別設置在半導體基材202的光感測區202P中且在半導體基材202前側表面202F。輻射感測元件206A包含半導體材料，其帶隙能量小於1.77電子伏特。在一些實施例中，輻射感測元件206A的半導體材料的帶隙能量小於1.1電子伏特。輻射感測元件206A可包含例如鍺、矽鍺、砷化鎵、磷化銦、銻化鎵、碲化鎘、砷化銦、銻化銦、上述組合和/或其他合適的材料。如圖2所示，每一輻射感測元件206A從半導體基材202的前側表面202F延伸出。每一輻射感測元件206A的厚度T206A和寬度W206A分別為約100奈米至8微米和約0.9微米至3微 米。每一輻射感測元件206A的厚度T206A小於或等於半導體基材202的厚度T202。在一些實施例中，每一輻射感測元件206A的厚度T206A為約1.5微米至約3微米。在一些實施例中，依據各種設計需求，輻射感測元件206A可具有不同的厚度T206A和/或寬度W206A。
在半導體基材202為矽基材且輻射感測元件206A的半導體材料為鍺的實施例中，可採用退火製程以在半導體基材202與輻射感測元件206A之間的介面形成矽鍺鍵結(silicon-germanium bonds)。如此一來，在矽的半導體基材202上形成應變(strained)矽鍺異質磊晶(heteroepitaxial)層，且因此轉換鍺的間接帶隙至矽鍺的直接帶隙，而達成低帶隙能量和較佳的紅外線輻射吸收能力。在一些實施例中，退火製程可以是溫度為約攝氏500度至約攝氏600度的高溫原位(in-situ)退火製程，以減少半導體基材202與輻射感測元件206A之間的穿透差排(threading dislocations)，且退火製程的持續時間可為約10小時或小於10小時。
如圖2所示，每一輻射感測元件206A的一部分為釘扎(pinned)元件206B，例如P型釘扎光二極體(photodiode)。在一些示範實例中，釘扎元件206B包含p型摻雜物，例如硼、鋁、鎵、上述組合或相似者。釘扎元件206B用於輻射感測元件206A與元件層208之間的介面隔離。
元件層208係設置於半導體基材202前側表面202F、淺溝渠隔離204和輻射感測元件206A上方。元件層208可包含各種與輻射感測元件206A電性連接的電晶體，以收集由照射至半導體基材202的光感測區202P的入射光和/或入射輻射(例如可見光和/或紅外線輻射)所產生的電子，並將收集的電子轉換為電壓訊號。舉例而言，在元件層208中的電晶體可包含轉移電晶體(transfer transistor)、重設電晶體(reset transistor)、源極隨耦電晶體(source follower transistor)與列選擇電晶體(row select transistor)的組合和/或其他合適的電晶體。為簡化說明，圖2未繪示出在元件層208中的電晶體和其他元件(例如接觸栓、介層窗、導線等)的詳細結構。
依據一些實施例，元件層208亦可包含層間介電(inter-layer dielectric；ILD)層(圖未繪示)和位於層間介電層上方的金屬間介電(inter-metal dielectric；IMD)層(圖未繪示)。層間介電層(圖未繪示)可包含磷矽玻璃(phosphosilicate glass；PSG)、硼矽玻璃(borosilicate glass；BSG)、摻硼的磷矽玻璃(boron-doped phosphosilicate glass；BPSG)、四乙氧基矽烷(tetraethyl-orthosilicate；TEOS)氧化物等材料或相似者。此外，層間介電層(圖未繪示)可包含接觸栓，用以電性連接在元件層208中的電晶體。金屬間介電層(圖未繪示)可包含介層窗和導線；每一介層窗可電性連接於導 線之間，且導線可電性連接至元件層208中的電晶體，以傳輸電壓訊號。
此外，在一些實施例中，承載基材210可接合至元件層208。在一些實施例中，承載基材210可藉由分子力(molecular force)接合製程接合至元件層208，例如直接接合(direct bonding)製程、光學熔融接合(optical fusion bonding)製程或其他習知的合適接合製程。
深溝渠隔離(deep trench isolation；DTI)212可設置在半導體基材202的隔離區202I中，以避免入射光穿透隔離區202I。深溝渠隔離212包含隔離材料，例如氧化鉿、氧化鉭、氧化鋯、氧化鈦、氧化鋁、高介電常數材料、上述組合和/或其他合適的材料。如圖2所示，深溝渠隔離212從半導體基材202的背側表面202B延伸。深溝渠隔離212的頂部表面可在半導體基材202的背側表面202B的上方或與半導體基材202的背側表面202B共平面。深溝渠隔離212可包含厚度TDTI(即從半導體基材202的背側表面202B至深溝渠隔離212的底部表面)和寬度WDTI，且厚度TDTI與寬度WDTI的比值可等於或大於5，以提供良好的隔離效果。在一些實施例中，厚度TDTI與寬度WDTI的比值為約5至約15。在一些實施例中，寬度WDTI為約0.1微米至約0.5微米，且厚度TDTI為約1.5微米至約4微米。
在一些實施例中，深溝渠隔離212包含多層。 舉例而言，如圖2所繪示，不同隔離材料的第一層212A和第二層212B可依序設置在半導體基材202的背側表面202B 的上方。第一層212A可以是薄膜，其設置為與在半導體基材202之隔離區202I中的溝渠和半導體基材202的背側表面202B共形。第二層212B設置在第一層212A的上方且填充溝渠。第一層212A包含例如氧化鉿、氧化鉭、氧化鋯、氧化鈦、氧化鋁、上述組合和/或相似的高介電常數材料。第二層212B可包含例如氧化矽、氮化矽、氮氧化矽、碳化矽、上述組合和/或相似的介電材料。
金屬格柵(metal grid)214設置在半導體基材202之背側表面202B的上方。如圖2所示，金屬格柵214形成在半導體基材202的隔離區202I中且在深溝渠隔離212上。特別地，在一些實施例中，金屬格柵214與深溝渠隔離212對準。在一些實施例中，金屬格柵214覆蓋深溝渠隔離212。金屬格柵214可包含例如鋁、銅、鎢、鉭、鈦、上述組合和/或相似的金屬材料。金屬格柵214的每一部分可具有矩形、梯形、倒梯形、三角形之剖面形狀或其他合適的形狀。在一些實施例中，金屬格柵214的厚度T214為約10奈米至約0.1微米。
介電層216設置在金屬格柵214和半導體基材202的背側表面202B的上方。介電層216可包含氧化矽、氮化矽、氮氧化矽、低介電常數材料、旋塗玻璃(spin on glass；SOG)和/或其他合適的介電材料。介電層216的厚度T216等於或大於金屬格柵214的厚度T214。在一些實施例中，介電層216可具有多個介電層。
彩色濾光層218係設置在介電層216的上方。彩色濾光層218可使特定波長帶中的光成分通過並阻擋多餘的光成分。彩色濾光層218的通過波長帶可以是紅光波長帶、綠光波長帶、藍光波長帶或上述組合，但不限於此。紅外光可通過彩色濾光層218且在半導體基材202中被吸收。彩色濾光層218可包含例如顏料基(pigment-based)聚合物、染料基(dye-based)聚合物、樹脂或其他合適的材料。
微透鏡層220係設置在彩色濾光層218的上方。微透鏡層220在像素區域200R、200G、200B中分別具有凸面形狀，以提升光接收效率。微透鏡層220可由玻璃、丙烯酸(acrylic)聚合物或其他具有高透光率的合適材料形成。
圖3A至圖3J為依據本揭露之一些實施例之形成影像感測裝置之各種中間階段的剖面示意圖。如圖3A所示，提供半導體基材302，其可由例如矽的半導體材料形成。在一些示範實例中，半導體基材302包含摻雜或未摻雜的塊狀矽(例如p型、n型或其組合)。其他合適的材料亦可用於形成影像感測裝置。舉例而言，半導體基材302可由例如鍺、石英、藍寶石、玻璃和/或其他合適的材料形成。或者，可形成半導體基材302為絕緣物上半導體基材的主動層。
此外，如圖3A所示，半導體基材302包含用以感測入射光的光感測區302P和用以隔離光感測區302P之間的串擾的隔離區302I。淺溝渠隔離306在半導體基材302 的隔離區302I中形成。詳細而言，對半導體基材302的前側表面302F進行蝕刻製程，以形成淺溝渠304A，且接著進行沉積製程，填充隔離材料至淺溝渠304A中，以形成淺溝渠隔離306。在形成淺溝渠304A的蝕刻製程中，圖案化光阻(圖未繪示)用為覆蓋半導體基材302之光感測區302P的遮罩，以在半導體基材302的隔離區302I中形成淺溝渠304A。形成淺溝渠304A的蝕刻製程可以是例如反應式離子蝕刻(reactive ion etching；RIE)製程、電漿蝕刻(plasma etching)製程、乾式蝕刻製程、濕式蝕刻製程和/或其他合適的蝕刻製程。圖案化光阻(圖未繪示)在形成淺溝渠304A的蝕刻製程後被剝除。接著，在淺溝渠304A中填充隔離材料，以在半導體基材302的隔離區302I中形成淺溝渠隔離306。用於形成淺溝渠隔離306的隔離材料可以是例如氧化矽、二氧化矽、摻碳的二氧化矽、摻鎳的二氧化矽、摻鍺的二氧化矽、摻磷的二氧化矽、可流動氧化物、上述組合和/或其他合適的材料。在一些實施例中，可藉由利用例如化學氣相沉積(chemical vapor deposition；CVD)製程、選擇性區域化學氣相沉積(selective area CVD；SACVD)製程、高密度電漿化學氣相沉積(high density plasma CVD；HDPCVD)製程、高深寬比製程(high aspect ratio process；HARP)、旋轉塗佈(spin-on coating)製程、濺鍍(sputtering)製程、上述組合和/或其他合適的製程來填充隔離材料。在一些實施例中，可進行化學機械研磨(chemical mechanical polishing；CMP)製程以平坦 化淺溝渠隔離306，使得淺溝渠隔離306的頂部表面與半導體基材302的前側表面302F共平面。
接著，如圖3B所示，對半導體基材302進行蝕刻製程，以分別在半導體基材302的光感測區302P中形成凹陷308。在形成凹陷308的蝕刻製程中，圖案化光阻(圖未繪示)用為覆蓋半導體基材302之隔離區302I的遮罩，以分別在半導體基材302的光感測區302P中形成凹陷308。形成凹陷308的蝕刻製程可以是非等向性(anisotropic)蝕刻製程和/或等向性(isotropic)蝕刻製程，例如反應式離子蝕刻製程、電漿蝕刻(plasma etching)製程、乾式蝕刻製程、濕式蝕刻製程和/或其他合適的蝕刻製程。圖案化光阻(圖未繪示)在形成凹陷308的蝕刻製程後被剝除。每一凹陷308的深度D308和寬度W308分別為約100奈米至約8微米和為約0.9微米至約3微米。在一些實施例中，每一凹陷308的深度D308為約1.5微米至約3微米。在一些實施例中，凹陷308可具有不同的深度D308和/或寬度W308。
然後，如圖3C所示，進行沉積製程以填充半導體材料至凹陷308中，以分別在半導體基材302的光感測區302P中形成輻射感測元件310A。用以形成輻射感測元件310A之半導體材料的帶隙能量小於1.77電子伏特。在一些實施例中，用以形成輻射感測元件310A之半導體材料的帶隙能量小於1.1電子伏特。輻射感測元件310A可由鍺、矽鍺、砷化鎵、磷化銦、銻化鎵、碲化鎘、砷化銦、銻化銦、上述組合和/或其他合適的材料形成。在一些實施例中，可 利用例如高密度電漿化學氣相沉積製程、高深寬比製程、化學氣相沉積製程、電漿輔助化學氣相沉積(plasma enhanced CVD；PECVD)製程、選擇性區域化學氣相沉積製程、旋轉塗佈製程、濺鍍製程、上述組合和/或其他合適的製程來填充半導體材料。在一些實施例中，可再進行化學機械研磨製程以平坦化輻射感測元件310A，使得每一輻射感測元件310A的頂部表面與半導體基材302的前側表面302F共平面，且因此輻射感測元件310A的厚度T310A和寬度W310A分別對應至至凹陷308的深度D308和寬度W308。
在半導體基材302係由矽形成且輻射感測元件310A係由鍺形成的實施例中，可採用退火製程以在半導體基材302與輻射感測元件310A之間的介面形成矽鍺鍵結。如此一來，在矽的半導體基材302上形成應變矽鍺異質磊晶層，且因此轉換鍺的間接帶隙至矽鍺的直接帶隙，達成低帶隙能量和較佳的紅外線輻射吸收能力。在一些實施例中，退火製程可以是溫度為約攝氏500度至約攝氏600度的高溫原位退火製程，以減少半導體基材302與輻射感測元件310A之間的穿透差排，且退火製程的持續時間可為約10小時或小於10小時。
在輻射感測元件310A的材料為矽鍺的實施例中，輻射感測元件310A可藉由電漿輔助化學氣相沉積製程形成。在輻射感測元件310A，矽與鍺的比例(即Si1-x Ge x 的鍺分數x)可藉由調整用以形成矽鍺之氫化矽(SiH4)與氫化鍺(GeH4)的量來控制。
接著，如圖3D所示，每一輻射感測元件310A的一部分是藉由離子佈植製程所佈植以形成釘扎元件310B。在示範實例中，每一釘扎元件310B為P型釘扎光二極體，其可由例如硼、鋁、鎵、上述組合或相似的p型摻雜物形成。釘扎元件310B用為輻射感測元件310A與將於後續步驟形成的元件層312之間的介面隔離。
接著，如圖3E所示，在半導體基材302的前側表面302F、淺溝渠隔離306、輻射感測元件310A和釘扎元件310B的上方形成元件層312。元件層312可被形成包含有各種與輻射感測元件310A電性連接的電晶體，以收集由入射光和/或入射輻射(例如可見光和/或紅外線輻射)通過至半導體基材302的光感測區302P所產生的電子，且將收集的電子轉換為電壓訊號。舉例而言，元件層312中的電晶體可包含轉移電晶體、重設電晶體、源極隨耦電晶體與列選擇電晶體的組合和/或其他合適的電晶體。為簡化說明，圖3E至圖3J未示出在元件層312中的電晶體和其他元件的詳細結構。
依據一些實施例，元件層312亦可被形成包含有層間介電層(圖未繪示)和在層間介電層上方的金屬間介電層(圖未繪示)。層間介電層(圖未繪示)可由磷矽玻璃、硼矽玻璃、摻硼的磷矽玻璃、四乙氧基矽烷氧化物或相似者形成。此外，在層間介電層(圖未繪示)中可形成接觸栓以電性連接在元件層312中的電晶體。金屬間介電層(圖未繪示)可包含介層窗和導線；每一介層窗可電性連接於導線之 間，且導線可電性連接至元件層312中的電晶體，以傳輸電壓訊號。
然後，依據一些實施例，如圖3F所示，藉由接合製程將承載基材314接合至元件層312。在一些實施例中，接合製程可包含分子力接合製程，例如直接接合製程和光學熔融接合製程。在其他實施例中，接合製程可包含其他習知的合適接合製程。
然後，如圖3G所示，在半導體基材302的背側表面302B上進行薄化製程，以減少半導體基材302的厚度。半導體基材302的厚度T302(即薄化後之半導體基材302的前側表面302F與新的背側表面302B'之間的距離)等於或大於每一輻射感測元件310A的厚度T310A。在一些實施例中，半導體基材302的厚度T302為約1.5微米至約8微米。在一些實施例中，半導體基材302的厚度T302為約6微米。半導體基材302的薄化製程可包含蝕刻製程、化學機械研磨製程和/或其他合適的製程。
然後，如圖3H所示，在半導體基材302的隔離區302I中形成深溝渠隔離316，以避免入射光穿透隔離區302I。詳細而言，可在半導體基材302的背側表面302B'上進行蝕刻製程，以形成深溝渠304B，且接著進行沉積製程，在深溝渠304B中填充隔離材料，以形成深溝渠隔離316。在形成深溝渠304B的蝕刻製程中，圖案化光阻(圖未繪示)用為覆蓋半導體基材302之光感測區302P的遮罩，以在半導體基材302的隔離區302I中形成深溝渠304B。形成深溝 渠304B的蝕刻製程可以是例如反應式離子蝕刻製程、電漿蝕刻製程、乾式蝕刻製程、濕式蝕刻製程和/或其他合適的蝕刻製程。深溝渠304B係被形成具有深度D304B和寬度W304B，且深度D304B與寬度W304B的比值可等於或大於5，以提供良好的隔離效果。在一些實施例中，深度D304B與寬度W304B的比值為約5至約15。在一些實施例中，寬度W304B為約0.1微米至約0.5微米，且深度D304B為約1.5微米至約4微米。圖案化光阻(圖未繪示)在形成深溝渠304B的蝕刻製程後被剝除。
接著，填充隔離材料至深溝渠304B中，以在半導體基材302的隔離區302I中形成深溝渠隔離316。用以形成深溝渠隔離316的隔離材料可以是例如氧化鉿、氧化鉭、氧化鋯、氧化鈦、氧化鋁、高介電常數材料、上述組合和/或其他合適的材料。在一些實施例中，藉由例如高密度電漿化學氣相沉積製程、高深寬比製程、化學氣相沉積製程、選擇性區域化學氣相沉積製程、旋轉塗佈製程、濺鍍製程、上述組合和/或其他合適的製程來填充隔離材料。在一些實施例中，可進行化學機械研磨製程，以平坦化深溝渠隔離316的頂部表面。深溝渠隔離316的頂部表面可在半導體基材302的背側表面302B'的上方或與半導體基材302的背側表面302B'共平面。
在一些實施例中，深溝渠隔離316係被形成包含有多層。舉例而言，如圖3H所繪示，在半導體基材302的背側表面302B'的上方依序形成不同隔離材料的第一層 316A和第二層316B。第一層316A可係被形成是與深溝渠304B和半導體基材302的背側表面302B'共形的薄膜。第二層316B在第一層316A的上方形成且填充深溝渠304B。第一層316A可由例如氧化鉿、氧化鉭、氧化鋯、氧化鈦、氧化鋁、上述組合和/或相似的高介電常數材料形成。第二層316B可由例如氧化矽、氮化矽、氮氧化矽、碳化矽、上述組合和/或相似者形成。每一第一層316A和第二層316B可藉由利用例如高密度電漿化學氣相沉積製程、高深寬比製程、化學氣相沉積製程、選擇性區域化學氣相沉積製程、旋轉塗佈製程、濺鍍製程、上述組合，和/或其他合適的製程來形成。
接著，如圖3I所示，在半導體基材302的背側表面302B'的上方形成金屬格柵318，且接著在金屬格柵318和半導體基材302的背側表面302B'的上方形成介電層320。
詳細而言，如圖3I所示，在半導體基材302的隔離區302I中和在深溝渠隔離316上形成金屬格柵318。具體而言，在一些實施例中，金屬格柵318與深溝渠隔離316對準。在一些實施例中，金屬格柵318係被形成覆蓋深溝渠隔離316。金屬格柵318可由例如鋁、銅、鎢、鉭、鈦、上述組合和/或類似的金屬材料形成。金屬格柵318藉由進行沉積製程和圖案化製程來形成。沉積製程可包含物理氣相沉積(physical vapor deposition；PVD)製程、化學氣相沉積製程、低壓化學氣相沉積(low pressure CVD； LPCVD)製程、電漿輔助化學氣相沉積製程、高密度電漿化學氣相沉積製程、原子層沉積(atomic layer deposition；ALD)製程、旋轉塗佈製程、電鍍製程、濺鍍製程和/或其他合適的製程。圖案化製程可包含微影製程和蝕刻製程，例如反應式離子蝕刻或其他合適的製程。金屬格柵318的每一部分可具有矩形、梯形、倒梯形、三角形之剖面形狀或其他合適的形狀。金屬格柵318係被形成具有為約10奈米至約0.1微米的厚度T318。
介電層320被形成覆蓋金屬格柵318。介電層320可由氧化矽、氮化矽、氮氧化矽、低介電常數材料、旋塗玻璃和/或其他合適的介電材料形成。介電層320可藉由例如物理氣相沉積製程、化學氣相沉積製程、低壓化學氣相沉積製程、電漿輔助化學氣相沉積製程、高密度電漿化學氣相沉積製程、原子層沉積製程、旋轉塗佈製程、濺鍍製程和/或其他合適的沉積製程來形成。可在介電層320上再進行化學機械研磨製程，例如化學機械研磨製程，以平坦化介電層320。介電層320係被形成具有等於或大於金屬格柵318之厚度T318的厚度T320。在一些實施例中，介電層320可被形成具有多層介電層。
之後，如圖3J所示，在介電層320的上方形成彩色濾光層322，且在彩色濾光層322的上方形成微透鏡層324。彩色濾光層322係被形成已讓特定波長帶中的光成分通過並阻擋多餘的光成分。彩色濾光層322的通過波長帶可以是紅光波長帶、綠光波長帶、藍光波長帶或上述組合，但 不限於此。紅外光可通過彩色濾光層322且在半導體基材302中被吸收。彩色濾光層322可由例如顏料基聚合物、染料基聚合物、樹脂或其他合適的材料形成，且可藉由塗佈製程或其他合適的製程形成。微透鏡層324係被形成在其光吸收側具有凸面形狀，以提升光接收效率。微透鏡層324可由玻璃、丙烯酸聚合物或其他具有高透光率的合適材料形成，且可藉由旋轉塗佈製程、化學氣相沉積製程、物理氣相沉積製程和/或其他合適的製程形成。
依據一些實施例，影像感測裝置包含半導體基材、輻射感測元件、元件層和溝渠隔離。半導體基材具有前側表面和與前側表面相對的背側表面。輻射感測元件設置於半導體基材的光感測區中且從半導體基材的前側表面延伸出，此輻射感測元件包含半導體材料，此半導體材料具有小於1.77電子伏特的帶隙能量。元件層位於半導體基材的前側表面及輻射感測元件的上方。溝渠隔離設置於半導體基材的隔離區中且從半導體基材的背側表面延伸出。
在一些實施例中，半導體材料為鍺或矽鍺。
在一些實施例中，半導體材料為砷化鎵、磷化銦、銻化鎵、碲化鎘、砷化銦或銻化銦。
在一些實施例中，半導體基材包含矽。
在一些實施例中，半導體基材的厚度實質為1.5微米至8微米。
在一些實施例中，輻射感測元件的厚度實質大於100奈米。
在一些實施例中，影像感測裝置更包含金屬格柵和介電層。金屬格柵位於半導體基材的背側表面及溝渠隔離的上方。介電層位於位於半導體基材的背側表面及金屬格柵的上方。
在一些實施例中，溝渠隔離的寬度實質為0.1微米至0.5微米。
在一些實施例中，影像感測裝置更包含承載基材，此承載基材位於元件層的上方。
依據一些實施例，形成影像感測裝置的方法包含下列步驟。提供半導體基材，此半導體基材具有前側表面和與前側表面相對的背側表面。蝕刻半導體基材的光感測區，以形成凹陷。沉積半導體材料於半導體基材上並填充凹陷，以形成輻射感測元件，此半導體材料具有小於1.77電子伏特的帶隙能量。形成元件層於半導體基材的前側表面及輻射感測元件的上方。形成溝渠隔離於半導體基材的隔離區中，此溝渠隔離從半導體基材的背側表面延伸出。
在一些實施例中，半導體材料由鍺或矽鍺形成。
在一些實施例中，半導體材料由砷化鎵、磷化銦、銻化鎵、碲化鎘、砷化銦或銻化銦形成。
在一些實施例中，半導體基材由矽形成。
在一些實施例中，半導體材料藉由進行物理氣相沉積製程、原子層沉積製程或電漿輔助化學氣相沉積製程沉積在半導體基材上。
在一些實施例中，方法更包含薄化半導體基材，直到半導體基材的厚度達到1.5微米至8微米。
在一些實施例中，輻射感測元件形成為具有實質大於100奈米的厚度。
在一些實施例中，方法更包含對半導體材料進行化學機械研磨製程以去除半導體材料之位於半導體基材上方的部分。
在一些實施例中，方法更包含形成承載基材於元件層上。
依據一些實施例，形成影像感測裝置的方法包含下列步驟。提供半導體基材，此半導體基材具有前側表面和與前側表面相對的背側表面。蝕刻半導體基材的光感測區，以形成凹陷。沉積鍺材料於半導體基材上並填充凹陷，以形成輻射感測元件。對輻射感測元件進行退火製程。形成元件層於半導體基材的前側表面及輻射感測元件的上方。形成溝渠隔離於半導體基材的隔離區中，此溝渠隔離從半導體基材的背側表面延伸出。
前述說明摘要數個實施例的特徵，使得熟習此技藝者可以更了解本揭露的態樣。熟習此技藝者應知其可以輕易地利用本揭露作為基礎，以進行設計或修改其他製程及結構，用以達成相同目的，和/或達成與在此提出實施例的相同態樣。熟習此技藝者也應可理解，這些等效的結構並不脫離本揭露的精神與範圍，而且在不脫離本揭露的精神與範圍下，可以做各種變更，替代及潤飾。

Claims (1)

  1. 一種影像感測裝置，包含：一半導體基材，具有一前側表面和與該前側表面相對之一背側表面；一輻射感測元件，設置於該半導體基材之一光感測區中且從該半導體基材之該前側表面延伸出，其中該輻射感測元件包含一半導體材料，該半導體材料具有小於1.77電子伏特之一帶隙(band gap)能量；一元件層，位於該半導體基材之該前側表面及該輻射感測元件之上方；以及一溝渠隔離，設置於該半導體基材之一隔離區中且從該半導體基材之該背側表面延伸出。
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