TW201919186A - Bumpless fan-out chip stacking structure and method for fabricating the same - Google Patents

Bumpless fan-out chip stacking structure and method for fabricating the same Download PDF

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TW201919186A
TW201919186A TW106139198A TW106139198A TW201919186A TW 201919186 A TW201919186 A TW 201919186A TW 106139198 A TW106139198 A TW 106139198A TW 106139198 A TW106139198 A TW 106139198A TW 201919186 A TW201919186 A TW 201919186A
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layer
die
circuit redistribution
cover layer
dielectric layer
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TW106139198A
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TWI647808B (en
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陳士弘
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旺宏電子股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors

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Abstract

A bumpless fan-out chip stacking structure includes a first die disposed on the substrate, a first dielectric layer conformally covering on the first die, a first RDL disposed on the first dielectric layer, a first via plug electrically connecting the first die to the first RDL, a first capping layer conformally covering on the first RDL, a second die attached on the first capping layer, a second dielectric layer conformally covering on the second die, a second RDL disposed on the second dielectric layer, a second via plug electrically connecting the second die to the second RDL, a second capping layer conformally covering on the second RDL, a patterned conductive layer disposed on the second capping layer and an interlayer connection structure electrically connecting the patterned conductive layer to the first RDL and the second RDL respectively.

Description

無銲墊外扇晶粒堆疊結構及其製作方法Solder pad-free outer fan grain stacking structure and manufacturing method thereof

本揭露書是有關於一種立體封裝結構及其製作方法。特別是有關於一種無銲墊的外扇晶粒堆疊結構(bumpless fan-out chip stacking structure)及其製作方法。This disclosure is about a three-dimensional packaging structure and its manufacturing method. In particular, it relates to a bumpless fan-out chip stacking structure without solder pads and a manufacturing method thereof.

隨著電子產品追求攜帶方便、更多高數位訊號處理功能、更高儲存容量和靈活性的需求，有需要將不同功能的電路(例如，具有數位邏輯、記憶體、類比/射頻或其他等不同功能的電路)和被動元件(例如，電容、電阻、連接器和天線)整合形成一個多晶片模組(Multi-Chip Module，MCM)。特別是在移動式通訊電子系統上的應用上，由於需要低功率和小體積的單位元件，不允許將電路整合在印刷電路板上(PCB)。故而發展出系統單晶片(System-on-a-chip，SoC)和系統級封裝(System in Package，SIP)等立體封裝技術。As electronic products pursue the requirements of portability, more high-level digital signal processing functions, higher storage capacity and flexibility, there is a need for circuits with different functions (for example, with digital logic, memory, analog / RF or other, etc.) Functional circuits) and passive components (eg, capacitors, resistors, connectors, and antennas) are integrated to form a multi-chip module (MCM). Especially in the application of mobile communication electronic systems, due to the need for low power and small volume of unit components, it is not allowed to integrate the circuit on the printed circuit board (PCB). Therefore, three-dimensional packaging technologies such as system-on-a-chip (SoC) and system-in-package (SIP) have been developed.

系統單晶片技術是將一個完整的電腦系統(例如，包括中央處理器 (CPU)、記憶體、圖形處理器以及週邊電路等)整合入單一個晶片中。隨著半導體製程技術從微米(micrometer)邁進奈米(nanometer)的快速演進，雖然單一晶片內所能容納的元件數目將愈來愈多，但是有鑑於製程微縮技術的瓶頸以及異質(heterogeneous integration)整合困難度快速提高，使得系統單晶片的開發成本與時間快速攀升。System-on-a-chip technology integrates a complete computer system (for example, including central processing unit (CPU), memory, graphics processor, and peripheral circuits, etc.) into a single chip. With the rapid evolution of semiconductor process technology from micrometer to nanometer, although the number of components that can be accommodated in a single chip will be more and more, in view of the bottleneck and heterogeneous integration of process miniaturization technology The difficulty of integration is rapidly increasing, making the development cost and time of system-on-a-chip rapidly rising.

系統級封裝技術，是將多個由不同的製程、材料所製作的封裝晶片統合形成一個系統。雖然具有可微型化、異質整合(Heterogeneous)、降低系統成本、縮短產品上市時間，以及提升產品效能等優點。但由於個別封裝晶片的基材(substrate)之間是採用導線接合(wire bonding)或覆晶技術(flip chip)來作為互連結構(interconnection)。因此，當系統中堆疊的晶片數增加時，所需保留打線或銲墊空間將越多，不僅會造成封裝厚度和體積快速增加，不利於系統的微縮。此外，由於覆晶技術係使用熔融的銲錫凸塊來將堆疊層中的封裝晶片接合，當系統中堆疊的晶片數增加時，不僅需要較高的熱預算(thermal budget)，且位於堆疊底層的封裝晶片銲錫凸塊，會因為受到過多的熱應力，而造成溢流與毀損，進而導致系統失效。System-level packaging technology is the integration of multiple packaging chips made by different processes and materials to form a system. Although it has the advantages of miniaturization, heterogeneous integration (Heterogeneous), reducing system cost, shortening time to market, and improving product performance. However, since the substrates of individual packaged chips use wire bonding or flip chip technology as the interconnection structure. Therefore, when the number of stacked wafers in the system increases, the more wire bonding or pad space is required, which not only causes the package thickness and volume to increase rapidly, which is not conducive to system scaling. In addition, since flip chip technology uses molten solder bumps to join the packaged wafers in the stacked layer, when the number of stacked wafers in the system increases, not only a higher thermal budget (thermal budget) is required, but also the bottom layer of the stack Solder bumps on packaged chips are subject to excessive thermal stress, which can cause overflow and damage, which can lead to system failure.

因此，有需要提供一種先進的無銲墊外扇晶粒堆疊結構及其製作方法，來解決習知技術所面臨的問題。Therefore, there is a need to provide an advanced solderless pad outer fan die stacking structure and a manufacturing method thereof to solve the problems faced by the conventional technology.

本說明書的一實施例揭露一種無銲墊外扇晶粒堆疊結構，包括：基材、第一晶粒(die)、第一介電層、第一線路重佈層(Redistribution Layer， RDL)、第一插塞、第一覆蓋層、第二晶粒、第二介電層、第二線路重佈層、第二插塞、第二覆蓋層、圖案化導電層以及層間連接結構。第一晶粒位於基材上。第一介電層共形地(conformally)覆蓋於第一晶粒上，並與基材接觸。第一線路重佈層位於第一介電層上。第一插塞穿過第一介電層，以電性連接第一晶粒和第一線路重佈層。第一覆蓋層共形地覆蓋於第一線路重佈層上，並與第一介電層接觸。第二晶粒貼附於第一覆蓋層上。第二介電層共形地覆蓋於第二晶粒上，並與第一覆蓋層接觸。第二線路重佈層位於第二介電層上。第二插塞穿過第二介電層，以電性連接第二晶粒和第二線路重佈層。第二覆蓋層共形地覆蓋於第二線路重佈層上，並與第二介電層接觸。圖案化導電層位於第二覆蓋層上。層間連接結構分別將第一線路重佈層和第二線路重佈層連接至圖案化導電層。An embodiment of the present specification discloses a die-free structure of a pad-less outer fan die, including: a substrate, a first die, a first dielectric layer, a first circuit redistribution layer (RDL), The first plug, the first cover layer, the second die, the second dielectric layer, the second circuit redistribution layer, the second plug, the second cover layer, the patterned conductive layer, and the interlayer connection structure. The first die is located on the substrate. The first dielectric layer conformally covers the first die and contacts the substrate. The first circuit redistribution layer is located on the first dielectric layer. The first plug passes through the first dielectric layer to electrically connect the first die and the first circuit redistribution layer. The first cover layer conformally covers the first circuit redistribution layer and contacts the first dielectric layer. The second die is attached to the first cover layer. The second dielectric layer conformally covers the second die and contacts the first cover layer. The second circuit redistribution layer is located on the second dielectric layer. The second plug passes through the second dielectric layer to electrically connect the second die and the second circuit redistribution layer. The second cover layer conformally covers the second circuit redistribution layer and contacts the second dielectric layer. The patterned conductive layer is located on the second cover layer. The interlayer connection structure respectively connects the first circuit redistribution layer and the second circuit redistribution layer to the patterned conductive layer.

本說明書的另一實施例揭露一種無銲墊外扇晶粒堆疊結構的製作方法，包括下述步驟：首先，提供一基材，並將至少一個第一晶粒固定於基材上。形成第一介電層，共形地覆蓋第一晶粒，並與基材接觸；於第一介電層上形成第一線路重佈層；形成至少一個第一插塞，穿過第一介電層，以電性連接第一晶粒和第一線路重佈層。形成第一覆蓋層，共形地覆蓋第一線路重佈層，並與第一介電層接觸。接著，將至少一個第二晶粒貼附於第一覆蓋層上。形成第二介電層，共形地覆蓋第二晶粒，並與第一覆蓋層接觸；於第二介電層上形成第二線路重佈層；形成至少一個第二插塞，穿過第二介電層，以電性連接第二晶粒和第二線路重佈層；形成第二覆蓋層，共形地覆蓋第二線路重佈層，並與第二介電層接觸。後續，於第二覆蓋層上形成圖案化導電層，並藉由層間連接結構，分別將第一線路重佈層和第二線路重佈層連接至圖案化導電層。Another embodiment of the present specification discloses a method for manufacturing a die-stacked structure of a solderless outer fan die, which includes the following steps: first, a substrate is provided, and at least one first die is fixed on the substrate. Forming a first dielectric layer, conformally covering the first die, and in contact with the substrate; forming a first circuit redistribution layer on the first dielectric layer; forming at least one first plug through the first dielectric The electrical layer is electrically connected to the first die and the first circuit redistribution layer. A first covering layer is formed, conformally covering the first circuit redistribution layer, and in contact with the first dielectric layer. Next, at least one second die is attached to the first cover layer. Forming a second dielectric layer, conformally covering the second die, and in contact with the first cover layer; forming a second circuit redistribution layer on the second dielectric layer; forming at least one second plug, passing through the first The second dielectric layer electrically connects the second die and the second circuit redistribution layer; forms a second covering layer, conformally covers the second circuit redistribution layer, and contacts the second dielectric layer. Subsequently, a patterned conductive layer is formed on the second cover layer, and the first circuit redistribution layer and the second circuit redistribution layer are respectively connected to the patterned conductive layer through an interlayer connection structure.

根據上述實施例，本說明書是在提供一種無銲墊外扇晶粒堆疊結構及其製作方法。其係先將至少一顆良好裸晶(Know Good Die，KGD) 貼合固定於基材之上；並以介電層共形覆蓋良好裸晶；再於介電層上形成線路重佈層，藉由插塞將良好裸晶的信號輸入/輸出端與電路重佈層電性連接，且經由電路重佈層的連接線，將信號輸入/輸出的接腳位置外扇至到遠離良好裸晶的落著區(landing area)上；再以介電覆蓋層共形地覆蓋電路重佈層，形成一個由至少一個良好裸晶與一個電路重佈層所構成的互聯結構。接著，以介電覆蓋層為基材，並重複上述步驟，將複數個包括至少一個良好裸晶和一個電路重佈層互的聯結構，垂直堆疊於介電覆蓋層上。後續，再於晶粒堆疊的結構上形成圖案化導電層，並藉由穿過晶粒堆疊結構的層間連接結構，分別將各個線路重佈層的落著區連接至圖案化導電層，進而與外部電路連接。According to the above embodiment, this specification is to provide a solderless pad outer fan die stacking structure and a manufacturing method thereof. It first fixes and fixes at least one Know Good Die (KGD) on the substrate; and conformally covers the good die with the dielectric layer; and then forms a circuit redistribution layer on the dielectric layer, The signal input / output terminal of the good die is electrically connected to the circuit redistribution layer through a plug, and the pin position of the signal input / output is externally fanned away from the good die through the connection line of the circuit redistribution layer On the landing area; and then the dielectric redistribution layer conformally covers the circuit redistribution layer to form an interconnection structure composed of at least one good die and a circuit redistribution layer. Next, using the dielectric cover layer as a substrate and repeating the above steps, a plurality of interconnected structures including at least one good die and one circuit redistribution layer are vertically stacked on the dielectric cover layer. Subsequently, a patterned conductive layer is formed on the die stack structure, and the landing areas of each circuit redistribution layer are connected to the patterned conductive layer through the interlayer connection structure through the die stack structure External circuit connection.

由於，晶粒堆疊結構是以共形堆疊於基材上的介電層和覆蓋層，對良好裸晶進行直接封裝，不需要額外的基材來對良好裸晶進行預先封裝，可簡化封裝步驟，並且減少晶粒堆疊結構的封裝厚度和體積。另外，由於各個良好裸晶之間可藉由穿過晶粒堆疊結構的層間連接結構來彼此互聯，不需要預留打線或銲墊空間，可使晶粒堆疊結構容納數目更多的良好裸晶，大幅增加封裝密度。Since the die stacking structure is a dielectric layer and a cover layer conformally stacked on the substrate, the good die is directly packaged, and no additional substrate is needed to pre-package the good die, which can simplify the packaging step And reduce the package thickness and volume of the die stack structure. In addition, since each good die can be interconnected by an interlayer connection structure passing through the die stack structure, no wire bonding or pad space is required, and the die stack structure can accommodate a larger number of good die , Greatly increase the packaging density.

本說明書是提供一種無銲墊外扇晶粒堆疊結構及其製作方法，可簡化封裝步驟，並減少晶粒堆疊結構的封裝厚度和體積，大幅增加封裝密度。為了對本說明書之上述實施例及其他目的、特徵和優點能更明顯易懂，下文特舉一記憶體元件及其製作方法作為較佳實施例，並配合所附圖式作詳細說明。This specification is to provide a die-free pad-out die stacking structure and manufacturing method thereof, which can simplify packaging steps, reduce the package thickness and volume of the die-stacking structure, and greatly increase the packaging density. In order to make the above-mentioned embodiments of the specification and other objects, features and advantages more obvious and understandable, a memory element and its manufacturing method are specifically cited below as preferred embodiments, which will be described in detail in conjunction with the accompanying drawings.

但必須注意的是，這些特定的實施案例與方法，並非用以限定本發明。本發明仍可採用其他特徵、元件、方法及參數來加以實施。較佳實施例的提出，僅係用以例示本發明的技術特徵，並非用以限定本發明的申請專利範圍。該技術領域中具有通常知識者，將可根據以下說明書的描述，在不脫離本發明的精神範圍內，作均等的修飾與變化。在不同實施例與圖式之中，相同的元件，將以相同的元件符號加以表示。It must be noted that these specific implementation cases and methods are not intended to limit the present invention. The invention can still be implemented with other features, elements, methods and parameters. The proposal of the preferred embodiment is only used to illustrate the technical features of the present invention, and is not intended to limit the scope of patent application of the present invention. Those with ordinary knowledge in the technical field can make equal modifications and changes according to the description of the following description without departing from the spirit of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.

請參照第1A圖至第1J圖，第1A圖至第1J圖係根據本說明書的一實施例所繪示製作無銲墊外扇晶粒堆疊結構100的製程結構剖面示意圖。製作無銲墊外扇晶粒堆疊結構100的方法包括下述步驟：首先，提供一個基材101。在本說明書的一些實施例中，基材101可以是一種由介電材質，例如矽氧化物、氮化矽、塑化材料或其他合適的材料，所構成的基板或薄膜。例如在本實施例中，基材101可以是一種藉由旋塗(spin coating) 、沉積或直接貼覆的方式，在一承載基材(carrier substrate)10上形成的塑化薄膜，例如聚醯亞胺(polyimide，PI)薄膜。Please refer to FIG. 1A to FIG. 1J. FIG. 1A to FIG. 1J are schematic cross-sectional views of a manufacturing process for manufacturing a solderless pad outer fan die stack structure 100 according to an embodiment of the present specification. The method for manufacturing the solderless pad outer fan die stacking structure 100 includes the following steps: First, a substrate 101 is provided. In some embodiments of the present specification, the substrate 101 may be a substrate or a thin film composed of a dielectric material, such as silicon oxide, silicon nitride, plasticized material, or other suitable materials. For example, in this embodiment, the substrate 101 may be a plasticized film formed on a carrier substrate 10, such as polyacrylic acid, by spin coating, deposition, or direct lamination. Polyimide (PI) film.

另外，在本說明書的一些實施例中，在形成基材101之前，可以選擇性的在承載基材10上先形成一離形膜(release film) 103。在本實施例中，離形膜103可以是位於承載基材10與基材101之間的一種塑化薄膜(如第1A圖所繪示)。在本說明書的另一些實施例中，基材101之前，還可以選擇性的在離形膜103上形成一個介電薄膜123。在本實施例中，介電薄膜123可以是位於離形膜103與基材101之間的一種矽氧化物層。In addition, in some embodiments of the present specification, before the substrate 101 is formed, a release film 103 may be selectively formed on the carrier substrate 10. In this embodiment, the release film 103 may be a plasticized film (as shown in FIG. 1A) between the carrier substrate 10 and the substrate 101. In other embodiments of the present specification, before the substrate 101, a dielectric film 123 may be selectively formed on the release film 103. In this embodiment, the dielectric film 123 may be a silicon oxide layer between the release film 103 and the substrate 101.

接著，將至少一顆第一晶粒102固定於基材101上，並與基材101接觸。在本說明書的一些實施例中，第一晶粒102是一種經過驗證測試的良好裸晶；且第一晶粒102由正面(front side)起算至晶背(back side)102a的厚度，實質小於50微米(µm)。在本實施例中，第一晶粒102的厚度實質介於25微米至30微米之間。固定第一晶粒102的方式，可以包括將第一晶粒102的晶背102a朝下黏貼於基材101的表面101a，並將位於第一晶粒102前端的輸入/輸出(Input/Output，I/O )埠102b暴露於外(如第1B圖所繪示)。Next, at least one first die 102 is fixed on the substrate 101 and contacts the substrate 101. In some embodiments of the present specification, the first die 102 is a good bare crystal that has been verified and tested; and the thickness of the first die 102 from the front side to the back side 102a is substantially less than 50 microns (µm). In this embodiment, the thickness of the first die 102 is substantially between 25 microns and 30 microns. The method of fixing the first die 102 may include attaching the back 102a of the first die 102 downward to the surface 101a of the substrate 101, and input / output (Input / Output, located at the front end of the first die 102) I / O) port 102b is exposed (as shown in FIG. 1B).

之後，形成第一介電層104，共形地覆蓋第一晶粒102，並且與基材101的表面101a接觸(如第1C圖所繪示)。在本說明書的一些實施例中，構成第一介電層104的材料可以是任何一種介電材質。例如在本實施例中，第一介電層104可以是藉由沉積製程所形成的二氧化矽層；且第一介電層104的厚度實質上小於50 微米。但第一介電層104的材料、尺寸和製作方法並不以此為限。在其他實施例中，第一介電層104也可以是氮化矽、塑化材料或類似材料。形成第一介電層104的方式，可以包括在第一晶粒102和基材101的表面101a上的旋塗製程；或直接將介電材料貼布(tape)黏貼在第一晶粒102和基材101的表面101a。After that, a first dielectric layer 104 is formed, conformally covers the first die 102, and contacts the surface 101a of the substrate 101 (as shown in FIG. 1C). In some embodiments of the present specification, the material constituting the first dielectric layer 104 may be any dielectric material. For example, in this embodiment, the first dielectric layer 104 may be a silicon dioxide layer formed by a deposition process; and the thickness of the first dielectric layer 104 is substantially less than 50 microns. However, the material, size and manufacturing method of the first dielectric layer 104 are not limited thereto. In other embodiments, the first dielectric layer 104 may also be silicon nitride, plasticized material, or the like. The method of forming the first dielectric layer 104 may include a spin coating process on the first die 102 and the surface 101a of the substrate 101; or directly attaching a dielectric material tape to the first die 102 and The surface 101a of the base material 101.

然後，於第一介電層104上形成第一線路重佈層105；並且形成第一插塞106，穿過第一介電層104，以電性連接第一晶粒102和第一線路重佈層105(如第1D圖所繪示)。在本說明書的一些實施例中，第一線路重佈層105的形成，可以包括下述步驟：首先，藉由沉積製程在第一介電層104上形成一金屬層，例如銅或鋁金屬層。再以蝕刻製程圖案化金屬層，將一部分的第一介電層104暴露於外。其中，第一線路重佈層105包括至少一個連接部105a、至少一個落著區105b以及至少一條連接線(未繪示)，用來將落著區105b連接至連接部105a。Then, a first circuit redistribution layer 105 is formed on the first dielectric layer 104; and a first plug 106 is formed through the first dielectric layer 104 to electrically connect the first die 102 and the first circuit layer The cloth layer 105 (as shown in FIG. 1D). In some embodiments of the present specification, the formation of the first circuit redistribution layer 105 may include the following steps: First, a metal layer, such as a copper or aluminum metal layer, is formed on the first dielectric layer 104 by a deposition process . Then, the metal layer is patterned by an etching process to expose a portion of the first dielectric layer 104 to the outside. The first circuit redistribution layer 105 includes at least one connecting portion 105a, at least one landing area 105b, and at least one connecting line (not shown) for connecting the landing area 105b to the connecting portion 105a.

第一插塞106的形成方法包括下述步驟：在尚未形成第一線路重佈層105之前，先在第一介電層104中形成至少一個通孔107，對準第一晶粒102的信號輸入/輸出埠102b，並將第一晶粒102的信號輸入/輸出埠102b暴露於外。並在形成第一線路重佈層105的同時，以金屬材料填充通孔107，形成與第一線路重佈層105電性接觸的第一插塞106。在本實施例中，連接部105a和第一晶粒102的輸入/輸出埠102b，皆與第一插塞106縱向(沿著Z軸方向)重疊，並且彼此電性接觸。落著區105b橫向(沿著X軸方向)遠離第一晶粒102。換言之，第一晶粒102的輸入/輸出埠102b，可以藉由第一插塞106、連接部105a、連接線(未繪示)電性連接至落著區105b；且藉由第一線路重佈層105和第一插塞106所形成的互連結構，可以將第一晶粒102的信號輸入/輸出埠102b外扇至遠離第一晶粒102範圍的落著區105b上。在一實施例中，第一插塞106具有垂直Z軸，且實質為2微米的截面寬度。The forming method of the first plug 106 includes the following steps: before the first circuit redistribution layer 105 is formed, at least one through hole 107 is formed in the first dielectric layer 104 to align the signal of the first die 102 The input / output port 102b exposes the signal input / output port 102b of the first die 102 to the outside. At the same time when the first circuit redistribution layer 105 is formed, the through hole 107 is filled with a metal material to form a first plug 106 that is in electrical contact with the first circuit redistribution layer 105. In this embodiment, both the connecting portion 105a and the input / output port 102b of the first die 102 overlap with the first plug 106 in the longitudinal direction (along the Z-axis direction) and are in electrical contact with each other. The landing region 105b is laterally (along the X-axis direction) away from the first die 102. In other words, the input / output port 102b of the first die 102 can be electrically connected to the landing area 105b through the first plug 106, the connecting portion 105a, and the connecting wire (not shown); The interconnection structure formed by the cloth layer 105 and the first plug 106 can fan the signal input / output port 102b of the first die 102 to the landing area 105b away from the first die 102. In one embodiment, the first plug 106 has a vertical Z axis and a cross-sectional width of substantially 2 microns.

後續，形成第一覆蓋層108，共形地覆蓋第一線路重佈層105，並與被暴露於外的第一介電層104接觸(如第1E圖所繪示)。在本說明書的一些實施例中，構成第一覆蓋層108的材質與其製作方式，可以與製作第一介電層104的材質與方法相同或不同。Subsequently, a first cover layer 108 is formed, conformally covers the first circuit redistribution layer 105, and contacts the exposed first dielectric layer 104 (as shown in FIG. 1E). In some embodiments of the present specification, the material and manufacturing method of the first cover layer 108 may be the same as or different from the material and method of manufacturing the first dielectric layer 104.

接著，將至少一個第二晶粒109貼附於第一覆蓋層108上。在本說明書的一些實施例中，第二晶粒109也是一種經過驗證測試的良好裸晶；且第二晶粒109的厚度實質小於50微米。在本實施例中，第二晶粒109的厚度實質介於25微米至30微米之間。第二晶粒109的貼附方式，可以與固定第一晶粒102的方式相同，將第二晶粒109的晶背109a朝下黏貼於第一覆蓋層108，並將位於第二晶粒109前端的輸入/輸出埠109b暴露於外(如第1F圖所繪示)。Next, at least one second die 109 is attached to the first cover layer 108. In some embodiments of the present specification, the second die 109 is also a good bare crystal that has been verified and tested; and the thickness of the second die 109 is substantially less than 50 microns. In this embodiment, the thickness of the second die 109 is substantially between 25 microns and 30 microns. The second die 109 can be attached in the same way as the first die 102 is fixed. The second die 109 is pasted down on the first cover layer 108 with its back 109a facing down, and will be located on the second die 109 The front input / output port 109b is exposed (as shown in FIG. 1F).

再形成第二介電層110，共形地覆蓋第二晶粒109，並與第一覆蓋層108接觸；且於第二介電層110上形成第二線路重佈層111，同時形成穿過第二介電層110的第二插塞112，以電性連接第二晶粒109的輸入/輸出埠109b和第二線路重佈層111；再形成第二覆蓋層113，共形地覆蓋第二線路重佈層111，並與第二介電層110接觸。藉由第二線路重佈層111的連接部111a和連接線(未繪示)以及第二插塞112所形成的互連結構，可以將第二晶粒109的信號輸入/輸出埠109b垂直X-Z平面外扇至遠離第二晶粒109範圍的落著區111b上(未繪示於第1G圖中)。由於製作第二介電層110、第二線路重佈層111、第二插塞112和第二覆蓋層113的材料及方法，分別與前述製作第一介電層104、第一線路重佈層105、第一插塞106和第一覆蓋層108的材料及方法相同，故不再此贅述。A second dielectric layer 110 is formed, conformally covering the second die 109, and in contact with the first cover layer 108; and a second circuit redistribution layer 111 is formed on the second dielectric layer 110, while forming a through The second plug 112 of the second dielectric layer 110 is electrically connected to the input / output port 109b of the second die 109 and the second circuit redistribution layer 111; a second cover layer 113 is formed to cover the first The second circuit redistribution layer 111 is in contact with the second dielectric layer 110. By the interconnection structure formed by the connection portion 111a of the second circuit redistribution layer 111 and the connection line (not shown) and the second plug 112, the signal input / output port 109b of the second die 109 can be perpendicular to XZ The out-of-plane fan is located on the landing area 111b (not shown in FIG. 1G) away from the second die 109. Since the materials and methods for fabricating the second dielectric layer 110, the second circuit redistribution layer 111, the second plug 112, and the second cover layer 113 are the same as those described above for manufacturing the first dielectric layer 104 and the first circuit redistribution layer, respectively 105. The materials and methods of the first plug 106 and the first cover layer 108 are the same, so details are not described here.

後續，再重複前述步驟，於第二覆蓋層113上貼附第三晶粒114，並且於第二覆蓋層113上形成第三介電層115、第三線路重佈層116(至少包括連接部116a和落著區116b)、第三插塞117和第三覆蓋層118。在本說明書的一些實施例中，第一線路重佈層105的落著區105b並未與第一晶粒102、第二晶粒109、第三晶粒114、第二線路重佈層111以及第三線路重佈層116重疊；且第二線路重佈層111的落著區111b並未與第三晶粒114以及第三線路重佈層116重疊。Subsequently, repeat the foregoing steps to attach the third die 114 on the second cover layer 113, and form the third dielectric layer 115 and the third circuit redistribution layer 116 (including at least the connection portion) on the second cover layer 113 116a and the landing zone 116b), the third plug 117 and the third cover layer 118. In some embodiments of the present specification, the landing area 105b of the first circuit redistribution layer 105 is not in contact with the first die 102, the second die 109, the third die 114, the second circuit redistribution layer 111, and The third circuit redistribution layer 116 overlaps; and the landing area 111b of the second circuit redistribution layer 111 does not overlap the third die 114 and the third circuit redistribution layer 116.

但值得注意的是，第一線路重佈層105、第二線路重佈層111和第三線路重佈層116之落著區的安排並不以此為限。在本說明書的一些實施例中，第一線路重佈層105、第二線路重佈層111和第三線路重佈層116還可以包括其他的落著區；且一部份的落著區可以與位於其上方的線路重佈層重疊。例如，在本實施例中，第一線路重佈層105還可以包括落著區105c、105d和105e；第二線路重佈層111還可以包括落著區111c和111d；第三線路重佈層116還可以包括落著區116c和116d。其中，第一線路重佈層105的落著區105e，可以與第三線路重佈層116的落著區116c重疊(如第1H圖所繪示)。However, it is worth noting that the arrangement of the landing areas of the first circuit redistribution layer 105, the second circuit redistribution layer 111, and the third circuit redistribution layer 116 is not limited to this. In some embodiments of the present specification, the first circuit redistribution layer 105, the second circuit redistribution layer 111, and the third circuit redistribution layer 116 may also include other landing areas; and a part of the landing areas may be It overlaps with the redistribution layer above it. For example, in this embodiment, the first circuit redistribution layer 105 may also include landing areas 105c, 105d, and 105e; the second circuit redistribution layer 111 may also include landing areas 111c and 111d; and the third circuit redistribution layer 116 may also include landing zones 116c and 116d. The landing area 105e of the first circuit redistribution layer 105 may overlap the landing area 116c of the third circuit redistribution layer 116 (as shown in FIG. 1H).

後續，於第三覆蓋層118上形成圖案化導電層119，並藉由層間連接結構120，分別將第一線路重佈層105、第二線路重佈層111和第三線路重佈層116連接至圖案化導電層119。在本說明書的一些實施例中，圖案化導電層119和層間連接結構120的形成，包括下述步驟：Subsequently, a patterned conductive layer 119 is formed on the third cover layer 118, and the first circuit redistribution layer 105, the second circuit redistribution layer 111, and the third circuit redistribution layer 116 are respectively connected by the interlayer connection structure 120 To pattern the conductive layer 119. In some embodiments of the present specification, the formation of the patterned conductive layer 119 and the interlayer connection structure 120 includes the following steps:

首先，以蝕刻製程圖案化第三覆蓋層118，以於第三覆蓋層118中形成複數個開口121a-121f，由第三覆蓋層118的上表面延伸進入第三覆蓋層118中。再以至少一次蝕刻製程，分別於每一個開口121a-121f中形成至少一個貫穿孔122a-122j，穿過對應的第三覆蓋層118、第三線路重佈層116、第三介電層115、第二覆蓋層113、第二線路重佈層111、第二介電層110和第一覆蓋層108，藉以分別將第一線路重佈層105的落著區105b、105c和105d、第二線路重佈層111的落著區111b、111c和111b以及第三線路重佈層116的落著區116b、116c和116d暴露於外。First, the third capping layer 118 is patterned by an etching process to form a plurality of openings 121a-121f in the third capping layer 118, extending from the upper surface of the third capping layer 118 into the third capping layer 118. At least one etching process is performed to form at least one through hole 122a-122j in each opening 121a-121f, respectively, through the corresponding third cladding layer 118, third circuit redistribution layer 116, third dielectric layer 115, The second cover layer 113, the second circuit redistribution layer 111, the second dielectric layer 110, and the first cover layer 108, respectively The landing regions 111b, 111c, and 111b of the redistribution layer 111 and the landing regions 116b, 116c, and 116d of the third circuit redistribution layer 116 are exposed to the outside.

在本實施例中，貫穿孔122a係形成於開口121a之中，用來將第一線路重佈層105的落著區105b暴露於外；貫穿孔122b係形成於開口121b之中，用來將第二線路重佈層111的落著區111b暴露於；貫穿孔122c係形成於開口121c之中，用來將第三線路重佈層116的落著區116b暴露於外；貫穿孔122d和122e係形成於開口121d之中，分別用來將第一線路重佈層105的落著區105c和105f暴露於外；貫穿孔122f和122g係形成於開口121e之中，分別用來將第三線路重佈層116的落著區116c和第二線路重佈層111的落著區111c暴露於外；以及貫穿孔122h、122i和122j係形成於開口121f之中，分別用來將第一線路重佈層105的落著區105d、第二線路重佈層111的落著區111d和第三線路重佈層116的落著區116d暴露於外(如第1I圖所繪示)。In this embodiment, the through hole 122a is formed in the opening 121a to expose the landing area 105b of the first circuit redistribution layer 105; the through hole 122b is formed in the opening 121b to The landing area 111b of the second circuit redistribution layer 111 is exposed; the through hole 122c is formed in the opening 121c to expose the landing area 116b of the third circuit redistribution layer 116; the through holes 122d and 122e It is formed in the opening 121d and is used to expose the landing areas 105c and 105f of the first circuit redistribution layer 105 respectively; through holes 122f and 122g are formed in the opening 121e and are respectively used for the third circuit The landing region 116c of the redistribution layer 116 and the landing region 111c of the second circuit redistribution layer 111 are exposed to the outside; and the through holes 122h, 122i, and 122j are formed in the opening 121f, and are respectively used to reposition the first circuit The landing area 105d of the cloth layer 105, the landing area 111d of the second circuit redistribution layer 111, and the landing area 116d of the third circuit redistribution layer 116 are exposed to the outside (as shown in FIG. 1I).

在本說明書的一些實施例中，具有相同深度的貫穿孔，例如貫穿孔122a、122d和122e，可以藉由同一個蝕刻製程形成。例如在一實施例之中，具有相同深度的貫穿孔122d和122e，可以藉由單一個蝕刻製程形成於開口121d之中；貫穿孔122a則藉由相同的蝕刻製程，同時形成於開口121a之中。但在另一實施例中，貫穿孔122d和122e可以藉由不同的蝕刻製程先後形成於同一開口121d中。另外，具有不同深度的貫穿孔，例如貫穿孔122h、122i和122j，可以藉由同一個蝕刻製程形成於同一個開口121f之中。但在另一實施例中，這些貫穿孔122h、122i和122j，可以藉由不同的蝕刻製程，先後形成於同一開口121f中。In some embodiments of the present specification, through holes having the same depth, such as through holes 122a, 122d, and 122e, may be formed by the same etching process. For example, in one embodiment, the through holes 122d and 122e having the same depth can be formed in the opening 121d by a single etching process; the through hole 122a is formed in the opening 121a at the same time by the same etching process . However, in another embodiment, the through holes 122d and 122e may be formed in the same opening 121d successively by different etching processes. In addition, through holes having different depths, such as through holes 122h, 122i, and 122j, can be formed in the same opening 121f by the same etching process. However, in another embodiment, the through holes 122h, 122i, and 122j can be formed in the same opening 121f successively by different etching processes.

然後，以導電材料，例如銅、鋁、鎢或上述之組合，覆蓋第三覆蓋層118，並填充開口121a-121f和貫穿孔122a-122g。後續，以第三覆蓋層118為停止層，進行平坦化製程，例如化學機械研磨(Chemical-Mechanical Polishing，CMP)，移除一部份導電材料，形成圖案化導電層119和層間連接結構120；並且在一系列後段製程(未繪示)後，以紫外線照射或熱處理，使離形膜103變性以移除承載基材10，完成如第1J圖所繪示的無銲墊外扇晶粒堆疊結構100的製備。Then, the third cover layer 118 is covered with a conductive material, such as copper, aluminum, tungsten, or a combination thereof, and the openings 121a-121f and the through holes 122a-122g are filled. Subsequently, the third capping layer 118 is used as a stop layer to perform a planarization process, such as chemical-mechanical polishing (CMP), to remove a part of the conductive material, to form a patterned conductive layer 119 and an interlayer connection structure 120; And after a series of back-end processes (not shown), the release film 103 is denatured by ultraviolet irradiation or heat treatment to remove the carrier substrate 10 to complete the solderless pad outer fan die stacking as shown in FIG. 1J Preparation of structure 100.

在本實施例之中，圖案化導電層119可以包括，分別形成於開口121a-121f中的複數個導電部119a-119f。層間連接結構120可以包括，分別形成於貫穿孔122a-122j中的複數個層間接觸120a-120j。其中，層間接觸120a電性連接第一線路重佈層105的落著區105b和圖案化導電層119的導電部119a；層間接觸120b電性連接第二線路重佈層111的落著區111b和圖案化導電層119的導電部119b；層間接觸120c電性連接第三線路重佈層116的落著區116b和圖案化導電層119的導電部119c；層間接觸120d電性連接第一線路重佈層105的落著區105f和圖案化導電層119的導電部119d；層間接觸120e電性連接第一線路重佈層105的落著區105c和圖案化導電層119的導電部119d；層間接觸120f電性連接第三線路重佈層116的落著區116c和圖案化導電層119的導電部119e；層間接觸120g電性連接第二線路重佈層111的落著區111c和圖案化導電層119的導電部119e；層間接觸120h電性連接第三線路重佈層116的落著區116d和圖案化導電層119的導電部119f；層間接觸120i電性連接第二線路重佈層111的落著區111d和圖案化導電層119的導電部119f；以及層間接觸120j電性連接第一線路重佈層105的落著區105d和圖案化導電層119的導電部119f。In this embodiment, the patterned conductive layer 119 may include a plurality of conductive portions 119a-119f formed in the openings 121a-121f, respectively. The interlayer connection structure 120 may include a plurality of interlayer contacts 120a-120j formed in the through holes 122a-122j, respectively. The interlayer contact 120a electrically connects the landing area 105b of the first circuit redistribution layer 105 and the conductive portion 119a of the patterned conductive layer 119; the interlayer contact 120b electrically connects the landing area 111b of the second circuit redistribution layer 111 to The conductive portion 119b of the patterned conductive layer 119; the interlayer contact 120c electrically connects the landing area 116b of the third circuit redistribution layer 116 and the conductive portion 119c of the patterned conductive layer 119; the interlayer contact 120d electrically connects the first circuit redistribution The landing area 105f of the layer 105 and the conductive portion 119d of the patterned conductive layer 119; the interlayer contact 120e electrically connects the landing area 105c of the first circuit redistribution layer 105 and the conductive portion 119d of the patterned conductive layer 119; the interlayer contact 120f Electrically connect the landing area 116c of the third circuit redistribution layer 116 and the conductive portion 119e of the patterned conductive layer 119; the interlayer contact 120g electrically connects the landing area 111c of the second circuit redistribution layer 111 and the patterned conductive layer 119 Conductive part 119e; the interlayer contact 120h electrically connects the landing area 116d of the third circuit redistribution layer 116 and the conductive part 119f of the patterned conductive layer 119; the interlayer contact 120i electrically connects the landing of the second circuit redistribution layer 111 Conductivity of the region 111d and the patterned conductive layer 119 119f; and down with the conductive portion 105d and 119f area patterned conductive layer 119 in contact with the interlayer 120j is electrically connected to a first redistribution layer 105.

然而，圖案化導電層119和層間連接結構120的連接設計並不以此為限。在本說明書的其他實施例中，還可以藉由第一線路重佈層105、第二線路重佈層111和第三線路重佈層116不同的落著區，搭配不同的導電部119a-119f和層間接觸120a-120j的組合，來產生多種不同的互連結構，以提供第一晶粒102、第二晶粒109和第三晶粒114不同的佈線方式。However, the connection design of the patterned conductive layer 119 and the interlayer connection structure 120 is not limited to this. In other embodiments of the present specification, the first circuit redistribution layer 105, the second circuit redistribution layer 111, and the third circuit redistribution layer 116 can be combined with different conductive regions 119a-119f by different landing areas In combination with the interlayer contacts 120a-120j, a variety of different interconnect structures are created to provide different wiring methods for the first die 102, the second die 109, and the third die 114.

由於，無銲墊外扇晶粒堆疊結構100的製備，並不需要使用額外的基材來對良好裸晶進行預先封裝，即可將第一晶粒102、第二晶粒109和第三晶粒114縱向堆疊形成一個立體晶粒堆疊結構。且藉由圖案化導電層119和層間連接結構120來取代習知的導線接合或覆晶技術，以形成第一晶粒102、第二晶粒109和第三晶粒114之間的內連結構，可節省習知技術預留給代打線或銲墊的空間，用來容納更多的晶粒，大幅增加封裝密度。又因為，無銲墊外扇晶粒堆疊結構100並不採用銲錫凸塊來形成第一晶粒102、第二晶粒109和第三晶粒114的的內連結構，可降低製程的熱預算，並且可防止熱應力造成銲錫凸塊溢流而導致系統失效的問題。Due to the preparation of the padless outer die stacking structure 100, there is no need to use an additional substrate to pre-package a good bare crystal, the first die 102, the second die 109 and the third die The grains 114 are vertically stacked to form a three-dimensional grain stacking structure. And by patterning the conductive layer 119 and the interlayer connection structure 120 to replace the conventional wire bonding or flip chip technology, to form the interconnection structure between the first die 102, the second die 109 and the third die 114 It can save the space reserved for bonding wires or bonding pads by the conventional technology to accommodate more dies and greatly increase the packaging density. Also, because the pad-free die stack structure 100 does not use solder bumps to form the interconnect structure of the first die 102, the second die 109, and the third die 114, the thermal budget of the process can be reduced And, it can prevent the problem that the thermal stress causes the solder bump to overflow and cause the system to fail.

根據上述實施例，本說明書是在提供一種無銲墊外扇晶粒堆疊結構及其製作方法。其係先將至少一顆良好裸晶貼合固定於基材之上；並以介電層共形覆蓋良好裸晶；再於介電層上形成線路重佈層，藉由插塞將良好裸晶的信號輸入/輸出端與電路重佈層電性連接，且經由電路重佈層的連接線，將信號輸入/輸出的接腳位置外扇至到遠離良好裸晶的落著區上；再以介電覆蓋層共形地覆蓋電路重佈層，形成一個由至少一個良好裸晶與一個電路重佈層所構成的互聯結構。接著，以介電覆蓋層為基材，並重複上述步驟，將複數個包括至少一個良好裸晶和一個電路重佈層互的聯結構，垂直堆疊於介電覆蓋層上。後續，再於晶粒堆疊的結構上形成圖案化導電層，並藉由穿過晶粒堆疊結構的層間連接結構，分別將各個線路重佈層的落著區連接至圖案化導電層，進而與外部電路連接。According to the above embodiment, this specification is to provide a solderless pad outer fan die stacking structure and a manufacturing method thereof. It first fixes and fixes at least one good die on the substrate; and conformally covers the good die with the dielectric layer; then forms a circuit redistribution layer on the dielectric layer, and plugs the good die The signal input / output terminal of the crystal is electrically connected to the circuit redistribution layer, and the pin position of the signal input / output is fanned out to the landing area away from a good bare crystal through the connection line of the circuit redistribution layer; The dielectric redistribution layer conformally covers the circuit redistribution layer to form an interconnection structure composed of at least one good die and one circuit redistribution layer. Next, using the dielectric cover layer as a substrate and repeating the above steps, a plurality of interconnected structures including at least one good die and one circuit redistribution layer are vertically stacked on the dielectric cover layer. Subsequently, a patterned conductive layer is formed on the die stack structure, and the landing areas of each circuit redistribution layer are connected to the patterned conductive layer through the interlayer connection structure through the die stack structure, and then External circuit connection.

由於，晶粒堆疊結構是以共形堆疊於基材上的介電層和覆蓋層，對良好裸晶進行直接封裝，不需要額外的基材來對良好裸晶進行預先封裝，可簡化封裝步驟，並且減少晶粒堆疊結構的封裝厚度和體積。另外，由於各個良好裸晶之間可藉由穿過晶粒堆疊結構的層間連接結構來彼此互聯，不需要預留打線或銲墊空間，可使晶粒堆疊結構容納數目更多的良好裸晶，大幅增加封裝密度。Since the die stacking structure is a dielectric layer and a cover layer conformally stacked on the substrate, the good die is directly packaged, and no additional substrate is needed to pre-package the good die, which can simplify the packaging step And reduce the package thickness and volume of the die stack structure. In addition, since each good die can be interconnected by an interlayer connection structure passing through the die stack structure, no wire bonding or pad space is required, and the die stack structure can accommodate a larger number of good die , Greatly increase the packaging density.

雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何該技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in this technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application.

10‧‧‧承載基材10‧‧‧bearing base material

100‧‧‧無銲墊外扇晶粒堆疊結構100‧‧‧no pad external fan die stacking structure

101‧‧‧基材101‧‧‧ Base material

101a‧‧‧基材的表面101a‧‧‧Substrate surface

102‧‧‧第一晶粒102‧‧‧First grain

102a‧‧‧第一晶粒的晶背102a‧‧‧The back of the first grain

102b‧‧‧第一晶粒的輸入/輸出埠102b‧‧‧I / O port of the first die

103‧‧‧離形膜103‧‧‧release film

104‧‧‧第一介電層104‧‧‧First dielectric layer

105‧‧‧第一線路重佈層105‧‧‧ Redistribution layer of the first line

105a、111a、116a‧‧‧連接部105a, 111a, 116a ‧‧‧ connection

105b-105f、111b-111d、116b-116d‧‧‧落著區105b-105f, 111b-111d, 116b-116d

106‧‧‧第一插塞106‧‧‧ First plug

107‧‧‧通孔107‧‧‧through hole

108‧‧‧第一覆蓋層108‧‧‧First cover

109‧‧‧第二晶粒109‧‧‧Second grain

109a‧‧‧第一晶粒的晶背109a‧‧‧The back of the first grain

109b‧‧‧第一晶粒的輸入/輸出埠109b‧‧‧I / O port of the first die

110‧‧‧第二介電層110‧‧‧Second dielectric layer

111‧‧‧第二線路重佈層111‧‧‧ Redistribution layer of the second line

112‧‧‧第二插塞112‧‧‧Second plug

113‧‧‧第二覆蓋層113‧‧‧Second cover

114‧‧‧第三晶粒114‧‧‧ third grain

115‧‧‧第三介電層115‧‧‧third dielectric layer

116‧‧‧第三線路重佈層116‧‧‧ Redistribution layer of the third line

117‧‧‧第三插塞117‧‧‧ third plug

118‧‧‧第三覆蓋層118‧‧‧The third cover

119‧‧‧圖案化導電層119‧‧‧patterned conductive layer

119a-119f‧‧‧導電部119a-119f‧‧‧Conducting Department

120‧‧‧層間連接結構120‧‧‧Interlayer connection structure

120a-120j‧‧‧層間接觸120a-120j‧‧‧‧interlayer contact

121a-121f‧‧‧開口121a-121f‧‧‧ opening

122a-122j‧‧‧貫穿孔122a-122j‧‧‧Through hole

123‧‧‧介電薄膜123‧‧‧Dielectric film

為了對本說明書之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式詳細說明如下： 第1A圖至第1J圖係根據本說明書的一實施例所繪示製作無銲墊外扇晶粒堆疊結構的製程結構剖面示意圖。In order to have a better understanding of the above and other aspects of this specification, the following specific examples are given in conjunction with the attached drawings to explain in detail as follows: Figures 1A to 1J are produced according to an embodiment of this specification. A schematic cross-sectional view of the manufacturing structure of the die stacking structure of the outer fan of the pad.

無。no.

Claims (10)

一種無銲墊外扇晶粒堆疊結構，包括： 一基材； 一第一晶粒(die)，位於該基材上； 一第一介電層，共形地(conformally)覆蓋於該第一晶粒上，並與該基材接觸； 一第一線路重佈層(Redistribution Layer， RDL)位於該第一介電層上； 一第一插塞，穿過該第一介電層，以電性連接該第一晶粒和該第一線路重佈層； 一第一覆蓋層，共形地覆蓋於該第一線路重佈層上，並與該第一介電層接觸； 一第二晶粒，貼附於該第一覆蓋層上； 一第二介電層，共形地覆蓋於該第二晶粒上，並與該第一覆蓋層接觸； 一第二線路重佈層，位於該第二介電層上； 一第二插塞，穿過該第二介電層，以電性連接該第二晶粒和該第二線路重佈層； 一第二覆蓋層，共形地覆蓋於該第二線路重佈層上，並與該第二介電層接觸； 一圖案化導電層，位於該第二覆蓋層上；以及 一層間連接結構，分別將該第一線路重佈層和該第二線路重佈層連接至該圖案化導電層。A solder pad-free outer fan die stacking structure, including: a substrate; a first die on the substrate; a first dielectric layer conformally covering the first On the die, and in contact with the substrate; a first redistribution layer (RDL) is located on the first dielectric layer; a first plug passes through the first dielectric layer A first cover layer conformally covering the first circuit redistribution layer and in contact with the first dielectric layer; a second crystal Particles, attached to the first cover layer; a second dielectric layer conformally covers the second die and contacts the first cover layer; a second circuit redistribution layer is located on the On the second dielectric layer; a second plug passing through the second dielectric layer to electrically connect the second die and the second circuit redistribution layer; a second cover layer, conformally covering On the second circuit redistribution layer and in contact with the second dielectric layer; a patterned conductive layer on the second cover layer; and an interlayer connection structure, Do the first redistribution layer and the second redistribution layer is connected to the patterned conductive layer. 如申請專利範圍第1項所述之無銲墊外扇晶粒堆疊結構，其中該層間連接結構包括： 一第一層間接觸，穿過該第二覆蓋層、該第二介電層和該第一覆蓋層，將該圖案化導電層的一第一導電部與該第一線路重佈層的一第一落著區(landing area)電性連接；以及 一第二層間接觸，穿過該第二覆蓋層，將該圖案化導電層的一第二導電部與該第二線路重佈層的一第二落著區電性連接； 其中，該第一落著區未與該第二晶粒和該第二落著區重疊。The solderless pad outer fan die stacking structure as described in item 1 of the patent application scope, wherein the interlayer connection structure includes: a first interlayer contact, passing through the second cover layer, the second dielectric layer and the The first cover layer electrically connects a first conductive portion of the patterned conductive layer to a first landing area of the first circuit redistribution layer; and a second interlayer contact passes through the A second covering layer, electrically connecting a second conductive portion of the patterned conductive layer to a second landing area of the second circuit redistribution layer; wherein, the first landing area is not connected to the second crystal The grain and the second landing zone overlap. 如申請專利範圍第2項所述之無銲墊外扇晶粒堆疊結構，其中該層間連接結構更包括: 一第三層間接觸，穿過該第二覆蓋層、該第二介電層和該第一覆蓋層，將該圖案化導電層的一第三導電部與該第一線路重佈層的一第三落著區電性連接；以及 一第四層間接觸，穿過該第二覆蓋層、該第二介電層和該第一覆蓋層，將該第三導電部與該第一線路重佈層的一第四落著區電性連接；且該第一落著區、該第三落著區和該第四落著區彼此隔離。The solderless pad outer fan die stacking structure as described in item 2 of the patent application scope, wherein the interlayer connection structure further includes: a third interlayer contact, passing through the second cover layer, the second dielectric layer and the The first cover layer electrically connects a third conductive portion of the patterned conductive layer to a third landing area of the first circuit redistribution layer; and a fourth interlayer contact through the second cover layer , The second dielectric layer and the first cover layer, electrically connecting the third conductive portion to a fourth landing area of the first circuit redistribution layer; and the first landing area and the third The falling area and the fourth falling area are isolated from each other. 如申請專利範圍第2項所述之無銲墊外扇晶粒堆疊結構，其中該層間連接結構更包括: 一第三層間接觸，穿過該第二覆蓋層、該第二介電層和該第一覆蓋層，將該圖案化導電層的一第三導電部與該第一線路重佈層的一第三落著區電性連接；以及 一第四層間接觸，穿過該第二覆蓋層，將該第三導電部與該第二線路重佈層的一第四落著區電性連接。The solderless pad outer fan die stacking structure as described in item 2 of the patent application scope, wherein the interlayer connection structure further includes: a third interlayer contact, passing through the second cover layer, the second dielectric layer and the The first cover layer electrically connects a third conductive portion of the patterned conductive layer to a third landing area of the first circuit redistribution layer; and a fourth interlayer contact through the second cover layer , Electrically connecting the third conductive portion to a fourth landing area of the second circuit redistribution layer. 一種無銲墊外扇晶粒堆疊結構的製作方法，包括: 提供一基材； 將至少一第一晶粒固定於該基材上； 形成一第一介電層，共形地覆蓋該第一晶粒，並與該基材接觸； 於該第一介電層上形成一第一線路重佈層； 形成至少一第一插塞，穿過該第一介電層，以電性連接該第一晶粒和該第一線路重佈層； 形成一第一覆蓋層，共形地覆蓋該第一線路重佈層，並與該第一介電層接觸； 將至少一第二晶粒貼附於該第一覆蓋層上； 形成一第二介電層，共形地覆蓋該第二晶粒，並與該第一覆蓋層接觸； 於該第二介電層上形成一第二線路重佈層； 形成至少一第二插塞，穿過該第二介電層，以電性連接該第二晶粒和該第二線路重佈層； 形成一第二覆蓋層，共形地覆蓋該第二線路重佈層，並與該第二介電層接觸； 於該第二覆蓋層上形成一圖案化導電層；以及 形成一層間連接結構，分別將該第一線路重佈層和該第二線路重佈層連接至該圖案化導電層。A method for manufacturing a pad-less die structure for an outer fan, comprising: providing a substrate; fixing at least one first die on the substrate; forming a first dielectric layer to conformally cover the first Die and contact with the substrate; forming a first circuit redistribution layer on the first dielectric layer; forming at least a first plug through the first dielectric layer to electrically connect the first A die and the first circuit redistribution layer; forming a first cover layer, conformally covering the first circuit redistribution layer, and in contact with the first dielectric layer; attaching at least one second die On the first cover layer; forming a second dielectric layer, conformally covering the second die, and in contact with the first cover layer; forming a second circuit redistribution on the second dielectric layer Layer; forming at least a second plug, passing through the second dielectric layer, to electrically connect the second die and the second circuit redistribution layer; forming a second cover layer, conformally covering the first Two circuit redistribution layers, in contact with the second dielectric layer; forming a patterned conductive layer on the second cover layer; and forming a Between the connecting structure, the first redistribution layer and the second redistribution layer is connected to the patterned conductive layer, respectively. 如申請專利範圍第5項所述之無銲墊外扇晶粒堆疊結構的製作方法，其中提供該基材的步驟包括： 在一承載基材(carrier substrate)上形成一離形膜；以及 於該離形膜上形成一介電薄膜。The method for manufacturing a padless outer fan die stack structure as described in item 5 of the patent application scope, wherein the step of providing the substrate includes: forming a release film on a carrier substrate; and A dielectric thin film is formed on the release film. 如申請專利範圍第5項所述之無銲墊外扇晶粒堆疊結構的製作方法，其中形成該圖案化導電層和該層間連接結構的步驟，包括： 圖案化該第二覆蓋層，以於該第二覆蓋層中至少形成一第一開口和一第二開口； 於該第一開口中形成一第一貫穿孔，穿過該第二覆蓋層、該第二介電層和該第一覆蓋層，將該第一線路重佈層的一第一落著區暴露於外； 於該第二開口中形成一第二貫穿孔，穿過該第二覆蓋層，將該第二線路重佈層的一第二落著區暴露於外；以及 以一導電材料填充該第一開口、該第二開口、該第一貫穿孔和該第二貫穿孔。The method for manufacturing a pad-free die stack structure as described in item 5 of the patent application scope, wherein the step of forming the patterned conductive layer and the interlayer connection structure includes: patterning the second cover layer, so that At least a first opening and a second opening are formed in the second covering layer; a first through hole is formed in the first opening, passing through the second covering layer, the second dielectric layer and the first covering Layer, a first landing area of the first circuit redistribution layer is exposed to the outside; a second through hole is formed in the second opening, through the second cover layer, the second circuit redistribution layer A second landing area is exposed to the outside; and the first opening, the second opening, the first through hole and the second through hole are filled with a conductive material. 如申請專利範圍第7項所述之無銲墊外扇晶粒堆疊結構的製作方法，其中圖案化的該第二覆蓋層更包括一第三開口，形成該圖案化導電層和該層間連接結構的步驟，更包括： 於該第三開口中形成一第三貫穿孔及一第四貫穿孔，該第三貫穿孔穿過該第二覆蓋層、該第二介電層和該第一覆蓋層，將該第一線路重佈層的一第三落著區暴露於外，該第四貫穿孔穿過該第二覆蓋層、該第二介電層和該第一覆蓋層，將該第一線路重佈層的一第四落著區暴露於外；以及 以該導電材料填充該第三開口、該第三貫穿孔和該第四貫穿孔。The method for manufacturing a pad-free outer fan die stack structure as described in item 7 of the patent application scope, wherein the patterned second cover layer further includes a third opening to form the patterned conductive layer and the interlayer connection structure The step further includes: forming a third through hole and a fourth through hole in the third opening, the third through hole passing through the second cover layer, the second dielectric layer and the first cover layer , A third landing area of the first circuit redistribution layer is exposed to the outside, the fourth through hole passes through the second cover layer, the second dielectric layer and the first cover layer, the first A fourth landing area of the circuit redistribution layer is exposed to the outside; and the third opening, the third through hole and the fourth through hole are filled with the conductive material. 如申請專利範圍第7項所述之無銲墊外扇晶粒堆疊結構的製作方法，其中圖案化的該第二覆蓋層更包括一第三開口，形成該圖案化導電層和該層間連接結構的步驟，更包括： 於該第三開口中形成一第三貫穿孔及一第四貫穿孔，該第三貫穿孔穿過該第二覆蓋層、該第二介電層和該第一覆蓋層，將該第一線路重佈層的一第三落著區暴露於外，該第四貫穿孔穿過該第二覆蓋層，將該第二線路重佈層的一第四落著區暴露於外；以及 以該導電材料填充該第三開口、該第三貫穿孔和該第四貫穿孔。The method for manufacturing a pad-free outer fan die stack structure as described in item 7 of the patent application scope, wherein the patterned second cover layer further includes a third opening to form the patterned conductive layer and the interlayer connection structure The step further includes: forming a third through hole and a fourth through hole in the third opening, the third through hole passing through the second cover layer, the second dielectric layer and the first cover layer , A third landing area of the first circuit redistribution layer is exposed to the outside, the fourth through hole passes through the second cover layer, and a fourth landing area of the second circuit redistribution layer is exposed to Outside; and filling the third opening, the third through hole and the fourth through hole with the conductive material. 如申請專利範圍第7項所述之無銲墊外扇晶粒堆疊結構的製作方法，其中圖案化的該第二覆蓋層更包括一第三開口，形成該圖案化導電層和該層間連接結構的步驟，更包括： 於該第三開口中形成一第三貫穿孔，穿過該第二覆蓋層、該第二介電層和該第一覆蓋層，將該第一線路重佈層的一第三落著區暴露於外；以及 於該第三開口中形成一第四貫穿孔，穿過該第二覆蓋層，將該第二線路重佈層的一第四落著區暴露於外；以及 以該導電材料填充該第三開口、該第三貫穿孔和該第四貫穿孔。The method for manufacturing a pad-free outer fan die stack structure as described in item 7 of the patent application scope, wherein the patterned second cover layer further includes a third opening to form the patterned conductive layer and the interlayer connection structure The step further includes: forming a third through hole in the third opening, passing through the second cover layer, the second dielectric layer and the first cover layer, and redistributing one of the first circuit layers The third landing area is exposed to the outside; and a fourth through hole is formed in the third opening, passes through the second cover layer, and exposes a fourth landing area of the second circuit redistribution layer to the outside; And filling the third opening, the third through hole and the fourth through hole with the conductive material.
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US20170098629A1 (en) * 2015-10-05 2017-04-06 Mediatek Inc. Stacked fan-out package structure
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