TW201911438A - 整合扇出型封裝的製造方法 - Google Patents

整合扇出型封裝的製造方法 Download PDF

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Publication number
TW201911438A
TW201911438A TW107125984A TW107125984A TW201911438A TW 201911438 A TW201911438 A TW 201911438A TW 107125984 A TW107125984 A TW 107125984A TW 107125984 A TW107125984 A TW 107125984A TW 201911438 A TW201911438 A TW 201911438A
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Taiwan
Prior art keywords
conductive
layer
dielectric layer
vias
integrated circuit
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TW107125984A
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English (en)
Inventor
蔡惠榕
郭宏瑞
彭竣翔
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台灣積體電路製造股份有限公司
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Publication of TW201911438A publication Critical patent/TW201911438A/zh

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Abstract

提供一種整合扇出型封裝的製造方法。方法包含以下步驟。在基板上提供積體電路元件。在基板上形成絕緣密封體以密封積體電路元件的側壁。沿建構方向在積體電路元件和絕緣密封體上形成重佈線路結構。重佈線路結構的形成包含以下步驟。形成介電層和嵌入於介電層中的多個導通孔，其中導通孔中的每一個的橫向尺寸沿建構方向減小。在多個導通孔和介電層上形成多個導電佈線。

Description

整合扇出型封裝的製造方法
本公開是有關於一種封裝，且特別是有關於一種整合扇出型封裝的製造方法。
由於各種電子元件（即，電晶體、二極體、電阻器、電容器等）的集成密度的持續改進，半導體行業已經歷快速發展。在很大程度上，集成密度的這種改進來自最小特徵大小的重複減小，這允許將更多較小的元件集成到給定區域中。這些較小的電子元件也需要比先前封裝利用更少區域的較小封裝。用於半導體元件的一些較小類型的封裝包含方形扁平封裝（quad flat package；QFP）、針腳柵格陣列（pin grid array；PGA）封裝、球柵陣列（ball grid array；BGA）封裝，等等。
當前，整合扇出型封裝因其緊密性而變得越來越流行。由整合扇出型封裝所提供的改進的佈線能力和可靠性對於將來的封裝來說是關鍵因素。
本發明實施例的一種整合扇出型封裝的製造方法包括：在基板上提供積體電路元件；在所述基板上形成絕緣密封體以密封所述積體電路元件的側壁；沿建構方向在所述積體電路元件以及所述絕緣密封體上形成重佈線路結構，形成所述重佈線路結構包括：形成介電層以及嵌入於所述介電層中的多個導通孔，其中所述導通孔中的每一個的橫向尺寸沿所述建構方向減小；以及在所述多個導通孔以及所述介電層上形成多個導電佈線。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同實施例或實例。下文描述元件和佈置的特定實例以簡化本公開。當然，這些元件和佈置僅為實例且並不意圖為限制性的。舉例來說，在以下描述中，第一特徵形成在第二特徵上方或上可包含其中第一特徵與第二特徵直接接觸地形成的實施例，且還可包含其中額外特徵可形成在第一特徵與第二特徵之間以使得第一特徵與第二特徵可不直接接觸的實施例。另外，本公開可在各種實例中重複附圖標號和/或字母。這種重複是出於簡化和清楚的目的，且本身並不規定所論述的各種實施例和/或配置之間的關係。
另外，為了便於描述，在本文中可使用空間相對術語，如“在…之下”、“在…下方”、“下部”、“在…上方”、“上部”等，以描述如圖式中所說明的一個元件或特徵與另一（一些）元件或特徵的關係。除圖式中所描繪的定向以外，空間相對術語意欲涵蓋器件在使用或操作中的不同定向。裝置可以其它方式定向（旋轉90度或處於其它定向），且本文中所使用的空間相對描述詞同樣可相應地進行解釋。
還可包含其它特徵和過程。舉例來說，可包含測試結構以說明驗證測試3D封裝或3DIC器件。測試結構可包含例如形成於重佈線層中或基板上的測試墊，所述重佈線層或基板允許測試3D封裝或3DIC、使用探針和/或探針卡等等。驗證測試可在中間結構以及最終結構上執行。另外，本文中所公開的結構和方法可以與併入有已知良好晶粒的中間驗證的測試方法結合使用以增加產率並降低成本。
圖1到圖12說明根據一些實施例的用於製造整合扇出型封裝的過程流程。
參考圖1，提供一種包含佈置成陣列的多個晶粒或積體電路元件200的晶圓100。在對晶圓100執行晶圓切割製程之前，晶圓100的積體電路元件200彼此以物理方式連接。在一些實施例中，晶圓100包含半導體基板110、形成於半導體基板110上的多個導電墊120以及鈍化層130。鈍化層130形成於基板110上方且具有多個接觸開口132，使得導電墊120通過鈍化層130的接觸開口132部分地暴露。舉例來說，半導體基板110可以是包含形成於其中的主動元件（例如，電晶體或類似物）和被動元件（例如，電阻器、電容器、感應器或類似物）的矽基板；導電墊120可以是鋁墊、銅墊或其它合適的金屬墊；且鈍化層130可以是氧化矽層、氮化矽層、氮氧化矽層或由其它合適的介電材料形成的介電層。
如圖1中所繪示，在一些實施例中，晶圓100可任選地包含形成於鈍化層130上方的後鈍化層140。後鈍化層140覆蓋鈍化層130且具有多個接觸開口142。通過鈍化層130的接觸開口132部分地暴露的導電墊120通過後鈍化層140的接觸開口142部分地暴露。舉例來說，後鈍化層140可以是聚醯亞胺（polyimide；PI）層、聚苯並噁唑（polybenzoxazole；PBO）層、苯並環丁烯（benzocyclobutene；BCB）層或由其它合適的聚合物製成的介電層，或類似物。在一些實施例中，介電層由以下形成：氮化物，如氮化矽；氧化物，如氧化矽；磷矽酸鹽玻璃（phosphosilicate glass；PSG）；硼矽酸鹽玻璃（borosilicate glass；BSG）；硼摻雜磷矽酸鹽玻璃（boron-doped phosphosilicate glass；BPSG），或類似物。在某些實施例中，鈍化層130和後鈍化層140可由任何可接受的沉積製程形成，所述沉積製程如旋轉塗布、化學氣相沉積（chemical vapor deposition；CVD）、疊層或類似製程，或這些方法的組合。
參考圖2，多個導電柱150形成於晶圓100的導電墊120上。在一些實施例中，導電柱150通過導電材料的鍍覆製程形成於導電墊120上。下文詳細描述導電柱150的鍍覆製程。首先，將晶種層濺鍍到後鈍化層140和通過接觸開口142暴露的導電墊120上。接著通過光阻材料層的旋轉塗布、光阻材料層的烘烤以及微影（即曝光和顯影過程）來在晶種層上方形成具有預定圖案的圖案化光阻層（未繪示）。對應於導電墊120的晶種層的部分通過圖案化光阻層暴露。接著將包含形成於其上的圖案化光阻層的晶圓100浸入到鍍覆浴中的鍍覆液中，使得將導電柱150鍍覆在對應於導電墊120且通過圖案化光阻層顯露的晶種層的部分上。形成導電柱150之後，通過例如刻蝕、灰化或其它合適的去除方法剝離圖案化光阻層。此後，例如，通過使用導電柱150作為硬掩模，通過刻蝕來去除未由導電柱150覆蓋的晶種層的另一部分，直到暴露後鈍化層140。
在一些實施例中，導電柱150是鍍覆銅導柱（pillars）或其它合適的金屬導柱。在一些替代性實施例中，導電柱150是由焊料帽（例如，無鉛焊料帽）覆蓋的銅導柱或其它合適的金屬導柱。在某些實施例中，導電柱150的材料可包含銅、鎢、鋁、銀、金或類似物，或其組合。在一些實施例中，這些導電材料可通過電化學鍍覆製程、無電極鍍覆製程、化學氣相沉積（CVD）、原子層沉積（atomic layer deposition；ALD）、物理氣相沉積（physical vapor deposition；PVD）或類似製程或其組合形成。
參考圖3，在形成導電柱150之後，在晶圓100的後鈍化層140上形成保護層160使得導電柱150由保護層160覆蓋。在一些實施例中，保護層160可以是具有足以密封和保護導電柱150的厚度的聚合物層。在一些實施例中，保護層160可以是聚苯並噁唑（PBO）層、聚醯亞胺（PI）層、苯並環丁烯（BCB）層或由其它合適的聚合物製成的介電層，或類似者。在一些實施例中，介電層由以下形成：氮化物，如氮化矽；氧化物，如氧化矽；磷矽酸鹽玻璃（PSG）；硼矽酸鹽玻璃（BSG）；硼摻雜磷矽酸鹽玻璃（BPSG），或類似物。在某些實施例中，保護層160可由任何可接受的沉積製程形成，所述沉積製程如旋轉塗布、化學氣相沉積（CVD）、疊層或類似製程，或這些方法的組合。在一些替代性實施例中，保護層160可由無機材料製成。如圖3中所繪示，保護層160具有大體上平坦頂部表面，且保護層160的最大厚度大於導電柱150的高度。
參考圖4，在形成保護層160之後，可任選地對晶圓100的背表面執行背側研磨製程。在背側研磨製程期間，將半導體基板110部分地研磨以使得形成包含薄化半導體基板110'的薄化晶圓100'。在一些實施例中，可通過機械研磨或其它合適的研磨或拋光製程來研磨晶圓100的背表面。
參考圖5，在執行背側研磨製程之後，對薄化晶圓100'執行晶圓切割製程以使得薄化晶圓100'中的積體電路元件200彼此單一化。單一化的積體電路元件200中的每一個可包含半導體基板110a、形成於半導體基板110a上的導電墊120、鈍化層130a、後鈍化層140a、導電柱150以及保護層160a。如圖4和圖5中所繪示，半導體基板110a、鈍化層130a、後鈍化層140a以及保護層160a的材料和特徵與半導體基板100、鈍化層130、後鈍化層140以及保護層160的材料和特徵相同。因此，省略對半導體基板110a、鈍化層130a、後鈍化層140a以及保護層160a的詳細描述。
如圖4和圖5中所繪示，在背側研磨製程和晶圓切割製程期間，保護層160和保護層160a可以很好地保護積體電路元件200的導電柱150。另外，可保護積體電路元件200的導電柱150不受到依序執行的如積體電路元件200的拾取和放置製程、模制製程等的製程的破壞。
參考圖6，在積體電路200從薄化晶圓100'（圖4中所繪示）單一化之後，提供具有形成於其上的脫膠層DB和介電層DI的載體基板C，其中脫膠層DB在載體基板C與介電層DI之間。在一些實施例中，載體基板C可以是玻璃基板，脫膠層DB可以是形成於玻璃基板上的光熱轉換（light-to-heat conversion；LTHC）釋放層，且介電層DI可以是聚苯並噁唑（PBO）層、聚醯亞胺（PI）層、苯並環丁烯（BCB）層或形成於脫膠層DB上的其它類型的介電層。其它類型的介電層可包含：氮化物，如氮化矽；氧化物，如氧化矽；磷矽酸鹽玻璃（PSG）；硼矽酸鹽玻璃（BSG）；硼摻雜磷矽酸鹽玻璃（BPSG），或類似物。介電層DI可由任何可接受的沉積製程形成，所述沉積製程如旋轉塗布、化學氣相沉積（CVD）、疊層或類似製程，或這些方法的組合。
提供具有形成於其上的脫膠層DB和介電層DI的載體基板C之後，在介電層DI上形成多個導電穿孔TV。在一些實施例中，多個導電穿孔TV通過光阻材料層的旋轉塗布、光阻材料層的烘烤、微影（即曝光和顯影製程）、鍍覆（例如，電鍍或無電鍍覆）以及光阻剝離製程形成。舉例來說，導電穿孔TV包含銅柱（posts）或其它合適的金屬柱。
在一些實施例中，在形成導電穿孔TV之前，可在載體C所承載的介電層DI上形成背側重佈線路結構（未繪示），且導電穿孔TV可形成於背側重佈線路結構上且電連接到背側重佈線路結構。
如圖6所繪示，在一些實施例中，挑選包含形成於其上的導電墊120、導電柱150以及保護層160a的積體電路元件200中的一個並將其放置在載體基板C所承載的介電層DI上。積體電路元件200通過晶粒貼合膜（die attach film；DAF）、粘合膏或類似物貼合或粘合在介電層DI上。在一些替代性實施例中，挑選積體電路元件200中的兩個或大於兩個並將其放置在載體基板C所承載的介電層DI上，其中放置在介電層DI上的積體電路元件200可佈置成陣列。在一些實施例中，當放置在介電層DI上的積體電路元件200佈置成陣列時，導電穿孔TV可分成多個組。積體電路元件200的數目對應於導電穿孔TV的組的數目。
如圖6所繪示，在所說明的實施例中，保護層160a的頂部表面低於導電穿孔TV的頂部表面，且保護層160a的頂部表面高於導電柱150的頂部表面。然而，本公開不限於此。在一些替代性實施例中，保護層160a的頂部表面可與導電穿孔TV的頂部表面大體上對準。在又一些替代性實施例中，保護層160a的頂部表面可高於導電穿孔TV的頂部表面，且導電柱150的頂部表面可以低於導電穿孔TV的頂部表面、高於導電穿孔TV的頂部表面或與導電穿孔TV的頂部表面大體上對準。
如圖6所繪示，在形成導電穿孔TV之後，挑選積體電路元件200並將其放置在介電層DI上。然而，本公開不限於此。在一些替代性實施例中，在形成導電穿孔TV之前，挑選積體電路元件200並將其放置在介電層DI上。
參考圖7，絕緣材料210形成於介電層DI上以覆蓋積體電路元件200和導電穿孔TV。在一些實施例中，絕緣材料210是由模制製程形成的模制化合物。積體電路元件200的導電柱150和保護層160a由絕緣材料210覆蓋。換句話說，積體電路元件200的導電柱150和保護層160a不顯露且由絕緣材料210很好地保護。在一些實施例中，絕緣材料210包含環氧樹脂或其它合適的介電材料。
參考圖8，接著研磨絕緣材料210直到暴露導電柱150的頂部表面、導電穿孔TV的頂部表面以及保護層160a的頂部表面。在一些實施例中，絕緣材料210通過機械研磨製程和/或化學機械拋光（chemical mechanical polishing；CMP）製程來研磨。研磨絕緣材料210之後，在介電層DI上方形成絕緣密封體210'。在絕緣材料210的研磨製程期間，研磨保護層160a的部分以形成保護層160a'。在一些實施例中，在絕緣材料210和保護層160a的研磨製程期間，還略微研磨導電穿孔TV的部分和導電柱150的部分。
如圖8中所繪示，絕緣密封體210'橫向地密封積體電路元件200的側壁，且絕緣密封體210'由導電穿孔TV穿透。換句話說，積體電路200和導電穿孔TV嵌入於絕緣密封體210'中。應注意，導電穿孔TV的頂部表面、絕緣密封體210'的頂部表面以及導電柱150的頂部表面與保護層160a'的頂部表面大體上共面。
參考圖9，在形成絕緣密封體210'和保護層160a'之後，沿建構方向X1在積體電路元件200和絕緣密封體210'上形成重佈線路結構（圖10中的重佈線路結構300）。如圖9所繪示，在形成重佈線路結構的第一步驟中，形成介電層302和嵌入於介電層302中的多個導通孔304。接著在多個導通孔304和介電層302上形成多個導電佈線306，其中積體電路元件200可以或可以不通過導通孔304和導電佈線306連接到導電穿孔TV。一般來說，建構方向X1是指多個介電層302和多個重佈線導電層（導通孔304和導電佈線306）交替地堆疊的方向。舉例來說，在一些實施例中，介電層302和重佈線導電層（導通孔304和導電佈線306）沿垂直於載體基板C的方向（可稱作建構方向X1）交替地堆疊。在某些實施例中，在後續步驟中，沿建構方向X1在導電佈線306上方交替地形成導通孔304，且導通孔304允許電信號傳遞到上層。
此外，在一些實施例中，導通孔304中的每一個的橫向尺寸LD沿建構方向X1減小。舉例來說，導通孔304中的每一個具有第一表面S1（第一端E1）和與第一表面S1（第一端E1）相對的第二表面S2（第二端E2）。第一表面S1（第一端E1）具有大於第二表面S2（第二端E2）的面積，且第二表面S2（第二端E2）與多個導電佈線306接觸。在一些實施例中，第一表面S1（第一端E1）位於第二表面S2（第二端E2）與積體電路元件200之間。導通孔304中的每一個的橫向尺寸LD也從第一表面S1（第一端E1）減小到第二表面S2（第二端E2)。在一些示範性實施例中，導通孔304的第一表面S1（第一端E1）處的橫向尺寸LD在0.1 μm到10 μm的範圍內，且導通孔304的第二表面S2（第二端E2）處的橫向尺寸LD在0.1 μm到10 μm的範圍內。在某些實施例中，第一表面S1（第一端E1）面向載體基板C或面向積體電路元件200，然而第二表面S2（第二端E2）背離載體基板C或背離積體電路元件200。如圖9所繪示，導通孔304中的每一個具有錐形側壁SW，導通孔304的第一表面S1（第一端E1）通過錐形側壁SW與導通孔304的第二表面S2（第二端E2）結合。換句話說，通過具有錐形側壁SW，導通孔304可視為具有梯形形狀輪廓。
參考圖10，重佈線路結構300的形成可通過重複如圖9的實施例中所繪示及描述的介電層302、導通孔304以及導電佈線306的形成來完成。舉例來說，為了在建構方向X1上形成重佈線路結構300，可首先形成多個導通孔304，接著在形成導通孔304之後形成介電層302以覆蓋導通孔304。接著可使介電層304平面化以暴露導通孔304的頂部表面（第二表面S2）。接著形成導電佈線306以覆蓋導通孔304的暴露的頂部表面（第二表面S2），且部分地覆蓋介電層302。通過交替地重複上述步驟，完成重佈線路結構300的形成。
如圖10所繪示，在一些實施例中，導通孔304中的每一個嵌入於介電層302中，且所有導通孔304滿足導通孔304的橫向尺寸LD從第一表面S1（第一端E1）減小到第二表面S2（第二端E2）的條件。然而，本公開不限於此。舉例來說，在替代性實施例中，僅重佈線路結構300中的導通孔304中的一些具有滿足上述條件的錐形側壁SW，而其它導通孔304可具有豎直側壁。在替代性實施例中，在具有介電層302和重佈線導電層（導通孔304和導電佈線306）的三個堆疊層的重佈線路結構300中，僅第一堆疊層（最底層）中的導通孔304採用錐形側壁SW，而第二堆疊層或第三堆疊層中的導通孔304具有豎直側壁。此外，在圖10中所繪示的實施例中，雖然在重佈線路結構300中僅展示了介電層302和重佈線導電層（導通孔304和導電佈線306）的三個堆疊層，然而，本公開不限於此。在其它實施例中，重佈線路結構300基於要求可具有介電層302和重佈線導電層（導通孔304和導電佈線306）的三個或大於三個堆疊層。
參考圖11，在形成介電層302和重佈線導電層（導通孔304和導電佈線306）的堆疊層之後，可形成用於球座的多個球下金屬（under-ball metallurgy；UBM）圖案410a和/或用於安裝被動元件的至少一個連接墊410b。在本公開中，未限制球下金屬圖案410a和連接墊410b的數目。如圖11中所繪示，多個導電球420放置在球下金屬圖案410a上，且一或多個被動元件430安裝在連接墊410b上。在一些實施例中，可通過球體放置製程來將導電球420放置在球下金屬圖案410a上，且可通過焊接製程將被動元件430安裝在連接墊410b上。
參考圖12，在將導電球420和被動元件430安裝在重佈線路結構300上之後，將在絕緣密封體210'的表面上形成的介電層DI從脫膠層DB剝離以使得介電層DI與載體基板C分離。在一些實施例中，可通過UV鐳射照射脫膠層DB（例如，LTHC釋放層），使得介電層DI從載體基板C剝落。如圖12中所繪示，接著圖案化介電層DI以使得形成多個接觸開口從而暴露導電穿孔TV的底部表面。接觸開口的數目對應於導電穿孔TV的數目。在介電層DI中形成接觸開口之後，將多個導電球440放置在通過接觸開口暴露的導電穿孔TV的底部表面上。舉例來說，回焊導電球440以與導電穿孔TV的底部表面粘合。如圖12中所繪示，在形成導電球420和導電球440之後，完成具有雙側端子的積體電路元件200的整合扇出型封裝。
圖13到圖16說明根據一些其它實施例的用於製造整合扇出型封裝的過程流程。與圖1到圖12中所繪示的實施例相比，圖13到圖16中所繪示的實施例之間的差異在於：在形成/放置積體電路元件200之前，在載體基板C上製造重佈線路結構300。
參考圖13，在一些實施例中，沿建構方向Y1在載體基板C上形成重佈線路結構（圖14中的重佈線路結構300）。類似於圖6中所繪示的實施例，圖13中的載體基板C可具有形成於其上的脫膠層DB和介電層DI。關於載體基板C、脫膠層DB以及介電層DI的說明可參考圖6中所繪示的實施例，且將省略具體的論述。如圖13中所繪示，在形成重佈線路結構300的第一步驟中，在載體基板C上形成多個導電佈線306。接著形成覆蓋導電佈線306的多個導通孔304和介電層302。
類似於圖9的實施例中所描述的導通孔304，圖13中所繪示的導通孔304中的每一個的橫向尺寸LD沿建構方向Y1從第一端E1（第一表面S1）減小到第二端E2（第二表面S2）。建構方向Y1的定義類似於建構方向X1的定義，所述建構方向X1是指多個介電層302和多個重佈線導電層（導通孔304和導電佈線306）交替堆疊的方向。在圖13中所繪示的實施例中，第一端E1（第一表面S1）面向載體基板C且第二端E2（第二表面S2）面向積體電路元件200（在後續步驟中提供），且第二端E2（第二表面S2）位於積體電路元件200（在後續步驟中提供）與第一端E1（第一表面S1）之間。在一些示範性實施例中，導通孔304的第一表面S1（第一端E1）處的橫向尺寸LD在0.1 μm到10 μm的範圍內，且導通孔的第二表面S2（第二端E2）處的橫向尺寸LD在0.1 μm到10 μm的範圍內。然而，本公開不限於此。如圖13中所繪示，導通孔304中的每一個具有錐形側壁SW，導通孔304的第一端E1（第一表面S1）通過錐形側壁SW與導通孔304的第二端E2（第二表面S2）結合。換句話說，通過具有錐形側壁SW，導通孔304可視為具有梯形形狀輪廓。
參考圖14，重佈線路結構300的形成可通過重複如圖13的實施例中所繪示及描述的介電層302、導通孔304以及導電佈線306的形成來完成。舉例來說，在一些實施例中，為了在建構方向Y1上形成重佈線路結構300，可首先在載體基板C上形成多個導電佈線306。隨後，可接著在多個導電佈線306上形成介電層302的第一部分（未繪示）。可使介電層302的第一部分平面化以暴露導電佈線306的頂部表面。接著在導電佈線306的頂部表面上形成多個導通孔304，以使得導通孔304的第一端E1（第一表面S1）與導電佈線306的頂部表面接觸。隨後，可在導通孔304上形成介電層302的第二部分（未繪示）以覆蓋導通孔304，且接著可使介電層302的第二部分平面化以暴露導通孔304的第二端E2（第二表面S2）。通過交替重複以上步驟，完成圖14中所繪示的重佈線路結構300的形成。
可替代地，可通過使用另一方法完成圖14中所繪示的重佈線路結構300的形成。舉例來說，在某些實施例中，為了在建構方向Y1上形成重佈線路結構300，可首先在載體基板C上形成多個導電佈線306。接著，可在導電佈線306上形成多個導通孔304。隨後，可在導電佈線306和導通孔304兩者上形成介電層304，以覆蓋導電佈線306和導通孔304，其中使介電層304平面化以暴露導通孔304的第二端E2（第二表面S2）。通過交替重複以上步驟，完成圖14中所繪示的重佈線路結構300的形成。
如圖14所繪示，導通孔304的第一端E1（第一表面S1）與導電佈線306之間的接觸表面CS1（介面）大於導通孔304的第二端E2（第二表面S2）與另一導電特徵（導電佈線306或隨後形成的導電凸塊310）之間的接觸表面CS2（介面）。此外，在一些實施例中，導通孔304中的每一個嵌入於介電層302中，且所有導通孔滿足導通孔304的橫向尺寸LD從第一端E1（第一表面S1）減小到第二端部E2（第二表面E2）的條件。然而，本公開不限於此。舉例來說，在替代性實施例中，僅重佈線路結構300中的導通孔304中的一些具有滿足上述條件的錐形側壁SW，而其它導通孔304可具有豎直側壁。此外，在圖14中繪示的實施例中，雖然在重佈線路結構300中僅展示了介電層302和重佈線導電層（導通孔304和導電佈線306）的三個堆疊層，然而，本公開不限於此。在其它實施例中，重佈線路結構300基於要求可具有介電層302和重佈線導電層（導通孔304和導電佈線306）的三個或大於三個堆疊層。
參考圖15，在形成重佈線路結構300之後，可在重佈線路結構300上形成多個導電凸塊310，其中導電凸塊310電連接到多個導通孔304。舉例來說，導電凸塊310與導通孔304的第二端E2（第二表面S2）接觸。隨後，可提供具有多個導電柱150的積體電路元件200且將其用於粘合到重佈線路結構300。圖15的積體電路元件200類似於圖5中所描述的積體電路元件200，但不具有保護層160a'。因此，圖15中的積體電路元件200的詳細描述可參考上述實施例，且將在本文中省略。
如圖15中所繪示，在一些實施例中，焊料帽510可形成于重佈線路結構300側上的導電凸塊310上，以使得導電凸塊310通過焊料帽510粘合到導電柱150。然而，本公開不限於此。在替代性實施例中，焊料帽510可形成於積體電路元件200側上的導電柱150上，以使得導電凸塊310通過焊料帽510粘合到導電柱150。
參考圖16，在將導電凸塊310粘合到導電柱150之後，在重佈線路結構300與積體電路元件200之間形成絕緣密封體210'以便密封導電凸塊310和導電柱150。絕緣密封體210'可由類似於圖7的絕緣材料210的材料製成，因此在本文中省略其描述。實施例的整合扇出型封裝可通過圖12中所繪示的相似方法實現。舉例來說，重佈線路結構300可從脫膠層DB剝離以使得介電層DI與載體基板C分離。隨後，可圖案化介電層以形成接觸開口，其中導電球可放置在接觸開口中且電連接到重佈線路結構300。
在上文所提到的實施例中，由整合扇出型封裝提供的佈線能力、電效率以及可靠性通過使用具有錐形側壁SW的導通孔304來改進。與傳統結構相比，具有梯形形狀輪廓的導通孔304將具有較低應力和較大微影製程窗口。
根據本公開的一些實施例，提供一種整合扇出型封裝的製造方法。所述方法包含以下步驟。在基板上提供積體電路元件。在基板上形成絕緣密封體以密封積體電路元件的側壁。沿建構方向在積體電路元件和絕緣密封體上形成重佈線路結構。重佈線路結構的形成包含以下步驟。形成介電層和嵌入於介電層中的多個導通孔，其中導通孔中的每一個的橫向尺寸沿建構方向減小。在多個導通孔和介電層上形成多個導電佈線。
在一些實施例中，所述導通孔中的每一個具有第一表面以及與所述第一表面相對的第二表面，所述第一表面具有大於所述第二表面的面積，且所述第二表面與所述多個導電佈線接觸。在一些實施例中，所述導通孔中的每一個的所述橫向尺寸從所述第一表面減小到所述第二表面。在一些實施例中，所述導通孔中的每一個具有錐形側壁，所述導通孔的所述第一表面通過所述錐形側壁與所述導通孔的所述第二表面結合。在一些實施例中，沿所述建構方向形成所述重佈線路結構包括交替地進行以下步驟：形成所述多個導通孔；在形成所述多個導通孔之後，形成所述介電層；使所述介電層平面化以暴露所述多個導通孔的頂部表面；以及形成所述多個導電佈線以覆蓋所述多個導通孔的暴露的頂部表面，且部分地覆蓋所述介電層。在一些實施例中，所述的整合扇出型封裝的製造方法，進一步包括：形成穿過所述絕緣密封體的多個導電穿孔，其中所述多個導電穿孔電連接到所述多個導通孔。
根據本公開的替代性實施例，提供一種整合扇出型封裝的製造方法。所述方法包含以下步驟。沿建構方向在基板上形成重佈線路結構。重佈線路結構的形成包含以下步驟。在基板上形成多個導電佈線。形成多個導通孔和介電層以覆蓋多個導電佈線，且導通孔中的每一個的橫向尺寸沿建構方向從第一端減小到第二端。第一端面向基板，且第二端與背離基板的第一端相對。接著，在電連接到多個導通孔的重佈線路結構上形成多個導電凸塊。接著提供具有多個導電柱的積體電路元件。將導電凸塊粘合到導電柱。在重佈線路結構與積體電路元件之間形成絕緣密封體以密封導電凸塊和導電柱。
在一些實施例中，所述重佈線路結構的形成包括交替地進行以下步驟：在所述基板上形成所述多個導電佈線；在所述多個導電佈線上形成所述介電層的第一部分；使所述介電層的所述第一部分平面化以暴露所述多個導電佈線的頂部表面；在所述多個導電佈線的所述頂部表面上形成所述多個導通孔；在所述多個導通孔上形成所述介電層的第二部分；以及使所述介電層的所述第二部分平面化以暴露所述多個導通孔的所述第二端。在一些實施例中，所述重佈線路結構的形成包括交替地進行以下步驟：在所述基板上形成所述多個導電佈線；在所述多個導電佈線上形成所述多個導通孔；以及在所述多個導電佈線以及所述多個導通孔兩者上形成所述介電層；使所述介電層平面化以暴露所述多個導通孔的所述第二端。在一些實施例中，所述導通孔形成為具有錐形側壁，且所述導通孔的所述第一端通過所述錐形側壁與所述導通孔的所述第二端結合。在一些實施例中，所述第一端面向所述基板且所述第二端面向所述積體電路元件，且所述第二端位於所述積體電路元件與所述第一端之間。在一些實施例中，所述導通孔的所述第一端與所述導電佈線之間的接觸表面大於所述導通孔的所述第二端與另一導電特徵之間的接觸表面。在一些實施例中，所述的整合扇出型封裝的製造方法，進一步包括：在所述導電凸塊上形成焊料帽，接著通過所述焊料帽將所述導電凸塊粘合到所述導電柱。在一些實施例中，所述的製造整合扇出型封裝的方法，進一步包括：在所述導電柱上形成焊料帽，接著通過所述焊料帽將所述導電凸塊粘合到所述導電柱。
根據本公開的又一替代性實施例，提供包含積體電路元件、絕緣密封體、重佈線路結構的整合扇出型封裝。絕緣密封體橫向地密封積體電路元件的側壁。重佈線路結構包含嵌入於介電層中的多個導通孔以及多個導電佈線。導通孔中的每一個的橫向尺寸從第一端減小到第二端，第一端位於第二端與積體電路元件之間。多個導電佈線設置在多個導通孔和介電層上。
在一些實施例中，所述導通孔中的每一個具有錐形側壁，且所述導通孔的所述第一端通過所述錐形側壁與所述導通孔的所述第二端結合。在一些實施例中，所述第一端與所述第二端相對，且所述第一端具有大於所述第二端的表面積，且所述第二端與所述多個導電佈線接觸。在一些實施例中，所述第一端面向所述積體電路元件且所述第二端背離所述積體電路元件。在一些實施例中，所述導通孔的所述第一端處的所述橫向尺寸在0.1 μm到10 μm的範圍內，且所述導通孔的所述第二端處的所述橫向尺寸在0.1 μm到10 μm的範圍內。一些實施例中，所述的整合扇出型封裝，進一步包括：多個導電穿孔，其中所述導電穿孔穿過所述絕緣密封體，且所述導電穿孔電連接到所述導通孔，且與所述導通孔的所述第一端接觸。
前文概述若干實施例的特徵以使得本領域的技術人員可更好地理解本公開的各方面。本領域的技術人員應瞭解，其可易於使用本公開作為設計或修改用於進行本文中所引入的實施例的相同目的和/或獲得相同優勢的其它過程和結構的基礎。本領域的技術人員還應認識到，這些等效構造並不脫離本公開的精神和範圍，且本領域的技術人員可在不脫離本公開的精神和範圍的情況下在本文中進行各種改變、替代和更改。
100‧‧‧晶圓
100'‧‧‧薄化晶圓
110、110a‧‧‧半導體基板
110'‧‧‧薄化半導體基板
120‧‧‧導電墊
130、130a‧‧‧鈍化層
132、142‧‧‧接觸開口
140、140a‧‧‧後鈍化層
150‧‧‧導電柱
160、160a、160a'‧‧‧保護層
200‧‧‧晶粒/積體電路元件
210‧‧‧絕緣材料
210'‧‧‧絕緣密封體
300‧‧‧重佈線路結構
302、DI‧‧‧介電層
304‧‧‧導通孔
306‧‧‧導電佈線
310‧‧‧導電凸塊
410a‧‧‧球下金屬圖案
410b‧‧‧連接墊
420、440‧‧‧導電球
430‧‧‧被動元件
510‧‧‧焊料帽
C‧‧‧載體基板
CS1、CS2‧‧‧接觸表面
DB‧‧‧脫膠層
E1‧‧‧第一端
E2‧‧‧第二端
LD‧‧‧橫向尺寸
S1‧‧‧第一表面
S2‧‧‧第二表面
SW‧‧‧錐形側壁
TV‧‧‧導電穿孔
X1、Y1‧‧‧建構方向
當結合圖式閱讀時，根據以下詳細描述最好地理解本公開的各方面。應注意，根據行業中的標準慣例，各種特徵未按比例繪製。實際上，為了論述清楚起見，可以任意地增大或減小各種特徵的尺寸。 圖1到圖12說明根據一些實施例的用於製造整合扇出型封裝的過程流程。 圖13到圖16說明根據一些其它實施例的用於製造整合扇出型封裝的過程流程。

Claims (1)

  1. 一種整合扇出型封裝的製造方法，包括： 在基板上提供積體電路元件； 在所述基板上形成絕緣密封體以密封所述積體電路元件的側壁； 沿建構方向在所述積體電路元件以及所述絕緣密封體上形成重佈線路結構，形成所述重佈線路結構包括： 形成介電層以及嵌入於所述介電層中的多個導通孔，其中所述導通孔中的每一個的橫向尺寸沿所述建構方向減小；以及 在所述多個導通孔以及所述介電層上形成多個導電佈線。
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