TW201906163A - Multi-gate high electron mobility transistor with aligned internal gate and negative capacitance ferroelectric dielectrics and manufacturing method thereof - Google Patents
Multi-gate high electron mobility transistor with aligned internal gate and negative capacitance ferroelectric dielectrics and manufacturing method thereof Download PDFInfo
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本發明係與高電子遷移率場效電晶體(High Electron Mobility Transistor,HEMT)有關，特別是關於一種採用對準式背向閘極及負電容鐵電介電質之多閘極高電子遷移率場效電晶體及其製造方法。 The present invention relates to a High Electron Mobility Transistor (HEMT), and more particularly to a multi-gate high electron mobility using an aligned back gate and a negative capacitance ferroelectric dielectric. Field effect transistor and its manufacturing method.
一般而言，由於氮化鎵(GaN)高電子遷移率場效電晶體(HEMT)屬於常導通型元件，故其耗電量會較常關閉型元件來得更大。 In general, since gallium nitride (GaN) high electron mobility field effect transistors (HEMTs) are normally-on components, their power consumption is greater than that of normally-off components.
為了改善此一缺點，現今技術均期望能將其設計為增強型元件。然而，一般的氮化鎵高電子遷移率場效電晶體通常僅具有單一個金屬閘極，而其氮化鋁鎵(AlGaN)/氮化鎵(GaN)異質介面具有二維的電子通道，由於單一個金屬閘極之控制能力不足，難以有效控制此一異質介面，因而導致其閘極電壓之穩定度不佳。 In order to improve this drawback, today's technology is expected to be designed as an enhanced component. However, a typical gallium nitride high electron mobility field effect transistor usually has only a single metal gate, and its aluminum gallium nitride (AlGaN)/gallium nitride (GaN) hetero interface has a two-dimensional electron channel due to The control capability of a single metal gate is insufficient, and it is difficult to effectively control this heterogeneous interface, resulting in poor stability of its gate voltage.
另外，傳統的氮化鎵高電子遷移率場效電晶體也常會遇到功率電晶體散熱不佳的問題，因而導致其可靠度和穩定度變差。 In addition, the conventional gallium nitride high electron mobility field effect transistor often encounters the problem of poor heat dissipation of the power transistor, which leads to deterioration of reliability and stability.
因此，本發明提出一種採用對準式背向閘極及負電容鐵電介電質之多閘極高電子遷移率場效電晶體及其製造方法，藉以解決先前技術所遭遇到之上述問題。 Therefore, the present invention provides a multi-gate high electron mobility field effect transistor using an aligned back gate and a negative capacitance ferroelectric dielectric, and a method of fabricating the same, thereby solving the above problems encountered in the prior art.
根據本發明之一較佳具體實施例為一種多閘極高電子遷移率場效電晶體。於此實施例中，多閘極高電子遷移率場效電晶體包含基材、通道層、阻障層、複數個閘極、複數個對準式背向閘極及負電容鐵電介電質。通道層設置於基材上方。阻障層設置於通道層上方。複數個閘極分別設置於阻障層上方並往下延伸至阻障層內。複數個對準式背向閘極分別相對於該複數個閘極而設置於基材下方並往通道層延伸。負電容鐵電介電質分別設置於複數個閘極與阻障層之間以及複數個對準式背向閘極與基材之間。 A preferred embodiment of the invention is a multi-gate high electron mobility field effect transistor. In this embodiment, the multi-gate high electron mobility field effect transistor comprises a substrate, a channel layer, a barrier layer, a plurality of gates, a plurality of aligned back gates, and a negative capacitance ferroelectric dielectric. . The channel layer is disposed above the substrate. The barrier layer is disposed above the channel layer. A plurality of gates are respectively disposed above the barrier layer and extend downward into the barrier layer. A plurality of aligned back gates are respectively disposed under the substrate and extending toward the channel layer with respect to the plurality of gates. The negative capacitance ferroelectric dielectric is disposed between the plurality of gates and the barrier layer and between the plurality of aligned back gates and the substrate.
於一實施例中，基材包含半導體基板。 In one embodiment, the substrate comprises a semiconductor substrate.
於一實施例中，基材進一步包含緩衝層，設置於半導體基板與通道層之間。 In one embodiment, the substrate further includes a buffer layer disposed between the semiconductor substrate and the channel layer.
於一實施例中，基材進一步包含晶種層，設置於半導體基板與緩衝層之間。 In one embodiment, the substrate further includes a seed layer disposed between the semiconductor substrate and the buffer layer.
於一實施例中，該複數個對準式背向閘極係延伸超 過基材而進入通道層內。 In one embodiment, the plurality of aligned back gates extend beyond the substrate into the channel layer.
於一實施例中，多閘極高電子遷移率場效電晶體進一步包含汲極與源極。汲極與源極分別設置於阻障層上。汲極與源極分別位於該複數個閘極之兩側並與該複數個閘極彼此分隔。 In one embodiment, the multi-gate high electron mobility field effect transistor further includes a drain and a source. The drain and the source are respectively disposed on the barrier layer. The drain and the source are respectively located on opposite sides of the plurality of gates and are separated from each other by the plurality of gates.
於一實施例中，通道層包含氮化鎵(GaN)、氧化鋅(ZnO)、碳化矽(SiC)、氮化鋁鎵銦(AlxGayIn1-x-yN)、磷化鋁鎵銦(AlxGayIn1-x-yP)或砷化鋁鎵銦(AlxGayIn1-x-yAs)，且0≦x+y≦1。 In one embodiment, the channel layer comprises gallium nitride (GaN), zinc oxide (ZnO), tantalum carbide (SiC), aluminum gallium indium nitride (Al x Ga y In 1-xy N), aluminum gallium indium phosphide (Al x Ga y In 1-xy P) or aluminum gallium indium arsenide (Al x Ga y In 1-xy As), and 0 ≦ x + y ≦ 1.
於一實施例中，負電容鐵電介電質係由具有負電容特性的高介電常數(High-K)鐵電材料構成，包含矽氧化鉿(HfSiO)、鋅氧化鉿(HfZrO)、鋁氧化鉿(HfAlO)、釔氧化鉿(HfYO)、鑭氧化鉿(HfLaO)、釓氧化鉿(HfGdO)或鍶氧化鉿(HfSrO)。 In one embodiment, the negative capacitance ferroelectric dielectric is composed of a high dielectric constant (High-K) ferroelectric material having a negative capacitance characteristic, including hafnium niobium oxide (HfSiO), zinc antimony oxide (HfZrO), aluminum. HbAlO, HfYO, HfLaO, HfGdO or HfSrO.
於一實施例中，負電容鐵電介電質包含鋯鈦酸鉛(Pb(ZrTi)O3,PZT)、鈦酸鍶鋇(Ba(SrTi)O3,BST)或鉭酸鍶鉍(Bi2(SrTa2)O9,SBT)。 In one embodiment, the negative capacitance ferroelectric dielectric comprises lead zirconate titanate (Pb(ZrTi)O 3 , PZT), barium titanate (Ba(SrTi)O 3 , BST) or bismuth ruthenate (Bi) 2 (SrTa 2 )O 9 , SBT).
於一實施例中，該複數個閘極係由氮化或碳化金屬材料構成，包含氮化鉭(TaN)、氮化鈦(TiN)、碳化鈦(TiC)、碳化鉭(TaC)或氮化鎢(WN)。 In one embodiment, the plurality of gates are made of a nitrided or carbonized metal material, including tantalum nitride (TaN), titanium nitride (TiN), titanium carbide (TiC), tantalum carbide (TaC), or nitride. Tungsten (WN).
於一實施例中，該複數個對準式背向閘極係由金屬材料構成，包含鋁(Al)或銅(Cu)。 In one embodiment, the plurality of aligned back gates are made of a metallic material and comprise aluminum (Al) or copper (Cu).
於一實施例中，負電容鐵電介電質提供鐵電負電容效應，藉以降低多閘極高電子遷移率場效電晶體之次臨界擺幅(Sub-threshold Swing,SS)與關閉狀態漏電流。 In one embodiment, the negative capacitance ferroelectric dielectric provides a ferroelectric negative capacitance effect, thereby reducing Sub-threshold Swing (SS) and off-state leakage of a multi-gate high electron mobility field effect transistor. Current.
於一實施例中，該複數個對準式背向閘極與該複數個閘極彼此對準且分別設置於多閘極高電子遷移率場效電晶體之相對兩側，藉以增加多閘極高電子遷移率場效電晶體之可散熱面積與可接合面積。 In one embodiment, the plurality of aligned back gates and the plurality of gates are aligned with each other and respectively disposed on opposite sides of the multi-gate high electron mobility field effect transistor, thereby increasing the plurality of gates The heat dissipating area and the bondable area of the high electron mobility field effect transistor.
根據本發明之另一較佳具體實施例為一種多閘極高電子遷移率場效電晶體製造方法。於此實施例中，多閘極高電子遷移率場效電晶體製造方法用以製造一多閘極高電子遷移率場效電晶體。 Another preferred embodiment of the present invention is a method of fabricating a multi-gate high electron mobility field effect transistor. In this embodiment, a multi-gate high electron mobility field effect transistor manufacturing method is used to fabricate a multi-gate high electron mobility field effect transistor.
該多閘極高電子遷移率場效電晶體製造方法包含下列步驟：(a)提供一基材；(b)將一通道層設置於基材上方；(c)將一阻障層設置於通道層上方；(d)分別於阻障層與基材形成彼此相對的複數個第一凹陷區域與複數個第二凹陷區域，其中該複數個第一凹陷區域延伸至阻障層內且該複數個第二凹陷區域往通道層延伸；(e)分別將負電容鐵電介電質設置於該複數個第一凹陷區域與該複數個第二凹陷區域內；(f)分別將複數個閘極設置於該複數個第一凹陷區域內並覆蓋於負電容鐵電介電質上，致使該複數個閘極延伸至阻障層內；以及(g)分別將複數個對準式背向閘極設置於該複數個第 二凹陷區域內並覆蓋於負電容鐵電介電質上，致使該複數個對準式背向閘極往通道層延伸。 The multi-gate high electron mobility field effect transistor manufacturing method comprises the following steps: (a) providing a substrate; (b) placing a channel layer over the substrate; (c) placing a barrier layer on the channel Above the layer; (d) forming a plurality of first recessed regions and a plurality of second recessed regions opposite to each other of the barrier layer and the substrate, wherein the plurality of first recessed regions extend into the barrier layer and the plurality of The second recessed region extends toward the channel layer; (e) respectively, a negative capacitance ferroelectric dielectric is disposed in the plurality of first recessed regions and the plurality of second recessed regions; (f) respectively setting a plurality of gates And covering the negative capacitance ferroelectric dielectric in the plurality of first recess regions, such that the plurality of gates extend into the barrier layer; and (g) respectively setting the plurality of aligned back gates And covering the negative capacitance ferroelectric dielectric in the plurality of second recess regions, such that the plurality of aligned back gates extend toward the channel layer.
相較於先前技術，根據本發明之多閘極高電子遷移率場效電晶體及其製造方法可具有下列優點及功效：(1)採用多閘極(Multi-gate)結構來強化閘極之控制能力，藉以達到穩定操作電壓及降低功耗之效果；(2)採用負電容鐵電介電質來提供負電容效應，藉以降低次臨界擺幅(Sub-threshold Swing,SS)及關閉狀態漏電流，進而達到提高驅動電流及電流開關比之效果；(3)採用對準式背向閘極來增加功率電晶體之可散熱面積，藉以提升其散熱效能及可靠度，還能夠降低打線接合之難度，有助於三維積體電路之實現；(4)上述結構亦有助於改善氮化鎵多閘極高電子遷移率場效電晶體之高壓及高頻輸出特性。 Compared with the prior art, the multi-gate high electron mobility field effect transistor and the manufacturing method thereof according to the present invention can have the following advantages and effects: (1) using a multi-gate structure to strengthen the gate Controlling ability to achieve stable operating voltage and reduce power consumption; (2) Negative capacitance ferroelectric dielectric to provide negative capacitance effect, thereby reducing Sub-threshold Swing (SS) and off-state leakage Current, which in turn increases the drive current and current switching ratio; (3) Aligns the back gate to increase the heat dissipation area of the power transistor, thereby improving its heat dissipation efficiency and reliability, and also reducing wire bonding. The difficulty helps the realization of the three-dimensional integrated circuit; (4) The above structure also contributes to the improvement of the high voltage and high frequency output characteristics of the gallium nitride multi-gate high electron mobility field effect transistor.
關於本發明之優點與精神可以藉由以下的發明詳述及所附圖式得到進一步的瞭解。 The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.
S10~S22‧‧‧步驟 S10~S22‧‧‧Steps
1‧‧‧多閘極高電子遷移率場效電晶體 1‧‧‧Multi-gate high electron mobility field effect transistor
10‧‧‧通道層 10‧‧‧channel layer
12‧‧‧阻障層 12‧‧‧Barrier layer
14‧‧‧半導體基板 14‧‧‧Semiconductor substrate
16‧‧‧負電容鐵電介電質 16‧‧‧Negative Capacitance Ferroelectric Dielectric
18‧‧‧緩衝層 18‧‧‧ Buffer layer
SUB‧‧‧基材 SUB‧‧‧Substrate
D‧‧‧汲極 D‧‧‧汲
S‧‧‧源極 S‧‧‧ source
G1‧‧‧閘極 G1‧‧‧ gate
G2‧‧‧對準式背向閘極 G2‧‧‧ Aligned back gate
ID‧‧‧汲極電流 I D ‧‧‧汲polar current
VG‧‧‧閘極電壓 V G ‧‧‧ gate voltage
P/E‧‧‧程式化/抹除 P/E‧‧‧Standing/Erasing
VD‧‧‧汲極電壓 V D ‧‧‧汲polar voltage
Vbackgate‧‧‧背向閘極電壓 V backgate ‧‧‧back gate voltage
gm‧‧‧轉導值 g m ‧‧‧transduction value
圖1係繪示根據本發明之一較佳具體實施例的多閘極高電子遷移率場效電晶體之示意圖。 1 is a schematic diagram of a multi-gate high electron mobility field effect transistor according to a preferred embodiment of the present invention.
圖2係繪示根據本發明之另一較佳具體實施例的多閘極高電子遷移率場效電晶體製造方法之流程圖。 2 is a flow chart showing a method of fabricating a multi-gate high electron mobility field effect transistor in accordance with another preferred embodiment of the present invention.
圖3係繪示鐵電材料可具有小於60mv/dec的次臨界擺 幅(Subthreshold swing)以降低電晶體元件之操作電壓並提升其可靠度的示意圖。 Figure 3 is a schematic diagram showing that the ferroelectric material can have a Subthreshold swing of less than 60 mv/dec to reduce the operating voltage of the transistor element and improve its reliability.
圖4係繪示負電容鐵電介電質可調變電容元件之平帶電壓值相當於調變電晶體元件之臨界電壓值的示意圖。 FIG. 4 is a schematic diagram showing the flat-band voltage value of the negative-capacitance ferroelectric dielectric variable-capacitance device equivalent to the threshold voltage value of the modulated transistor component.
圖5係繪示材料之晶相由介穩態的單斜晶相轉變成更穩定的斜方晶相代表負電容的行為之示意圖。 Figure 5 is a schematic diagram showing the behavior of a crystalline phase of a material from a metastable monoclinic phase to a more stable orthorhombic phase representing a negative capacitance.
圖6係繪示具有負電容特性之鐵電介電質可於開啟狀態與關閉狀態之間高速切換的示意圖。 FIG. 6 is a schematic diagram showing that a ferroelectric dielectric having a negative capacitance characteristic can be switched at a high speed between an on state and a off state.
圖7係分別繪示具有鐵電介電質與沒有鐵電介電質的多閘極高電子遷移率場效電晶體在不同的閘極電壓下的汲極電流變化曲線圖。 FIG. 7 is a graph showing the peak current variation of a multi-gate high electron mobility field effect transistor having a ferroelectric dielectric and no ferroelectric dielectric at different gate voltages.
圖8係繪示分別繪示具有鐵電介電質與沒有鐵電介電質的多閘極高電子遷移率場效電晶體在不同的閘極電壓下的轉導值變化曲線圖。 FIG. 8 is a graph showing the change of transduction values at different gate voltages of a multi-gate high electron mobility field effect transistor having a ferroelectric dielectric and no ferroelectric dielectric, respectively.
根據本發明之一較佳具體實施例為一種多閘極(Multi-gate)高電子遷移率場效電晶體(HEMT)，由於其具有多閘極、負電容鐵電介電質與對準式背向閘極等結構特徵，不僅可有效降低其次臨界擺幅與閘極漏電流，還可改善其散熱效果與高壓及高頻輸出特性。 A preferred embodiment of the present invention is a multi-gate high electron mobility field effect transistor (HEMT) having a multi-gate, negative capacitance ferroelectric dielectric and alignment The structural features such as the back gate can not only effectively reduce the sub-threshold swing and gate leakage current, but also improve the heat dissipation effect and high-voltage and high-frequency output characteristics.
於此實施例中，多閘極高電子遷移率場效電晶體至少包含有基材、通道層、阻障層、複數個閘極、複數個對準式背 向閘極及負電容鐵電介電質。其中，通道層設置於基材上方。阻障層設置於通道層上方。複數個閘極分別設置於阻障層上方並往下延伸至阻障層內。複數個對準式背向閘極分別相對於該複數個閘極而設置於基材下方並往通道層延伸。負電容鐵電介電質分別設置於複數個閘極與阻障層之間以及複數個對準式背向閘極與基材之間。 In this embodiment, the multi-gate high electron mobility field effect transistor includes at least a substrate, a channel layer, a barrier layer, a plurality of gates, a plurality of aligned back gates, and a negative capacitance ferroelectric Electricity quality. Wherein the channel layer is disposed above the substrate. The barrier layer is disposed above the channel layer. A plurality of gates are respectively disposed above the barrier layer and extend downward into the barrier layer. A plurality of aligned back gates are respectively disposed under the substrate and extending toward the channel layer with respect to the plurality of gates. The negative capacitance ferroelectric dielectric is disposed between the plurality of gates and the barrier layer and between the plurality of aligned back gates and the substrate.
請參照圖1，圖1係繪示根據本發明之一較佳具體實施例的多閘極高電子遷移率場效電晶體之示意圖。 Please refer to FIG. 1. FIG. 1 is a schematic diagram of a multi-gate high electron mobility field effect transistor according to a preferred embodiment of the present invention.
如圖1所示，多閘極高電子遷移率場效電晶體1包含有基材SUB、通道層10、阻障層12、負電容鐵電介電質16、汲極D、源極S、複數個閘極G1及複數個對準式背向閘極G2。 As shown in FIG. 1, the multi-gate high electron mobility field effect transistor 1 includes a substrate SUB, a channel layer 10, a barrier layer 12, a negative capacitance ferroelectric dielectric 16, a drain D, and a source S. A plurality of gates G1 and a plurality of aligned back gates G2.
需說明的是，此實施例中之基材SUB包含半導體基板14與緩衝層18，但不以此為限。實際上，基材SUB亦可以僅包含半導體基板14，抑或基材SUB除了包含半導體基板14與緩衝層18之外，還可進一步包含設置於半導體基板14與緩衝層18之間的晶種層(圖未示)。其中，緩衝層18則可用以減少半導體基板14(或晶種層)與後續形成的通道層10之間的晶格錯位(Mismatch)，以及解決磊晶成長時因熱膨脹係數不相同而影響半導體基板14上之磊晶層均勻度的問題；晶種層可用以補償半導體基板14與緩衝層18之間的晶格錯位。 It should be noted that the substrate SUB in this embodiment includes the semiconductor substrate 14 and the buffer layer 18, but is not limited thereto. In fact, the substrate SUB may also include only the semiconductor substrate 14 , or the substrate SUB may further include a seed layer disposed between the semiconductor substrate 14 and the buffer layer 18 in addition to the semiconductor substrate 14 and the buffer layer 18 ( The figure is not shown). The buffer layer 18 can be used to reduce the lattice mismatch between the semiconductor substrate 14 (or the seed layer) and the subsequently formed channel layer 10, and to solve the semiconductor substrate due to the difference in thermal expansion coefficient during epitaxial growth. The problem of uniformity of the epitaxial layer on 14; the seed layer can be used to compensate for the lattice misalignment between the semiconductor substrate 14 and the buffer layer 18.
於實際應用中，半導體基板14可以由矽(Si)、碳化矽(SiC)、藍寶石(Sapphire)、氮化鎵(GaN)、氮化鋁鎵(AlGaN)、氮化 鋁(AlN)、砷化鎵(GaAs)、砷化鋁鎵(AlGaAs)或其他III-V族元素之化合物構成，但不以此為限。緩衝層18可包含氮化鎵(GaN)或經摻雜的氮化鎵(GaN)，可使用磊晶製程或其他適當的方法製得，但不以此為限。 In practical applications, the semiconductor substrate 14 may be made of bismuth (Si), tantalum carbide (SiC), sapphire, gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), arsenic. It is composed of a compound of gallium (GaAs), aluminum gallium arsenide (AlGaAs) or other group III-V elements, but is not limited thereto. The buffer layer 18 may comprise gallium nitride (GaN) or doped gallium nitride (GaN), which may be produced using an epitaxial process or other suitable method, but is not limited thereto.
需說明的是，通道層10的能隙(Band gap)需小於阻障層12的能隙，並且通道層10與阻障層12之組合及厚度需能產生二維電子氣。 It should be noted that the energy gap of the channel layer 10 needs to be smaller than the energy gap of the barrier layer 12, and the combination and thickness of the channel layer 10 and the barrier layer 12 are required to generate two-dimensional electron gas.
實際上，通道層10可以由III-V族元素之化合物或經摻雜的III-V族元素之化合物、II-VI族元素之化合物或經摻雜的II-VI族元素之化合物或IV-IV族元素之化合物或經摻雜的IV-IV族元素之化合物構成，例如氮化鎵(GaN)、氧化鋅(ZnO)、碳化矽(SiC)、氮化鋁鎵銦(AlxGayIn1-x-yN)、磷化鋁鎵銦(AlxGayIn1-x-yP)或砷化鋁鎵銦(AlxGayIn1-x-yAs)等，且0≦x+y≦1，但不以此為限。阻障層12可以由III-V族元素之化合物構成，例如氮化鋁(AlN)、氮化鋁銦(AlInN)、氮化鋁鎵(AlGaN)、氮化鎵(GaN)、氮化銦鎵(InGaN)、氮化鋁銦鎵(AlInGaN)等，但不以此為限。 In fact, the channel layer 10 may be a compound of a group III-V element or a compound of a doped group III-V element, a compound of a group II-VI element or a compound of a doped group II-VI element or IV- a compound of a group IV element or a compound of a group of doped group IV-IV elements, such as gallium nitride (GaN), zinc oxide (ZnO), tantalum carbide (SiC), aluminum gallium indium nitride (Al x Ga y In 1-xy N), aluminum gallium indium phosphide (Al x Ga y In 1-xy P) or aluminum gallium indium arsenide (Al x Ga y In 1-xy As), and 0 ≦ x + y ≦ 1, But not limited to this. The barrier layer 12 may be composed of a compound of a group III-V element, such as aluminum nitride (AlN), aluminum indium nitride (AlInN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), indium gallium nitride. (InGaN), aluminum indium gallium nitride (AlInGaN), etc., but not limited thereto.
於一較佳具體實施例中，多閘極高電子遷移率場效電晶體1可採用矽(Si)基板作為半導體基板14、採用氮化鎵(GaN)作為通道層10以及採用氮化鋁鎵(AlGaN)作為阻障層12，但不以此為限。 In a preferred embodiment, the multi-gate high electron mobility field effect transistor 1 can employ a bismuth (Si) substrate as the semiconductor substrate 14, gallium nitride (GaN) as the channel layer 10, and aluminum gallium nitride. (AlGaN) is used as the barrier layer 12, but is not limited thereto.
至於負電容鐵電介電質16可以是傳統的鋯鈦酸鉛(Pb(ZrTi)O3,PZT)、鈦酸鍶鋇(Ba(SrTi)O3,BST)或鉭酸鍶鉍 (Bi2(SrTa2)O9,SBT)，或是由具有負電容特性的高介電常數(High-K)鐵電材料構成，例如矽氧化鉿(HfSiO)、鋅氧化鉿(HfZrO)、鋁氧化鉿(HfAlO)、釔氧化鉿(HfYO)、鑭氧化鉿(HfLaO)、釓氧化鉿(HfGdO)或鍶氧化鉿(HfSrO)等，但不以此為限。 As for the negative capacitance ferroelectric dielectric 16, it may be a conventional lead zirconate titanate (Pb(ZrTi)O 3 , PZT), barium titanate (Ba(SrTi)O 3 , BST) or bismuth ruthenate (Bi 2 ). (SrTa 2 )O 9 ,SBT), or consisting of high dielectric constant (High-K) ferroelectric materials with negative capacitance characteristics, such as hafnium oxide (HfSiO), zinc antimony oxide (HfZrO), aluminum antimony oxide (HfAlO), HfYO, HfLaO, HfGdO or HfSrO, but not limited thereto.
此外，該複數個閘極G1可以由氮化或碳化金屬材料構成，例如氮化鉭(TaN)、氮化鈦(TiN)、碳化鈦(TiC)、碳化鉭(TaC)或氮化鎢(WN)等，但不以此為限。至於該複數個對準式背向閘極G2則可以由金屬材料構成，例如鋁(Al)或銅(Cu)等，但不以此為限。 In addition, the plurality of gates G1 may be composed of a nitrided or carbonized metal material such as tantalum nitride (TaN), titanium nitride (TiN), titanium carbide (TiC), tantalum carbide (TaC) or tungsten nitride (WN). ), etc., but not limited to this. The plurality of aligned back gates G2 may be made of a metal material, such as aluminum (Al) or copper (Cu), but not limited thereto.
於此實施例中，通道層10設置於半導體基板14上方且阻障層12設置於通道層10上方。阻障層12與半導體基板14會分別形成有彼此相對的複數個第一凹陷區域與複數個第二凹陷區域，其中該複數個第一凹陷區域會延伸至阻障層12內且該複數個第二凹陷區域會往通道層10延伸。於此實施例中，該複數個第二凹陷區域會延伸超過半導體基板14與緩衝層18而進入通道層10內，但不以此為限。 In this embodiment, the channel layer 10 is disposed above the semiconductor substrate 14 and the barrier layer 12 is disposed above the channel layer 10. The barrier layer 12 and the semiconductor substrate 14 are respectively formed with a plurality of first recess regions and a plurality of second recess regions facing each other, wherein the plurality of first recess regions extend into the barrier layer 12 and the plurality of The second recessed area will extend toward the channel layer 10. In this embodiment, the plurality of second recessed regions may extend beyond the semiconductor substrate 14 and the buffer layer 18 into the channel layer 10, but are not limited thereto.
負電容鐵電介電質16會分別設置於該複數個第一凹陷區域與該複數個第二凹陷區域內。彼此電性連接的該複數個閘極G1分別填滿該複數個第一凹陷區域並覆蓋於負電容鐵電介電質16上，致使該複數個閘極G1得以延伸至阻障層12內。彼此電性連接的該複數個對準式背向閘極G2分別填滿該複數個第二凹陷區域並覆蓋於負電容鐵電介電質16上，致使該複數個對準式背向閘極G2往通道層10延伸。於此實施例中，由於該複數個第二凹陷區域 會延伸超過半導體基板14與緩衝層18而進入通道層10內，因此，該複數個對準式背向閘極G2亦會延伸超過半導體基板14與緩衝層18而進入通道層10內，但不以此為限。藉此，該複數個對準式背向閘極G2即可與該複數個閘極G1對準而使得多閘極高電子遷移率場效電晶體1具有雙掘入式閘極(Double recess gate)的結構。 The negative capacitance ferroelectric dielectric 16 is disposed in the plurality of first recess regions and the plurality of second recess regions, respectively. The plurality of gates G1 electrically connected to each other fill the plurality of first recessed regions and over the negative capacitance ferroelectric dielectric 16, so that the plurality of gates G1 are extended into the barrier layer 12. The plurality of aligned back gates G2 electrically connected to each other fill the plurality of second recess regions and overlying the negative capacitance ferroelectric dielectric 16, causing the plurality of aligned back gates G2 extends toward the channel layer 10. In this embodiment, since the plurality of second recessed regions extend beyond the semiconductor substrate 14 and the buffer layer 18 into the channel layer 10, the plurality of aligned back gates G2 also extend beyond the semiconductor substrate. 14 and the buffer layer 18 enter the channel layer 10, but not limited thereto. Thereby, the plurality of aligned back gates G2 can be aligned with the plurality of gates G1 such that the multi-gate high electron mobility field effect transistor 1 has a double recess gate (Double recess gate) )Structure.
汲極D與源極S分別設置於阻障層12上。汲極D與源極S分別位於該複數個閘極G1之兩側並與該複數個閘極G1彼此分隔。 The drain D and the source S are respectively disposed on the barrier layer 12. The drain D and the source S are respectively located on both sides of the plurality of gates G1 and are separated from each other by the plurality of gates G1.
根據本發明之另一較佳具體實施例為一種多閘極高電子遷移率場效電晶體製造方法。於此實施例中，多閘極高電子遷移率場效電晶體製造方法可用以製造如圖1所示的多閘極高電子遷移率場效電晶體1，但不以此為限。 Another preferred embodiment of the present invention is a method of fabricating a multi-gate high electron mobility field effect transistor. In this embodiment, the multi-gate high electron mobility field effect transistor manufacturing method can be used to manufacture the multi-gate high electron mobility field effect transistor 1 as shown in FIG. 1 , but not limited thereto.
請參照圖2，圖2係繪示根據本發明之另一較佳具體實施例的多閘極高電子遷移率場效電晶體製造方法之流程圖。 Please refer to FIG. 2. FIG. 2 is a flow chart showing a method for fabricating a multi-gate high electron mobility field effect transistor according to another preferred embodiment of the present invention.
如圖2所示，多閘極高電子遷移率場效電晶體製造方法包含下列步驟：步驟S10：提供包含半導體基板14及緩衝層18之基材SUB，其中緩衝層18係位於半導體基板14上方；步驟S12：將通道層10設置於基材SUB上方；步驟S14：將阻障層12設置於通道層10上方；步驟S16：分別於阻障層12與半導體基板14形成彼此相對的複數個第一凹陷區域與複數個第二凹陷區域，其中該複數個第一凹陷區域延伸至阻障層12內且該複數個第二凹陷區域往通 道層10延伸；步驟S18：分別將負電容鐵電介電質16設置於該複數個第一凹陷區域與該複數個第二凹陷區域內；步驟S20：分別將複數個閘極G1設置於該複數個第一凹陷區域內並覆蓋於負電容鐵電介電質16上，致使該複數個閘極G1延伸至阻障層12內；以及步驟S22：分別將複數個對準式背向閘極G2設置於該複數個第二凹陷區域內並覆蓋於負電容鐵電介電質16上，致使該複數個對準式背向閘極G2往通道層10延伸。 As shown in FIG. 2, the method for fabricating a multi-gate high electron mobility field effect transistor includes the following steps: Step S10: providing a substrate SUB including a semiconductor substrate 14 and a buffer layer 18, wherein the buffer layer 18 is located above the semiconductor substrate 14. Step S12: disposing the channel layer 10 over the substrate SUB; step S14: disposing the barrier layer 12 over the channel layer 10; step S16: forming a plurality of layers opposite to each other of the barrier layer 12 and the semiconductor substrate 14 a recessed region and a plurality of second recessed regions, wherein the plurality of first recessed regions extend into the barrier layer 12 and the plurality of second recessed regions extend toward the channel layer 10; and step S18: respectively, the negative capacitance ferroelectric The electric material 16 is disposed in the plurality of first recessed regions and the plurality of second recessed regions; and step S20: respectively setting a plurality of gates G1 in the plurality of first recessed regions and covering the negative capacitance ferroelectric The plurality of gates G1 extend into the barrier layer 12; and step S22: respectively placing a plurality of aligned back gates G2 in the plurality of second recess regions and covering the negative Capacitor ferroelectric The dielectric substance 16, so that the plurality of back-aligning gate G2 extending to the channel layer 10.
藉此，該複數個對準式背向閘極G2即可與該複數個閘極G1對準而使得多閘極高電子遷移率場效電晶體1具有雙掘入式閘極(Double recess gate)的結構。 Thereby, the plurality of aligned back gates G2 can be aligned with the plurality of gates G1 such that the multi-gate high electron mobility field effect transistor 1 has a double recess gate (Double recess gate) )Structure.
於此實施例中，由於該複數個第二凹陷區域會延伸超過半導體基板14與緩衝層18而進入通道層10內，因此，分別填入至該複數個第二凹陷區域的該複數個對準式背向閘極G2亦會延伸超過半導體基板14與緩衝層18而進入通道層10內，但不以此為限。 In this embodiment, since the plurality of second recessed regions extend beyond the semiconductor substrate 14 and the buffer layer 18 into the channel layer 10, the plurality of alignments respectively filled into the plurality of second recessed regions are respectively filled. The back gate G2 also extends beyond the semiconductor substrate 14 and the buffer layer 18 into the channel layer 10, but is not limited thereto.
需說明的是，雖然此實施例中之基材SUB包含半導體基板14與緩衝層18，但在其他實施例中，基材亦可以僅包含半導體基板14，抑或基材SUB除了包含半導體基板14及緩衝層18之外，還可進一步包含設置於半導體基板14與緩衝層18之間的晶種層(圖未示)。 It should be noted that although the substrate SUB in this embodiment includes the semiconductor substrate 14 and the buffer layer 18, in other embodiments, the substrate may also include only the semiconductor substrate 14, or the substrate SUB includes the semiconductor substrate 14 and In addition to the buffer layer 18, a seed layer (not shown) disposed between the semiconductor substrate 14 and the buffer layer 18 may be further included.
依照上述製造方法所得到的多閘極高電子遷移率場 效電晶體1具有多閘極、負電容鐵電介電質及對準式背向閘極等結構特徵，不僅可強化閘極的控制能力以穩定操作電壓並降低功耗，還可降低次臨界擺幅與關閉狀態漏電流以提高驅動電流及電流開關比，更能有效提升散熱效能、可靠度、高壓及高頻輸出特性。 The multi-gate high electron mobility field effect transistor 1 obtained according to the above manufacturing method has structural features such as a multi-gate, a negative-capacitance ferroelectric dielectric and an aligned back gate, which not only enhances gate control The ability to stabilize the operating voltage and reduce power consumption, can also reduce the sub-threshold swing and off-state leakage current to improve the drive current and current switching ratio, and can effectively improve the heat dissipation performance, reliability, high voltage and high-frequency output characteristics.
需說明的是，基本的電晶體物理現象(次臨界擺幅最小值為60mV/dec)對傳統的金氧半場效應電晶體造成限制，而無法進一步降低其操作電壓與切換耗能。由於陡峭的次臨界擺幅不只能降低切換耗能，還能減少直流的關閉狀態漏電流，因此，下一世代的綠能電晶體元件均須具備低操作電壓與高切換速度，以有效節省切換耗能。 It should be noted that the basic transistor physics phenomenon (minimum sub-threshold swing is 60mV/dec) limits the conventional MOS half-effect transistor, and cannot further reduce its operating voltage and switching energy consumption. Since the steep sub-threshold swing can not only reduce the switching energy consumption, but also reduce the DC off-state leakage current, the next generation of green-energy crystal components must have low operating voltage and high switching speed to effectively save switching. Energy consumption.
請參照圖3，圖3左側係繪示多閘極高電子遷移率場效電晶體之汲極電流ID對閘極電壓VG的曲線圖，而圖3右側係繪示多閘極高電子遷移率場效電晶體之次臨界擺幅對寫入/抹除次數的曲線圖。由圖3可知：由於負電容鐵電介電質所採用的鐵電材料可具有小於60mv/dec的次臨界擺幅，故可達到降低多閘極高電子遷移率場效電晶體之操作電壓並提升其可靠度的具體功效。 Please refer to FIG. 3 , the left side of FIG. 3 is a graph showing the gate current ID of the multi-gate high electron mobility field effect transistor on the gate voltage VG, and the right side of FIG. 3 shows the high gate mobility of the multi-gate. A plot of the sub-threshold swing of the field effect transistor versus the number of write/erase times. It can be seen from FIG. 3 that since the ferroelectric material used for the negative-capacitance ferroelectric dielectric can have a sub-threshold swing of less than 60 mV/dec, the operating voltage of the multi-gate high electron mobility field-effect transistor can be reduced and Improve the specific effectiveness of its reliability.
請參照圖4，圖4係繪示多閘極高電子遷移率場效電晶體之閘極-基板電容對閘極電壓VG的曲線圖。由圖4可知：由於負電容鐵電介電質可調變通道表面電位及電容元件之平帶電壓值，亦即負電容鐵電介電質可調變多閘極高電子遷移率場效電晶體之臨界電壓值，故能在將臨界電壓拉至正值的前提下，改善多 閘極高電子遷移率場效電晶體之關閉電流與次臨界擺幅特性。 Please refer to FIG. 4. FIG. 4 is a graph showing gate-substrate capacitance versus gate voltage VG of a multi-gate high electron mobility field effect transistor. It can be seen from Fig. 4 that the negative-capacitance ferroelectric dielectric can change the surface potential of the channel and the flat-band voltage value of the capacitive component, that is, the negative-capacitance ferroelectric dielectric can be changed into multiple gates and high electron mobility field-effect electricity. The critical voltage value of the crystal can improve the off current and sub-threshold swing characteristics of the multi-gate high electron mobility field effect transistor under the premise that the threshold voltage is pulled to a positive value.
請參照圖5，如圖5所示，當鐵電材料的晶相由能量較高之介穩態(Metastable state)的單斜晶相(Monoclinic phase)轉變成能量較低且更穩定的斜方晶相(Orthorhombic phase)時係代表著一種負電容的行為。 Referring to FIG. 5, as shown in FIG. 5, when the crystal phase of the ferroelectric material is converted into a lower energy and more stable rhombic by a higher energy metastable state monoclinic phase. The Orthorhombic phase represents the behavior of a negative capacitance.
請參照圖6，如圖6所示，由於具有負電容特性的鐵電介電質所製成的多閘極高電子遷移率場效電晶體可快速進行開啟狀態(On state)與關閉狀態(Off state)之間的切換，而能達成奈米秒(ns)等級的高切換速度，故本發明的多閘極高電子遷移率場效電晶體可應用於高頻元件上。 Referring to FIG. 6, as shown in FIG. 6, a multi-gate high electron mobility field effect transistor made of a ferroelectric dielectric having a negative capacitance characteristic can quickly perform an on state and a closed state ( The switching between Off state) can achieve a high switching speed of the nanosecond (ns) level, so that the multi-gate high electron mobility field effect transistor of the present invention can be applied to a high frequency component.
請參照圖7及圖8，圖7係分別繪示具有鐵電介電質與沒有鐵電介電質的多閘極高電子遷移率場效電晶體在不同的閘極電壓下之汲極電流曲線圖；圖8係繪示分別繪示具有鐵電介電質與沒有鐵電介電質的多閘極高電子遷移率場效電晶體在不同的閘極電壓下之轉導值曲線圖。 Please refer to FIG. 7 and FIG. 8. FIG. 7 is a diagram showing the gate currents of the multi-gate high electron mobility field effect transistor having ferroelectric dielectric and no ferroelectric dielectric at different gate voltages. FIG. 8 is a graph showing transduction values of a multi-gate high electron mobility field effect transistor having a ferroelectric dielectric and no ferroelectric dielectric at different gate voltages, respectively.
由圖7及圖8可知：當對準式背向閘極電壓Vbackgate為固定值時，多閘極高電子遷移率場效電晶體的次臨界擺幅與轉導值(gm)可明顯獲得改善。比較圖7及圖8中之有鐵電介電質與無鐵電介電質兩條曲線亦可知：當多閘極高電子遷移率場效電晶體除了對準式背向閘極之外還進一步結合負電容鐵電介電質時，多閘極高電子遷移率場效電晶體的元件特性亦可明顯獲得改善。 It can be seen from FIG. 7 and FIG. 8 that the subcritical swing amplitude and the transduction value (g m ) of the multi-gate high electron mobility field effect transistor are obvious when the aligned back gate voltage V backgate is a fixed value. Get improved. Comparing the two curves of ferroelectric dielectric and ferroelectric dielectric in FIGS. 7 and 8 also shows that when the multi-gate high electron mobility field effect transistor is in addition to the aligned back gate When combined with a negative-capacitance ferroelectric dielectric, the component characteristics of a multi-gate high electron mobility field-effect transistor can be significantly improved.
相較於先前技術，根據本發明之多閘極高電子遷移 率場效電晶體及其製造方法可具有下列優點及功效：(1)採用多閘極結構來強化閘極之控制能力，藉以達到穩定操作電壓及降低功耗之效果；(2)採用負電容鐵電介電質來提供負電容效應，藉以降低次臨界擺幅及關閉狀態漏電流，進而達到提高驅動電流及電流開關比之效果；(3)採用對準式背向閘極來增加功率電晶體之可散熱面積，藉以提升其散熱效能及可靠度，還能夠降低打線接合之難度，有助於三維積體電路之實現；(4)上述結構亦有助於改善氮化鎵多閘極高電子遷移率場效電晶體之高壓及高頻輸出特性。 Compared with the prior art, the multi-gate high electron mobility field effect transistor and the manufacturing method thereof according to the present invention can have the following advantages and effects: (1) using a multi-gate structure to strengthen the control ability of the gate, thereby achieving The effect of stabilizing the operating voltage and reducing power consumption; (2) using a negative-capacitance ferroelectric dielectric to provide a negative-capacitance effect, thereby reducing the sub-threshold swing and the off-state leakage current, thereby improving the effect of driving current and current switching ratio (3) Aligning the back gate to increase the heat dissipation area of the power transistor, thereby improving the heat dissipation performance and reliability, and also reducing the difficulty of wire bonding, and contributing to the realization of the three-dimensional integrated circuit; 4) The above structure also contributes to improving the high voltage and high frequency output characteristics of the gallium nitride multi-gate high electron mobility field effect transistor.
由以上較佳具體實施例之詳述，係希望能更加清楚描述本發明之特徵與精神，而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地，其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。藉由以上較佳具體實施例之詳述，係希望能更加清楚描述本發明之特徵與精神，而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地，其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。 The features and spirits of the present invention are intended to be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed. The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed.
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| DE102021201791A1 (en) | 2021-02-25 | 2022-08-25 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung eingetragener Verein | High Electron Mobility Transistor (HEMT), Transistor Assembly, Method of Controlling a HEMT, and Method of Making a HEMT |
| TWI806071B (en) * | 2020-06-29 | 2023-06-21 | 台灣積體電路製造股份有限公司 | Memory structure and method of forming memory structure |
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| US8188459B2 (en) * | 2007-04-12 | 2012-05-29 | Massachusetts Institute Of Technology | Devices based on SI/nitride structures |
| US7915643B2 (en) * | 2007-09-17 | 2011-03-29 | Transphorm Inc. | Enhancement mode gallium nitride power devices |
| US8669591B2 (en) * | 2011-12-27 | 2014-03-11 | Eta Semiconductor Inc. | E-mode HFET device |
| MY188298A (en) * | 2014-09-09 | 2021-11-25 | Intel Corp | Multi-gate high electron mobility transistors and methods of fabrication |
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| TWI806071B (en) * | 2020-06-29 | 2023-06-21 | 台灣積體電路製造股份有限公司 | Memory structure and method of forming memory structure |
| DE102021201791A1 (en) | 2021-02-25 | 2022-08-25 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung eingetragener Verein | High Electron Mobility Transistor (HEMT), Transistor Assembly, Method of Controlling a HEMT, and Method of Making a HEMT |
| WO2022180127A1 (en) | 2021-02-25 | 2022-09-01 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | High electron mobility transistor (hemt), transistor arrangement, method of controlling an hemt and method of producing an hemt |
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