TW201839770A - Non-volatile memory apparatus with bytes erase and program disturb less - Google Patents
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本發明是有關於一種記憶體裝置，且特別是有關於一種具有字元抹除與減少寫入干擾的非揮發性記憶體裝置。This invention relates to a memory device, and more particularly to a non-volatile memory device having word erase and reduced write interference.
非揮發性記憶體由於具有可多次進行資料的存入、讀取、抹除等動作，且存入的資料在斷電後也不會消失的優點，已廣泛採用在個人電腦和電子設備。隨著記憶體相關技術的進步，記憶體裝置的容量越來越大、尺寸越來越小，記憶胞抗寫入干擾能力越來越弱，將大幅地降低產品良率，而增加記憶體裝置的製造成本。由於面積的考量，資料抹除的單元區域越來越大，但小區域的資料抹除操作，對於使用者有極大的便利性。舉例來說，美國專利公開號：US20080123416公開一種非揮發性記憶體的電路架構設計，主要透過多個電晶體開關以及區域控制閘極線(local CG line)來達到減少記憶胞寫入干擾(program disturb)的功效。然而，此前案仍以大範圍的方式進行抹除操作，因此未有字元抹除(byte erase)的功能。再舉例來說，美國專利證書號：US9443594公開一種非揮發性記憶體的電路架構設計，主要透過多個P型電晶體開關以及區域控制閘極線來達到區域抹除的功能。然而，此前案仍以大範圍的方式進行寫入操作，因此仍未克服寫入干擾的問題。有鑑於此，以下將提出多個實施方式來克服上述問題。Non-volatile memory has been widely used in personal computers and electronic devices because it has the advantages of allowing data to be stored, read, erased, etc., and the stored data does not disappear after power-off. With the advancement of memory-related technologies, the capacity of memory devices is getting larger and larger, the size is getting smaller and smaller, and the memory cells are weaker in anti-write interference, which will greatly reduce the yield of products and increase the memory device. Manufacturing costs. Due to the area considerations, the unit area of the data erased is getting larger and larger, but the data erasing operation of the small area is extremely convenient for the user. For example, U.S. Patent Publication No. US20080123416 discloses a circuit architecture design for non-volatile memory, which mainly reduces memory cell write interference through a plurality of transistor switches and a local CG line. The effect of disturb). However, the previous case still performs the erase operation in a wide range of ways, so there is no function of byte erase. For example, U.S. Patent No.: U.S. Patent No. 7,944,594 discloses a circuit architecture design for non-volatile memory, which mainly achieves the function of area erasing through a plurality of P-type transistor switches and regional control gate lines. However, the previous case still performs the write operation in a wide range of manners, so the problem of write disturb has not been overcome. In view of this, various embodiments will be presented below to overcome the above problems.
本發明提供一種非揮發性記憶體裝置具有多個記憶胞區塊，並且這些記憶胞區塊可執行小區域性的資料讀取操作、資料寫入操作以及資料抹除操作，且可大幅減少記憶胞寫入干擾(program disturb)與達到字元抹除(byte erase)的功能。The invention provides a non-volatile memory device having a plurality of memory cell blocks, and the memory cell blocks can perform small-area data reading operations, data writing operations, and data erasing operations, and can greatly reduce memory. Program disturb and function to achieve byte erase.
本發明的非揮發性記憶體裝置包括多個記憶胞區塊。所述多個記憶胞區塊配置為記憶胞陣列。所述記憶胞區塊為一個抹除單元，各別包括多個記憶胞單元、第一字元線以及第二字元線。所述多個記憶胞單元各別包括第一記憶胞以及第二記憶胞。所述第一字元線耦接每一所述多個記憶胞單元的所述第一記憶胞，並且用以提供第一字元信號。所述第二字元線耦接每一所述多個記憶胞單元的所述第二記憶胞，並且用以提供第二字元信號。所述記憶胞陣列中的每一行設置選擇信號線。所述選擇信號線透過多個N型電晶體耦接每一行當中的所述多個記憶胞區塊。所述多個記憶胞區塊依據每一行的所述選擇信號線提供的選擇信號來各別決定是否執行讀取操作、寫入操作或抹除操作。The non-volatile memory device of the present invention includes a plurality of memory cell blocks. The plurality of memory cells are configured as a memory cell array. The memory cell block is an erase unit, and each includes a plurality of memory cell units, a first word line, and a second word line. The plurality of memory cell units each include a first memory cell and a second memory cell. The first word line is coupled to the first memory cell of each of the plurality of memory cells and configured to provide a first word signal. The second word line is coupled to the second memory cell of each of the plurality of memory cells and configured to provide a second word signal. Each row in the array of memory cells is provided with a selection signal line. The selection signal line is coupled to the plurality of memory cell blocks in each row through a plurality of N-type transistors. The plurality of memory cells respectively determine whether to perform a read operation, a write operation, or an erase operation according to a selection signal provided by the selection signal line of each row.
在本發明的一實施例中，上述的多個記憶胞區塊各別更包括區域抹除閘極線。所述區域抹除閘極線用以提供抹除電壓，並且透過第一N型電晶體耦接每一所述多個記憶胞單元的所述第一記憶胞以及所述第二記憶胞各別的抹除閘極。所述第一N型電晶體藉由控制端接收所述選擇信號，以決定是否提供所述抹除電壓至每一所述多個記憶胞單元的所述第一記憶胞以及所述第二記憶胞各別的所述抹除閘極。In an embodiment of the invention, the plurality of memory cell blocks each further comprise an area erasing gate line. The area erase gate line is configured to provide an erase voltage, and the first memory cell and the second memory cell of each of the plurality of memory cell units are coupled through the first N-type transistor Wipe the gate. The first N-type transistor receives the selection signal by the control terminal to determine whether to provide the erase voltage to the first memory cell and the second memory of each of the plurality of memory cells The respective gates of the cells are erased.
在本發明的一實施例中，上述的多個記憶胞區塊各別更包括區域控制源極線。所述區域控制源極線用以提供源極信號，並且透過第二N型電晶體耦接每一所述多個記憶胞單元的共用源極。所述第二N型電晶體藉由控制端接收所述選擇信號，以決定是否將所述源極信號提供至每一所述多個記憶胞單元的所述共用源極。In an embodiment of the invention, the plurality of memory cell blocks further include a region control source line. The region control source line is configured to provide a source signal, and is coupled to a common source of each of the plurality of memory cells through a second N-type transistor. The second N-type transistor receives the selection signal by the control terminal to determine whether to provide the source signal to the common source of each of the plurality of memory cells.
在本發明的一實施例中，上述的多個記憶胞區塊各別更包括區域控制閘極線。所述區域控制閘極線用以提供閘極信號，並且透過第三N型電晶體耦接每一所述多個記憶胞單元的控制閘極。所述第三N型電晶體藉由控制端接收所述選擇信號，以決定是否將所述閘極信號提供至每一所述多個記憶胞單元的所述控制閘極。In an embodiment of the invention, the plurality of memory cell blocks each further comprise an area control gate line. The area control gate line is configured to provide a gate signal, and the control gate of each of the plurality of memory cells is coupled through a third N-type transistor. The third N-type transistor receives the selection signal by the control terminal to determine whether to provide the gate signal to the control gate of each of the plurality of memory cells.
在本發明的一實施例中，上述的多個記憶胞區塊各別的該區域控制源極線更耦接每一所述多個記憶胞單元的一控制閘極，以將提供的該源極信號作為一閘極信號，並且所述第二N型電晶體藉由控制端接收所述選擇信號，以決定是否將所述閘極信號提供至每一所述多個記憶胞單元的所述控制閘極。In an embodiment of the present invention, the respective control source lines of the plurality of memory cells are further coupled to a control gate of each of the plurality of memory cells to provide the source. a pole signal as a gate signal, and the second N-type transistor receives the selection signal by a control terminal to determine whether to provide the gate signal to each of the plurality of memory cells Control the gate.
在本發明的一實施例中，上述的多個記憶胞區塊各別更包括全域控制源極線。所述全域控制源極線用以提供源極信號，並且耦接每一所述多個記憶胞區塊的所述多個記憶胞單元的共用源極。In an embodiment of the invention, the plurality of memory cell blocks each further comprise a global control source line. The global control source line is configured to provide a source signal and is coupled to a common source of the plurality of memory cells of each of the plurality of memory cells.
在本發明的一實施例中，上述的多個記憶胞區塊各別的所述第一字元線以及所述第二字元線分別透過第四N型電晶體以及第五N型電晶體耦接每一所述多個記憶胞區塊的所述第一記憶胞以及所述第二記憶胞。所述第一字元線以及所述第二字元線分別用以提供適當電壓於讀取操作、寫入操作或抹除操作。所述第四N型電晶體以及所述第五N型電晶體分別藉由控制端接收所述選擇信號，以決定是否將適當電壓提供至每一所述多個記憶胞單元的所述第一記憶胞以及所述第二記憶胞。In an embodiment of the invention, the first word line and the second word line of each of the plurality of memory cells respectively pass through the fourth N-type transistor and the fifth N-type transistor. The first memory cell and the second memory cell of each of the plurality of memory cells are coupled. The first word line and the second word line are respectively used to provide an appropriate voltage for a read operation, a write operation, or an erase operation. The fourth N-type transistor and the fifth N-type transistor respectively receive the selection signal by the control terminal to determine whether to provide an appropriate voltage to the first of each of the plurality of memory cells The memory cell and the second memory cell.
在本發明的一實施例中，上述的第一字元信號以及第二字元信號為相同信號。In an embodiment of the invention, the first character signal and the second character signal are the same signal.
在本發明的一實施例中，上述的第一字元信號以及第二字元信號為不同信號。In an embodiment of the invention, the first character signal and the second character signal are different signals.
在本發明的一實施例中，當上述多個記憶胞區塊的其中之一被選擇操作在所述寫入操作時，所述多個記憶胞區塊的其中之一接收的所述選擇信號的電壓高於或等於控制閘極電壓加上所述N型電晶體的臨界電壓。In an embodiment of the invention, when one of the plurality of memory cell blocks is selectively operated in the writing operation, the selection signal received by one of the plurality of memory cell blocks is received The voltage is higher than or equal to the control gate voltage plus the threshold voltage of the N-type transistor.
在本發明的一實施例中，當上述多個記憶胞區塊的其中之一被選擇操作在所述抹除操作時，所述多個記憶胞區塊的其中之一接收的所述選擇信號的電壓高於或等於抹除電壓加上所述N型電晶體的臨界電壓。In an embodiment of the invention, when one of the plurality of memory cells is selectively operated in the erase operation, the selection signal received by one of the plurality of memory cells is received The voltage is higher than or equal to the erase voltage plus the threshold voltage of the N-type transistor.
基於上述，本發明的非揮發性記憶體裝置包括多個記憶胞區塊。本發明的非揮發性記憶體裝置可藉由多個N型電晶體來獨立控制每一個記憶胞區塊的操作模式。也就是說，本發明的非揮發性記憶體裝置可區域性的執行資料讀取操作、資料寫入操作或資料抹除操作。Based on the above, the non-volatile memory device of the present invention includes a plurality of memory cell blocks. The non-volatile memory device of the present invention can independently control the operation mode of each memory cell block by a plurality of N-type transistors. That is, the non-volatile memory device of the present invention can perform a data reading operation, a data writing operation, or a data erasing operation regionally.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
以下提出多個實施例來說明本發明，然而本發明不限於所例示的多個實施例。又實施例之間也允許有適當的結合。在本案說明書全文（包括申請專利範圍）中所使用的「耦接」一詞可指任何直接或間接的連接手段。舉例而言，若文中描述第一裝置耦接至第二裝置，則應該被解釋成該第一裝置可以直接連接於該第二裝置，或者該第一裝置可以透過其他裝置或某種連接手段而間接地連接至該第二裝置。此外，「信號」一詞可指至少一電流、電壓、電荷、溫度、資料、或任何其他一或多個信號。The following examples are presented to illustrate the invention, but the invention is not limited to the illustrated embodiments. Further combinations are also allowed between the embodiments. The term "coupled" as used throughout the specification (including the scope of the patent application) may be used in any direct or indirect connection. For example, if the first device is described as being coupled to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be connected through other devices or some means of connection. Connected to the second device indirectly. Furthermore, the term "signal" can refer to at least one current, voltage, charge, temperature, data, or any other signal or signals.
圖1A為依照本發明之第一實施例所繪示的一種非揮發性記憶體裝置的電路圖。請參照圖1A，非揮發性記憶體裝置100包括多個記憶胞區塊，並且這些記憶胞區塊排列配置為記憶胞陣列。在本實施例中，一個記憶胞區塊110包括多個記憶胞單元111、位元線BL000、BL001~BL00N、第一字元線WL1、第二字元線WL2。位元線的數量等於記憶胞單元的數量，其中N為大於0的正整數。在本實施例中，一個記憶胞單元111耦接一個位元線。在記憶胞陣列中的每一行的記憶胞區塊110各別透過選擇信號線BSEL接收選擇信號，並且各別依據選擇信號來決定是否執行讀取操作(read)、寫入操作(program)或抹除操作(erase)，以使非揮發性記憶體裝置100可執行區域性的資料讀取、資料寫入或資料抹除。並且，在本實施例中，記憶胞區塊110更包括區域抹除閘極線EGL、區域控制源極線CSL以及區域控制閘極線CGL。1A is a circuit diagram of a non-volatile memory device in accordance with a first embodiment of the present invention. Referring to FIG. 1A, the non-volatile memory device 100 includes a plurality of memory cell blocks, and the memory cell blocks are arranged in a memory cell array. In this embodiment, one memory cell block 110 includes a plurality of memory cell units 111, bit lines BL000, BL001 to BL00N, a first word line WL1, and a second word line WL2. The number of bit lines is equal to the number of memory cells, where N is a positive integer greater than zero. In this embodiment, one memory cell unit 111 is coupled to one bit line. The memory cell block 110 of each row in the memory cell array receives the selection signal through the selection signal line BSEL, and each determines whether to perform a read operation, a write operation, or a wipe according to the selection signal. In addition to the operation, the non-volatile memory device 100 can perform regional data reading, data writing, or data erasing. Moreover, in the embodiment, the memory cell block 110 further includes an area erase gate line EGL, a region control source line CSL, and a region control gate line CGL.
在本實施例中，在記憶胞陣列中的每一行(row)的記憶胞區塊110設置一個選擇信號線，並且在每一行當中的每一個記憶胞單元111設置一個位元線。在記憶胞陣列中的每一列(column)的記憶胞區塊110設置一個第一字元線WL1以及第二字元線WL2。基於上述各電壓信號條件，本實施例的非揮發性記憶體裝置100的各個記憶胞區塊110可獨立執行讀取操作、寫入操作或抹除操作。並且，本實施例的第一記憶胞MC1以及第二記憶胞MC2可用以接收相同字元信號，以使儲存相同資料信號，但本發明並不限於此。在一實施例中，第一記憶胞MC1以及第二記憶胞MC2也可分別透過第一字元線WL1以及第二字元線WL2接收不同字元信號，以分別儲存不同資料信號。In the present embodiment, one selection signal line is set in each of the memory cell blocks 110 in the memory cell array, and one bit line is provided in each of the memory cells 111 in each of the rows. A memory cell block 110 of each column in the memory cell array is provided with a first word line WL1 and a second word line WL2. Based on the above-described respective voltage signal conditions, each of the memory cell blocks 110 of the non-volatile memory device 100 of the present embodiment can independently perform a read operation, a write operation, or an erase operation. Moreover, the first memory cell MC1 and the second memory cell MC2 of the present embodiment can be used to receive the same word signal so that the same data signal is stored, but the present invention is not limited thereto. In an embodiment, the first memory cell MC1 and the second memory cell MC2 can also receive different word signals through the first word line WL1 and the second word line WL2, respectively, to store different data signals.
在本實施例中，區域抹除閘極線EGL用以提供抹除電壓。區域抹除閘極線EGL透過第一N型電晶體121耦接記憶胞區塊110當中的記憶胞單元111的第一記憶胞MC1以及第二記憶胞MC2各別的抹除閘極。在本實施例中，第一N型電晶體121藉由控制端自選擇信號線BSEL接收選擇信號，以決定是否透過抹除閘極線EGL提供抹除電壓至記憶胞單元111的第一記憶胞MC1以及第二記憶胞MC2各別的抹除閘極。In this embodiment, the area erase gate line EGL is used to provide an erase voltage. The area erase gate line EGL is coupled to the first memory cell MC1 of the memory cell unit 111 and the erase electrode of the second memory cell MC2 in the memory cell block 110 through the first N-type transistor 121. In this embodiment, the first N-type transistor 121 receives the selection signal from the selection signal line BSEL through the control terminal to determine whether to provide the erase voltage to the first memory cell of the memory cell unit 111 by erasing the gate line EGL. The gates of the MC1 and the second memory cell MC2 are erased.
在本實施例中，區域控制源極線CSL用以提供源極信號。區域控制源極線CSL透過第二N型電晶體122耦接記憶胞單元111的共用源極。在本實施例中，第二N型電晶體122藉由控制端自選擇信號線BSEL接收選擇信號，以決定是否透過區域控制源極線CSL將源極信號提供至記憶胞單元111的共用源極。In this embodiment, the area control source line CSL is used to provide a source signal. The area control source line CSL is coupled to the common source of the memory cell unit 111 through the second N-type transistor 122. In this embodiment, the second N-type transistor 122 receives the selection signal from the selection signal line BSEL through the control terminal to determine whether to provide the source signal to the common source of the memory cell unit 111 through the region control source line CSL. .
在本實施例中，區域控制閘極線CGL用以提供閘極信號。區域控制閘極線CGL透過第三N型電晶體123耦接記憶胞單元111的控制閘極。在本實施例中，第三N型電晶體123藉由控制端自選擇信號線BSEL接收選擇信號，以決定是否透過區域控制閘極線CGL將閘極信號提供至記憶胞單元111的控制閘極。In this embodiment, the area control gate line CGL is used to provide a gate signal. The area control gate line CGL is coupled to the control gate of the memory cell unit 111 through the third N-type transistor 123. In this embodiment, the third N-type transistor 123 receives the selection signal from the selection signal line BSEL through the control terminal to determine whether to provide the gate signal to the control gate of the memory cell unit 111 through the region control gate line CGL. .
在本實施例中，第一N型電晶體121、第二N型電晶體122以及第三N型電晶體123為N型金屬氧化物半導體場效電晶體(N type Metal-Oxide-Semiconductor Field-Effect Transistor, NMOS)。In the present embodiment, the first N-type transistor 121, the second N-type transistor 122, and the third N-type transistor 123 are N-type metal-oxide-type field effect transistors (N type Metal-Oxide-Semiconductor Field- Effect Transistor, NMOS).
據此，本實施例的在記憶胞陣列中的每一列(column)的記憶胞區塊110的每一個記憶胞單元111可選擇性的單獨進行資料寫入操作以及資料抹除操作。因此，本實施例的非揮發性記憶體裝置100可具有字元抹除(byte erase)的功能。並且，本實施例的非揮發性記憶體裝置100於寫入操作時，可有效降低寫入干擾的影響(program disturb less)。Accordingly, each of the memory cell units 111 of each column of the memory cell block 110 in the memory cell array of the present embodiment can selectively perform a data writing operation and a data erasing operation separately. Therefore, the non-volatile memory device 100 of the present embodiment can have a function of byte erase. Moreover, the non-volatile memory device 100 of the present embodiment can effectively reduce the influence of the write disturbance during the write operation.
為了使所屬技術領域的通常知識者可進一步了解本實施例所述具有字元抹除與減少寫入干擾的非揮發性記憶體裝置，因此以下進一步舉出各電壓偏壓條件的一實施範例說明之，但本發明並不限於此。下表1記載圖1A實施例當中的字元線WL1、WL2、位元線BL000、區域抹除閘極線EGL、區域控制閘極線CGL、區域控制源極線CSL以及選擇信號線BSEL分別在不同操作模式下提供的電壓偏壓條件。
依據上述表1，符號Se1代表被選擇到的記憶胞單元的電壓偏壓條件。符號Unsel代表未被選擇到的記憶體單元的電壓信號條件。符號VCC代表系統電壓。符號VWLP代表字元寫入電壓。符號VBLR代表位元讀取電壓。符號IBL代表位元寫入電流。符號VCGP代表控制閘極寫入電壓。符號VCSP代表控制源極寫入電壓。符號VEPE代表抹除閘極抹除電壓。符號Vt代表N型電晶體的臨界電壓。According to Table 1 above, the symbol Se1 represents the voltage bias condition of the selected memory cell. The symbol Unsel represents the voltage signal condition of the memory cell that is not selected. The symbol VCC represents the system voltage. The symbol VWLP represents the character write voltage. The symbol VBLR represents the bit read voltage. The symbol IBL represents the bit write current. The symbol VCGP represents the control gate write voltage. The symbol VCSP represents the control source write voltage. The symbol VEPE represents the erase gate erase voltage. The symbol Vt represents the threshold voltage of the N-type transistor.
依據上述表1，選擇信號線BSEL提供的選擇信號可依據不同操作模式來決定。舉例來說，當記憶胞區塊110被選擇操作在讀取操作時，記憶胞區塊110接收的選擇信號的高於或等於系統電壓VCC加上N型電晶體的臨界電壓Vt。當記憶胞區塊110被選擇操作在寫入操作時，記憶胞區塊110接收的選擇信號的電壓高於或等於控制閘極電壓VCGP加上N型電晶體的臨界電壓Vt。當記憶胞區塊110被選擇操作在抹除操作時，記憶胞區塊110接收的選擇信號的電壓高於或等於抹除電壓VEPE加上N型電晶體的臨界電壓Vt。According to Table 1 above, the selection signal provided by the selection signal line BSEL can be determined according to different operation modes. For example, when the memory cell block 110 is selectively operated in a read operation, the memory cell block 110 receives a selection signal that is higher than or equal to the system voltage VCC plus the threshold voltage Vt of the N-type transistor. When the memory cell block 110 is selectively operated in a write operation, the voltage of the selection signal received by the memory cell block 110 is higher than or equal to the control gate voltage VCGP plus the threshold voltage Vt of the N-type transistor. When the memory cell block 110 is selectively operated in the erase operation, the voltage of the selection signal received by the memory cell block 110 is higher than or equal to the erase voltage VEPE plus the threshold voltage Vt of the N-type transistor.
再舉例來說，在一實施例中，上述的位元讀取電壓VBLR可為0.5~1伏特(V)。上述的字元寫入電壓VWLP可為0.8~1.5伏特。上述的位元寫入電流可為1~5微安培(uA)。上述的控制閘極寫入電壓VCGP可為7~10伏特。上述的控制源極寫入電壓VCSP可為4~6伏特。上述的抹除閘極抹除電壓VEPE可為9~12伏特。然而，上述各電壓偏壓條件可依據不同電路規格或產品需求對應設計之，本發明並不限於此。For another example, in an embodiment, the bit read voltage VBLR may be 0.5 to 1 volt (V). The above-described character write voltage VWLP may be 0.8 to 1.5 volts. The above described bit write current can be 1 to 5 microamperes (uA). The above-mentioned control gate write voltage VCGP can be 7-10 volts. The above-mentioned control source write voltage VCSP can be 4-6 volts. The above erase gate erase voltage VEPE can be 9-12 volts. However, the above various voltage bias conditions may be designed according to different circuit specifications or product requirements, and the present invention is not limited thereto.
圖1B為依照本發明之第一實施例所繪示的另一種非揮發性記憶體裝置的電路圖。請參照圖1B，非揮發性記憶體裝置100包括多個記憶胞區塊，並且這些記憶胞區塊排列配置為記憶胞陣列。在本實施例中，一個記憶胞區塊110包括多個記憶胞單元111、位元線BL000、BL001~BL00N、第一字元線WL1、第二字元線WL2。位元線的數量等於記憶胞單元的數量，其中N為大於0的正整數。在本實施例中，一個記憶胞單元111耦接一個位元線。在記憶胞陣列中的每一行的記憶胞區塊110各別透過選擇信號線BSEL接收選擇信號，並且各別依據選擇信號來決定是否執行讀取操作、寫入操作或抹除操作，以使非揮發性記憶體裝置100可執行區域性的資料讀取、資料寫入或資料抹除。並且，在本實施例中，記憶胞區塊110更包括區域抹除閘極線EGL以及區域控制源極線CSL。FIG. 1B is a circuit diagram of another non-volatile memory device according to a first embodiment of the present invention. Referring to FIG. 1B, the non-volatile memory device 100 includes a plurality of memory cell blocks, and the memory cell blocks are arranged in a memory cell array. In this embodiment, one memory cell block 110 includes a plurality of memory cell units 111, bit lines BL000, BL001 to BL00N, a first word line WL1, and a second word line WL2. The number of bit lines is equal to the number of memory cells, where N is a positive integer greater than zero. In this embodiment, one memory cell unit 111 is coupled to one bit line. The memory cell block 110 of each row in the memory cell array receives the selection signal through the selection signal line BSEL, and each determines whether to perform a read operation, a write operation or an erase operation according to the selection signal, so as to The volatile memory device 100 can perform regional data reading, data writing, or data erasing. Moreover, in the embodiment, the memory cell block 110 further includes an area erase gate line EGL and a region control source line CSL.
在本實施例中，區域抹除閘極線EGL用以提供抹除電壓。區域抹除閘極線EGL透過第一N型電晶體121耦接記憶胞區塊110當中的記憶胞單元111的第一記憶胞MC1以及第二記憶胞MC2各別的抹除閘極。在本實施例中，第一N型電晶體121藉由控制端自選擇信號線BSEL接收選擇信號，以決定是否透過抹除閘極線EGL提供抹除電壓至記憶胞單元111的第一記憶胞MC1以及第二記憶胞MC2各別的抹除閘極。In this embodiment, the area erase gate line EGL is used to provide an erase voltage. The area erase gate line EGL is coupled to the first memory cell MC1 of the memory cell unit 111 and the erase electrode of the second memory cell MC2 in the memory cell block 110 through the first N-type transistor 121. In this embodiment, the first N-type transistor 121 receives the selection signal from the selection signal line BSEL through the control terminal to determine whether to provide the erase voltage to the first memory cell of the memory cell unit 111 by erasing the gate line EGL. The gates of the MC1 and the second memory cell MC2 are erased.
在本實施例中，區域控制源極線CSL用以提供源極信號。區域控制源極線CSL透過第二N型電晶體122耦接記憶胞單元111的共用源極。在本實施例中，第二N型電晶體122藉由控制端自選擇信號線BSEL接收選擇信號，以決定是否透過區域控制源極線CSL將源極信號提供至記憶胞單元111的共用源極。In this embodiment, the area control source line CSL is used to provide a source signal. The area control source line CSL is coupled to the common source of the memory cell unit 111 through the second N-type transistor 122. In this embodiment, the second N-type transistor 122 receives the selection signal from the selection signal line BSEL through the control terminal to determine whether to provide the source signal to the common source of the memory cell unit 111 through the region control source line CSL. .
相較於圖1A實施例，本實施例的每一列的記憶胞區塊110的每一個記憶胞單元111的控制閘極分別耦接同一條信號線，並且耦接至區域控制源極線CSL，以將區域控制源極線CSL提供的源極信號作為閘極信號。也就是說，本實施例的每一列的記憶胞區塊110的每一個記憶胞單元111的共用源極與控制閘極由區域控制源極線CSL接收相同控制信號。The control gates of each of the memory cell units 111 of the memory cell block 110 of each column of the present embodiment are coupled to the same signal line and coupled to the area control source line CSL, respectively, as compared with the embodiment of FIG. The source signal supplied from the area control source line CSL is used as a gate signal. That is to say, the common source and the control gate of each of the memory cell units 111 of the memory cell block 110 of each column of the present embodiment receive the same control signal from the area control source line CSL.
為了使所屬技術領域的通常知識者可進一步了解本實施例所述具有字元抹除與減少寫入干擾的非揮發性記憶體裝置，因此以下進一步舉出各電壓偏壓條件的一實施範例說明之，但本發明並不限於此。下表2記載圖1B實施例當中的字元線WL1、WL2、位元線BL000、區域抹除閘極線EGL、區域控制源極線CSL以及選擇信號線BSEL分別在不同操作模式下提供的電壓偏壓條件。
依據上述表2，選擇信號線BSEL提供的選擇信號可依據不同操作模式來決定。並且，有關於本實施例的選擇信號的各種偏壓條件、選擇信號線、位元線以及字元線相關技術特徵以及實施方式可參照上述圖1A實施例之敘述中獲致足夠的教示、建議與實施說明，因此不再贅述。According to Table 2 above, the selection signal provided by the selection signal line BSEL can be determined according to different operation modes. Further, various bias conditions, selection signal lines, bit lines, and word line related technical features and embodiments of the selection signal of the present embodiment can be obtained with sufficient teaching, suggestions, and suggestions in the description of the embodiment of FIG. 1A. Implementation instructions, so I won't go into details.
圖2為依照本發明之第二實施例所繪示的一種非揮發性記憶體裝置的電路圖。請參照圖2，非揮發性記憶體裝置200包括多個記憶胞區塊，並且這些記憶胞區塊排列配置為記憶胞陣列。在本實施例中，一個記憶胞區塊210包括多個記憶胞單元211、位元線BL000、BL001~BL00N、第一字元線WL1、第二字元線WL2。位元線的數量等於記憶胞單元的數量，其中N為大於0的正整數。在本實施例中，一個記憶胞單元211耦接一個位元線。在記憶胞陣列中的每一行的記憶胞區塊210各別透過選擇信號線BSEL接收選擇信號，並且各別依據選擇信號來決定是否執行讀取操作、寫入操作或抹除操作，以使非揮發性記憶體裝置100可執行區域性的資料讀取、資料寫入或資料抹除。並且，在本實施例中，記憶胞區塊210更包括區域抹除閘極線EGL、全域控制源極線CSL’以及區域控制閘極線CGL。2 is a circuit diagram of a non-volatile memory device in accordance with a second embodiment of the present invention. Referring to FIG. 2, the non-volatile memory device 200 includes a plurality of memory cell blocks, and the memory cell blocks are arranged to be arranged as a memory cell array. In this embodiment, one memory cell block 210 includes a plurality of memory cell units 211, bit lines BL000, BL001~BL00N, a first word line WL1, and a second word line WL2. The number of bit lines is equal to the number of memory cells, where N is a positive integer greater than zero. In this embodiment, one memory cell unit 211 is coupled to one bit line. The memory cell block 210 of each row in the memory cell array receives the selection signal through the selection signal line BSEL, and each determines whether to perform a read operation, a write operation or an erase operation according to the selection signal, so as to The volatile memory device 100 can perform regional data reading, data writing, or data erasing. Moreover, in the embodiment, the memory cell block 210 further includes an area erase gate line EGL, a global control source line CSL', and a region control gate line CGL.
在本實施例中，區域抹除閘極線EGL用以提供抹除電壓。區域抹除閘極線EGL透過第一N型電晶體221耦接記憶胞區塊210當中的記憶胞單元211的第一記憶胞MC1以及第二記憶胞MC2各別的抹除閘極。在本實施例中，第一N型電晶體221藉由控制端自選擇信號線BSEL接收選擇信號，以決定是否透過抹除閘極線EGL提供抹除電壓至記憶胞單元211的第一記憶胞MC1以及第二記憶胞MC2各別的抹除閘極。In this embodiment, the area erase gate line EGL is used to provide an erase voltage. The area erase gate line EGL is coupled to the first memory cell MC1 of the memory cell unit 211 and the erase electrode of the second memory cell MC2 in the memory cell block 210 through the first N-type transistor 221 . In this embodiment, the first N-type transistor 221 receives the selection signal from the selection signal line BSEL through the control terminal to determine whether to provide the erase voltage to the first memory cell of the memory cell unit 211 through the erase gate line EGL. The gates of the MC1 and the second memory cell MC2 are erased.
在本實施例中，每一列的記憶胞區塊210設置一個全域控制源極線CSL’。相較於圖1A實施例，本實施例的全域控制源極線CSL’用以提供源極信號至每一列的記憶胞區塊210當中的每一個記憶胞單元211的共用源極。In the present embodiment, each column of memory cells 210 is provided with a global control source line CSL'. Compared to the embodiment of FIG. 1A, the global control source line CSL' of the present embodiment is used to provide a source signal to the common source of each of the memory cells 211 of the memory cell block 210 of each column.
在本實施例中，區域控制閘極線CGL用以提供閘極信號。區域控制閘極線CGL透過第三N型電晶體223耦接記憶胞單元211的控制閘極。在本實施例中，第三N型電晶體223藉由控制端自選擇信號線BSEL接收選擇信號，以決定是否透過區域控制閘極線CGL將閘極信號提供至記憶胞單元211的控制閘極。In this embodiment, the area control gate line CGL is used to provide a gate signal. The area control gate line CGL is coupled to the control gate of the memory cell unit 211 through the third N-type transistor 223. In this embodiment, the third N-type transistor 223 receives the selection signal from the selection signal line BSEL through the control terminal to determine whether to provide the gate signal to the control gate of the memory cell unit 211 through the region control gate line CGL. .
為了使所屬技術領域的通常知識者可進一步了解本實施例所述具有字元抹除與減少寫入干擾的非揮發性記憶體裝置，因此以下進一步舉出各電壓偏壓條件的一實施範例說明之，但本發明並不限於此。下表3記載圖2實施例當中的字元線WL1、WL2、位元線BL000、區域抹除閘極線EGL、區域控制閘極線CGL、全域控制源極線CSL’以及選擇信號線BSEL分別在不同操作模式下提供的電壓偏壓條件。
依據上述表3，選擇信號線BSEL提供的選擇信號可依據不同操作模式來決定。有關於本實施例的選擇信號的各種偏壓條件、選擇信號線、位元線以及字元線相關技術特徵以及實施方式可參照上述圖1A實施例之敘述中獲致足夠的教示、建議與實施說明，因此不再贅述。According to Table 3 above, the selection signal provided by the selection signal line BSEL can be determined according to different operation modes. For various bias conditions, selection signal lines, bit lines, and word line related technical features and embodiments of the selection signal of the present embodiment, sufficient teaching, suggestions, and implementation instructions can be obtained by referring to the description of the embodiment of FIG. 1A above. Therefore, I will not repeat them.
圖3A為依照本發明之第一實施例以及第二實施例所繪示的一種記憶胞的結構示意圖。圖3B為依照本發明之第一實施例以及第二實施例所繪示的另一種記憶胞的結構示意圖。FIG. 3A is a schematic structural diagram of a memory cell according to a first embodiment and a second embodiment of the present invention. FIG. 3B is a schematic structural diagram of another memory cell according to the first embodiment and the second embodiment of the present invention.
請參照圖3A，第一實施例以及第二實施例所適用的記憶胞的詳細結構可如圖3A所示。在圖3A實施例中，記憶胞MC1以及記憶胞MC2具有對稱結構，其中記憶胞MC1以及記憶胞MC2各別包括堆疊結構320、輔助閘介電層330、抹除閘介電層332、浮置閘極340、穿隧介電層342、共用源極CS、汲極348、控制閘極CG以及閘間介電層352。此外，基底300上更具有層間絕緣層360、插塞362與位元線364。堆疊結構320從基底300起依序由閘介電層322、輔助閘極324、絕緣層326以及抹除閘極EP構成。閘介電層322例如是設置於輔助閘極324與基底300之間。閘介電層322的材質例如是氧化矽。閘介電層322的厚度例如小於或等於穿隧介電層342的厚度。其中浮置閘極340例如是設置於堆疊結構320之第一側的側壁，且此浮置閘極340的頂部具有轉角部341。抹除閘極EP包覆浮置閘極340的轉角部341。此轉角部341角度小於或等於90度。Referring to FIG. 3A, the detailed structure of the memory cell to which the first embodiment and the second embodiment are applied may be as shown in FIG. 3A. In the embodiment of FIG. 3A, the memory cell MC1 and the memory cell MC2 have a symmetrical structure, wherein the memory cell MC1 and the memory cell MC2 respectively include a stacked structure 320, an auxiliary gate dielectric layer 330, an erase gate dielectric layer 332, and a floating Gate 340, tunnel dielectric layer 342, common source CS, drain 348, control gate CG, and gate dielectric layer 352. In addition, the substrate 300 further has an interlayer insulating layer 360, a plug 362 and a bit line 364. The stacked structure 320 is sequentially composed of the gate dielectric layer 322, the auxiliary gate 324, the insulating layer 326, and the erase gate EP from the substrate 300. The gate dielectric layer 322 is disposed, for example, between the auxiliary gate 324 and the substrate 300. The material of the gate dielectric layer 322 is, for example, hafnium oxide. The thickness of the gate dielectric layer 322 is, for example, less than or equal to the thickness of the tunneling dielectric layer 342. The floating gate 340 is, for example, a sidewall disposed on a first side of the stacked structure 320, and the top of the floating gate 340 has a corner portion 341. The corner portion 341 of the gate electrode 340 is wiped off by the gate EP. The angle of the corner portion 341 is less than or equal to 90 degrees.
在本實施例中，抹除閘極EP耦接上述第一實施例以及第二實施例的抹除閘極線。共用源極CS耦接上述第一實施例以及第二實施例所述的控制源極線。控制閘極CG耦接上述第一實施例以及第二實施例所述的控制閘極線。輔助閘極324耦接上述第一實施例以及第二實施例所述的字元線。位元線364為上述第一實施例以及第二實施例所述位元線。In the present embodiment, the erase gate EP is coupled to the erase gate lines of the first embodiment and the second embodiment described above. The common source CS is coupled to the control source lines described in the first embodiment and the second embodiment. The control gate CG is coupled to the control gate lines described in the first embodiment and the second embodiment. The auxiliary gate 324 is coupled to the word lines described in the first embodiment and the second embodiment. The bit line 364 is the bit line described in the first embodiment and the second embodiment described above.
請參照圖3B，第一實施例以及第二實施例所適用的記憶胞的詳細結構亦可如圖3B所示。在圖3B實施例中，記憶胞MC1以及記憶胞MC2具有對稱結構，其中記憶胞MC1以及記憶胞MC2各別包括堆疊結構320’、輔助閘介電層330’、抹除閘介電層332’、浮置閘極340’、穿隧介電層342’、共用源極CS、汲極348’、控制閘極CG以及閘間介電層352’。此外，基底300’上更具有層間絕緣層360’、插塞362’與位元線364’。堆疊結構320’從基底300’起依序由閘介電層322’、輔助閘極324’、絕緣層326’以及抹除閘極EP構成。閘介電層322’例如是設置於輔助閘極324’與基底300’之間。閘介電層322’的材質例如是氧化矽。閘介電層322’的厚度例如小於或等於穿隧介電層342’的厚度。浮置閘極340’例如是設置於堆疊結構320’之第一側的側壁，且此浮置閘極340’的頂部具有轉角部341’。此轉角部341’鄰近抹除閘極EP，且此轉角部341’高度落於抹除閘極EP高度間。此轉角部341’角度小於或等於90度。Referring to FIG. 3B, the detailed structure of the memory cell to which the first embodiment and the second embodiment are applied may also be as shown in FIG. 3B. In the embodiment of FIG. 3B, the memory cell MC1 and the memory cell MC2 have a symmetric structure, wherein the memory cell MC1 and the memory cell MC2 respectively include a stacked structure 320', an auxiliary gate dielectric layer 330', and an erase gate dielectric layer 332'. The floating gate 340', the tunneling dielectric layer 342', the common source CS, the drain 348', the control gate CG, and the inter-gate dielectric layer 352'. Further, the substrate 300' further has an interlayer insulating layer 360', a plug 362' and a bit line 364'. The stacked structure 320' is sequentially composed of a gate dielectric layer 322', an auxiliary gate 324', an insulating layer 326', and an erase gate EP from the substrate 300'. The gate dielectric layer 322' is disposed, for example, between the auxiliary gate 324' and the substrate 300'. The material of the gate dielectric layer 322' is, for example, hafnium oxide. The thickness of the gate dielectric layer 322' is, for example, less than or equal to the thickness of the tunnel dielectric layer 342'. The floating gate 340' is, for example, a sidewall disposed on the first side of the stacked structure 320', and the top of the floating gate 340' has a corner portion 341'. The corner portion 341' is adjacent to the erase gate EP, and the corner portion 341' is horizontally located between the erase gate EP heights. The angle of the corner portion 341' is less than or equal to 90 degrees.
值得注意的是，圖3A以及圖3B的記憶胞的具體結構可適用於圖1A、1B實施例以及圖2實施例的記憶胞，但本發明並不限於此。上述圖1A、1B實施例以及圖2實施例的記憶胞的結構特徵也可依據使用者需求以及記憶體電路配置方式對應設計之。It is to be noted that the specific structure of the memory cell of FIGS. 3A and 3B can be applied to the memory cells of the embodiment of FIGS. 1A, 1B and the embodiment of FIG. 2, but the present invention is not limited thereto. The structural features of the memory cell of the embodiment of FIGS. 1A and 1B and the embodiment of FIG. 2 can also be designed according to user requirements and memory circuit configuration.
圖4為依照本發明之第三實施例所繪示的一種非揮發性記憶體裝置的電路圖。請參照圖4，非揮發性記憶體裝置400包括多個記憶胞區塊，並且這些記憶胞區塊排列配置為記憶胞陣列。在本實施例中，一個記憶胞區塊410包括多個記憶胞單元411、位元線BL000、BL001~BL00N、第一字元線WL1、第二字元線WL2。位元線的數量等於記憶胞單元的數量，其中N為大於0的正整數。在本實施例中，一個記憶胞單元411耦接一個位元線。在記憶胞陣列中的每一行的記憶胞區塊410各別透過選擇信號線BSEL接收選擇信號，並且各別依據選擇信號來決定是否執行讀取操作、寫入操作或抹除操作，以使非揮發性記憶體裝置400可執行區域性的資料讀取、資料寫入或資料抹除。並且，在本實施例中，記憶胞區塊410更包括區域抹除閘極線EGL以及區域控制源極線CSL。4 is a circuit diagram of a non-volatile memory device in accordance with a third embodiment of the present invention. Referring to FIG. 4, the non-volatile memory device 400 includes a plurality of memory cell blocks, and the memory cell blocks are arranged to be a memory cell array. In this embodiment, one memory cell block 410 includes a plurality of memory cell units 411, bit lines BL000, BL001~BL00N, a first word line WL1, and a second word line WL2. The number of bit lines is equal to the number of memory cells, where N is a positive integer greater than zero. In this embodiment, one memory cell unit 411 is coupled to one bit line. The memory cell block 410 of each row in the memory cell array receives the selection signal through the selection signal line BSEL, and each determines whether to perform a read operation, a write operation or an erase operation according to the selection signal, so as to The volatile memory device 400 can perform regional data reading, data writing, or data erasing. Moreover, in the embodiment, the memory cell block 410 further includes an area erase gate line EGL and a region control source line CSL.
在本實施例中，區域抹除閘極線EGL透過第一N型電晶體421耦接記憶胞單元411，以及區域控制源極線CSL透過第二N型電晶體422耦接記憶胞單元411。然而，相較於上述圖1實施例，本實施例的非揮發性記憶體裝置400不包括區域控制閘極線CGL。本實施例的其他相關電路特徵以及操作方法可參照上述圖1實施例之敘述中獲致足夠的教示、建議與實施說明，因此不再贅述。In the present embodiment, the area erase gate line EGL is coupled to the memory cell unit 411 through the first N-type transistor 421, and the area control source line CSL is coupled to the memory cell unit 411 through the second N-type transistor 422. However, the non-volatile memory device 400 of the present embodiment does not include the area control gate line CGL as compared to the above-described embodiment of FIG. For other related circuit features and operation methods of the present embodiment, sufficient teachings, suggestions, and implementation descriptions may be obtained by referring to the description of the embodiment of FIG. 1 described above, and thus no further description is provided.
為了使所屬技術領域的通常知識者可進一步了解本實施例所述具有字元抹除與減少寫入干擾的非揮發性記憶體裝置，因此以下進一步舉出各電壓偏壓條件的一實施範例說明之，但本發明並不限於此。下表4記載圖4實施例當中的字元線WL1、WL2、位元線BL000、區域抹除閘極線EGL、區域控制源極線CSL以及選擇信號線BSEL分別在不同操作模式下提供的電壓偏壓條件。
依據上述表4，選擇信號線BSEL提供的選擇信號可依據不同操作模式來決定。並且，有關於本實施例的選擇信號的各種偏壓條件、選擇信號線、位元線以及字元線相關技術特徵以及實施方式可參照上述圖1A實施例之敘述中獲致足夠的教示、建議與實施說明，因此不再贅述。According to Table 4 above, the selection signal provided by the selection signal line BSEL can be determined according to different operation modes. Further, various bias conditions, selection signal lines, bit lines, and word line related technical features and embodiments of the selection signal of the present embodiment can be obtained with sufficient teaching, suggestions, and suggestions in the description of the embodiment of FIG. 1A. Implementation instructions, so I won't go into details.
圖5A為依照本發明之第三實施例所繪示的一種記憶胞的結構示意圖。圖5B為依照本發明之第三實施例所繪示的另一種記憶胞的結構示意圖。FIG. 5A is a schematic structural diagram of a memory cell according to a third embodiment of the present invention. FIG. 5B is a schematic structural diagram of another memory cell according to a third embodiment of the present invention.
請參照圖5A，上述圖4實施例所適用的記憶胞的詳細結構可例如圖5A所示。在本實施例中，記憶胞MC1以及記憶胞MC2具有對稱結構，其中記憶胞MC1以及記憶胞MC2各別包括堆疊結構520、輔助閘介電層530、抹除閘介電層532、浮置閘極540、穿隧介電層542、共用源極CS、汲極548以及閘間介電層552。此外，基底500上更具有層間絕緣層560、插塞562與位元線564。堆疊結構520從基底500起依序由閘介電層522、輔助閘極524、絕緣層526以及抹除閘極EP構成。然而，相較於圖3A實施例，本實施例的記憶胞MC1以及記憶胞MC2不包括控制閘極。另外，本實施例的相關記憶胞的各結構的詳細描述可參照上述圖3A實施例之敘述中獲致足夠的教示、建議與實施說明，因此不再贅述。Referring to FIG. 5A, the detailed structure of the memory cell to which the above-described embodiment of FIG. 4 is applied may be, for example, as shown in FIG. 5A. In this embodiment, the memory cell MC1 and the memory cell MC2 have a symmetrical structure, wherein the memory cell MC1 and the memory cell MC2 respectively include a stacked structure 520, an auxiliary gate dielectric layer 530, an erase gate dielectric layer 532, and a floating gate. The pole 540, the tunneling dielectric layer 542, the common source CS, the drain 548, and the inter-gate dielectric layer 552. In addition, the substrate 500 further has an interlayer insulating layer 560, a plug 562 and a bit line 564. The stacked structure 520 is sequentially composed of the gate dielectric layer 522, the auxiliary gate 524, the insulating layer 526, and the erase gate EP from the substrate 500. However, compared to the embodiment of FIG. 3A, the memory cell MC1 and the memory cell MC2 of the present embodiment do not include a control gate. In addition, a detailed description of each structure of the associated memory cell of the present embodiment can be referred to the description of the embodiment of FIG. 3A to obtain sufficient teaching, suggestion, and implementation description, and thus will not be described again.
請參照圖5B，上述圖4實施例所適用的記憶胞的詳細結構也可例如圖5B所示。在本實施例中，記憶胞MC1以及記憶胞MC2具有對稱結構，其中記憶胞MC1以及記憶胞MC2各別包括堆疊結構520’、輔助閘介電層530’、抹除閘介電層532’、浮置閘極540’、穿隧介電層542’、共用源極CS、汲極548’以及閘間介電層552’。此外，基底500’上更具有層間絕緣層560’、插塞562’與位元線564’。堆疊結構520’從基底500’起依序由閘介電層522’、輔助閘極524’、絕緣層526’以及抹除閘極EP構成。然而，相較於圖3B實施例，本實施例的記憶胞MC1以及記憶胞MC2不包括控制閘極。另外，本實施例的相關記憶胞的各結構的詳細描述可參照上述圖3B實施例之敘述中獲致足夠的教示、建議與實施說明，因此不再贅述。Referring to FIG. 5B, the detailed structure of the memory cell to which the above-described embodiment of FIG. 4 is applied may also be, for example, as shown in FIG. 5B. In this embodiment, the memory cell MC1 and the memory cell MC2 have a symmetrical structure, wherein the memory cell MC1 and the memory cell MC2 respectively include a stacked structure 520', an auxiliary gate dielectric layer 530', an erase gate dielectric layer 532', Floating gate 540', tunneling dielectric layer 542', common source CS, drain 548', and inter-gate dielectric layer 552'. Further, the substrate 500' further has an interlayer insulating layer 560', a plug 562' and a bit line 564'. The stacked structure 520' is sequentially composed of a gate dielectric layer 522', an auxiliary gate 524', an insulating layer 526', and an erase gate EP from the substrate 500'. However, compared to the embodiment of FIG. 3B, the memory cell MC1 and the memory cell MC2 of the present embodiment do not include a control gate. In addition, a detailed description of each structure of the associated memory cell of the present embodiment can be referred to the description of the embodiment of FIG. 3B to obtain sufficient teaching, suggestion, and implementation description, and thus will not be described again.
值得注意的是，圖5A以及圖5B的記憶胞的具體結構可適用於圖4實施例的記憶胞，但本發明並不限於此。上述圖4實施例的結構特徵也可依據使用者需求以及記憶體電路配置方式對應設計之。It is to be noted that the specific structure of the memory cell of FIGS. 5A and 5B can be applied to the memory cell of the embodiment of FIG. 4, but the present invention is not limited thereto. The structural features of the above embodiment of FIG. 4 can also be designed according to user requirements and memory circuit configuration.
圖6A為依照本發明之第四實施例所繪示的一種非揮發性記憶體裝置的電路圖。請參照圖6A，非揮發性記憶體裝置600包括多個記憶胞區塊，並且這些記憶胞區塊排列配置為記憶胞陣列。在本實施例中，一個記憶胞區塊610包括多個記憶胞單元611、位元線BL000、BL001~BL00N、第一字元線WL1、第二字元線WL2。位元線的數量等於記憶胞單元的數量，其中N為大於0的正整數。在本實施例中，一個記憶胞單元611耦接一個位元線。在記憶胞陣列中的每一行的記憶胞區塊610各別透過選擇信號線BSEL接收選擇信號，並且各別依據選擇信號來決定是否執行讀取操作、寫入操作或抹除操作，以使非揮發性記憶體裝置600可執行區域性的資料讀取、資料寫入或資料抹除。並且，在本實施例中，記憶胞區塊610更包括區域控制源極線CSL以及區域控制閘極線CGL。FIG. 6A is a circuit diagram of a non-volatile memory device according to a fourth embodiment of the present invention. Referring to FIG. 6A, the non-volatile memory device 600 includes a plurality of memory cell blocks, and the memory cell blocks are arranged to be arranged as a memory cell array. In the present embodiment, one memory cell block 610 includes a plurality of memory cell units 611, bit lines BL000, BL001 to BL00N, a first word line WL1, and a second word line WL2. The number of bit lines is equal to the number of memory cells, where N is a positive integer greater than zero. In this embodiment, one memory cell unit 611 is coupled to one bit line. The memory cell block 610 of each row in the memory cell array receives the selection signal through the selection signal line BSEL, and each determines whether to perform a read operation, a write operation or an erase operation according to the selection signal, so as to The volatile memory device 600 can perform regional data reading, data writing, or data erasing. Moreover, in the embodiment, the memory cell block 610 further includes a region control source line CSL and a region control gate line CGL.
在本實施例中，區域控制源極線CSL透過第二N型電晶體622耦接記憶胞單元611，以及區域控制閘極線CGL透過第三N型電晶體623耦接記憶胞單元611。然而，相較於上述圖1實施例，本實施例的非揮發性記憶體裝置600不包括區域抹除閘極線EGL。在本實施例中，非揮發性記憶體裝置600的每一個記憶胞區塊610各別透過第四N型電晶體624以及第五N型電晶體625分別耦接第一字元線WL1以及第二字元線WL2。在本實施例中，第四N型電晶體624以及第五N型電晶體625為N型金屬氧化物半導體場效電晶體。In the present embodiment, the area control source line CSL is coupled to the memory cell unit 611 through the second N-type transistor 622, and the area control gate line CGL is coupled to the memory cell unit 611 through the third N-type transistor 623. However, the non-volatile memory device 600 of the present embodiment does not include the area erase gate line EGL as compared to the embodiment of FIG. 1 described above. In this embodiment, each of the memory cells 610 of the non-volatile memory device 600 is coupled to the first word line WL1 and the fourth N-type transistor 625, respectively, through the fourth N-type transistor 624 and the fifth N-type transistor 625. Two word line WL2. In the present embodiment, the fourth N-type transistor 624 and the fifth N-type transistor 625 are N-type metal oxide semiconductor field effect transistors.
在本實施例中，非揮發性記憶體裝置600的每一個記憶胞區塊610可各別藉由第一字元線WL1以及第二字元線WL2接收抹除電壓。也就是說，相較於上述圖1A實施例，本實施例的非揮發性記憶體裝置600的每一個記憶胞區塊610可各別依據第一字元線WL1以及第二字元線WL2是否接收抹除電壓，來決定執行抹除操作。In this embodiment, each memory cell block 610 of the non-volatile memory device 600 can receive the erase voltage by the first word line WL1 and the second word line WL2, respectively. That is, compared with the above-mentioned embodiment of FIG. 1A, each memory cell block 610 of the non-volatile memory device 600 of the present embodiment may be independent of whether the first word line WL1 and the second word line WL2 are respectively The erase voltage is received to determine the erase operation.
為了使所屬技術領域的通常知識者可進一步了解本實施例所述具有字元抹除與減少寫入干擾的非揮發性記憶體裝置，因此以下進一步舉出各電壓偏壓條件的一實施範例說明之，但本發明並不限於此。下表5記載圖6A實施例當中的字元線WL1、WL2、位元線BL000、區域控制閘極線CGL、區域控制源極線CSL以及選擇信號線BSEL分別在不同操作模式下提供的電壓偏壓條件。
依據上述表5，選擇信號線BSEL提供的選擇信號可依據不同操作模式來決定。而相較於圖1A實施例，當記憶胞區塊611被選擇操作在抹除操作時，本實施例的第一字元線WL1以及第二字元線WL2可分別提供抹除電壓VEPE。並且，有關於本實施例的選擇信號的各種偏壓條件、選擇信號線、位元線以及字元線相關技術特徵以及實施方式可參照上述圖1A實施例之敘述中獲致足夠的教示、建議與實施說明，因此不再贅述。According to Table 5 above, the selection signal provided by the selection signal line BSEL can be determined according to different operation modes. As compared with the embodiment of FIG. 1A, when the memory cell block 611 is selectively operated in the erase operation, the first word line WL1 and the second word line WL2 of the present embodiment may respectively provide the erase voltage VEPE. Further, various bias conditions, selection signal lines, bit lines, and word line related technical features and embodiments of the selection signal of the present embodiment can be obtained with sufficient teaching, suggestions, and suggestions in the description of the embodiment of FIG. 1A. Implementation instructions, so I won't go into details.
圖6B為依照本發明之第四實施例所繪示的一種非揮發性記憶體裝置的電路圖。請參照圖6B，非揮發性記憶體裝置600包括多個記憶胞區塊，並且這些記憶胞區塊排列配置為記憶胞陣列。在本實施例中，一個記憶胞區塊610包括多個記憶胞單元611、位元線BL000、BL001~BL00N、第一字元線WL1、第二字元線WL2。位元線的數量等於記憶胞單元的數量，其中N為大於0的正整數。在本實施例中，一個記憶胞單元611耦接一個位元線。在記憶胞陣列中的每一行的記憶胞區塊610各別透過選擇信號線BSEL接收選擇信號，並且各別依據選擇信號來決定是否執行讀取操作、寫入操作或抹除操作，以使非揮發性記憶體裝置600可執行區域性的資料讀取、資料寫入或資料抹除。並且，在本實施例中，記憶胞區塊610更包括區域控制源極線CSL。FIG. 6B is a circuit diagram of a non-volatile memory device according to a fourth embodiment of the present invention. Referring to FIG. 6B, the non-volatile memory device 600 includes a plurality of memory cell blocks, and the memory cell blocks are arranged to be arranged as a memory cell array. In the present embodiment, one memory cell block 610 includes a plurality of memory cell units 611, bit lines BL000, BL001 to BL00N, a first word line WL1, and a second word line WL2. The number of bit lines is equal to the number of memory cells, where N is a positive integer greater than zero. In this embodiment, one memory cell unit 611 is coupled to one bit line. The memory cell block 610 of each row in the memory cell array receives the selection signal through the selection signal line BSEL, and each determines whether to perform a read operation, a write operation or an erase operation according to the selection signal, so as to The volatile memory device 600 can perform regional data reading, data writing, or data erasing. Moreover, in the embodiment, the memory cell block 610 further includes a region control source line CSL.
在本實施例中，區域控制源極線CSL透過第二N型電晶體622耦接記憶胞單元611。並且，每一列的記憶胞區塊610的每一個記憶胞單元611的控制閘極分別耦接同一條信號線，並且耦接至區域控制源極線CSL，以將區域控制源極線CSL提供的源極信號作為閘極信號。也就是說，本實施例的每一列的記憶胞區塊610的每一個記憶胞單元611的共用源極與控制閘極由區域控制源極線CSL接收相同控制信號。In the embodiment, the region control source line CSL is coupled to the memory cell unit 611 through the second N-type transistor 622. Moreover, the control gates of each of the memory cell units 611 of each column of the memory cell block 610 are respectively coupled to the same signal line, and are coupled to the area control source line CSL to provide the area control source line CSL. The source signal acts as a gate signal. That is to say, the common source and the control gate of each memory cell unit 611 of the memory cell block 610 of each column of the present embodiment receive the same control signal from the area control source line CSL.
然而，相較於上述圖1A實施例，本實施例的非揮發性記憶體裝置600不包括區域抹除閘極線EGL。在本實施例中，非揮發性記憶體裝置600的每一個記憶胞區塊610各別透過第四N型電晶體624以及第五N型電晶體625分別耦接第一字元線WL1以及第二字元線WL2。在本實施例中，第四N型電晶體624以及第五N型電晶體625為N型金屬氧化物半導體場效電晶體。However, the non-volatile memory device 600 of the present embodiment does not include the area erase gate line EGL as compared to the above-described embodiment of FIG. 1A. In this embodiment, each of the memory cells 610 of the non-volatile memory device 600 is coupled to the first word line WL1 and the fourth N-type transistor 625, respectively, through the fourth N-type transistor 624 and the fifth N-type transistor 625. Two word line WL2. In the present embodiment, the fourth N-type transistor 624 and the fifth N-type transistor 625 are N-type metal oxide semiconductor field effect transistors.
在本實施例中，非揮發性記憶體裝置600的每一個記憶胞區塊610可各別藉由第一字元線WL1以及第二字元線WL2接收抹除電壓。也就是說，相較於上述圖1A實施例，本實施例的非揮發性記憶體裝置600的每一個記憶胞區塊610可各別依據第一字元線WL1以及第二字元線WL2是否接收抹除電壓，來決定執行抹除操作。In this embodiment, each memory cell block 610 of the non-volatile memory device 600 can receive the erase voltage by the first word line WL1 and the second word line WL2, respectively. That is, compared with the above-mentioned embodiment of FIG. 1A, each memory cell block 610 of the non-volatile memory device 600 of the present embodiment may be independent of whether the first word line WL1 and the second word line WL2 are respectively The erase voltage is received to determine the erase operation.
為了使所屬技術領域的通常知識者可進一步了解本實施例所述具有字元抹除與減少寫入干擾的非揮發性記憶體裝置，因此以下進一步舉出各電壓偏壓條件的一實施範例說明之，但本發明並不限於此。下表6記載圖6B實施例當中的字元線WL1、WL2、位元線BL000、區域控制源極線CSL以及選擇信號線BSEL分別在不同操作模式下提供的電壓偏壓條件。
依據上述表6，選擇信號線BSEL提供的選擇信號可依據不同操作模式來決定。而相較於圖1A實施例，當記憶胞區塊611被選擇操作在抹除操作時，本實施例的第一字元線WL1以及第二字元線WL2可分別提供抹除電壓VEPE。並且，有關於本實施例的選擇信號的各種偏壓條件、選擇信號線、位元線以及字元線相關技術特徵以及實施方式可參照上述圖1A實施例之敘述中獲致足夠的教示、建議與實施說明，因此不再贅述。According to Table 6 above, the selection signal provided by the selection signal line BSEL can be determined according to different operation modes. As compared with the embodiment of FIG. 1A, when the memory cell block 611 is selectively operated in the erase operation, the first word line WL1 and the second word line WL2 of the present embodiment may respectively provide the erase voltage VEPE. Further, various bias conditions, selection signal lines, bit lines, and word line related technical features and embodiments of the selection signal of the present embodiment can be obtained with sufficient teaching, suggestions, and suggestions in the description of the embodiment of FIG. 1A. Implementation instructions, so I won't go into details.
圖7為依照本發明之第五實施例所繪示的一種非揮發性記憶體裝置的電路圖。請參照圖7，非揮發性記憶體裝置700包括多個記憶胞區塊，並且這些記憶胞區塊排列配置為記憶胞陣列。在本實施例中，一個記憶胞區塊710包括多個記憶胞單元711、位元線BL000、BL001~BL00N、第一字元線WL1、第二字元線WL2。位元線的數量等於記憶胞單元的數量，其中N為大於0的正整數。在本實施例中，一個記憶胞單元711耦接一個位元線。在記憶胞陣列中的每一行的記憶胞區塊710各別透過選擇信號線BSEL接收選擇信號，並且各別依據選擇信號來決定是否執行讀取操作、寫入操作或抹除操作，以使非揮發性記憶體裝置700可執行區域性的資料讀取、資料寫入或資料抹除。並且，在本實施例中，記憶胞區塊710更包括全域控制源極線CSL’以及區域控制閘極線CGL。FIG. 7 is a circuit diagram of a non-volatile memory device according to a fifth embodiment of the present invention. Referring to FIG. 7, the non-volatile memory device 700 includes a plurality of memory cell blocks, and the memory cell blocks are arranged in a memory cell array. In this embodiment, one memory cell block 710 includes a plurality of memory cell units 711, bit lines BL000, BL001~BL00N, a first word line WL1, and a second word line WL2. The number of bit lines is equal to the number of memory cells, where N is a positive integer greater than zero. In this embodiment, one memory cell unit 711 is coupled to one bit line. The memory cell block 710 of each row in the memory cell array receives the selection signal through the selection signal line BSEL, and each determines whether to perform a read operation, a write operation or an erase operation according to the selection signal, so as to The volatile memory device 700 can perform regional data reading, data writing, or data erasing. Moreover, in the embodiment, the memory cell block 710 further includes a global control source line CSL' and a region control gate line CGL.
在本實施例中，每一列的記憶胞區塊710設置一個全域控制源極線CSL’。全域控制源極線CSL’用以提供源極信號至每一列的記憶胞區塊710當中的每一個記憶胞單元711的共用源極。In the present embodiment, the memory cell block 710 of each column is provided with a global control source line CSL'. The global control source line CSL' is used to provide a source signal to the common source of each of the memory cells 711 in each of the memory cells 710 of each column.
在本實施例中，區域控制閘極線CGL透過第三N型電晶體723耦接記憶胞單元711。然而，相較於上述圖1實施例，本實施例的非揮發性記憶體裝置700不包括區域抹除閘極線EGL。在本實施例中，非揮發性記憶體裝置700的每一個記憶胞區塊710各別透過第四N型電晶體724以及第五N型電晶體725分別耦接第一字元線WL1以及第二字元線WL2。在本實施例中，第四N型電晶體724以及第五N型電晶體725為N型金屬氧化物半導體場效電晶體。In the embodiment, the area control gate line CGL is coupled to the memory cell unit 711 through the third N-type transistor 723. However, the non-volatile memory device 700 of the present embodiment does not include the area erase gate line EGL as compared to the above-described embodiment of FIG. In this embodiment, each memory cell block 710 of the non-volatile memory device 700 is coupled to the first word line WL1 and the first N-type transistor 725 and the fifth N-type transistor 725, respectively. Two word line WL2. In the present embodiment, the fourth N-type transistor 724 and the fifth N-type transistor 725 are N-type metal oxide semiconductor field effect transistors.
在本實施例中，非揮發性記憶體裝置700的每一個記憶胞區塊710可各別藉由第一字元線WL1以及第二字元線WL2接收抹除電壓。也就是說，相較於上述圖1實施例，本實施例的非揮發性記憶體裝置700的每一個記憶胞區塊710可各別依據第一字元線WL1以及第二字元線WL2是否接收抹除電壓，來決定執行抹除操作。In this embodiment, each memory cell block 710 of the non-volatile memory device 700 can receive the erase voltage by the first word line WL1 and the second word line WL2, respectively. That is to say, compared with the embodiment of FIG. 1 above, each memory cell block 710 of the non-volatile memory device 700 of the present embodiment may be independent of whether the first word line WL1 and the second word line WL2 are respectively The erase voltage is received to determine the erase operation.
為了使所屬技術領域的通常知識者可進一步了解本實施例所述具有字元抹除與減少寫入干擾的非揮發性記憶體裝置，因此以下進一步舉出各電壓偏壓條件的一實施範例說明之，但本發明並不限於此。下表7記載圖7實施例當中的字元線WL1、WL2、位元線BL000、區域控制閘極線CGL、全域控制源極線CSL’以及選擇信號線BSEL分別在不同操作模式下提供的電壓偏壓條件。
依據上述表7，選擇信號線BSEL提供的選擇信號可依據不同操作模式來決定。而相較於圖1A實施例，當記憶胞區塊710被選擇操作在抹除操作時，本實施例的第一字元線WL1以及第二字元線WL2可分別提供抹除電壓VEPE。有關於本實施例的選擇信號的各種偏壓條件、選擇信號線、位元線以及字元線相關技術特徵以及實施方式可參照上述圖1A實施例之敘述中獲致足夠的教示、建議與實施說明，因此不再贅述。According to Table 7 above, the selection signal provided by the selection signal line BSEL can be determined according to different operation modes. In contrast to the embodiment of FIG. 1A, when the memory cell block 710 is selectively operated in the erase operation, the first word line WL1 and the second word line WL2 of the present embodiment may respectively provide the erase voltage VEPE. For various bias conditions, selection signal lines, bit lines, and word line related technical features and embodiments of the selection signal of the present embodiment, sufficient teaching, suggestions, and implementation instructions can be obtained by referring to the description of the embodiment of FIG. 1A above. Therefore, I will not repeat them.
圖8A為依照本發明之第四實施例以及第五實施例所繪示的一種記憶胞的結構示意圖。圖8B為依照本發明之第四實施例以及第五實施例所繪示的另一種記憶胞的結構示意圖。FIG. 8A is a schematic structural diagram of a memory cell according to a fourth embodiment and a fifth embodiment of the present invention. FIG. 8B is a schematic structural diagram of another memory cell according to a fourth embodiment and a fifth embodiment of the present invention.
請參照圖8A，上述圖6A、圖6B以及圖7實施例所適用的記憶胞的詳細結構可例如圖8A所示。在本實施例中，記憶胞MC1以及記憶胞MC2具有對稱結構，其中記憶胞MC1以及記憶胞MC2各別包括堆疊結構820、輔助閘介電層830、抹除閘介電層832、浮置閘極840、穿隧介電層842、共用源極CS、汲極848、控制閘極CG以及閘間介電層852。此外，基底800上更具有層間絕緣層860、插塞862與位元線864。堆疊結構820從基底800起依序由閘介電層822以及輔助閘極824構成。然而，相較於圖3A實施例，本實施例的記憶胞MC1以及記憶胞MC2不包括抹除閘極。另外，本實施例的相關記憶胞的各結構的詳細描述可參照上述圖3A實施例之敘述中獲致足夠的教示、建議與實施說明，因此不再贅述。Referring to FIG. 8A, the detailed structure of the memory cell to which the above-described embodiments of FIGS. 6A, 6B, and 7 are applied may be, for example, as shown in FIG. 8A. In this embodiment, the memory cell MC1 and the memory cell MC2 have a symmetrical structure, wherein the memory cell MC1 and the memory cell MC2 respectively include a stacked structure 820, an auxiliary gate dielectric layer 830, an erase gate dielectric layer 832, and a floating gate. The pole 840, the tunneling dielectric layer 842, the common source CS, the drain 848, the control gate CG, and the inter-gate dielectric layer 852. In addition, the substrate 800 further has an interlayer insulating layer 860, a plug 862 and a bit line 864. The stacked structure 820 is sequentially composed of a gate dielectric layer 822 and an auxiliary gate 824 from the substrate 800. However, compared to the embodiment of FIG. 3A, the memory cell MC1 and the memory cell MC2 of the present embodiment do not include an erase gate. In addition, a detailed description of each structure of the associated memory cell of the present embodiment can be referred to the description of the embodiment of FIG. 3A to obtain sufficient teaching, suggestion, and implementation description, and thus will not be described again.
請參照圖8B，上述圖6A、圖6B以及圖7實施例所適用的記憶胞的詳細結構可例如圖8B所示。在本實施例中，記憶胞MC1以及記憶胞MC2具有對稱結構，其中記憶胞MC1以及記憶胞MC2各別包括堆疊結構820’、輔助閘介電層830’、抹除閘介電層832’、浮置閘極840’、穿隧介電層842’、共用源極CS、汲極848’、控制閘極CG以及閘間介電層852’。此外，基底800’上更具有層間絕緣層860’、插塞862’與位元線864’。堆疊結構820’從基底800’起依序由閘介電層822’以及輔助閘極824’構成。然而，相較於圖3B實施例，本實施例的記憶胞MC1以及記憶胞MC2不包括抹除閘極。另外，本實施例的相關記憶胞的各結構的詳細描述可參照上述圖3B實施例之敘述中獲致足夠的教示、建議與實施說明，因此不再贅述。Referring to FIG. 8B, the detailed structure of the memory cell to which the above-described embodiments of FIGS. 6A, 6B, and 7 are applied may be, for example, as shown in FIG. 8B. In this embodiment, the memory cell MC1 and the memory cell MC2 have a symmetrical structure, wherein the memory cell MC1 and the memory cell MC2 respectively include a stacked structure 820', an auxiliary gate dielectric layer 830', an erase gate dielectric layer 832', The floating gate 840', the tunneling dielectric layer 842', the common source CS, the drain 848', the control gate CG, and the inter-gate dielectric layer 852'. Further, the substrate 800' further has an interlayer insulating layer 860', a plug 862' and a bit line 864'. The stacked structure 820' is sequentially composed of a gate dielectric layer 822' and an auxiliary gate 824' from the substrate 800'. However, compared to the embodiment of FIG. 3B, the memory cell MC1 and the memory cell MC2 of the present embodiment do not include an erase gate. In addition, a detailed description of each structure of the associated memory cell of the present embodiment can be referred to the description of the embodiment of FIG. 3B to obtain sufficient teaching, suggestion, and implementation description, and thus will not be described again.
綜上所述，本發明的非揮發性記憶體裝置包括多個記憶胞區塊，並且可藉由多個N型電晶體來獨立控制每一個記憶胞區塊的操作模式。本發明的非揮發性記憶體裝置可藉由選擇信號線輸出選擇信號至這些N型電晶體的控制端，以獨立控制每一個記憶胞區塊是否接收讀取電壓、寫入電壓或抹除電壓等，以使有效地執行區域性的資料讀取操作、資料寫入操作或資料抹除操作。據此，本發明的非揮發性記憶體裝置可具有字元抹除的功能。並且，本實施例的非揮發性記憶體裝置於寫入操作時，可有效降低寫入干擾的影響。In summary, the non-volatile memory device of the present invention includes a plurality of memory cell blocks, and the operation mode of each memory cell block can be independently controlled by a plurality of N-type transistors. The non-volatile memory device of the present invention can output a selection signal to the control terminals of the N-type transistors by selecting a signal line to independently control whether each memory cell block receives a read voltage, a write voltage, or an erase voltage. Etc., so that a regional data reading operation, a data writing operation, or a data erasing operation can be performed efficiently. Accordingly, the non-volatile memory device of the present invention can have the function of word erasing. Moreover, the non-volatile memory device of the present embodiment can effectively reduce the influence of write disturbance during a write operation.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100、200、400、600、700‧‧‧非揮發性記憶體裝置100, 200, 400, 600, 700‧‧‧ non-volatile memory devices
110、210、410、610、710‧‧‧記憶胞區塊110, 210, 410, 610, 710‧‧‧ memory cell blocks
111、211、411、611、711‧‧‧記憶胞單元111, 211, 411, 611, 711‧‧‧ memory cell
121、122、123、221、223、421、422、622、623、624、625、723、724、725‧‧‧N型電晶體121, 122, 123, 221, 223, 421, 422, 622, 623, 624, 625, 723, 724, 725‧‧‧N type transistors
300、300’、500、500’、800、800’‧‧‧基底300, 300', 500, 500', 800, 800' ‧ ‧ base
320、320’、520、520’、820、820’‧‧‧堆疊結構320, 320', 520, 520', 820, 820' ‧ ‧ stack structure
322、322’、522、522’、822、822’‧‧‧閘介電層322, 322', 522, 522', 822, 822'‧‧‧ gate dielectric layer
324、324’、524、524’、824、824’‧‧‧輔助閘極324, 324', 524, 524', 824, 824' ‧ ‧ auxiliary gate
326、326’、526、526’‧‧‧絕緣層326, 326', 526, 526' ‧ ‧ insulation
330、330’、530、530’、830、830’‧‧‧輔助閘介電層330, 330', 530, 530', 830, 830' ‧ ‧ auxiliary gate dielectric layer
332、332’、532、532’、832、832’‧‧‧抹除閘介電層332, 332', 532, 532', 832, 832' ‧ ‧ wipe the gate dielectric layer
340、340’、540、540’、840、840’‧‧‧浮置閘極340, 340', 540, 540', 840, 840' ‧ ‧ floating gate
341、341’、541、541’、841、841’‧‧‧轉角部341, 341', 541, 541', 841, 841' ‧ ‧ corner
342、342’、542、542’、842、842’‧‧‧穿隧介電層342, 342', 542, 542', 842, 842' ‧ ‧ tunneling dielectric layers
348、348’、548、548’、848、848’‧‧‧汲極348, 348’, 548, 548’, 848, 848’ ‧ ‧ 汲
352、352’、552、552’、852、852’‧‧‧閘間介電層352, 352', 552, 552', 852, 852' ‧ ‧ gate dielectric layer
360、360’、560、560’、860、860’‧‧‧層間絕緣層360, 360', 560, 560', 860, 860' ‧ ‧ interlayer insulation
362、362’、562、562’、862、862’‧‧‧插塞362, 362', 562, 562', 862, 862'‧‧‧ plugs
364、364’、564、564’、864、864’‧‧‧位元線364, 364’, 564, 564’, 864, 864’ ‧ ‧ bit lines
BSEL‧‧‧選擇信號線BSEL‧‧‧Select signal line
BL000、BL001、BL00N‧‧‧位元線BL000, BL001, BL00N‧‧‧ bit line
CG‧‧‧控制閘極CG‧‧‧Control gate
CS‧‧‧共用源極CS‧‧‧Shared source
CSL、CSL’‧‧‧控制源極線CSL, CSL’‧‧‧ Control source line
CGL‧‧‧控制閘極線CGL‧‧‧Control gate line
EP‧‧‧抹除閘極EP‧‧‧ erasing gate
EGL‧‧‧抹除閘極線EGL‧‧‧ erasing gate line
MC1、MC2‧‧‧記憶胞MC1, MC2‧‧‧ memory cells
WL1、WL2‧‧‧字元線WL1, WL2‧‧‧ character line
圖1A為依照本發明之第一實施例所繪示的一種非揮發性記憶體裝置的電路圖。 圖1B為依照本發明之第一實施例所繪示的另一種非揮發性記憶體裝置的電路圖。 圖2為依照本發明之第二實施例所繪示的一種非揮發性記憶體裝置的電路圖。 圖3A為依照本發明之第一實施例以及第二實施例所繪示的一種記憶胞的結構示意圖。 圖3B為依照本發明之第一實施例以及第二實施例所繪示的另一種記憶胞的結構示意圖。 圖4為依照本發明之第三實施例所繪示的一種非揮發性記憶體裝置的電路圖。 圖5A為依照本發明之第三實施例所繪示的一種記憶胞的結構示意圖。 圖5B為依照本發明之第三實施例所繪示的另一種記憶胞的結構示意圖。 圖6A為依照本發明之第四實施例所繪示的一種非揮發性記憶體裝置的電路圖。 圖6B為依照本發明之第四實施例所繪示的另一種非揮發性記憶體裝置的電路圖。 圖7為依照本發明之第五實施例所繪示的一種非揮發性記憶體裝置的電路圖。 圖8A為依照本發明之第四實施例以及第五實施例所繪示的一種記憶胞的結構示意圖。 圖8B為依照本發明之第四實施例以及第五實施例所繪示的另一種記憶胞的結構示意圖。1A is a circuit diagram of a non-volatile memory device in accordance with a first embodiment of the present invention. FIG. 1B is a circuit diagram of another non-volatile memory device according to a first embodiment of the present invention. 2 is a circuit diagram of a non-volatile memory device in accordance with a second embodiment of the present invention. FIG. 3A is a schematic structural diagram of a memory cell according to a first embodiment and a second embodiment of the present invention. FIG. 3B is a schematic structural diagram of another memory cell according to the first embodiment and the second embodiment of the present invention. 4 is a circuit diagram of a non-volatile memory device in accordance with a third embodiment of the present invention. FIG. 5A is a schematic structural diagram of a memory cell according to a third embodiment of the present invention. FIG. 5B is a schematic structural diagram of another memory cell according to a third embodiment of the present invention. FIG. 6A is a circuit diagram of a non-volatile memory device according to a fourth embodiment of the present invention. FIG. 6B is a circuit diagram of another non-volatile memory device according to a fourth embodiment of the present invention. FIG. 7 is a circuit diagram of a non-volatile memory device according to a fifth embodiment of the present invention. FIG. 8A is a schematic structural diagram of a memory cell according to a fourth embodiment and a fifth embodiment of the present invention. FIG. 8B is a schematic structural diagram of another memory cell according to a fourth embodiment and a fifth embodiment of the present invention.
Claims (17)
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| US10644011B1 (en) | 2018-11-09 | 2020-05-05 | Iotmemory Technology Inc. | Non-volatile memory |
| TWI823398B (en) * | 2022-03-30 | 2023-11-21 | 物聯記憶體科技股份有限公司 | Non-volatile memory device |
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| US20070091682A1 (en) * | 2005-07-13 | 2007-04-26 | Kang Sung-Taeg | Byte-Erasable Nonvolatile Memory Devices |
| DE102006033395A1 (en) * | 2005-07-13 | 2007-03-15 | Samsung Electronics Co., Ltd., Suwon | Integrated circuit component with erasable EEPROM memory, has first semiconductor-trough region of substrate which is split and electrically coupled by global control line by first and second byte-selection transistor |
| US7495958B2 (en) * | 2006-11-06 | 2009-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Program and erase methods and structures for byte-alterable flash memory |
| US20150213898A1 (en) * | 2014-01-27 | 2015-07-30 | Silicon Storage Technololgy, Inc. | Byte Erasable Non-volatile Memory Architecture And Method Of Erasing Same |
| FR3021806B1 (en) * | 2014-05-28 | 2017-09-01 | St Microelectronics Sa | METHOD FOR PROGRAMMING NONVOLATILE MEMORY CELL COMPRISING A SHARED SELECTION TRANSISTOR GRID |
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| US10644011B1 (en) | 2018-11-09 | 2020-05-05 | Iotmemory Technology Inc. | Non-volatile memory |
| TWI694592B (en) * | 2018-11-09 | 2020-05-21 | 物聯記憶體科技股份有限公司 | Non-volatile memory and manufacturing method thereof |
| TWI823398B (en) * | 2022-03-30 | 2023-11-21 | 物聯記憶體科技股份有限公司 | Non-volatile memory device |
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