TW201837995A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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TW201837995A
TW201837995A TW106126957A TW106126957A TW201837995A TW 201837995 A TW201837995 A TW 201837995A TW 106126957 A TW106126957 A TW 106126957A TW 106126957 A TW106126957 A TW 106126957A TW 201837995 A TW201837995 A TW 201837995A
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Taiwan
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fin
layer
separation wall
fin structure
dielectric
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TW106126957A
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Chinese (zh)
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TWI662601B (en
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江國誠
王志豪
陳志良
朱熙甯
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台灣積體電路製造股份有限公司
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Abstract

In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.

Description

半導體元件及其製造方法    Semiconductor element and manufacturing method thereof   

本揭露係關於半導體積體電路，更特定而言，係關於具有鰭片結構之半導體元件及其製造方法。 The present disclosure relates to a semiconductor integrated circuit, and more particularly, to a semiconductor device having a fin structure and a manufacturing method thereof.

隨著半導體工業已經發展到追求更高元件密度、更高效能及更低成本之奈米(nm)技術製程節點，在諸如鰭式場效電晶體(fin field effect transistor；Fin FET)之三維設計之發展過程中遇到了來自製造及設計問題的雙重挑戰。鰭式場效電晶體元件通常包含具有大深寬比之半導體鰭片及在其中形成半導體電晶體元件之通道及源極/汲極區。利用通道及源極/汲極區之增大的表面積之優勢在鰭片結構上方及沿鰭片結構之側面(例如，包裹)形成閘極，以生產更快、更可靠及更好控制之半導體電晶體元件。金屬閘極結構與具有高介電常數之高介電常數閘極介電質一起通常用於鰭式場效電晶體元件中，並藉由閘極取代技術來製造。 As the semiconductor industry has evolved to nanometer (nm) technology process nodes pursuing higher component density, higher efficiency, and lower cost, the design of 3D designs such as fin field effect transistors (Fin FETs) The development process encountered double challenges from manufacturing and design issues. Fin-type field-effect transistor elements generally include semiconductor fins with a large aspect ratio and channels and source / drain regions in which the semiconductor transistor elements are formed. Take advantage of the increased surface area of the channel and source / drain regions to form gates above and along the sides (e.g., packages) of the fin structure to produce faster, more reliable, and more controlled semiconductors Transistor element. Metal gate structures, together with high-dielectric constant-gate dielectrics with high dielectric constants, are commonly used in fin-type field-effect transistor devices, and are manufactured by gate replacement technology.

依據本揭露之一些實施方式，半導體元件的製造方法包含：形成分離壁於兩鰭片結構之間，分離壁的材質為介電材料；形成虛設閘極結構於分離壁以及兩鰭片結構上方；形成層間介電層於虛設閘極結構上方；移除層間介電層之上部位，進而暴露虛設閘極結構；藉由金屬閘極結構取代虛設閘極結構；以及執行平坦化操作以暴露分離壁，進而將金屬閘極結構分隔為第一閘極結構及第二閘極結構，其中第一閘極結構與第二閘極結構藉由分離壁而相互分離。 According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes forming a separation wall between two fin structures, and a material of the separation wall is a dielectric material; forming a dummy gate structure above the separation wall and the two fin structures; Forming an interlayer dielectric layer over the dummy gate structure; removing the portion above the interlayer dielectric layer to expose the dummy gate structure; replacing the dummy gate structure with a metal gate structure; and performing a planarization operation to expose the separation wall The metal gate structure is further divided into a first gate structure and a second gate structure, wherein the first gate structure and the second gate structure are separated from each other by a separation wall.

依據本揭露之另一些實施方式，半導體元件的製造方法包含：形成第一鰭片結構、第二鰭片結構以及第三鰭片結構，實質上第二鰭片結構位於實質上第一鰭片結構與第三鰭片結構之間，實質上第一鰭片結構、實質上第二鰭片結構以及實質上第三鰭片結構中之每一者的材質為半導體材料，且具有絕緣覆蓋層；形成隔離絕緣層，使得實質上第鰭片結構、實質上第二鰭片結構以及實質上第三鰭片結構係嵌入於實質上隔離絕緣層，且實質上絕緣覆蓋層被暴露出；形成第一遮罩圖案於實質上隔離絕緣層上方，實質上第一遮罩圖案具有第一開口，實質上第一開口位於實質上第二鰭片結構上方；藉由蝕刻製程使實質上第二鰭片結構凹陷，且實質上第一遮罩圖案作為蝕刻遮罩；形成介電分離壁於凹陷之實質上第二鰭片結構上；使實質上隔離絕緣層凹陷，使得實質上第一鰭片結構及第三鰭片結構的複數個上部位與實質上介電分離壁的上部位被暴露出；形成第一虛設閘極結構於暴露之實質上第一鰭片結構、暴露之實質上第三鰭片結構以及暴露之實質上介電分離壁上 方；形成層間介電層於實質上第一虛設閘極結構上方；移除實質上層間介電層的上部位，進而暴露實質上第一虛設閘極結構；藉由金屬閘極結構取代實質上第一閘極結構；以及執行平坦化操作以暴露實質上介電分離壁，進而將實質上金屬閘極結構分隔為第一閘極結構及第二閘極結構，其中實質上第一閘極結構與實質上第二閘極結構藉由實質上介電分離壁而相互分離。 According to other embodiments of the present disclosure, a method for manufacturing a semiconductor device includes forming a first fin structure, a second fin structure, and a third fin structure. The second fin structure is substantially located on the first fin structure. And the third fin structure, the material of each of the substantially first fin structure, the substantially second fin structure, and the substantially third fin structure is a semiconductor material and has an insulating cover layer; Isolate the insulating layer so that the substantially first fin structure, the substantially second fin structure, and the substantially third fin structure are embedded in the substantially isolated insulating layer, and the substantially insulating cover layer is exposed; forming a first shield The mask pattern is above the substantially isolating insulation layer. The first mask pattern has a first opening. The first opening is substantially above the second fin structure. The second fin structure is recessed by an etching process. And substantially the first mask pattern is used as an etching mask; a dielectric separation wall is formed on the substantially second fin structure of the recess; the substantially insulating insulating layer is recessed so that the The plurality of upper portions of the one fin structure and the third fin structure and the substantially upper portion of the dielectric separation wall are exposed; the first dummy gate structure is formed on the exposed substantially first fin structure, the exposed essence The upper third fin structure and the exposed substantially dielectric separation wall; forming an interlayer dielectric layer above the substantially first dummy gate structure; removing the upper portion of the substantially interlayer dielectric layer, thereby exposing the substantially first A dummy gate structure; replacing a substantially first gate structure with a metal gate structure; and performing a planarization operation to expose a substantially dielectric separation wall, thereby separating the substantially metal gate structure into a first gate structure And a second gate structure, wherein the substantially first gate structure and the substantially second gate structure are separated from each other by a substantially dielectric separation wall.

依據本揭露之再一些實施方式，半導體元件包含第一閘極電極、第二閘極電極以及介電分離壁。第一閘極電極設置於隔離絕緣層上方，隔離絕緣層形成於基板上。第二閘極電極設置於隔離絕緣層上方，第一閘極電極與第二閘極電極延伸於第一方向，且沿著第一方向對準。介電分離壁突出於隔離絕緣層，且設置於第一閘極電極與第二閘極電極之間，且將第一閘極電極分離於第二閘極電極。介電分離壁的材質為一介電材料，隔離絕緣層的材質為介電材料，且介電分離壁的介電材料不同於隔離絕緣層的介電材料。 According to still other embodiments of the present disclosure, the semiconductor device includes a first gate electrode, a second gate electrode, and a dielectric separation wall. The first gate electrode is disposed above the isolation insulating layer, and the isolation insulating layer is formed on the substrate. The second gate electrode is disposed above the insulation layer. The first gate electrode and the second gate electrode extend in a first direction and are aligned along the first direction. The dielectric separation wall protrudes from the isolation insulating layer, is disposed between the first gate electrode and the second gate electrode, and separates the first gate electrode from the second gate electrode. The material of the dielectric separation wall is a dielectric material, the material of the isolation insulation layer is a dielectric material, and the dielectric material of the dielectric separation wall is different from the dielectric material of the isolation insulation layer.

10‧‧‧基板 10‧‧‧ substrate

20‧‧‧半導體鰭片 20‧‧‧Semiconductor Fin

24‧‧‧墊氧化物層 24‧‧‧ Pad oxide layer

25‧‧‧遮罩層 25‧‧‧Mask layer

29‧‧‧蝕刻殘餘部位 29‧‧‧ Etching Remains

30‧‧‧隔離絕緣層 30‧‧‧Isolation insulation

40‧‧‧第一遮罩層 40‧‧‧ first mask layer

42‧‧‧第二遮罩層 42‧‧‧ second mask layer

45‧‧‧光致抗蝕劑層 45‧‧‧ photoresist layer

46‧‧‧開口 46‧‧‧ opening

50‧‧‧介電分離壁 50‧‧‧ Dielectric separation wall

50H‧‧‧高部位 50H‧‧‧High part

50L‧‧‧低部位 50L‧‧‧Low part

51‧‧‧第一覆蓋層 51‧‧‧first cover

52‧‧‧第三遮罩層 52‧‧‧ third mask layer

54‧‧‧抗蝕圖案 54‧‧‧ resist pattern

56、58‧‧‧開口 56, 58‧‧‧ opening

65‧‧‧虛設閘極介電層 65‧‧‧Dummy gate dielectric layer

70‧‧‧虛設閘極電極 70‧‧‧ dummy gate electrode

72、74‧‧‧遮罩層 72, 74‧‧‧Mask layer

76‧‧‧側壁間隙壁 76‧‧‧ sidewall spacer

80‧‧‧源極/汲極磊晶層 80‧‧‧source / drain epitaxial layer

82‧‧‧蝕刻終止層 82‧‧‧ Etch stop layer

84‧‧‧層間介電層 84‧‧‧ Interlayer dielectric layer

89‧‧‧閘極間距 89‧‧‧Gate Pitch

90‧‧‧閘極結構 90‧‧‧Gate structure

92‧‧‧閘極介電層 92‧‧‧Gate dielectric layer

94‧‧‧功函數調整層 94‧‧‧ work function adjustment layer

96‧‧‧主體閘極電極 96‧‧‧main gate electrode

110‧‧‧基板 110‧‧‧ substrate

120‧‧‧半導體鰭片 120‧‧‧Semiconductor Fin

122‧‧‧第一覆蓋層 122‧‧‧first cover

124‧‧‧第二覆蓋層 124‧‧‧second cover

130‧‧‧隔離絕緣層 130‧‧‧Isolation insulation

135‧‧‧氧化層 135‧‧‧oxide

140‧‧‧犧牲層 140‧‧‧ sacrificial layer

142‧‧‧第一虛設層 142‧‧‧First dummy layer

143‧‧‧第二虛設層 143‧‧‧Second dummy layer

144‧‧‧第三虛設層 144‧‧‧The third dummy layer

150‧‧‧介電分離壁 150‧‧‧ Dielectric separation wall

150A‧‧‧第一介電分離壁 150A‧‧‧The first dielectric separation wall

150B‧‧‧第二介電分離壁 150B‧‧‧Second dielectric separation wall

152‧‧‧遮罩層 152‧‧‧Mask layer

154‧‧‧光致抗蝕劑圖案 154‧‧‧Photoresist pattern

170‧‧‧第四虛設層 170‧‧‧ Fourth dummy layer

172、174‧‧‧層狀結構 172, 174‧‧‧‧ layered structure

175‧‧‧虛設閘極電極 175‧‧‧Dummy gate electrode

176‧‧‧側壁間隙壁 176‧‧‧ sidewall spacer

180‧‧‧源極/汲極磊晶層 180‧‧‧source / drain epitaxial layer

182‧‧‧蝕刻終止層 182‧‧‧etch stop layer

184‧‧‧層間介電層 184‧‧‧Interlayer dielectric layer

189‧‧‧閘極間距 189‧‧‧Gate Pitch

190‧‧‧閘極結構 190‧‧‧Gate structure

192‧‧‧閘極介電層 192‧‧‧Gate dielectric layer

194‧‧‧功函數調整層 194‧‧‧Work function adjustment layer

196‧‧‧主體閘極電極 196‧‧‧main gate electrode

F1‧‧‧第一鰭片 F1‧‧‧First fin

F2‧‧‧第二鰭片 F2‧‧‧Second Fin

F3‧‧‧第三鰭片 F3‧‧‧ third fin

F4‧‧‧第四鰭片 F4‧‧‧ Fourth fin

F11‧‧‧第一鰭片 F11‧‧‧First Fin

F12‧‧‧第二鰭片 F12‧‧‧Second Fin

F13‧‧‧第三鰭片 F13‧‧‧The third fin

F14‧‧‧第四鰭片 F14‧‧‧ Fourth fin

FP‧‧‧基礎鰭片節距 FP‧‧‧Basic Fin Pitch

H1、H2、H4‧‧‧距離 H1, H2, H4 ‧‧‧ distance

H5、H6、H7、H11、H13、H14、H15、H17、H18、H19、H20‧‧‧高度 H5, H6, H7, H11, H13, H14, H15, H17, H18, H19, H20‧‧‧ height

H31、H32‧‧‧距離 H31, H32 ‧‧‧ distance

H42‧‧‧高度 H42‧‧‧height

L1‧‧‧線 L1‧‧‧line

P1、P2、P3、P31、P32、P33‧‧‧節距 P1, P2, P3, P31, P32, P33‧‧‧ pitch

S1、S2‧‧‧距離 S1, S2‧‧‧ distance

S11‧‧‧寬度 S11‧‧‧Width

S31、S32‧‧‧距離 S31, S32‧‧‧ distance

S41、S42、S43、S44、S45‧‧‧間距 S41, S42, S43, S44, S45‧‧‧Pitch

W31、W32、W41‧‧‧寬度 W31, W32, W41‧‧‧Width

X、Y‧‧‧方向 X, Y‧‧‧ directions

X1-X1、X2-X2、Y1-Y1、X11-X11、X12-X12‧‧‧線段 X1-X1, X2-X2, Y1-Y1, X11-X11, X12-X12‧‧‧ line segments

本揭露當結合附圖閱讀時自以下詳細描述最佳地理解。應強調，依據工業標準實踐，各特徵並未按比例繪製且僅用於繪示之目的。事實上，為論述清楚，各特徵之大小可任意地增加或縮小。 This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with industry standard practice, features are not drawn to scale and are used for illustration purposes only. In fact, for the sake of clarity, the size of each feature can be arbitrarily increased or decreased.

第1A圖繪示依據本揭露之一些實施方式之半導體元件的立體圖。 FIG. 1A illustrates a perspective view of a semiconductor device according to some embodiments of the present disclosure.

第1B圖繪示依據本揭露之一些實施方式之半導體元件的平面圖。 FIG. 1B is a plan view of a semiconductor device according to some embodiments of the present disclosure.

第1C圖繪示沿著第1B圖中線段X1-X1的剖視圖。 FIG. 1C is a cross-sectional view taken along line X1-X1 in FIG. 1B.

第1D圖繪示沿著第1B圖中線段X2-X2的剖視圖。 FIG. 1D is a cross-sectional view taken along line X2-X2 in FIG. 1B.

第1E圖繪示沿著第1B圖中線段Y1-Y1的剖視圖。 FIG. 1E is a cross-sectional view taken along line Y1-Y1 in FIG. 1B.

第1F圖繪示依據本揭露之其他實施方式之沿著第1B圖中線段Y1-Y1的剖視圖。 FIG. 1F illustrates a cross-sectional view along line Y1-Y1 in FIG. 1B according to other embodiments of the present disclosure.

第2A圖、第3A圖、第4A圖、第5A圖、第6A圖、第7A圖、第8A圖、第9A圖、第10A圖、第11A圖、第12A圖、第13A圖、第14A圖、第15A圖、第16A圖、第17A圖、第18A圖、第19A圖、第20A圖、第21A圖以及第22A圖分別繪示依據本揭露之一些實施方式之半導體元件於不同中間製造階段下的立體圖。 Figure 2A, Figure 3A, Figure 4A, Figure 5A, Figure 6A, Figure 7A, Figure 8A, Figure 9A, Figure 10A, Figure 11A, Figure 12A, Figure 13A, Figure 14A FIG. 15A, 16A, 17A, 18A, 19A, 20A, 21A, and 22A respectively illustrate semiconductor devices manufactured in different intermediates according to some embodiments of the present disclosure. Perspective view of the stage.

第2B圖、第3B圖、第4B圖、第5B圖、第6B圖、第7B圖、第8B圖、第9B圖、第10B圖、第11B圖、第12B圖、第13B圖、第14B圖、第15B圖、第16B圖、第17B圖、第18B圖、第19B圖、第20B圖、第21B圖以及第22B圖分別繪示第2A圖、第3A圖、第4A圖、第5A圖、第6A圖、第7A圖、第8A圖、第9A圖、第10A圖、第11A圖、第12A圖、第13A圖、第14A圖、第15A圖、第16A圖、第17A圖、第18A圖、第19A圖、第20A圖、第21A圖以及第22A圖中沿著對應之第1B圖中線段X1-X1的剖視圖。 Figure 2B, Figure 3B, Figure 4B, Figure 5B, Figure 6B, Figure 7B, Figure 8B, Figure 9B, Figure 10B, Figure 11B, Figure 12B, Figure 13B, and Figure 14B Figures 15B, 16B, 17B, 18B, 19B, 20B, 21B, and 22B show Figures 2A, 3A, 4A, and 5A, respectively. Figure 6A, Figure 7A, Figure 8A, Figure 9A, Figure 10A, Figure 11A, Figure 12A, Figure 13A, Figure 14A, Figure 15A, Figure 16A, Figure 17A, 18A, 19A, 20A, 21A, and 22A are cross-sectional views taken along line X1-X1 of the corresponding 1B diagram.

第12C圖以及第14C圖分別繪示第12A圖以及第14A圖中沿著對應之第1B圖中線段Y1-Y1的剖視圖。 Figures 12C and 14C show cross-sectional views along the corresponding line segments Y1-Y1 in Figure 1B and Figure 14A, respectively, in Figures 12A and 14A.

第21C圖以及第22C圖分別繪示第21A圖以及第22A圖的平面圖。 21C and 22C show plan views of FIGS. 21A and 22A, respectively.

第23A圖、第24A圖、第25A圖、第26A圖、第27A圖、第28A圖、第29A圖、第30A圖、第31A圖、第32A圖、第33A圖、第34A圖、第35A圖、第36A圖、第37A圖、第38A圖、第39A圖、第40A圖、第41A圖、第42A圖、第43A圖、第44A圖以及第45圖分別繪示依據本揭露之一些實施方式之半導體元件的立體圖。 Figure 23A, Figure 24A, Figure 25A, Figure 26A, Figure 27A, Figure 28A, Figure 29A, Figure 30A, Figure 31A, Figure 32A, Figure 33A, Figure 34A, Figure 35A Figure 36A, Figure 37A, Figure 38A, Figure 38A, Figure 39A, Figure 40A, Figure 41A, Figure 42A, Figure 43A, Figure 44A, and Figure 45 respectively show some implementations in accordance with this disclosure. A perspective view of a semiconductor device of a mode.

第23B圖繪示依據本揭露之一些實施方式之半導體元件的平面圖。 FIG. 23B is a plan view of a semiconductor device according to some embodiments of the present disclosure.

第23C圖繪示沿著第23B圖中線段X11-X11的剖視圖。 FIG. 23C is a cross-sectional view taken along line X11-X11 in FIG. 23B.

第23D圖繪示沿著第23B圖中線段X12-X12的剖視圖。 FIG. 23D is a cross-sectional view taken along line X12-X12 in FIG. 23B.

第24B圖、第25B圖、第26B圖、第27B圖、第28B圖、第29B圖、第30B圖、第31B圖、第32B圖、第33B圖、第34B圖、第35B圖、第36B圖、第37B圖、第38B圖、第39B圖、第40B圖、第41B圖、第42B圖、第43B圖、第44B圖以及第45B圖分別繪示第24A圖、第25A圖、第26A圖、第27A圖、第28A圖、第29A圖、第30A圖、第31A圖、第32A圖、第33A圖、第34A圖、第35A圖、第36A圖、第37A圖、第38A圖、第39A圖、第40A圖、第41A圖、第42A圖、第43A圖、第44A圖以及第45A圖中沿著對應之第23B圖中線段X12-X12的剖視圖。 Figure 24B, Figure 25B, Figure 26B, Figure 27B, Figure 28B, Figure 29B, Figure 30B, Figure 31B, Figure 32B, Figure 33B, Figure 34B, Figure 35B, Figure 36B Figures, 37B, 38B, 39B, 40B, 41B, 42B, 43B, 44B, and 45B show Figures 24A, 25A, and 26A, respectively. Figure 27A, Figure 28A, Figure 29A, Figure 30A, Figure 31A, Figure 32A, Figure 33A, Figure 34A, Figure 35A, Figure 36A, Figure 37A, Figure 38A, 39A, 40A, 41A, 42A, 43A, 44A, and 45A are cross-sectional views taken along line X12-X12 of the corresponding 23B diagram.

第36C圖、第39C圖以及第44C圖分別繪示第36A圖、第39A圖以及第44A圖的平面圖。 Figures 36C, 39C, and 44C show plan views of Figures 36A, 39A, and 44A, respectively.

第39D圖繪示沿著第39A圖中方向Y之軸的側視圖。 Figure 39D shows a side view along the axis of the direction Y in Figure 39A.

應理解，以下揭示內容提供用於實現本揭露之不同特徵的許多不同實施方式或實例。下文描述組件及排列之特定實施方式或實例以簡化本揭露。當然，此等僅僅為實例且不意欲作為限制。例如，元件之尺寸並不限於所揭示之範圍或數值，但可取決於元件之製程條件及/或所要性質。此外，在隨後描述中在第二特徵上方或在第二特徵上之第一特徵之形成可包含第一及第二特徵以直接接觸形成之實施方式，以及亦可包含可形成***在第一及第二特徵之間的額外特徵，以使得第一及第二特徵可不直接接觸之實施方式。為了簡明及清晰考慮，各特徵可任意以不同比例繪製。 It should be understood that the following disclosure provides many different implementations or examples for implementing different features of the disclosure. Specific implementations or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the size of the device is not limited to the disclosed range or value, but may depend on the process conditions and / or desired properties of the device. In addition, in the following description, the formation of the first feature above or on the second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an insert that may be formed in the first and second features. An embodiment in which additional features are provided between the second features so that the first and second features may not be in direct contact. For conciseness and clarity, each feature can be arbitrarily drawn at different scales.

另外，空間相對術語，諸如「在…之下」、「在…下方」、「下部」、「在…上方」、「上部」及類似者，為便於描述在本文中可用於描述諸圖中所繪示一個元件或特徵與另一元件(或多個元件)或特徵(或多個特徵)之關係。除附圖中描繪之方向外，空間相對術語意欲包含在使用或操作中之元件的不同定向。元件可為不同之定向(旋轉90度或以其他定向)及在本文中使用之空間相對的描述詞可同樣地解釋。另外，術語「由…組成(made of)」可意謂「包含(comprising)」或「由…組成(consisting of)」。 In addition, spatially relative terms, such as "below", "below", "lower", "above", "upper" and the like, may be used in this text to describe Draw the relationship between one element or feature and another element (or elements) or feature (or features). In addition to the directions depicted in the figures, spatially relative terms are intended to encompass different orientations of the elements in use or operation. Elements can be in different orientations (rotated 90 degrees or at other orientations) and spatially relative descriptors used herein can be interpreted the same. In addition, the term "made of" may mean "comprising" or "consisting of".

第1A圖、第1B圖、第1C圖、第1D圖以及第1E圖分別繪示依據本揭露之一些實施方式之半導體鰭式場效電晶體(fin field effect transistor；FinFET)的各視圖。 FIG. 1A, FIG. 1B, FIG. 1C, FIG. 1D, and FIG. 1E respectively show views of a fin field effect transistor (FinFET) of a semiconductor fin field effect transistor according to some embodiments of the present disclosure.

在本揭露中，兩個閘極圖案沿著方向X延伸且對準之，並藉由分離壁而實體分離。前述之分離壁的材質為介電材料。如第1A圖、第1B圖、第1C圖、第1D圖以及第1E圖中所示，半導體元件包含基板10、半導體鰭片20以及閘極結構90。半導體鰭片20之底部位嵌入於隔離絕緣層30中。隔離絕緣層30亦稱為淺溝槽隔離(shallow trench isolation；STI)層。在第1A圖、第1B圖、第1C圖、第1D圖以及第1E圖中，四個半導體鰭片20，包含第一鰭片F1、第二鰭片F2、第三鰭片F3以及第四鰭片F4，設置於基板10上方，但半導體鰭片20的數目並不限於四個。一些閘極結構90藉由介電分離壁50而實體分離。介電分離壁50由介電材料組成。於一些實施方式中，介電分離壁50進一步藉由第一覆蓋層51覆蓋。在閘極結構90之相對側上，設置側壁間隙壁76。閘極結構90包含閘極介電層92、功函數調整層94以及主體閘極電極96。 In the present disclosure, the two gate patterns extend along the direction X and are aligned, and are physically separated by a separation wall. The material of the aforementioned separation wall is a dielectric material. As shown in FIGS. 1A, 1B, 1C, 1D, and 1E, the semiconductor element includes a substrate 10, a semiconductor fin 20, and a gate structure 90. The bottom of the semiconductor fin 20 is embedded in the isolation insulating layer 30. The isolation insulating layer 30 is also referred to as a shallow trench isolation (STI) layer. In FIGS. 1A, 1B, 1C, 1D, and 1E, the four semiconductor fins 20 include a first fin F1, a second fin F2, a third fin F3, and a fourth fin. The fins F4 are disposed above the substrate 10, but the number of the semiconductor fins 20 is not limited to four. Some gate structures 90 are physically separated by a dielectric separation wall 50. The dielectric separation wall 50 is composed of a dielectric material. In some embodiments, the dielectric separation wall 50 is further covered by the first covering layer 51. On the opposite side of the gate structure 90, a side wall spacer 76 is provided. The gate structure 90 includes a gate dielectric layer 92, a work function adjustment layer 94, and a main gate electrode 96.

半導體鰭片20中不被閘極結構90所覆蓋的部位為源極/汲極(source/drain；S/D)區域。源極/汲極(source/drain,S/D)磊晶層80在半導體鰭片20之源極/汲極區域上形成，且蝕刻終止層(etch stop layer；ESL)82在源極/汲極磊晶層80上方形成。另外，層間介電(interlayer dielectric；ILD)層84係形成以覆蓋源極/汲極結構。 A portion of the semiconductor fin 20 that is not covered by the gate structure 90 is a source / drain (S / D) region. A source / drain (S / D) epitaxial layer 80 is formed on the source / drain region of the semiconductor fin 20, and an etch stop layer (ESL) 82 is formed on the source / drain An extremely epitaxial layer 80 is formed. In addition, an interlayer dielectric (ILD) layer 84 is formed to cover the source / drain structure.

於一些實施方式中，在第1A圖、第1B圖、第1C圖、第1D圖以及第1E圖中，半導體鰭片20(亦可稱為鰭片結構)包含依序設置之第一鰭片F1、第二鰭片F2、第三鰭片F3以及第四鰭片F4。第二鰭片F2為在其上形成介電分離壁50之虛設 鰭片。於一些實施方式中，當第一鰭片F1與第二鰭片F2之間的節距P1(pitch)為基礎鰭片節距FP時，第一鰭片F1與第三鰭片F3之間的節距P2為兩倍的基礎鰭片節距FP及第三鰭片F3與第四鰭片F4之間的節距P3為三倍或三倍以上的基礎鰭片節距FP。於一些實施方式中，鰭片節距P1為約14奈米(nm)至約30奈米(nm)。 In some embodiments, in FIGS. 1A, 1B, 1C, 1D, and 1E, the semiconductor fin 20 (also referred to as a fin structure) includes a first fin disposed in sequence. F1, the second fin F2, the third fin F3, and the fourth fin F4. The second fin F2 is a dummy fin on which the dielectric separation wall 50 is formed. In some embodiments, when the pitch P1 (pitch) between the first fin F1 and the second fin F2 is the base fin pitch FP, the distance between the first fin F1 and the third fin F3 The pitch P2 is twice the base fin pitch FP and the pitch P3 between the third fin F3 and the fourth fin F4 is three times or more the base fin pitch FP. In some embodiments, the fin pitch P1 is about 14 nanometers (nm) to about 30 nanometers (nm).

如第1C圖及第1D圖中所示，於一些實施方式中，在源極/汲極區域上之蝕刻終止層82與層間介電層84之上表面之間的距離H1位於自約14奈米(nm)至約30奈米(nm)之範圍內。於一些實施方式中，在介電分離壁50上之蝕刻終止層82與層間介電層84之上表面之間的距離H2位於自約20奈米(nm)至約50奈米(nm)之範圍內。於一些實施方式中，在第一鰭片F1上之功函數調整層94與主體閘極電極96之上表面之間的距離H3位於自約14奈米(nm)至約30奈米(nm)之範圍內。於一些實施方式中，在第一鰭片F1之頂部位與主體閘極電極96之上表面之間的距離H4位於自約18奈米(nm)至約40奈米(nm)之範圍內。 As shown in FIG. 1C and FIG. 1D, in some embodiments, the distance H1 between the etch stop layer 82 on the source / drain region and the upper surface of the interlayer dielectric layer 84 is about 14 nanometers. In the range of meters (nm) to about 30 nanometers (nm). In some embodiments, the distance H2 between the etch stop layer 82 on the dielectric separation wall 50 and the upper surface of the interlayer dielectric layer 84 is between about 20 nanometers (nm) and about 50 nanometers (nm). Within range. In some embodiments, the distance H3 between the work function adjustment layer 94 on the first fin F1 and the upper surface of the main gate electrode 96 is from about 14 nanometers (nm) to about 30 nanometers (nm). Within range. In some embodiments, the distance H4 between the top position of the first fin F1 and the upper surface of the main gate electrode 96 is in a range from about 18 nanometers (nm) to about 40 nanometers (nm).

在第1A圖、第1B圖、第1C圖、第1D圖以及第1E圖中，在介電分離壁50與鄰近鰭片之間的最小距離S1實質上等於鰭片之間的間距。距離S1可為多個鰭片間距。介電分離壁50之寬度實質上等於或略小於鰭片寬度(例如，約5奈米(nm)至約10奈米(nm))。 In FIGS. 1A, 1B, 1C, 1D, and 1E, the minimum distance S1 between the dielectric separation wall 50 and the adjacent fins is substantially equal to the distance between the fins. The distance S1 may be a plurality of fin pitches. The width of the dielectric separation wall 50 is substantially equal to or slightly smaller than the width of the fins (eg, about 5 nanometers (nm) to about 10 nanometers (nm)).

介電分離壁50之寬度於一些實施方式中為約4奈米(nm)至約8奈米(nm)。介電分離壁50與鄰近之鰭片(例如， 第一鰭片F1或第三鰭片F3)之間的最小距離S1(在第1B圖及第1C圖中可見)於一些實施方式中為約8奈米(nm)至約16奈米(nm)。另外，於一些實施方式中，在第三鰭片F3與蝕刻終止層82，即閘極結構之端部之間的距離S2位於自約8奈米(nm)至約16奈米(nm)之範圍內。 The width of the dielectric separation wall 50 is in some embodiments from about 4 nanometers (nm) to about 8 nanometers (nm). The minimum distance S1 between the dielectric separation wall 50 and an adjacent fin (for example, the first fin F1 or the third fin F3) (visible in FIG. 1B and FIG. 1C) is about 100 Å in some embodiments. 8 nanometers (nm) to about 16 nanometers (nm). In addition, in some embodiments, the distance S2 between the third fin F3 and the etch stop layer 82, that is, the end of the gate structure is located from about 8 nanometers (nm) to about 16 nanometers (nm). Within range.

如第1C圖以及第1D圖中所示，介電分離壁50之底部位在隔離絕緣層30下方。在第1E圖中，線L1對應於隔離絕緣層30之上表面。介電分離壁50包含分離部位50H及虛設部位50L以避免如第1E圖中所示之倒塌(collapse)。閘極結構90延伸於介電分離壁50之虛設部位50L上方，且僅在金屬閘極之頂部產生閘極連接。於此實施方式中，存在「山谷(valley)」部位，此「山谷」部位具有比分離部位50H與虛設部位50L之間的虛設部分更低之高度。 As shown in FIGS. 1C and 1D, the bottom of the dielectric separation wall 50 is located below the isolation insulating layer 30. In FIG. 1E, the line L1 corresponds to the upper surface of the isolation insulating layer 30. The dielectric separation wall 50 includes a separation portion 50H and a dummy portion 50L to avoid collapse as shown in FIG. 1E. The gate structure 90 extends above the dummy portion 50L of the dielectric separation wall 50 and generates a gate connection only on top of the metal gate. In this embodiment, there is a "valley" portion, which has a lower height than the dummy portion between the separation portion 50H and the dummy portion 50L.

在第1E圖中，於一些實施方式中，自第二鰭片F2之頂部位量測之分離部位50H的高度H5位於自約80奈米(nm)至約120奈米(nm)之範圍內。於一些實施方式中，自第二鰭片F2之頂部位量測之虛設部位50L的高度H6位於自約60奈米(nm)至約100奈米(nm)之範圍內。於一些實施方式中，自第二鰭片F2之頂部位量測之嵌入在隔離絕緣層30中之介電分離壁50的底部位的高度H7位於自約5奈米(nm)至約30奈米(nm)之範圍內。 In FIG. 1E, in some embodiments, the height H5 of the separation site 50H measured from the top position of the second fin F2 is in a range from about 80 nanometers (nm) to about 120 nanometers (nm). . In some embodiments, the height H6 of the dummy portion 50L measured from the top position of the second fin F2 is in a range from about 60 nanometers (nm) to about 100 nanometers (nm). In some embodiments, the height H7 of the bottom position of the dielectric separation wall 50 embedded in the isolation insulation layer 30 measured from the top position of the second fin F2 is from about 5 nanometers (nm) to about 30 nanometers. Within meters (nm).

介電分離壁50的材料可為碳氮化矽(SiCN)、碳氮氧化矽(SiOCN)以及金屬氧化物(metal oxide)(例如，氧化鉿 (HfO2)、氧化鋯(ZrO2)氧化鋁(Al2O3)或任何適合的介電材料。於一些實施方式中，碳氮化矽(SiCN)用作介電分離壁50。 The material of the dielectric separation wall 50 may be silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and metal oxide (for example, hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3 ) Or any suitable dielectric material. In some embodiments, silicon carbonitride (SiCN) is used as the dielectric separation wall 50.

第1F圖為本揭露之另一實施方式。於此實施方式中，在分離部位50H與虛設部位50L之間不存在「山谷」部位。 FIG. 1F is another embodiment of the disclosure. In this embodiment, there is no "valley" portion between the separation portion 50H and the dummy portion 50L.

第2A圖至第22C圖繪示依據本揭露之一些實施方式之半導體元件於不同中間製造階段下的示意圖。於第2A圖至第22C圖中，「A」圖(例如，第1A圖或第2A圖等)繪示為立體圖，「B」圖(例如，第1B圖或第2B圖等)繪示沿著對應於第1B圖中線段X1-X1之方向X的剖視圖，而「C」圖(例如，第21C圖等)繪示為平面圖。應理解，可在由第2A圖至第22C圖繪示之製程之前、期間及之後提供額外操作，且對於方法之額外實施方式，可取代或去除下文所述之一些操作。操作/製程之順序可互換。 2A to 22C are schematic diagrams of a semiconductor device according to some embodiments of the present disclosure at different intermediate manufacturing stages. In FIGS. 2A to 22C, “A” (for example, FIG. 1A or 2A, etc.) is shown as a perspective view, and “B” (for example, FIG. 1B or 2B, etc.) is shown along A cross-sectional view corresponding to the direction X of the line segment X1-X1 in FIG. 1B is shown, and the “C” drawing (for example, FIG. 21C, etc.) is shown as a plan view. It should be understood that additional operations may be provided before, during, and after the process illustrated by FIGS. 2A to 22C, and for additional implementations of the method, some operations described below may be replaced or eliminated. The order of operations / processes is interchangeable.

在第2A圖以及第2B圖中，半導體鰭片20在基板10上方形成。為製造鰭片結構，藉由例如熱氧化(thermal oxidation)製程及/或化學氣相沉積(chemical vapor deposition；CVD)製程而在基板10(例如，半導體晶圓)上方形成遮罩層。舉例來說，基板10為具有一雜質濃度之p型矽基板，此雜質濃度位於自約1×1015cm-3與約5×1015cm-3之範圍內。於其他實施方式中，基板10為具有雜質濃度之n型矽基板，此雜質濃度位於自約1×1015cm-3與約5×1015cm-3之範圍內。 In FIGS. 2A and 2B, the semiconductor fins 20 are formed above the substrate 10. To manufacture the fin structure, a mask layer is formed over the substrate 10 (for example, a semiconductor wafer) by, for example, a thermal oxidation process and / or a chemical vapor deposition (CVD) process. For example, the substrate 10 is a p-type silicon substrate having an impurity concentration, and the impurity concentration is in a range from about 1 × 10 15 cm -3 and about 5 × 10 15 cm -3 . In other embodiments, the substrate 10 is an n-type silicon substrate having an impurity concentration, and the impurity concentration is in a range from about 1 × 10 15 cm -3 and about 5 × 10 15 cm -3 .

可選地，基板10可包含：另一元素半導體，諸如鍺(germanium)；化合物半導體，其包含諸如碳化矽(SiC)及鍺化矽(SiGe)之IV-IV族化合物半導體及諸如砷化鎵 (GaAs)、磷化鎵(GaP)、氮化鎵(GaN)、磷化銦(InP)、砷化銦(InAs)、銻化銦(InSb)、磷砷化鎵(GaAsP)、氮化鋁鎵(AlGaN)、砷銦化鋁(AlInAs)、鋁鎵砷(AlGaAs)、砷銦化鎵(GaInAs)、磷銦化鎵(GaInP)及/或磷砷化銦鎵(GaInAsP)之III-V族化合物半導體；或前述之任意組合。於一實施方式中，基板10係絕緣體覆矽(silicon-on insulator；SOI)基板之矽層。非晶體基板(諸如非晶體矽(amorphous Si)或非晶體碳化矽(amorphous SiC)或諸如二氧化矽(silicon oxide)之絕緣材料)亦可作為基板10。基板10可包含已適當摻雜有雜質(例如，P型或N型導電性)的區域。 Alternatively, the substrate 10 may include: another element semiconductor such as germanium; a compound semiconductor including a group IV-IV compound semiconductor such as silicon carbide (SiC) and silicon germanium (SiGe); and a compound semiconductor such as gallium arsenide (GaAs), gallium phosphide (GaP), gallium nitride (GaN), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), gallium phosphorus arsenide (GaAsP), aluminum nitride III-V of gallium (AlGaN), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium arsenide (GaInAs), gallium indium phosphide (GaInP) and / or indium gallium arsenide (GaInAsP) Group compound semiconductor; or any combination of the foregoing. In one embodiment, the substrate 10 is a silicon layer of a silicon-on insulator (SOI) substrate. An amorphous substrate (such as amorphous Si or amorphous SiC or an insulating material such as silicon oxide) can also be used as the substrate 10. The substrate 10 may include a region that has been appropriately doped with impurities (for example, P-type or N-type conductivity).

於一些實施方式中，遮罩層包含，襯墊氧化物層24(例如，氧化矽(silicon oxide))及氮化矽遮罩層25。襯墊氧化物層24可藉由使用熱氧化製程或化學氣相沉積製程來形成。氮化矽遮罩層25可藉由諸如濺射方法之物理氣相沉積(physical vapor deposition；PVD)製程、化學氣相沉積(chemical vapor deposition；CVD)製程、電漿增強化學氣相沉積(plasma-enhanced chemical vapor deposition；PECVD)製程、大氣壓化學氣相沉積(atmospheric pressure chemical vapor deposition；APCVD)製程、低壓化學氣相沉積(low-pressure CVD；LPCVD)製程、高密度電漿化學氣相沉積(high density plasma CVD；HDPCVD)製程、原子層沉積(atomic layer deposition；ALD)製程及/或其他製程而形成。 In some embodiments, the masking layer includes a pad oxide layer 24 (eg, silicon oxide) and a silicon nitride masking layer 25. The pad oxide layer 24 may be formed by using a thermal oxidation process or a chemical vapor deposition process. The silicon nitride mask layer 25 may be formed by a physical vapor deposition (PVD) process such as a sputtering method, a chemical vapor deposition (CVD) process, or a plasma enhanced chemical vapor deposition (plasma) process. -enhanced chemical vapor deposition (PECVD) process, atmospheric pressure chemical vapor deposition (APCVD) process, low-pressure chemical vapor deposition (LPCVD) process, high-density plasma chemical vapor deposition ( High density plasma CVD (HDPCVD) process, atomic layer deposition (ALD) process, and / or other processes.

於一些實施方式中，襯墊氧化物層24之厚度位於自約2奈米(nm)至約15奈米(nm)之範圍內，而氮化矽遮罩層25之厚度位於自約2奈米(nm)至約50奈米(nm)之範圍內。遮罩圖案進一步在遮罩層上方形成。舉例來說，遮罩圖案為藉由光蝕刻法形成之光致抗蝕劑圖案。 In some embodiments, the thickness of the pad oxide layer 24 is in a range from about 2 nanometers (nm) to about 15 nanometers (nm), and the thickness of the silicon nitride masking layer 25 is in a range from about 2 nanometers. In the range of meters (nm) to about 50 nanometers (nm). A mask pattern is further formed over the mask layer. For example, the mask pattern is a photoresist pattern formed by a photo-etching method.

藉由使用遮罩圖案作為蝕刻遮罩，形成襯墊氧化物層24及氮化矽遮罩層25之硬遮罩圖案。 By using the mask pattern as an etching mask, a hard mask pattern of the pad oxide layer 24 and the silicon nitride mask layer 25 is formed.

藉由使用硬遮罩圖案作為蝕刻遮罩，並藉由使用乾式蝕刻法及/或濕式蝕刻法之溝槽蝕刻而將基板10圖案化成半導體鰭片20。 The substrate 10 is patterned into the semiconductor fins 20 by using a hard mask pattern as an etching mask and by trench etching using a dry etching method and / or a wet etching method.

於一實施方式中，在基板10上方設置之半導體鰭片20由與基板10相同之材料組成並自基板10連續地延伸。半導體鰭片20可為本征的，或適當摻雜有n型雜質或p型雜質。 In one embodiment, the semiconductor fins 20 disposed above the substrate 10 are composed of the same material as the substrate 10 and continuously extend from the substrate 10. The semiconductor fin 20 may be intrinsic, or appropriately doped with n-type impurities or p-type impurities.

在圖中，設置四個半導體鰭片20。半導體鰭片20用於p型鰭式場效電晶體及/或n型鰭式場效電晶體。半導體鰭片20之數目並不限於四個。此數目可小至一個，或多於四個。另外，多個虛設鰭片結構之一者可鄰近於半導體鰭片20之兩側設置以改進圖案化製程中之圖案保真度。於一些實施方式中，半導體鰭片20之寬度位於自約5奈米(nm)至約30奈米(nm)之範圍內。於一些實施方式中，半導體鰭片20之寬度位於自約7奈米(nm)至約20奈米(nm)之範圍內。於一些實施方式中，半導體鰭片20之高度H11位於自約100奈米(nm)至約300奈米(nm)之範圍內。於一些實施方式中，半導體鰭片20之高度H11位於約50奈米(nm)至100奈米(nm)之範圍內。當半導體鰭片 20之高度不均勻時，基板10之高度可自平面量測，此平面對應於半導體鰭片20之平均高度。於一些實施方式中，在鰭片蝕刻之後的遮罩圖案的高度H12位於約4奈米(nm)至約50(nm)奈米之間。 In the figure, four semiconductor fins 20 are provided. The semiconductor fin 20 is used for a p-type fin-type field effect transistor and / or an n-type fin-type field effect transistor. The number of the semiconductor fins 20 is not limited to four. This number can be as small as one or more than four. In addition, one of the plurality of dummy fin structures may be disposed adjacent to both sides of the semiconductor fin 20 to improve pattern fidelity in the patterning process. In some embodiments, the width of the semiconductor fin 20 is in a range from about 5 nanometers (nm) to about 30 nanometers (nm). In some embodiments, the width of the semiconductor fins 20 is in a range from about 7 nanometers (nm) to about 20 nanometers (nm). In some embodiments, the height H11 of the semiconductor fin 20 is in a range from about 100 nanometers (nm) to about 300 nanometers (nm). In some embodiments, the height H11 of the semiconductor fin 20 is in a range of about 50 nanometers (nm) to 100 nanometers (nm). When the height of the semiconductor fins 20 is not uniform, the height of the substrate 10 can be measured from a plane, and this plane corresponds to the average height of the semiconductor fins 20. In some embodiments, the height H12 of the mask pattern after the fin etch is between about 4 nanometers (nm) to about 50 (nm) nanometers.

在第3A圖及第3B圖中，形成隔離絕緣層30。用以形成隔離絕緣層30之絕緣材料層在基板10上方形成以便完全地覆蓋半導體鰭片20。 In FIGS. 3A and 3B, an isolation insulating layer 30 is formed. An insulating material layer for forming the isolation insulating layer 30 is formed over the substrate 10 so as to completely cover the semiconductor fins 20.

舉例來說，隔離絕緣層30的絕緣材料可為二氧化矽(silicon dioxide)。前述之二氧化矽(silicon dioxide)的形成方法包含，例如，低氣壓化學氣相沉積(low-pressure CVD；LPCVD)製程、電漿化學氣相沉積(plasma CVD)製程或流動化學氣相沉積(flowable CVD)製程。在可流動化學氣相沉積製程中，可流動介電材料被沉積，而非氧化矽(silicon oxide)被沉積。可流動介電材料，如其名稱所表示，可在沉積期間「流動」以充填具有高深寬比之間隙或間距。通常，將各種化學劑添加至含矽前驅物以允許沉積膜流動。於一些實施方式中，添加氮氫鍵(nitrogen hydride bond)。可流動介電前驅物，尤其可流動氧化矽前驅物之實例包含矽酸鹽(silicate)、矽氧烷(siloxane)、甲基倍半矽氧烷(methyl silsesquioxane；MSQ)、氫倍半矽氧烷(hydrogen silsesquioxane；HSQ)、甲基倍半矽氧烷/氫倍半矽氧烷(MSQ/HSQ)、全氫矽氮烷(perhydrosilazane；TCPS)、全氫聚矽氮烷(perhydro-polysilazane；PSZ)、四乙基原矽酸酯(tetraethyl orthosilicate；TEOS)或甲矽烷基醯胺(silyl-amine)，諸如三 甲矽烷基(trisilylamine；TSA)。此等可流動氧化矽材料在多個操作製程中形成。在沉積可流動膜之後，其經固化及隨後退火以移除不需要之元素以形成氧化矽。當移除不需要之元素時，可流動膜緻密化及縮小。於一些實施方式中，進行多個退火製程。可流動膜可進行多於一次地固化及退火。隔離絕緣層30可為旋轉塗佈玻璃(SOG)、氧化矽(SiO)、氮氧化矽(SiON)、碳氮氧化矽(SiOCN)或摻氟矽酸鹽玻璃(fluorine-doped silicate glass；FSG)。隔離絕緣層30可摻雜有硼及/或磷。 For example, the insulating material of the isolation insulating layer 30 may be silicon dioxide. The aforementioned method for forming silicon dioxide includes, for example, a low-pressure chemical vapor deposition (LPCVD) process, a plasma chemical vapor deposition (plasma CVD) process, or a flow chemical vapor deposition ( flowable CVD) process. In a flowable chemical vapor deposition process, a flowable dielectric material is deposited instead of silicon oxide. A flowable dielectric material, as its name implies, can "flow" during deposition to fill gaps or gaps with high aspect ratios. Generally, various chemicals are added to the silicon-containing precursor to allow the deposited film to flow. In some embodiments, a nitrogen hydride bond is added. Examples of flowable dielectric precursors, especially flowable silicon oxide precursors, include silicate, siloxane, methyl silsesquioxane (MSQ), and hydrogen silsesquioxane (Hydrogen silsesquioxane (HSQ), methyl silsesquioxane / hydrogen silsesquioxane (MSQ / HSQ), perhydrosilazane (TCPS), perhydro-polysilazane; (PSZ), tetraethyl orthosilicate (TEOS), or silyl-amine, such as trisilylamine (TSA). These flowable silicon oxide materials are formed in a number of operating processes. After the flowable film is deposited, it is cured and subsequently annealed to remove unwanted elements to form silicon oxide. When unwanted elements are removed, the flowable film is densified and shrunk. In some embodiments, multiple annealing processes are performed. The flowable film can be cured and annealed more than once. The isolation insulating layer 30 may be spin-on-glass (SOG), silicon oxide (SiO), silicon oxynitride (SiON), silicon carbonitride (SiOCN), or fluorine-doped silicate glass (FSG). . The isolation insulating layer 30 may be doped with boron and / or phosphorus.

另外，執行平坦化操作，諸如化學機械研磨(chemical mechanical polishing；CMP)方法，從而暴露氮化矽遮罩層25，如第3A圖及第3B圖所示。 In addition, a planarization operation such as a chemical mechanical polishing (CMP) method is performed to expose the silicon nitride mask layer 25 as shown in FIGS. 3A and 3B.

在第4A圖及第4B圖中，第一遮罩層40在隔離絕緣層30上形成，且第二遮罩層42在第一遮罩層40上形成。第一遮罩層40包含氮化矽(SiN)及氮氧化矽(SiON)之一或多個層。第二遮罩層42由IV族材料之非晶或多晶材料組成，諸如非晶矽(amorphous silicon)或多晶矽(poly silicon)、矽鍺(silicon germanium)或鍺(germanium)。於一些實施方式中，第一遮罩層40為具有約5奈米(nm)至約30奈米(nm)之厚度的氮化矽(SiN)，且第二遮罩層42由非晶矽組成，此非晶矽具有約5奈米(nm)至約30奈米(nm)之厚度。第一遮罩層40及第二遮罩層42藉由化學氣相沉積製程、物理氣相沉積製程或原子層沉積製程或任何適合薄膜形成方法而形成。 In FIGS. 4A and 4B, the first mask layer 40 is formed on the isolation insulating layer 30, and the second mask layer 42 is formed on the first mask layer 40. The first masking layer 40 includes one or more layers of silicon nitride (SiN) and silicon oxynitride (SiON). The second mask layer 42 is composed of an amorphous or polycrystalline material of a group IV material, such as amorphous silicon or poly silicon, silicon germanium, or germanium. In some embodiments, the first masking layer 40 is silicon nitride (SiN) having a thickness of about 5 nanometers (nm) to about 30 nanometers (nm), and the second masking layer 42 is made of amorphous silicon. The amorphous silicon has a thickness of about 5 nanometers (nm) to about 30 nanometers (nm). The first mask layer 40 and the second mask layer 42 are formed by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or any suitable thin film formation method.

在第5A圖及第5B圖中，光致抗蝕劑層45在第二遮罩層42上方形成，且藉由使用微影(lithography)及蝕刻(etching)操作，移除在第二鰭片F2上方之第一遮罩層40及第二遮罩層42之一部分。 In FIGS. 5A and 5B, a photoresist layer 45 is formed over the second mask layer 42 and is removed from the second fin by using a lithography and etching operation. A portion of the first mask layer 40 and the second mask layer 42 above F2.

在第6A圖及第6B圖中，藉由使用穿過開口46之適宜蝕刻操作，移除在第二鰭片F2上形成之襯墊氧化物層24(可視為遮罩層)以及氮化矽遮罩層25(可視為遮罩層)。藉由此蝕刻，暴露第二鰭片F2之頂表面。 In FIGS. 6A and 6B, the pad oxide layer 24 (which can be regarded as a mask layer) and the silicon nitride formed on the second fin F2 are removed by using a suitable etching operation through the opening 46. The mask layer 25 (can be regarded as a mask layer). By this etching, the top surface of the second fin F2 is exposed.

在第7A圖及第7B圖中，藉由適當乾式蝕刻使第二鰭片F2產生凹陷。隨著蝕刻，第二鰭片F2之上部位具有U形蝕刻殘餘部位29，如在第7B圖中繪示。 In FIGS. 7A and 7B, the second fin F2 is recessed by appropriate dry etching. With the etching, a U-shaped etching residual portion 29 is formed on the second fin F2, as shown in FIG. 7B.

在第8A圖及第8B圖中，藉由適宜濕式蝕刻來移除蝕刻殘餘部位29。在製造作業之階段中，第二鰭片F2之蝕刻深度H13於一些實施方式中位於自約100奈米(nm)至約300奈米(nm)之範圍內。 In FIGS. 8A and 8B, the etching residue 29 is removed by suitable wet etching. In the stage of the manufacturing operation, the etch depth H13 of the second fin F2 is in a range from about 100 nanometers (nm) to about 300 nanometers (nm) in some embodiments.

在第9A圖以及第9B圖中，形成介電分離壁50之介電材料。藉由化學氣相沉積製程或原子層沉積製程形成介電材料之毯覆層，隨後執行化學機械研磨或回蝕操作。介電分離壁50包含氮化矽(SiN)、碳氮化矽(SiCN)、碳氮氧化矽(SiOCN)及金屬氧化物(metal oxide)，諸如氧化鉿(HfO2)、氧化鋯(ZrO2)及氧化鋁(Al2O3)或任何適合介電材料之一或多個層。 In FIGS. 9A and 9B, a dielectric material of the dielectric separation wall 50 is formed. A blanket of a dielectric material is formed by a chemical vapor deposition process or an atomic layer deposition process, and then a chemical mechanical polishing or etch-back operation is performed. The dielectric separation wall 50 includes silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and metal oxides such as hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ) And alumina (Al 2 O 3 ) or one or more layers of any suitable dielectric material.

於一些實施方式中，在形成介電分離壁50之介電材料之前，形成第一覆蓋層51。第一覆蓋層51由，例如，氧 化矽(silicon oxide)或其他適宜介電材料組成並可藉由化學氣相沉積製程或原子層沉積製程形成。第一覆蓋層51之厚度於一些實施方式中位於約0.5奈米(nm)至約2奈米(nm)之範圍內。 In some embodiments, the first cover layer 51 is formed before the dielectric material of the dielectric separation wall 50 is formed. The first cover layer 51 is made of, for example, silicon oxide or other suitable dielectric materials and can be formed by a chemical vapor deposition process or an atomic layer deposition process. The thickness of the first cover layer 51 is in a range of about 0.5 nanometers (nm) to about 2 nanometers (nm) in some embodiments.

在第10A圖及第10B圖中，第三遮罩層52在隔離絕緣層30上方形成，且形成具有開口56之抗蝕圖案54。第三遮罩層52由IV族材料之非晶或多晶材料組成，諸如非晶矽(poly silicon)或多晶矽(poly silicon)、矽鍺(silicon germanium)或鍺(germanium)。於一些實施方式中，第三遮罩層52由具有約5奈米(nm)至約30奈米(nm)之厚度的非晶矽組成。開口56之尺寸實質上與閘極之間的節距(pitch)相等，並位於隨後分隔閘極之位置處。 In FIGS. 10A and 10B, the third mask layer 52 is formed above the isolation insulating layer 30, and a resist pattern 54 having an opening 56 is formed. The third mask layer 52 is composed of an amorphous or polycrystalline material of a group IV material, such as poly silicon or poly silicon, silicon germanium, or germanium. In some embodiments, the third mask layer 52 is composed of amorphous silicon having a thickness of about 5 nanometers (nm) to about 30 nanometers (nm). The size of the opening 56 is substantially equal to the pitch between the gates, and is located at a position where the gates are subsequently separated.

在第11A圖及第11B圖中，藉由使用抗蝕圖案54(也可為光致抗蝕劑圖案)作為蝕刻遮罩來蝕刻第三遮罩層52，進而以一個閘極間距寬度在第三遮罩層52中形成開口58。開口58在方向Y上之寬度S11於一些實施方式中位於自約20奈米(nm)至約50奈米(nm)之範圍中。隨後，移除抗蝕圖案54。 In FIGS. 11A and 11B, the third mask layer 52 is etched by using the resist pattern 54 (which may also be a photoresist pattern) as an etching mask, and then a gate pitch width of An opening 58 is formed in the three masking layers 52. The width S11 of the opening 58 in the direction Y is in a range from about 20 nanometers (nm) to about 50 nanometers (nm) in some embodiments. Subsequently, the resist pattern 54 is removed.

在第12A圖、第12B圖以及第12C圖中，藉由使用圖案化之第三遮罩層52作為蝕刻遮罩，來使介電分離壁50之一部分產生凹陷。隨後，移除第三遮罩層52。藉由此凹陷蝕刻，介電分離壁50具有經凹陷之低部位50L(也可稱之為虛設部位)，及未經凹陷之高部位50H(也可稱之為分離部位)，如在第 12C圖中繪示。於一些實施方式中，蝕刻高度H14的量位於自約20奈米(nm)至約100奈米(nm)之範圍中。 In FIGS. 12A, 12B, and 12C, a portion of the dielectric separation wall 50 is recessed by using the patterned third mask layer 52 as an etching mask. Subsequently, the third mask layer 52 is removed. By this recess etching, the dielectric separation wall 50 has a recessed low portion 50L (also referred to as a dummy portion) and a high portion 50H (also referred to as a separated portion) that is not recessed, as in section 12C. Shown in the figure. In some embodiments, the amount of etch height H14 is in a range from about 20 nanometers (nm) to about 100 nanometers (nm).

在第13A圖以及第13B圖中，移除襯墊氧化物層24及氮化矽遮罩層25。藉由此操作，亦部分地蝕刻隔離絕緣層30，且部分地暴露介電分離壁50。在製造製程之此階段中，介電分離壁50(或未經凹陷之高部位50H)自隔離絕緣層30之上表面的伸出高度H15於一些實施方式中位於自約5奈米(nm)至約20奈米(nm)之範圍內。介電分離壁50的高部位50H與第一鰭片F1或第三鰭片F3之間的高度差於一些實施方式中位於自約10奈米(nm)至約40奈米(nm)之範圍內。第二鰭片F2與第一鰭片F1或第三鰭片F3之間的差異高度H17於一些實施方式中位於自約100奈米(nm)至約300奈米(nm)之範圍內。於一些實施方式中，高部位50H之高度H18位於自約150奈米(nm)至約400奈米(nm)之範圍內，且低部位50L之高度H19位於自約100奈米(nm)至約300奈米(nm)之範圍內。 In FIGS. 13A and 13B, the pad oxide layer 24 and the silicon nitride mask layer 25 are removed. With this operation, the isolation insulating layer 30 is also partially etched, and the dielectric separation wall 50 is partially exposed. At this stage of the manufacturing process, the protruding height H15 of the dielectric separation wall 50 (or the high portion without depression 50H) from the upper surface of the isolation insulating layer 30 is located from about 5 nanometers (nm) in some embodiments. To about 20 nanometers (nm). The height difference between the high portion 50H of the dielectric separation wall 50 and the first fin F1 or the third fin F3 is in a range from about 10 nanometers (nm) to about 40 nanometers (nm) in some embodiments. Inside. The difference height H17 between the second fin F2 and the first fin F1 or the third fin F3 is in some embodiments within a range from about 100 nanometers (nm) to about 300 nanometers (nm). In some embodiments, the height H18 of the high portion 50H is in a range from about 150 nanometers (nm) to about 400 nanometers (nm), and the height H19 of the low portion 50L is in a range from about 100 nanometers (nm) to In the range of about 300 nanometers (nm).

在第15A圖及第15B圖中，進一步凹陷隔離絕緣層30以便暴露第一鰭片F1、第三鰭片F3及第四鰭片F4以及介電分離壁50之上部位。此處，經凹陷之第二鰭片F2不暴露且仍然嵌入於隔離絕緣層30中。第一鰭片F1、第三鰭片F3及第四鰭片F4於一些實施方式中以約50奈米(nm)至約200奈米(nm)的高度H20而暴露出。 In FIGS. 15A and 15B, the isolation insulating layer 30 is further recessed so as to expose the first fin F1, the third fin F3 and the fourth fin F4, and the upper portion of the dielectric separation wall 50. Here, the recessed second fin F2 is not exposed and is still embedded in the isolation insulating layer 30. The first fin F1, the third fin F3, and the fourth fin F4 are exposed at a height H20 of about 50 nanometers (nm) to about 200 nanometers (nm) in some embodiments.

在第16A圖及第16B圖中，虛設閘極介電層65在經暴露之鰭片及介電分離壁50上形成。虛設閘極介電層65例如於一些實施方式中由具有約0.5奈米(nm)至約2奈米(nm)之 厚度的氧化矽(silicon oxide)組成，及可藉由化學氣相沉積製程及/或原子層沉積製程而形成。虛設閘極介電層65亦在隔離絕緣層30之上表面上形成。 In FIGS. 16A and 16B, a dummy gate dielectric layer 65 is formed on the exposed fins and the dielectric separation wall 50. The dummy gate dielectric layer 65 is, for example, composed of silicon oxide having a thickness of about 0.5 nanometers (nm) to about 2 nanometers (nm) in some embodiments, and may be formed by a chemical vapor deposition process. And / or an atomic layer deposition process. A dummy gate dielectric layer 65 is also formed on the upper surface of the isolation insulating layer 30.

在第17A圖及第17B圖中，形成虛設閘極電極層，且虛設閘極電極層藉由使用包含遮罩層72及遮罩層74之硬遮罩而圖案化，進而形成虛設閘極電極70。至少一個虛設閘極電極70經設置於第一鰭片F1及第三鰭片F3及介電分離壁50之低部位50L的上方，及至少一個虛設閘極電極70經設置於第一鰭片F1及第三鰭片F3及介電分離壁50之高部位50H的上方。於一些實施方式中，遮罩層72由諸如氮化矽(SiN)之基於氮化矽材料組成，及遮罩層74由諸如氧化矽(SiO2)之基於矽氧化物材料(silicon oxide based material)所組成。 In FIGS. 17A and 17B, a dummy gate electrode layer is formed, and the dummy gate electrode layer is patterned by using a hard mask including a mask layer 72 and a mask layer 74 to form a dummy gate electrode. 70. At least one dummy gate electrode 70 is disposed above the low portion 50L of the first fin F1 and the third fin F3 and the dielectric separation wall 50, and at least one dummy gate electrode 70 is disposed at the first fin F1. And the third fin F3 and above the high portion 50H of the dielectric separation wall 50. In some embodiments, the mask layer 72 is composed of a silicon nitride-based material such as silicon nitride (SiN), and the mask layer 74 is composed of a silicon oxide based material such as silicon oxide (SiO2) Composed of.

在第18A圖及第18B圖中，側壁間隙壁76在虛設閘極電極70之相對側面上形成。形成基於矽氮化物材料(silicon nitride based material)(例如，氮化矽(SiN)、氮氧化矽(SiON)或碳氮化矽(SiCN))之毯覆層，且隨後執行各向異性蝕刻。藉由此蝕刻，移除在暴露之鰭片上形成之虛設閘極介電層65。另外，於一些實施方式中使經暴露之介電分離壁50凹陷。在此情況下，可獲得如第1E圖中繪示之結構。在其他實施方式中，不凹陷介電分離壁50。在此情況下，獲得如第1F圖中繪示之結構。 In FIGS. 18A and 18B, the sidewall spacer 76 is formed on the opposite side of the dummy gate electrode 70. A blanket layer based on a silicon nitride based material (for example, silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbon nitride (SiCN)) is formed, and then anisotropic etching is performed. By this etching, the dummy gate dielectric layer 65 formed on the exposed fins is removed. In addition, in some embodiments, the exposed dielectric separation wall 50 is recessed. In this case, a structure as shown in FIG. 1E can be obtained. In other embodiments, the dielectric separation wall 50 is not recessed. In this case, a structure as shown in FIG. 1F is obtained.

在第19A圖及第19B圖中，源極/汲極磊晶層80在經暴露之鰭片上形成。源極/汲極磊晶層80在暴露之鰭片上磊晶地形成，及包含磷化矽(SiP)、碳化矽(SiC)、碳磷化矽 (SiCP)、硼化矽(SiB)、矽鍺(SiGe)及鍺(Ge)之一或多個結晶層。於一些實施方式中，矽化物層進一步在源極/汲極磊晶層80上方形成。 In FIGS. 19A and 19B, a source / drain epitaxial layer 80 is formed on the exposed fins. The source / drain epitaxial layer 80 is epitaxially formed on the exposed fins, and includes silicon phosphide (SiP), silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon boride (SiB), silicon One or more crystalline layers of germanium (SiGe) and germanium (Ge). In some embodiments, a silicide layer is further formed over the source / drain epitaxial layer 80.

隨後，形成蝕刻終止層(ESL)82，且在具有側壁間隙壁76之虛設閘極電極70之間及源極/汲極區域上方的間距中形成層間介電層84。層間介電層84可包含氧化矽(silicon oxide)、氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride；SiON)、氮碳氧化矽(SiOCN)、摻氟矽酸鹽玻璃(fluorine-doped silicate glass；FSG)或低介電常數介電材料(low-k dielectric material)，及可由化學氣相沉積製程或其他適宜製程組成。介電分離壁50之絕緣材料不同於隔離絕緣層30及層間介電層84之絕緣材料。 Subsequently, an etch stop layer (ESL) 82 is formed, and an interlayer dielectric layer 84 is formed in the gaps between the dummy gate electrodes 70 having sidewall spacers 76 and above the source / drain regions. The interlayer dielectric layer 84 may include silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon oxynitride (SiOCN), and fluorine-doped glass. silicate glass (FSG) or low-k dielectric material, and may be composed of a chemical vapor deposition process or other suitable processes. The insulating material of the dielectric separation wall 50 is different from the insulating materials of the isolation insulating layer 30 and the interlayer dielectric layer 84.

執行平坦化操作，諸如回蝕製程及/或化學機械研磨製程，以便暴露虛設閘極電極70及介電分離壁50之上部位。隨後，移除虛設閘極電極70及虛設閘極介電層65，進而形成閘極間距89，如第20A圖及第20B圖所示。 A planarization operation, such as an etch-back process and / or a chemical mechanical polishing process, is performed in order to expose the portions above the dummy gate electrode 70 and the dielectric separation wall 50. Subsequently, the dummy gate electrode 70 and the dummy gate dielectric layer 65 are removed to form a gate pitch 89, as shown in FIGS. 20A and 20B.

在第21A圖、第21B圖以及第21C圖中，包含閘極介電層92及主體閘極電極96(也可為金屬閘極電極層)之金屬閘極結構90在閘極間距89中形成。於某些實施方式中，閘極介電層92包含諸如氧化矽(silicon oxide)、氮化矽(silicon nitride)、或高介電常數介電材料(high-k dielectric material)、其他適宜介電材料及/或其組合之介電材料的一或多個層。高介電常數介電材料之實例包含二氧化鉿(HfO2)、氧化矽鉿(HfSiO)、氮氧化矽鉿(HfSiON，)、氧化鉭鉿 (HfTaO)、氧化鈦鉿(HfTiO)、氧化鋯鉿(HfZrO)、氧化鋯(zirconium oxide)、氧化鋁(aluminum oxide)、氧化鈦(titanium oxide)、氧化鉿-氧化鋁(hafnium dioxide-alumina；HfO2-Al2O3)合金、其他適宜高介電常數介電材料(high-k dielectric material)及/或其組合。 In FIGS. 21A, 21B, and 21C, a metal gate structure 90 including a gate dielectric layer 92 and a main gate electrode 96 (may also be a metal gate electrode layer) is formed in a gate pitch 89. . In some embodiments, the gate dielectric layer 92 includes, for example, silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric materials. One or more layers of a material and / or a combination of dielectric materials. Examples of high dielectric constant dielectric materials include hafnium dioxide (HfO2), silicon oxide (HfSiO), silicon oxynitride (HfSiON,), tantalum oxide (HfTaO), titanium oxide (HfTiO), zirconium oxide (HfZrO), zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO 2 -Al 2 O 3 ) alloy, other suitable high dielectrics High-k dielectric material and / or combinations thereof.

主體閘極電極96包含任何適合材料，諸如鋁(aluminum)、銅(copper)、鈦(titanium)、鉭(tantalum)、鎢(tungsten)、鈷(cobalt)、鉬(molybdenum)、氮化鉭(tantalum nitride)、矽化鎳(nickel silicide)、矽化鈷(cobalt silicide)、氮化鈦(TiN)、氮化鎢(WN)、鋁化鈦(TiAl)、氮化鋁鈦(TiAlN)、碳氮化鉭(TaCN)、碳化鉭(TaC)、氮化矽鉭(TaSiN)、金屬合金(metal alloys)、其他適宜材料及/或其組合。 The body gate electrode 96 includes any suitable material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum ( tantalum nitride), nickel silicide, cobalt silicide, titanium nitride (TiN), tungsten nitride (WN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), carbonitride Tantalum (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), metal alloys, other suitable materials and / or combinations thereof.

於某些實施方式中，一或多個功函數調整層94亦設置於閘極介電層92與主體閘極電極96之間。功函數調整層94由導電材料組成，諸如氮化鈦(TiN)、氮化鉭(TaN)、碳化鉭鋁(TaAlC)、碳化鈦(TiC)、碳化鉭(TaC)、鈷(Co)、鋁(Al)、鋁化鈦(TiAl)、鈦化鉿(HfTi)、矽化鈦(TiSi)、矽化鉭(TaSi)或碳化鈦鋁(TiAlC)之單層、或兩個或兩個以上彼等材料之多層。對於n通道鰭式場效電晶體，氮化鉭(TaN)、碳化鉭鋁(TaAlC)、氮化鈦(TiN)、碳化鈦(TiC)、鈷(Co)、鋁化鈦(TiAl)、鈦化鉿(HfTi)、矽化鈦(TiSi)及矽化鉭(TaSi)之一或多者用作功函數調整層94；及對於p通道鰭式場效電晶體，碳化鉭鋁(TiAlC)、鋁(Al)、鋁化鈦(TiAl)、氮化鉭(TaN)、碳化 鉭鋁(TaAlC)、氮化鈦(TiN)、碳化鈦(TiC)及鈷(Co)之一或多者用作功函數調整層94。功函數調整層94可藉由原子層沉積製程、物理氣相沉積製程、化學氣相沉積製程、電子束蒸發製程或其他適宜製程而形成。另外，可對於可使用不同金屬層之n通道鰭式場效電晶體及p通道鰭式場效電晶體分別形成功函數調整層94。 In some embodiments, one or more work function adjustment layers 94 are also disposed between the gate dielectric layer 92 and the main gate electrode 96. The work function adjustment layer 94 is composed of a conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), titanium carbide (TiC), tantalum carbide (TaC), cobalt (Co), aluminum (Al), single layer of titanium aluminide (TiAl), hafnium titanate (HfTi), titanium silicide (TiSi), tantalum silicide (TaSi), or titanium aluminum carbide (TiAlC), or two or more of them Of multiple layers. For n-channel fin field effect transistors, tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), titanium nitride (TiN), titanium carbide (TiC), cobalt (Co), titanium aluminide (TiAl), titanium One or more of hafnium (HfTi), titanium silicide (TiSi), and tantalum silicide (TaSi) are used as the work function adjustment layer 94; and for p-channel fin field effect transistors, tantalum aluminum carbide (TiAlC), aluminum (Al) , One or more of titanium aluminum (TiAl), tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), titanium nitride (TiN), titanium carbide (TiC), and cobalt (Co) as a work function adjustment layer 94. The work function adjustment layer 94 may be formed by an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process, an electron beam evaporation process, or other suitable processes. In addition, the successful function adjustment layer 94 may be formed separately for the n-channel fin-type field effect transistor and the p-channel fin-type field effect transistor that can use different metal layers.

在形成金屬閘極結構90時，閘極介電層92、功函數調整層94及主體閘極電極96(也可為閘極電極層)係藉由適宜薄膜形成方法，例如用於主體閘極電極96之化學氣相沉積製程或原子層沉積製程、及用於金屬層之化學氣相沉積製程、物理氣相沉積製程、原子層沉積製程或電鍍製程而形成，及隨後執行諸如化學機械研磨之平坦化操作以移除在層間介電層84上方形成之多餘材料。 When forming the metal gate structure 90, the gate dielectric layer 92, the work function adjustment layer 94, and the main gate electrode 96 (also may be a gate electrode layer) are formed by a suitable thin film forming method, for example, for the main gate The electrode 96 is formed by a chemical vapor deposition process or an atomic layer deposition process, and a chemical vapor deposition process for a metal layer, a physical vapor deposition process, an atomic layer deposition process, or an electroplating process, and subsequently performs a process such as chemical mechanical polishing A planarization operation is performed to remove excess material formed over the interlayer dielectric layer 84.

在第22A圖、第22B圖以及第22C圖中，進一步藉由諸如化學機械研磨之平坦化操作來使層間介電層84及金屬閘極結構90凹陷，進而暴露介電分離壁50之高部位50H。 In FIGS. 22A, 22B, and 22C, the interlayer dielectric layer 84 and the metal gate structure 90 are further recessed by a planarization operation such as chemical mechanical polishing, thereby exposing the high portion of the dielectric separation wall 50. 50H.

在其他實施方式中，在第20A圖及第20B圖之操作期間，暴露介電分離壁50以將虛設閘極結構分隔為兩個子虛設閘極結構，及在第21A圖至第22C圖之操作期間，兩個子虛設閘極結構分別取代為金屬閘極結構。 In other embodiments, during the operation of FIGS. 20A and 20B, the dielectric separation wall 50 is exposed to separate the dummy gate structure into two sub-dummy gate structures, and in FIGS. 21A to 22C During operation, the two sub-dummy gate structures were replaced with metal gate structures, respectively.

如上文闡明，介電分離壁50在虛設閘極結構之前形成及形成金屬閘極結構。因此，可最小化介電分離壁50之寬度，且可將金屬閘極電極及鰭片結構之端部大小放大。 As explained above, the dielectric separation wall 50 forms and forms a metal gate structure before the dummy gate structure. Therefore, the width of the dielectric separation wall 50 can be minimized, and the end sizes of the metal gate electrode and the fin structure can be enlarged.

應理解，結構進行另一互補式金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor；CMOS)製程以形成諸如互連通孔、互連金屬層、鈍化層等之各特徵。 It should be understood that the structure performs another complementary metal oxide semiconductor (Complementary Metal-Oxide-Semiconductor; CMOS) process to form features such as interconnect vias, interconnect metal layers, passivation layers, and the like.

第23A圖、第23B圖、第23C圖以及第23D圖繪示依據本揭露之其他實施方式之半導體鰭式場效電晶體的各視圖。與第1A圖至第22C圖之彼等相同或類似之材料、配置、製程及/或結構可應用至以下實施方式中，且可略去詳細說明。 23A, 23B, 23C, and 23D illustrate views of a semiconductor fin field effect transistor according to other embodiments of the present disclosure. The same or similar materials, configurations, processes, and / or structures as those in FIGS. 1A to 22C may be applied to the following embodiments, and detailed descriptions may be omitted.

在以下實施方式中，介電分離壁150與半導體鰭片120之間的距離實質上不同。此距離可藉由虛設層之厚度來界定。介電分離壁150位於隔離絕緣層130上。閘極介電層192(介面氧化矽及高介電常數介電材料)沉積在半導體鰭片120及介電分離壁150上。 In the following embodiments, the distance between the dielectric separation wall 150 and the semiconductor fin 120 is substantially different. This distance can be defined by the thickness of the dummy layer. The dielectric separation wall 150 is located on the isolation insulating layer 130. A gate dielectric layer 192 (interface silicon oxide and high dielectric constant dielectric material) is deposited on the semiconductor fins 120 and the dielectric separation wall 150.

如第23A圖、第23B圖、第23C圖以及第23D圖所示，半導體元件包含基板110、半導體鰭片120及閘極結構190(也可為金屬閘極結構)。半導體鰭片120之底部位嵌入在隔離絕緣層130中，其亦稱為淺溝槽隔離(shallow trench isolation；STI)。在第23A圖、第23B圖、第23C圖以及第23D圖中，四個半導體鰭片120，即第一鰭片F11、第二鰭片F12、第三鰭片F13以及第四鰭片F14，設置於基板110上方，但半導體鰭片120之數目並不限於四個。閘極結構190中的一些係藉由第一介電分離壁150A(亦可稱為分離壁)或第二介電分離壁150B(亦可稱為分離壁)而實體分離，此第一介電分離壁150A或第二介電分離壁150B由介電材料組成。在閘極結構190之相 對側面上，設置側壁間隙壁176。閘極結構190包含閘極介電層192、功函數調整層194及主體閘極電極196。 As shown in FIG. 23A, FIG. 23B, FIG. 23C, and FIG. 23D, the semiconductor element includes a substrate 110, a semiconductor fin 120, and a gate structure 190 (may also be a metal gate structure). The bottom of the semiconductor fin 120 is embedded in the isolation insulating layer 130, which is also referred to as shallow trench isolation (STI). In FIGS. 23A, 23B, 23C, and 23D, the four semiconductor fins 120, that is, the first fin F11, the second fin F12, the third fin F13, and the fourth fin F14, The number of the semiconductor fins 120 is not limited to four. Some of the gate structures 190 are physically separated by a first dielectric separation wall 150A (also referred to as a separation wall) or a second dielectric separation wall 150B (also referred to as a separation wall). This first dielectric The separation wall 150A or the second dielectric separation wall 150B is composed of a dielectric material. On the opposite side of the gate structure 190, a side wall spacer 176 is provided. The gate structure 190 includes a gate dielectric layer 192, a work function adjustment layer 194, and a main gate electrode 196.

不由閘極結構190覆蓋之半導體鰭片120為源極/汲極區域。源極/汲極(source/drain,S/D)磊晶層180在半導體鰭片120之源極/汲極區域上形成，且蝕刻終止層182在源極/汲極磊晶層180上方形成。另外，形成層間介電層184以覆蓋源極/汲極結構。 The semiconductor fins 120 not covered by the gate structure 190 are source / drain regions. A source / drain (S / D) epitaxial layer 180 is formed on the source / drain region of the semiconductor fin 120, and an etch stop layer 182 is formed over the source / drain epitaxial layer 180. . In addition, an interlayer dielectric layer 184 is formed to cover the source / drain structure.

在第23A圖、第23B圖、第23C圖以及第23D圖中，半導體鰭片120(亦可稱為鰭片結構)於一些實施方式中包含依序設置之第一鰭片F11、第二鰭片F12、第三鰭片F13及第四鰭片F14。在第一鰭片F11與第二鰭片F12之間的節距P31為兩倍的基礎鰭片節距FP，在第二鰭片F12與第三鰭片F13之間的節距P32為三倍的基礎鰭片節距FP，且在第三鰭片F13與第四鰭片F14之間的節距P33為四倍或四倍以上的基礎鰭片節距FP。於一些實施方式中，其中基礎鰭片節距FP為藉由設計規則界定之最小鰭片節距，於一些實施方式中基礎鰭片節距FP為約14奈米(nm)至30奈米(nm)。 In FIG. 23A, FIG. 23B, FIG. 23C, and FIG. 23D, the semiconductor fin 120 (also referred to as a fin structure) in some embodiments includes a first fin F11 and a second fin which are sequentially arranged. Sheet F12, third fin F13, and fourth fin F14. The pitch P31 between the first fin F11 and the second fin F12 is twice the base fin pitch FP, and the pitch P32 between the second fin F12 and the third fin F13 is three times And the pitch P33 between the third fin F13 and the fourth fin F14 is four times or more than the basic fin pitch FP. In some embodiments, the base fin pitch FP is the smallest fin pitch defined by design rules. In some embodiments, the base fin pitch FP is about 14 nm (nm) to 30 nm ( nm).

如第23C圖及第23D圖所示，於一些實施方式中，在源極/汲極區域上之蝕刻終止層182與層間介電層184之上表面之間的距離H32位於自約14奈米(nm)至約30奈米(nm)之範圍內。於一些實施方式中，在第一鰭片F11上之頂端與主體閘極電極96之上表面之間的距離H31位於自約18奈米(nm)至約40奈米(nm)之範圍內。 As shown in FIGS. 23C and 23D, in some embodiments, the distance H32 between the etch stop layer 182 on the source / drain region and the upper surface of the interlayer dielectric layer 184 is from about 14 nm. (nm) to about 30 nanometers (nm). In some embodiments, the distance H31 between the top end on the first fin F11 and the upper surface of the main gate electrode 96 is in a range from about 18 nanometers (nm) to about 40 nanometers (nm).

在第23A圖至第23D圖中，於一些實施方式中，在第一介電分離壁150A與附近之第一鰭片F11或第二鰭片F12之間的距離S31位於自約8奈米(nm)至約20奈米(nm)之範圍中，及在第二介電分離壁150B與附近之第三鰭片F13或第四鰭片F14之間的距離S32位於自約20奈米(nm)至約40奈米(nm)之範圍中。 In FIGS. 23A to 23D, in some embodiments, the distance S31 between the first dielectric separation wall 150A and the nearby first fin F11 or second fin F12 is located at about 8 nm ( nm) to about 20 nanometers (nm), and the distance S32 between the second dielectric separation wall 150B and the nearby third fin F13 or fourth fin F14 is located from about 20 nanometers (nm) ) To about 40 nanometers (nm).

第一介電分離壁150A之寬度W31於一些實施方式中為約4奈米(nm)至約8奈米(nm)。第二介電分離壁150B之寬度W32於一些實施方式中為約8奈米(nm)至約40奈米(nm)。 The width W31 of the first dielectric separation wall 150A is about 4 nanometers (nm) to about 8 nanometers (nm) in some embodiments. The width W32 of the second dielectric separation wall 150B is about 8 nanometers (nm) to about 40 nanometers (nm) in some embodiments.

如在第23C圖及第2D圖中繪示，介電分離壁150之底部位在隔離絕緣層130之上表面上。 As shown in FIGS. 23C and 2D, the bottom of the dielectric separation wall 150 is located on the upper surface of the isolation insulating layer 130.

介電分離壁150之材料可為碳氮化矽(SiCN)、碳氮氧化矽(SiOCN)及金屬氧化物(metal oxide)，諸如氧化鉿(HfO2)、氧化鋯(ZrO2)及氧化鋁(Al2O3)或任何適合介電材料。 The material of the dielectric separation wall 150 may be silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and metal oxides, such as hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), and aluminum oxide. (Al 2 O 3 ) or any suitable dielectric material.

第24A圖至第45B圖繪示依據本揭露之其他實施方式之順序半導體元件製造製程的各階段。在第24A圖至第45B圖中，「A」圖繪示了立體圖，「B」圖繪示了沿著對應於第23B圖之線段X12-X12之方向X的剖視圖，及「C」圖繪示平面圖。應理解，可在藉由第24A圖至第45B圖繪示之製程之前、期間及之後提供額外操作；及對於方法之額外實施方式，下文所述之一些操作可經取代或去除。操作/製程之順序可互換。與上述實施方式之彼等相同或類似之結構、配置、材料及/或製程可應用於以下實施方式中，且可略去詳細說明。 FIG. 24A to FIG. 45B illustrate stages of a sequential semiconductor device manufacturing process according to other embodiments of the present disclosure. In FIGS. 24A to 45B, “A” illustrates a perspective view, “B” illustrates a cross-sectional view along a direction X corresponding to a line segment X12-X12 of FIG. 23B, and “C” Show floor plan. It should be understood that additional operations may be provided before, during, and after the process illustrated by FIGS. 24A to 45B; and for additional implementations of the method, some operations described below may be replaced or removed. The order of operations / processes is interchangeable. Structures, configurations, materials, and / or processes that are the same as or similar to those of the above embodiments can be applied to the following embodiments, and detailed descriptions can be omitted.

在第24A圖及第24B圖中，半導體鰭片120在基板110上方形成。第一鰭片F11、第二鰭片F12、第三鰭片F13以及第四鰭片F14包含第一覆蓋層122及第二覆蓋層124。第一覆蓋層122由諸如二氧化鈦(titanium oxide)、二氧化鉿(hafnium oxide)及氧化鋯(zirconium oxide)之金屬氧化物(metal oxide)組成。第一覆蓋層122之厚度於一些實施方式中為約5奈米(nm)至約20奈米(nm)。第二覆蓋層124由IV族材料之非晶或多晶材料組成，諸如(amorphous silicon)或多晶矽(poly silicon)、矽鍺(silicon germanium)或鍺(germanium)。於一些實施方式中，第二覆蓋層124由具有約20奈米(nm)至約50奈米(nm)之厚度的非晶矽組成。 In FIGS. 24A and 24B, the semiconductor fins 120 are formed above the substrate 110. The first fin F11, the second fin F12, the third fin F13, and the fourth fin F14 include a first cover layer 122 and a second cover layer 124. The first cover layer 122 is composed of a metal oxide such as titanium oxide, hafnium oxide, and zirconium oxide. The thickness of the first cover layer 122 is about 5 nanometers (nm) to about 20 nanometers (nm) in some embodiments. The second cover layer 124 is composed of an amorphous or polycrystalline material of a group IV material, such as amorphous silicon or poly silicon, silicon germanium, or germanium. In some embodiments, the second cover layer 124 is composed of amorphous silicon having a thickness of about 20 nanometers (nm) to about 50 nanometers (nm).

另外，形成隔離絕緣層130亦稱為淺溝槽隔離(shallow trench isolation；STI)層。隔離絕緣層130之絕緣材料層在基板110上方形成以便完全地覆蓋半導體鰭片120。執行諸如化學機械研磨(chemical mechanical polishing；CMP)方法之平坦化操作，進而暴露第二覆蓋層124。 In addition, forming the isolation insulating layer 130 is also referred to as a shallow trench isolation (STI) layer. An insulating material layer of the isolation insulating layer 130 is formed over the substrate 110 so as to completely cover the semiconductor fins 120. A planarization operation such as a chemical mechanical polishing (CMP) method is performed to expose the second cover layer 124.

在第25A圖及第25B圖中，將隔離絕緣層130凹陷及形成氧化層135。於一些實施方式中，氧化層135可藉由原子層沉積(atomic layer deposition；ALD)製程及/或化學氣相沉積(chemical vapor deposition；CVD)製程而形成及具有約1奈米(nm)至約5奈米(nm)之厚度。在凹陷隔離絕緣層130之後，隔離絕緣層130之上表面與第二覆蓋層124之頂端之間的距離於一些實施方式中位於自約100奈米(nm)至約400奈米(nm)之範圍中。 In FIGS. 25A and 25B, the isolation insulating layer 130 is recessed and an oxide layer 135 is formed. In some embodiments, the oxide layer 135 may be formed by an atomic layer deposition (ALD) process and / or a chemical vapor deposition (CVD) process and has a thickness of about 1 nanometer (nm) to A thickness of about 5 nanometers (nm). After the isolation insulating layer 130 is recessed, the distance between the upper surface of the isolation insulating layer 130 and the top of the second cover layer 124 is in some embodiments from about 100 nanometers (nm) to about 400 nanometers (nm). In range.

在第26A圖及第26B圖中，犧牲層140在凹陷之隔離絕緣層130上方形成，以使得覆蓋有氧化層135之第二覆蓋層124自隔離絕緣層130伸出。於一些實施方式中，犧牲層140由諸如底部抗反射塗層(bottom anti reflective coating；BARC)或光致抗蝕劑之有機材料組成。首先形成厚層狀結構，隨後執行回蝕操作以調整犧牲層140之厚度。 In FIGS. 26A and 26B, the sacrificial layer 140 is formed over the recessed insulating layer 130 so that the second covering layer 124 covered with the oxide layer 135 protrudes from the insulating layer 130. In some embodiments, the sacrificial layer 140 is composed of an organic material such as a bottom anti reflective coating (BARC) or a photoresist. A thick layered structure is formed first, and then an etch-back operation is performed to adjust the thickness of the sacrificial layer 140.

在第27A圖及第27B圖中，在第二覆蓋層124上形成之氧化層135藉由濕式及/或乾式蝕刻而移除，且隨後移除犧牲層140。 In FIGS. 27A and 27B, the oxide layer 135 formed on the second cover layer 124 is removed by wet and / or dry etching, and then the sacrificial layer 140 is removed.

在第28A圖及第28B圖中，第一虛設層142在半導體鰭片120上方形成。第一虛設層142由IV族材料之非晶或多晶材料組成，諸如非晶矽(amorphous)或多晶矽(poly silicon)、矽鍺(silicon germanium)或鍺(germanium)。於一些實施方式中，第一虛設層142由具有約5奈米(nm)至約20奈米(nm)之厚度的非晶矽組成。此處，間距在形成於附近鰭片結構上之第一虛設層142之間形成。形成非晶矽之毯覆層，且隨後執行各向異性蝕刻。在形成於第一鰭片F11與第二鰭片F12上之第一虛設層142之間的間距S41於一些實施方式中位於自約4奈米(nm)至約14奈米(nm)的範圍中。在隔離絕緣層130之上表面與第一虛設層142之頂端之間的高度H42於一些實施方式中位於自約120奈米(nm)至約500奈米(nm)之範圍中。於一些實施方式中，因為第二覆蓋層124與第一虛設層142由同一材料組成，例如非晶矽(amorphous Si)，所以在第二覆蓋層124與第一虛設層142之間不存在可見邊界。 In FIGS. 28A and 28B, the first dummy layer 142 is formed over the semiconductor fin 120. The first dummy layer 142 is composed of an amorphous or polycrystalline material of a group IV material, such as amorphous or poly silicon, silicon germanium, or germanium. In some embodiments, the first dummy layer 142 is composed of amorphous silicon having a thickness of about 5 nanometers (nm) to about 20 nanometers (nm). Here, a space is formed between the first dummy layers 142 formed on the nearby fin structure. A blanket layer of amorphous silicon is formed, and then anisotropic etching is performed. The spacing S41 between the first dummy layer 142 formed on the first fin F11 and the second fin F12 is in a range from about 4 nanometers (nm) to about 14 nanometers (nm) in some embodiments. in. The height H42 between the upper surface of the isolation insulating layer 130 and the top of the first dummy layer 142 is in a range from about 120 nanometers (nm) to about 500 nanometers (nm) in some embodiments. In some embodiments, since the second cover layer 124 and the first dummy layer 142 are made of the same material, such as amorphous Si, there is no visible between the second cover layer 124 and the first dummy layer 142. boundary.

在第29A圖及第29B圖中，第二虛設層143藉由使用原子層沉積製程或化學氣相沉積製程共形形成。第二虛設層143由諸如氮化矽(SiN)及氮氧化矽(SiON)之基於氮化矽之材料組成。於一些實施方式中，第二虛設層143由具有約5奈米(nm)至約20奈米(nm)之厚度的氮化矽(SiN)組成。第二虛設層143完全地充填了在第一鰭片F11與第二鰭片F12之間的間距，而間距在第二鰭片F12與第三鰭片F13之間及在第三鰭片F13與第四鰭片F14之間形成。 In FIGS. 29A and 29B, the second dummy layer 143 is conformally formed by using an atomic layer deposition process or a chemical vapor deposition process. The second dummy layer 143 is composed of a silicon nitride-based material such as silicon nitride (SiN) and silicon oxynitride (SiON). In some embodiments, the second dummy layer 143 is composed of silicon nitride (SiN) having a thickness of about 5 nanometers (nm) to about 20 nanometers (nm). The second dummy layer 143 completely fills the gap between the first fin F11 and the second fin F12, and the gap is between the second fin F12 and the third fin F13 and between the third fin F13 and Formed between the fourth fins F14.

在第30A圖及第30B圖中，執行各向異性蝕刻以移除第二虛設層143之不必要部分，而保留在第一鰭片F11與第二鰭片F12之間的間距中的第二虛設層143。 In FIGS. 30A and 30B, an anisotropic etching is performed to remove unnecessary portions of the second dummy layer 143, and the second remaining in the space between the first fin F11 and the second fin F12 is retained. Dummy layer 143.

在第31A圖及第31B圖中，形成第三虛設層144。第三虛設層144由IV族材料之非晶或多晶材料組成，諸如非晶矽(amorphous silicon)或多晶矽(poly silicon)、矽鍺(silicon germanium)或鍺(germanium)。於一些實施方式中，第三虛設層144由具有約5奈米(nm)至約20奈米(nm)之厚度的非晶矽組成。此處，間距在形成於附近鰭片上之第三虛設層144之間形成。 In FIGS. 31A and 31B, a third dummy layer 144 is formed. The third dummy layer 144 is composed of an amorphous or polycrystalline material of a Group IV material, such as amorphous silicon or poly silicon, silicon germanium, or germanium. In some embodiments, the third dummy layer 144 is composed of amorphous silicon having a thickness of about 5 nanometers (nm) to about 20 nanometers (nm). Here, a space is formed between the third dummy layers 144 formed on the nearby fins.

在第32A圖及第32B圖中，執行各向異性蝕刻。在形成於第二鰭片F12與第三鰭片F13上之第三虛設層144之間的間距S42於一些實施方式中位於自約4奈米(nm)至約14奈米(nm)的範圍中。在形成於第三鰭片F13與第四鰭片F14上之第三虛設層144之間的間距S43於一些實施方式中位於自約8奈米(nm)至約40奈米(nm)的範圍中。 In FIGS. 32A and 32B, anisotropic etching is performed. The spacing S42 between the third dummy layer 144 formed on the second fin F12 and the third fin F13 is in a range from about 4 nanometers (nm) to about 14 nanometers (nm) in some embodiments. in. The spacing S43 between the third dummy layer 144 formed on the third fin F13 and the fourth fin F14 is in a range from about 8 nanometers (nm) to about 40 nanometers (nm) in some embodiments. in.

在第33A圖及第33B圖中，藉由濕式及/或乾式蝕刻移除第二虛設層143。在形成於第二鰭片F12與第三鰭片F13上之第三虛設層144之間的間距S44於一些實施方式中位於自約4奈米(nm)至約14奈米(nm)的範圍中。在形成於第三鰭片F13與第四鰭片F14上之第三虛設層144之間的間距S45於一些實施方式中位於自約8奈米(nm)至約40奈米(nm)的範圍中。 In FIGS. 33A and 33B, the second dummy layer 143 is removed by wet and / or dry etching. The spacing S44 between the third dummy layer 144 formed on the second fin F12 and the third fin F13 is in a range from about 4 nanometers (nm) to about 14 nanometers (nm) in some embodiments. in. The spacing S45 between the third dummy layer 144 formed on the third fin F13 and the fourth fin F14 is in a range from about 8 nanometers (nm) to about 40 nanometers (nm) in some embodiments. in.

在第34A圖及第34B圖中，形成介電分離壁150之介電材料。形成介電材料之毯覆層及隨後執行化學機械研磨或回蝕操作。介電分離壁150包含矽(Si)、碳氮化矽(SiCN)、碳氮氧化矽(SiOCN)、諸如氧化鉿(HfO2)、氧化鋯(ZrO2)及氧化鋁(Al2O3)之金屬氧化物(metal oxide)，或任一其他適宜介電材料之一或多個層。介電分離壁150之介電材料藉由化學氣相沉積製程、原子層沉積製程或任一其他適宜薄膜形成方法而形成。 In FIGS. 34A and 34B, a dielectric material of the dielectric separation wall 150 is formed. A blanket layer of dielectric material is formed and subsequently subjected to a chemical mechanical polishing or etch-back operation. The dielectric separation wall 150 includes silicon (Si), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), such as hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), and alumina (Al 2 O 3 ) One or more layers of metal oxide, or any other suitable dielectric material. The dielectric material of the dielectric separation wall 150 is formed by a chemical vapor deposition process, an atomic layer deposition process, or any other suitable thin film formation method.

在第35A圖及第35B圖中，在介電分離壁150及第一虛設層142及第二虛設層143之介電材料上形成遮罩層152。遮罩層152包含諸如氧化矽(SiO2)及氮氧化矽(SiON)之基於氧化矽材料之一或多個層。於一些實施方式中，遮罩層152為具有約5奈米(nm)至約30奈米(nm)之厚度的氧化矽(SiO2)。 In FIGS. 35A and 35B, a masking layer 152 is formed on the dielectric material of the dielectric separation wall 150 and the first dummy layer 142 and the second dummy layer 143. The mask layer 152 includes one or more layers of silicon oxide-based materials such as silicon oxide (SiO 2 ) and silicon oxynitride (SiON). In some embodiments, the masking layer 152 is silicon oxide (SiO 2 ) having a thickness of about 5 nanometers (nm) to about 30 nanometers (nm).

在第36A圖、第36B圖以及第36C圖中，藉由使用光致抗蝕劑圖案154，而圖案化遮罩層152。光致抗蝕劑圖案154之一者位於一區域上方，在此區域中單獨地形成兩個閘極電極組；及光致抗蝕劑圖案154之一者位於一區域上方，在此區域中單獨地形成另一閘極電極組。參看第23B圖。 In FIGS. 36A, 36B, and 36C, the mask layer 152 is patterned by using the photoresist pattern 154. One of the photoresist patterns 154 is located above a region, and two gate electrode groups are separately formed in this region; and one of the photoresist patterns 154 is located above a region, separately in this region Ground forms another gate electrode group. See Figure 23B.

在第37A圖及第37B圖中，藉由使用圖案化之遮罩層152作為蝕刻遮罩，圖案化介電分離壁150之介電材料，進而形成第一介電分離壁150A及第二介電分離壁150B。第一介電分離壁150A具有不同於第二介電分離壁150B之寬度。於一些實施方式中，第一介電分離壁150A之寬度為第二介電分離壁150B之寬度的兩倍或更多。 In FIGS. 37A and 37B, by using the patterned masking layer 152 as an etching mask, the dielectric material of the dielectric separation wall 150 is patterned to form a first dielectric separation wall 150A and a second dielectric. Electric separation wall 150B. The first dielectric separation wall 150A has a width different from that of the second dielectric separation wall 150B. In some embodiments, the width of the first dielectric separation wall 150A is twice or more than the width of the second dielectric separation wall 150B.

在第38A圖及第38B圖中，形成第四虛設層170。第四虛設層170由IV族材料之非晶或多晶材料組成，諸如非晶矽(amorphous silicon)或多晶矽(poly silicon)、矽鍺(silicon germanium)或鍺(germanium)。於一些實施方式中，第四虛設層170由多晶矽組成。於某些實施方式中，因為第二覆蓋層124、第一虛設層142、第三虛設層144及第四虛設層170由例如非晶矽之同一材料組成，所以其作為一個虛設閘極電極層。 In FIGS. 38A and 38B, a fourth dummy layer 170 is formed. The fourth dummy layer 170 is composed of an amorphous or polycrystalline material of a group IV material, such as amorphous silicon or poly silicon, silicon germanium, or germanium. In some embodiments, the fourth dummy layer 170 is composed of polycrystalline silicon. In some embodiments, since the second cover layer 124, the first dummy layer 142, the third dummy layer 144, and the fourth dummy layer 170 are made of the same material, such as amorphous silicon, they serve as a dummy gate electrode layer. .

在第39A圖、第39B圖、第39C圖以及第39D圖中，藉由使用包含層狀結構172及層狀結構174之硬遮罩圖案化虛設閘極電極層(例如，第二覆蓋層124、第一虛設層142、第三虛設層144及第四虛設層170)，進而形成虛設閘極電極175。至少一個虛設閘極電極175設置於第一鰭片F11及第二鰭片F12及第一介電分離壁150A上方，及至少一個虛設閘極電極175設置於第三鰭片F13及第四鰭片F14及第二介電分離壁150B上方。於一些實施方式中，如在第39C圖中繪示，兩個虛設閘極電極175設置於第一鰭片F11至第四鰭片F14及第一介電分離壁150A上方，及一個虛設閘極電極175設置於第一鰭片F11、第二鰭片F12、第三鰭片F13、第四鰭片F14及第二介電 分離壁150B上方。虛設閘極電極175之寬度W41於一些實施方式中位於自約4奈米(nm)至約20奈米(nm)之範圍中。 In FIGS. 39A, 39B, 39C, and 39D, the dummy gate electrode layer (for example, the second cover layer 124) is patterned by using a hard mask including the layered structure 172 and the layered structure 174. , The first dummy layer 142, the third dummy layer 144, and the fourth dummy layer 170) to form a dummy gate electrode 175. At least one dummy gate electrode 175 is disposed above the first fin F11 and the second fin F12 and the first dielectric separation wall 150A, and at least one dummy gate electrode 175 is disposed at the third fin F13 and the fourth fin. F14 and the second dielectric separation wall 150B are above. In some embodiments, as shown in FIG. 39C, two dummy gate electrodes 175 are disposed above the first to fourth fins F11 to F14 and the first dielectric separation wall 150A, and one dummy gate The electrode 175 is disposed above the first fin F11, the second fin F12, the third fin F13, the fourth fin F14, and the second dielectric separation wall 150B. The width W41 of the dummy gate electrode 175 is in a range from about 4 nanometers (nm) to about 20 nanometers (nm) in some embodiments.

在第40A圖及第40B圖中，側壁間隙壁176在虛設閘極電極175之相對側面上形成。形成基於氮化矽材料(氮化矽(SiN)、氮氧化矽(SiON)或碳氮化矽(SiCN))之毯覆層，且隨後執行各向異性蝕刻。藉由此蝕刻，移除在暴露之鰭片上形成之基於氮化矽之材料。於一些實施方式中，將不由虛設閘極電極及側壁間隙壁覆蓋之介電分離壁150凹陷。在其他實施方式中，不將介電分離壁150凹陷。 In FIGS. 40A and 40B, the sidewall spacer 176 is formed on the opposite side of the dummy gate electrode 175. A blanket layer based on a silicon nitride material (silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbon nitride (SiCN)) is formed, and then anisotropic etching is performed. By this etching, the silicon nitride-based material formed on the exposed fins is removed. In some embodiments, the dielectric separation wall 150 which is not covered by the dummy gate electrode and the sidewall spacer is recessed. In other embodiments, the dielectric separation wall 150 is not recessed.

在第41A圖及第41B圖中，源極/汲極磊晶層180在暴露之鰭片上形成。磊晶源極/汲極層包含磷化矽(SiP)、碳化矽(SiC)、碳磷化矽(SiCP)、硼化矽(SiB)、矽鍺(SiGe)及鍺(Ge)之一或多個結晶層。於一些實施方式中，矽化物層進一步在源極/汲極磊晶層180上方形成。 In FIGS. 41A and 41B, a source / drain epitaxial layer 180 is formed on the exposed fins. The epitaxial source / drain layer includes one of silicon phosphide (SiP), silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon boride (SiB), silicon germanium (SiGe), and germanium (Ge) or Multiple crystalline layers. In some embodiments, a silicide layer is further formed over the source / drain epitaxial layer 180.

在第42A圖及第42B圖中，形成蝕刻終止層182，且在具有側壁間隙壁176之虛設閘極電極175之間的間距中形成層間介電層184。層間介電層184可包含氧化矽(silicon oxide)、氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride；SiON)、氮碳氧化矽(SiOCN)、摻氟矽酸鹽玻璃(fluorine-doped silicate glass；FSG)或低介電常數介電材料(low-k dielectric material)，及可由化學氣相沉積製程或其他適宜製程製成。介電分離壁150之絕緣材料不同於隔離絕緣層130及層間介電層184之絕緣材料。 In FIGS. 42A and 42B, an etch stop layer 182 is formed, and an interlayer dielectric layer 184 is formed in a space between the dummy gate electrodes 175 having the sidewall spacers 176. The interlayer dielectric layer 184 may include silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon oxynitride (SiOCN), and fluorine-doped glass. silicate glass (FSG) or low-k dielectric material, and can be made by chemical vapor deposition process or other suitable processes. The insulating material of the dielectric separation wall 150 is different from the insulating materials of the isolation insulating layer 130 and the interlayer dielectric layer 184.

執行平坦化操作，諸如回蝕製程及/或化學機械研磨製程，以便暴露虛設閘極電極175及第一介電分離壁150A及第二介電分離壁150B之上部位。 A planarization operation, such as an etch-back process and / or a chemical mechanical polishing process, is performed to expose the dummy gate electrode 175 and the portions above the first dielectric separation wall 150A and the second dielectric separation wall 150B.

在第43A圖及第43B圖中，移除虛設閘極電極175、第一覆蓋層122及第二覆蓋層124及氧化層135，進而形成閘極間距189。 In FIGS. 43A and 43B, the dummy gate electrode 175, the first cover layer 122, the second cover layer 124, and the oxide layer 135 are removed to form a gate gap 189.

在第44A圖、第44B圖以及第44C圖中，包含閘極介電層192、功函數調整層194及主體閘極電極96之金屬閘極結構190在閘極空間189中形成。在形成金屬閘極結構190時，閘極介電層192、功函數調整層194及閘極電極層藉由適宜薄膜形成方法，例如用於閘極介電層192之化學氣相沉積製程或原子層沉積製程、及用於金屬層之化學氣相沉積製程、物理氣相沉積製程、原子層沉積製程或電鍍製程而形成，及隨後執行諸如化學機械研磨之平坦化操作以移除在層間介電層184上方形成之多餘材料。 In FIGS. 44A, 44B, and 44C, a metal gate structure 190 including a gate dielectric layer 192, a work function adjustment layer 194, and a main gate electrode 96 is formed in a gate space 189. When the metal gate structure 190 is formed, the gate dielectric layer 192, the work function adjustment layer 194, and the gate electrode layer are formed by a suitable thin film method, such as a chemical vapor deposition process or atom for the gate dielectric layer 192. Formed by a layer deposition process, and a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or an electroplating process for a metal layer, and subsequently performing a planarization operation such as chemical mechanical polishing to remove interlayer dielectric Excess material formed over layer 184.

在第45A圖以及第45B圖中，執行諸如化學機械研磨之平坦化操作以暴露第一介電分離壁150A及第二介電分離壁150B。 In FIGS. 45A and 45B, a planarization operation such as chemical mechanical polishing is performed to expose the first dielectric separation wall 150A and the second dielectric separation wall 150B.

於一些實施方式中，一個閘極結構190及側壁間距176之至少一者藉由第一介電分離壁150A與另一第二閘極結構190及側壁間隙壁176之至少一者分離。另外，於一些實施方式中，側壁間隙壁176在第一介電分離壁150A之側壁上連續地形成，及其他側壁間隙壁176在第一介電分離壁150A之其他側壁上連續地形成。 In some embodiments, at least one of the gate structure 190 and the sidewall spacing 176 is separated from at least one of the other second gate structure 190 and the sidewall spacer 176 by the first dielectric separation wall 150A. In addition, in some embodiments, the side wall spacer 176 is continuously formed on the side wall of the first dielectric separation wall 150A, and other side wall spacers 176 are continuously formed on the other side wall of the first dielectric separation wall 150A.

在其他實施方式中，在第42A圖及第42B圖之操作期間，暴露介電分離壁150以將虛設閘極結構分隔為兩個子虛設閘極結構，及在第43A圖至第45B圖之操作期間，兩個子虛設閘極結構分別取代為金屬閘極結構。 In other embodiments, during the operation of FIGS. 42A and 42B, the dielectric separation wall 150 is exposed to separate the dummy gate structure into two sub-dummy gate structures, and in FIGS. 43A to 45B During operation, the two sub-dummy gate structures were replaced with metal gate structures, respectively.

如上文闡明，介電分離壁150在虛設閘極結構之前形成，且形成金屬閘極結構190。因此，可更精確地控制介電分離壁150之寬度及可放大金屬閘極電極及鰭片結構之端部大小。 As explained above, the dielectric separation wall 150 is formed before the dummy gate structure, and a metal gate structure 190 is formed. Therefore, the width of the dielectric separation wall 150 and the size of the ends of the metal gate electrode and the fin structure can be controlled more accurately.

應理解，結構進行另一互補式金屬氧化物半導體製程以形成諸如互連通孔、互連金屬層、鈍化層等之各特徵。 It should be understood that the structure undergoes another complementary metal oxide semiconductor process to form features such as interconnect vias, interconnect metal layers, passivation layers, and the like.

本文描述之各實施方式或實例提供超過現有技術之若干優勢。藉由使用如上所述之介電分離壁，固定適當數量(尺寸)之端蓋(在介電分離壁與最近之鰭片之間的間距)及減少鰭片至鰭片間距是可能的。 The embodiments or examples described herein provide several advantages over the prior art. By using the dielectric separation wall as described above, it is possible to fix an appropriate number (size) of end caps (the distance between the dielectric separation wall and the nearest fin) and reduce the fin-to-fin pitch.

應理解，本文無必要論述所有優勢，且沒有特定優勢對於所有實施方式或實例為必需，以及其他實施方式或實例可提供不同優勢。 It should be understood that it is not necessary to discuss all advantages herein, and that no particular advantage is necessary for all embodiments or examples, and that other embodiments or examples may provide different advantages.

上文概述若干實施方式或實例之特徵，使得熟習此項技術者可更好地理解本揭露之態樣。熟習此項技術者應瞭解，可輕易使用本揭露作為用於設計或修改其他製程及結構的基礎，以便實施本文所介紹之實施方式或實例之相同目的及/或達成相同優勢。熟習此項技術者亦應認識到，此類等效結構並未脫離本揭露之精神及範疇，且可在不脫離本揭露之精神及範疇的情況下進行本文的各種變化、替代及更改。 The features of several embodiments or examples are summarized above, so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that the disclosure can be easily used as a basis for designing or modifying other processes and structures in order to implement the same purpose and / or achieve the same advantages of the embodiments or examples described herein. Those skilled in the art should also realize that such equivalent structures have not deviated from the spirit and scope of this disclosure, and can make various changes, substitutions and alterations without departing from the spirit and scope of this disclosure.

Claims (10)

一種半導體元件的製造方法，包含：形成一分離壁於兩鰭片結構之間，該分離壁的材質為一介電材料；形成一虛設閘極結構於該分離壁以及該兩鰭片結構上方；形成一層間介電層於該虛設閘極結構上方；移除該層間介電層之一上部位，進而暴露該虛設閘極結構；藉由一金屬閘極結構取代該虛設閘極結構；以及執行一平坦化操作以暴露該分離壁，進而將該金屬閘極結構分隔為一第一閘極結構及一第二閘極結構，其中該第一閘極結構與該第二閘極結構藉由該分離壁而相互分離。     A method for manufacturing a semiconductor element includes: forming a separation wall between two fin structures, and the material of the separation wall is a dielectric material; forming a dummy gate structure above the separation wall and the two fin structures; Forming an interlayer dielectric layer over the dummy gate structure; removing an upper part of the interlayer dielectric layer to expose the dummy gate structure; replacing the dummy gate structure with a metal gate structure; and performing A planarization operation is performed to expose the separation wall, and then the metal gate structure is divided into a first gate structure and a second gate structure, wherein the first gate structure and the second gate structure are separated by the The walls are separated from each other.     如請求項1所述之半導體元件的製造方法，更包含：形成該兩鰭片結構；以及形成一隔離絕緣層，使得該兩鰭片結構的複數個上部位突出於該隔離絕緣層，其中該分離壁之的一底部位係嵌入於該隔離絕緣層。     The method for manufacturing a semiconductor device according to claim 1, further comprising: forming the two fin structure; and forming an isolation insulating layer so that a plurality of upper portions of the two fin structure protrude from the isolation insulating layer, wherein the A bottom portion of the separation wall is embedded in the isolation insulation layer.     如請求項1所述之半導體元件的製造方法，更包含：形成該兩鰭片結構；以及 形成一隔離絕緣層，使得該兩鰭片結構的複數個上部位突出於該隔離絕緣層，其中該分離壁的一底部位係位於該隔離絕緣層的一上表面上或上方。     The method for manufacturing a semiconductor device according to claim 1, further comprising: forming the two fin structure; and forming an isolation insulating layer so that a plurality of upper portions of the two fin structure protrude from the isolation insulating layer, wherein the A bottom position of the separation wall is located on or above an upper surface of the isolation insulation layer.     如請求項1所述之半導體元件的製造方法，更包含：形成複數個側壁間隙壁於該虛設閘極結構的相對側上，其中在形成該第一閘極結構與該第二閘極結構之後，該第一閘極結構上的該些側壁間隙壁係藉由該分離壁而分離於該第二閘極結構上的該些側壁間隙壁。     The method for manufacturing a semiconductor device according to claim 1, further comprising: forming a plurality of sidewall spacers on opposite sides of the dummy gate structure, wherein after forming the first gate structure and the second gate structure The sidewall spacers on the first gate structure are separated from the sidewall spacers on the second gate structure by the separation wall.     如請求項1所述之半導體元件的製造方法，其中該第一閘極結構與該第二閘極結構分別包含一閘極介電層以及一閘極電極層，且該閘極介電層係形成於該分離壁之複數個側壁上。     The method for manufacturing a semiconductor device according to claim 1, wherein the first gate structure and the second gate structure include a gate dielectric layer and a gate electrode layer, respectively, and the gate dielectric layer is It is formed on a plurality of side walls of the separation wall.     一種半導體元件的製造方法，包含：形成一第一鰭片結構、一第二鰭片結構以及一第三鰭片結構，該第二鰭片結構位於該第一鰭片結構與第三鰭片結構之間，該第一鰭片結構、該第二鰭片結構以及該第三鰭片結構中之每一者的材質為半導體材料，且具有一絕緣覆蓋層；形成一隔離絕緣層，使得該第一鰭片結構、該第二鰭片結構以及該第三鰭片結構係嵌入於該隔離絕緣層，而該絕緣覆蓋層被暴露出； 形成一第一遮罩圖案於該隔離絕緣層上方，該第一遮罩圖案具有一第一開口，該第一開口位於該第二鰭片結構上方；藉由蝕刻製程使該第二鰭片結構凹陷，且該第一遮罩圖案作為一蝕刻遮罩；形成一介電分離壁於凹陷之該第二鰭片結構上；使該隔離絕緣層凹陷，使得該第一鰭片結構及第三鰭片結構的複數個上部位與該介電分離壁的上部位被暴露出；形成一第一虛設閘極結構於暴露之該第一鰭片結構、暴露之該第三鰭片結構以及暴露之該介電分離壁上方；形成一層間介電層於該第一虛設閘極結構上方；移除該層間介電層的一上部位，進而暴露該第一虛設閘極結構；藉由一金屬閘極結構取代該第一閘極結構；以及執行一平坦化操作以暴露該介電分離壁，進而將該金屬閘極結構分隔為一第一閘極結構及一第二閘極結構，其中該第一閘極結構與該第二閘極結構藉由該介電分離壁而相互分離。     A method for manufacturing a semiconductor device includes forming a first fin structure, a second fin structure, and a third fin structure. The second fin structure is located on the first fin structure and the third fin structure. In between, the material of each of the first fin structure, the second fin structure, and the third fin structure is a semiconductor material and has an insulating cover layer; an isolation insulating layer is formed so that the first A fin structure, the second fin structure, and the third fin structure are embedded in the isolation insulation layer, and the insulation cover layer is exposed; a first mask pattern is formed over the isolation insulation layer, and the The first mask pattern has a first opening, which is located above the second fin structure; the second fin structure is recessed by an etching process, and the first mask pattern serves as an etching mask; A dielectric separation wall is formed on the recessed second fin structure; the isolation insulating layer is recessed so that a plurality of upper portions of the first fin structure and the third fin structure and the upper portion of the dielectric separation wall The part is exposed; A first dummy gate structure above the exposed first fin structure, the exposed third fin structure, and the exposed dielectric separation wall; forming an interlayer dielectric layer over the first dummy gate structure; Removing an upper portion of the interlayer dielectric layer to expose the first dummy gate structure; replacing the first gate structure with a metal gate structure; and performing a planarization operation to expose the dielectric separation wall The metal gate structure is further divided into a first gate structure and a second gate structure, wherein the first gate structure and the second gate structure are separated from each other by the dielectric separation wall.     如請求項6所述之半導體元件的製造方法，更包含：在形成該第一虛設閘極結構的步驟與形成該層間介電層的步驟之間：形成複數個側壁間隙壁於該第一鰭片結構、該第三鰭片結構以及該介電分離壁的相對側上； 移除在該第一鰭片結構及第三鰭片結構上該側壁間隙壁的複數個部位，進而暴露該第一鰭片結構及第三鰭片結構的複數個源極/汲極部位；以及形成複數個源極/汲極磊晶層於暴露之該些源極/汲極部位上。     The method for manufacturing a semiconductor device according to claim 6, further comprising: between the step of forming the first dummy gate structure and the step of forming the interlayer dielectric layer: forming a plurality of sidewall spacers on the first fin Sheet structure, the third fin structure, and the dielectric separation wall on opposite sides; removing a plurality of portions of the sidewall gap on the first fin structure and the third fin structure, thereby exposing the first A plurality of source / drain regions of the fin structure and a third fin structure; and a plurality of source / drain epitaxial layers are formed on the exposed source / drain regions.     一種半導體元件，包含：一第一閘極電極，設置於一隔離絕緣層上方，該隔離絕緣層形成於一基板上；一第二閘極電極，設置於該隔離絕緣層上方，該第一閘極電極與該第二閘極電極延伸於一第一方向，且沿著該第一方向對準；以及一介電分離壁，突出於該隔離絕緣層，且設置於該第一閘極電極與該第二閘極電極之間，且將該第一閘極電極分離於該第二閘極電極，其中該介電分離壁的介電材料，係不同於該隔離絕緣層的介電材料。     A semiconductor element includes: a first gate electrode disposed above an isolation insulating layer formed on a substrate; a second gate electrode disposed above the isolation insulating layer; the first gate The electrode and the second gate electrode extend in a first direction and are aligned along the first direction; and a dielectric separation wall protrudes from the isolation insulating layer and is disposed between the first gate electrode and the first gate electrode. Between the second gate electrode and separating the first gate electrode from the second gate electrode, the dielectric material of the dielectric separation wall is different from the dielectric material of the isolation insulating layer.     如請求項8所述之半導體元件，更包含：一第一鰭片結構，突出於該隔離絕緣層；以及一第二鰭片結構，突出於該隔離絕緣層，其中該第一閘極電極係設置於該第一鰭片結構上方，該第二閘極電極係設置於該第二鰭片結構上方，且該介電分離壁與該第一鰭片結構之間的一中心距離實質上相同於該介電分離壁與該第二鰭片結構之間的一中心距離。     The semiconductor device according to claim 8, further comprising: a first fin structure protruding from the isolation insulating layer; and a second fin structure protruding from the isolation insulating layer, wherein the first gate electrode system Is disposed above the first fin structure, the second gate electrode is disposed above the second fin structure, and a center distance between the dielectric separation wall and the first fin structure is substantially the same as A central distance between the dielectric separation wall and the second fin structure.     如請求項8所述之半導體元件，更包含：一第一鰭片結構，突出於該隔離絕緣層；以及一第二鰭片結構，突出於該隔離絕緣層，其中該第一閘極電極係設置於該第一鰭片結構上方，該第二閘極電極係設置於該第二鰭片結構上方，該第一鰭片結構與該介電分離壁之間的一第一間距實質上相同於一基礎鰭片間距或為該基礎鰭片間距的倍數，且該第二鰭片結構與該介電分離壁之間的一第二間距等於該基礎鰭片間距或為該基礎鰭片間距的倍數。     The semiconductor device according to claim 8, further comprising: a first fin structure protruding from the isolation insulating layer; and a second fin structure protruding from the isolation insulating layer, wherein the first gate electrode system Is disposed above the first fin structure, the second gate electrode is disposed above the second fin structure, a first distance between the first fin structure and the dielectric separation wall is substantially the same as A base fin pitch or a multiple of the base fin pitch, and a second pitch between the second fin structure and the dielectric separation wall is equal to the base fin pitch or a multiple of the base fin pitch .    
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