TW201834386A - Methods for combining doherty amplifier signals with 90-degree lumped and distributed impedance inverters - Google Patents

Abstract

Apparatus and methods for a modified Doherty amplifier operating at gigahertz frequencies are described. The combining of signals from a main amplifier and a peaking amplifier occur prior to impedance matching of the amplifier's output to a load. An integrated distributed inductor may be used in an impedance inverter to combine the signals. A size of the impedance element can be selected by patterning during manufacture to tune the amplifier and to allow power scaling for the amplifier.

Description

用於結合杜赫放大器訊號與90度集總與分散式阻抗反相器的方法Method for combining a Duch amplifier signal with a 90 degree lumped and decentralized impedance inverter

本科技相關於高速高功率寬頻寬整合式放大器，此放大器可由氮化鎵電晶體或由其他半導體材料形成的電晶體來建置。This technology is related to high speed, high power, wide bandwidth wide integrated amplifiers that can be built from gallium nitride transistors or transistors formed from other semiconductor materials.

氮化鎵半導體材料近年來受到了很大的關注，因為氮化鎵半導體材料的可期望的電子性質與光電性質。GaN具有約3.4 eV的寬廣、直接的帶隙，這對應於可見光頻譜中的藍光波段。基於GaN與GaN合金的發光二極體（LED）與雷射二極體（LD）已被發展且已市售。這些裝置可發出從可見光頻譜的紫光區域至紅光區域的可見光。Gallium nitride semiconductor materials have received much attention in recent years because of the desirable electronic and optoelectronic properties of gallium nitride semiconductor materials. GaN has a broad, direct band gap of about 3.4 eV, which corresponds to the blue band in the visible spectrum. Light-emitting diodes (LEDs) and laser diodes (LDs) based on GaN and GaN alloys have been developed and are commercially available. These devices emit visible light from the violet to red region of the visible spectrum.

因為寬廣的帶隙，GaN較不受雪崩崩潰的影響，並可在較高的溫度下維持電氣性能（相較於其他半導體，例如矽）。GaN也具有比矽高的載子飽和速率。此外，GaN具有纖鋅礦晶體結構(Wurtzite crystal structure)、為非常穩定且堅硬的材料、具有高導熱率、並具有比其他習知半導體（諸如矽、鍺和砷化鎵）高得多的熔解點。因此，GaN對於高速、高電壓及高功率應用是有用的。例如，氮化鎵材料對於用於射頻(RF)通訊的半導體放大器、雷達、RF能量、與微波應用是有用的。Because of the wide bandgap, GaN is less susceptible to avalanche collapse and can maintain electrical performance at higher temperatures (compared to other semiconductors such as germanium). GaN also has a higher carrier saturation rate than 矽. In addition, GaN has a wurtzite crystal structure, is a very stable and hard material, has high thermal conductivity, and has much higher melting than other conventional semiconductors such as germanium, antimony and gallium arsenide. point. Therefore, GaN is useful for high speed, high voltage, and high power applications. For example, gallium nitride materials are useful for semiconductor amplifiers, radar, RF energy, and microwave applications for radio frequency (RF) communications.

支援當前通訊標準與已提出的未來通訊標準（諸如WiMax、4G、與5G）下的行動通訊與無線網際網路存取的應用，可對由半導體電晶體建置的高速或RF放大器提出苛刻的性能要求。放大器可需要達到相關於輸出功率、訊號線性度、訊號增益、頻寬、與效率的性能規格。Supports mobile communication and wireless Internet access applications under current communication standards and proposed future communication standards (such as WiMax, 4G, and 5G), which can be demanding for high-speed or RF amplifiers built by semiconductor transistors. Performance requirements. Amplifiers may need to meet performance specifications related to output power, signal linearity, signal gain, bandwidth, and efficiency.

說明用於改良高速高功率寬頻整合式放大器的性能的方法與結構。結構與方法相關於用於結合經放大訊號並在經修改杜赫放大器輸出處進行阻抗匹配的電路系統。重新安排訊號結合與阻抗匹配的順序（相較於習知杜赫放大器），並使用包含為微帶線形式的整合分散式電感性元件的阻抗反相器，可明顯改良放大器頻寬並允許訊號放大縮放至較高的功率。A method and structure for improving the performance of a high speed, high power, wide frequency integrated amplifier. The structure and method are related to circuitry for combining the amplified signals and performing impedance matching at the modified Duch amplifier output. Re-arranging the order of signal combining and impedance matching (compared to the conventional Duch amplifier) and using an impedance inverter including integrated decentralized inductive components in the form of microstrip lines, the amplifier bandwidth can be significantly improved and the signal can be allowed Zoom in to a higher power.

一些具體實施例相關於一種杜赫放大器，包含：RF輸入；主放大器，主放大器連接至RF輸入；峰化放大器，峰化放大器連接至RF輸入；結合節點，在結合節點處來自主放大器的輸出與來自峰化放大器的輸出結合；以及阻抗反相器，阻抗反相器包含連接至主放大器的輸出以及結合節點的整合分散式電感器。Some embodiments relate to a Duch amplifier comprising: an RF input; a main amplifier having a main amplifier connected to the RF input; a peaking amplifier connected to the RF input by a peaking amplifier; and a junction, an output from the main amplifier at the junction node In combination with the output from the peaking amplifier; and the impedance inverter, the impedance inverter includes an output connected to the main amplifier and an integrated decentralized inductor coupled to the node.

在一些態樣中，對阻抗反相器的輸入，包含連接至主放大器的輸出的一或更多個接合線。結合節點可位於峰化放大器的汲極接合墊處。在一些實施例中，在主放大器與阻抗反相器之間，不提供將把主放大器的輸出阻抗匹配至50歐姆的阻抗匹配元件。阻抗反相器可將主放大器放大的第一訊號的相位，旋轉不超過95度，相對於由峰化放大器放大的第二訊號的相位。In some aspects, the input to the impedance inverter includes one or more bond wires that are connected to the output of the main amplifier. The bonding node can be located at the drain pad of the peaking amplifier. In some embodiments, between the main amplifier and the impedance inverter, an impedance matching element that will match the output impedance of the main amplifier to 50 ohms is not provided. The impedance inverter can rotate the phase of the first signal amplified by the main amplifier by no more than 95 degrees with respect to the phase of the second signal amplified by the peaking amplifier.

根據一些實施例，分散式電感器包含整合在基板上的至少一個傳導帶線，傳導帶線具有寬度與長度。阻抗反相器可進一步包含集總電感性與電容性元件。在一些實施例中，帶線可主要為電感性的。在一些情形中，帶線可被分成兩個，並由電容器串聯連接設置。在一些態樣中，阻抗反相器可進一步包含接合線或傳導性互連結構，接合線或傳導性互連結構連接在傳導帶線與主放大器及峰化放大器的輸出之間。帶線的寬度可在約100微米與約1000微米之間。在一些態樣中，帶線的長度可在約2毫米與約6毫米之間。在一些情形中，主放大器與峰化放大器可被整合在與傳導帶線相同的基板上。According to some embodiments, a decentralized inductor includes at least one conductive strip line integrated on a substrate, the conductive strip line having a width and a length. The impedance inverter can further comprise a lumped inductive and capacitive component. In some embodiments, the strip line can be primarily inductive. In some cases, the strip line can be split into two and placed in series by capacitor connections. In some aspects, the impedance inverter can further comprise a bond wire or a conductive interconnect structure connected between the conductive strip line and the output of the main amplifier and the peaking amplifier. The width of the strip line can be between about 100 microns and about 1000 microns. In some aspects, the length of the strip line can be between about 2 mm and about 6 mm. In some cases, the main amplifier and the peaking amplifier can be integrated on the same substrate as the conductive strip line.

在一些實施例中，其上形成了傳導帶線的基板，包含高頻層壓結構。在一些情形中，基板可包含半導體。In some embodiments, a substrate with a conductive strip line is formed thereon, comprising a high frequency laminate structure. In some cases, the substrate can comprise a semiconductor.

根據一些態樣，主放大器與峰化放大器之一者或兩者包含氮化鎵電晶體。According to some aspects, one or both of the main amplifier and the peaking amplifier comprise a gallium nitride transistor.

在一些實施例中，阻抗反相器實質上由傳導帶線與接合線組成，傳導帶線整合在基板上且具有一寬度與一長度，接合線連接在傳導帶線與來自主放大器與峰化放大器的輸出之間。In some embodiments, the impedance inverter consists essentially of a conductive strip line and a bond line integrated on the substrate and having a width and a length, the bond line being connected to the conductive strip line and from the main amplifier and peaking Between the outputs of the amplifiers.

在一些態樣中，杜赫放大器可進一步包含阻抗匹配元件，阻抗匹配元件連接在結合節點與杜赫放大器的輸出埠之間。阻抗匹配元件可提供50歐姆的輸出阻抗。在一些實施例中，阻抗匹配元件可對杜赫放大器提供約25歐姆與約100歐姆之間的輸出阻抗。In some aspects, the Duch amplifier can further include an impedance matching component coupled between the bonding node and the output 埠 of the Duch amplifier. The impedance matching component provides an output impedance of 50 ohms. In some embodiments, the impedance matching component can provide an output impedance between about 25 ohms and about 100 ohms to the Duch amplifier.

在一些實施例中，對於放大器的RF部分頻寬，可在約6 %與約18 %之間。對於杜赫放大器的操作頻率，可在約500 MHz與約6 GHz之間。在一些情形中，杜赫放大器可對來自結合節點的輸出功率位準額定為約20瓦與約100瓦之間。In some embodiments, the RF portion bandwidth for the amplifier can be between about 6% and about 18%. For the operating frequency of the Duch amplifier, it can be between approximately 500 MHz and approximately 6 GHz. In some cases, the Duch amplifier can be rated for an output power level from the bonding node of between about 20 watts and about 100 watts.

在一些態樣中，杜赫放大器可連接至蜂巢式發送器（例如併入蜂巢式電話或蜂巢式基地台的設備中）。In some aspects, the Duch amplifier can be connected to a cellular transmitter (eg, a device incorporated into a cellular phone or a cellular base station).

一些具體實施例相關於用於放大訊號的方法。所實施的方法可包含：將所接收的訊號分成第一訊號與第二訊號，第二訊號具有相對於第一訊號的第一相位；由主放大器放大第一訊號；由峰化放大器放大第二訊號；將來自主放大器的輸出直接提供至阻抗反相器的輸入，其中阻抗反相器包含整合分散式電感器；以及由阻抗反相器引入第二相位以補償第一相位。Some embodiments relate to methods for amplifying signals. The method may include: dividing the received signal into a first signal and a second signal, the second signal having a first phase relative to the first signal; amplifying the first signal by the main amplifier; and amplifying the second by the peaking amplifier The signal; the output of the autonomous amplifier is provided directly to the input of the impedance inverter, wherein the impedance inverter comprises an integrated decentralized inductor; and the second phase is introduced by the impedance inverter to compensate for the first phase.

在一些態樣中，第二相位不超過95度。In some aspects, the second phase does not exceed 95 degrees.

根據一些實施例，方法可進一步包含：將來自阻抗反相器的輸出與來自峰化放大器的輸出結合，以產生結合輸出；以及提供結合輸出至阻抗匹配元件。根據一些實施例，方法可進一步包含：由阻抗匹配元件將一阻抗匹配至約25歐姆與約100歐姆之間的一值。可在峰化放大器的汲極接合墊處完成結合。在一些實施例中，整合分散式電感器包含整合在基板上的傳導帶線，傳導帶線具有寬度與長度。寬度可在約100微米與約1000微米之間。長度可位於約2毫米與約6毫米之間。在一些情形中，阻抗反相器進一步包含接合線或傳導性互連結構，接合線或傳導性互連結構連接在傳導帶線與主放大器及峰化放大器的輸出之間。According to some embodiments, the method may further comprise combining the output from the impedance inverter with the output from the peaking amplifier to produce a combined output; and providing a combined output to the impedance matching element. According to some embodiments, the method may further comprise: matching an impedance by the impedance matching element to a value between about 25 ohms and about 100 ohms. Bonding can be done at the drain pad of the peaking amplifier. In some embodiments, the integrated decentralized inductor comprises a conductive strip line integrated on a substrate, the conductive strip line having a width and a length. The width can be between about 100 microns and about 1000 microns. The length can be between about 2 mm and about 6 mm. In some cases, the impedance inverter further includes a bond wire or a conductive interconnect structure connected between the conductive strip line and the output of the main amplifier and the peaking amplifier.

在一些實施例中，主放大器與峰化放大器可被整合在與傳導帶線相同的基板上。基板可包含高頻層壓結構。在一些態樣中，所接收的訊號位於約500 MHz與約6 GHz之間的一頻率。根據一些態樣，用於放大訊號的一RF部分頻寬，可位於約6 %與約18 %之間。結合輸出的功率位準可位於約20瓦與約100瓦之間。In some embodiments, the main amplifier and the peaking amplifier can be integrated on the same substrate as the conductive strip line. The substrate can comprise a high frequency laminate structure. In some aspects, the received signal is at a frequency between about 500 MHz and about 6 GHz. According to some aspects, an RF portion bandwidth for amplifying the signal can be between about 6% and about 18%. The power level of the combined output can be between about 20 watts and about 100 watts.

在一些態樣中，方法可進一步包含提供結合輸出，以由蜂巢式基地台傳輸。方法亦可包含：在主放大器與阻抗反相器之間，不提供將把主放大器的輸出阻抗匹配至50歐姆的阻抗匹配元件。放大方法之任一者可由氮化鎵電晶體執行。In some aspects, the method can further include providing a combined output for transmission by the cellular base station. The method may also include: between the main amplifier and the impedance inverter, an impedance matching component that will match the output impedance of the main amplifier to 50 ohms is not provided. Any of the amplification methods can be performed by a gallium nitride transistor.

前述設備與方法具體實施例，可被實施在任何適合的與前述（以及下文詳細說明的）態樣、特徵與步驟的結合者中。連同附加圖式參閱下列說明之後，可更全面瞭解本教示內容的這些與其他的態樣、具體實施例與特徵。The foregoing apparatus and method embodiments can be implemented in any suitable combination with the foregoing (and described in detail below) aspects, features and steps. These and other aspects, embodiments, and features of the present teachings can be more fully understood from the following description.

如前述，因為氮化鎵(GaN)材料的良好材料性質，包含GaN材料電晶體的放大器對於高速、高電壓及高功率應用是有用的。在一些情況中，由其他半導體材料（諸如砷化鎵、碳化矽、矽鍺等等）形成的電晶體，可適合用於一些高速、高電壓、與高功率應用。GaN電晶體逐漸被運用在射頻（RF）通訊與雷達的科技領域中。例如在RF通訊中，GaN電晶體可用於基地台處的杜赫放大器中，以放大資料訊號而用於基地台所涵蓋的細胞元內的無線廣播。As mentioned above, amplifiers comprising GaN material transistors are useful for high speed, high voltage, and high power applications because of the good material properties of gallium nitride (GaN) materials. In some cases, transistors formed from other semiconductor materials, such as gallium arsenide, tantalum carbide, tantalum, and the like, may be suitable for use in some high speed, high voltage, and high power applications. GaN transistors are increasingly being used in the field of radio frequency (RF) communication and radar technology. For example, in RF communication, a GaN transistor can be used in a Duch amplifier at a base station to amplify data signals for use in radio broadcasts within cell elements covered by the base station.

第 1 圖 圖示一種杜赫放大器100的設置。杜赫放大器可包含設置在並聯電路分支上的主放大器（main amplifier）132與峰化放大器（peaking amplifier）138。輸入RF訊號被由90度耦合器110分割，90度耦合器110提供相位衰減訊號至主放大器並提供旋轉90度（通常為延遲90度）的衰減訊號至峰化放大器。在放大之後，使用包含90度旋轉補償的阻抗反相器150，以將兩個訊號再結合為經結合放大的輸出RF訊號。輸出阻抗匹配元件160可連接至結合節點，以將杜赫放大器的輸出阻抗匹配至負載（未圖示）的阻抗。 FIG 1 depicts a first set Doherty amplifier 100. The Duch amplifier may include a main amplifier 132 and a peaking amplifier 138 disposed on the branch of the parallel circuit. The input RF signal is split by a 90 degree coupler 110 that provides a phase attenuation signal to the main amplifier and provides a 90 degree (typically 90 degree delay) attenuation signal to the peaking amplifier. After amplification, an impedance inverter 150 containing 90 degree rotation compensation is used to recombine the two signals into a combined amplified output RF signal. Output impedance matching component 160 can be coupled to the bonding node to match the output impedance of the Doher amplifier to the impedance of a load (not shown).

在杜赫放大器中，可在主放大器與峰化放大器之前放置阻抗匹配部件122、124。這些匹配部件可用於將來自90度耦合器110的傳輸線阻抗匹配至兩個放大器的輸入阻抗，使得來自放大器的訊號反射被減少或實質上消除。可在主放大器與峰化放大器的輸出處放置額外的阻抗匹配部件142、144，以將阻抗匹配至阻抗反相器150的輸入（設計值可為50歐姆）以及結合節點155。阻抗匹配部件142、144可包含電阻性、電容性、及（或）電感性的電路元件。In a Duch amplifier, impedance matching components 122, 124 can be placed before the main amplifier and the peaking amplifier. These matching components can be used to match the transmission line impedance from the 90 degree coupler 110 to the input impedance of the two amplifiers such that signal reflection from the amplifier is reduced or substantially eliminated. Additional impedance matching components 142, 144 may be placed at the output of the main and peaking amplifiers to match the impedance to the input of the impedance inverter 150 (designed value may be 50 ohms) and the bonding node 155. The impedance matching components 142, 144 can include resistive, capacitive, and/or inductive circuit components.

發明人已認知並理解到，在阻抗匹配部件142、144放置在主放大器132與峰化放大器138的輸出以及阻抗反相器150與結合節點155之間時，杜赫放大器100的頻寬性能可付出代價。在這些位置處，阻抗匹配部件142、144在兩個放大器之間加入電性路徑長度，使得阻抗反相器150不可能僅利用90度旋轉就能補償90度耦合器引入的相位旋轉q 。相對的，阻抗反相器150可需要以90度的奇數整數倍的相位旋轉來操作，如下式： 方程式 1 其中n為整數值1或更大。The inventors have recognized and appreciated that when the impedance matching components 142, 144 are placed between the output of the main amplifier 132 and the peaking amplifier 138 and between the impedance inverter 150 and the bonding node 155, the bandwidth performance of the Duch amplifier 100 can be Pay the price. At these locations, the impedance matching components 142, 144 add an electrical path length between the two amplifiers such that the impedance inverter 150 cannot compensate for the phase rotation q introduced by the 90 degree coupler with only a 90 degree rotation. In contrast, the impedance inverter 150 may need to operate with an odd integer multiple of 90 degrees of phase rotation, as follows: Equation 1 where n is an integer value of 1 or greater.

為了調查杜赫放大器100由於阻抗匹配元件142、144所付出的頻寬性能代價，使用低功率電路模型200執行高頻模擬，如第 2 圖 繪製。低功率電路模型代表峰化放大器關閉時的情形。發明人已認知並理解到，在峰化放大器關閉時，杜赫放大器中主放大器132的輸出與結合節點155之間可發生大量的阻抗失配。因此，低功率作業可限制杜赫放大器的額定RF部分頻寬（例如對於所有訊號位準的保證頻寬）。在低功率電路模型200中，主放大器132呈現為第一電流源I_m ，而峰化放大器138呈現為第二電流源I_p （不輸出電流）。阻抗反相器150被模型化為傳輸線，具有電阻R_o 與可調式相位旋轉，在中心作業頻率（對於此模擬為2 GHz）下可調式相位旋轉可設為90度的奇數倍。負載阻抗為R_o /2。為了模擬，將峰化放大器關閉時的阻抗給定為20R_o 。To investigate the Doherty amplifier 100 due to the impedance matching element 142 performance penalty to pay for bandwidth, low power high frequency analog circuit model 200 performs, as the second drawing. The low power circuit model represents the situation when the peaking amplifier is turned off. The inventors have recognized and appreciated that a large amount of impedance mismatch can occur between the output of the main amplifier 132 and the bonding node 155 in the Duch amplifier when the peaking amplifier is turned off. Therefore, low power operation can limit the nominal RF portion bandwidth of the Duch amplifier (eg, guaranteed bandwidth for all signal levels). In the low-power circuit model 200, main amplifier 132 exhibits a first current source I _m, and the peaking amplifier 138 exhibits a second current source I _p (not the output current). The impedance inverter 150 is modeled as a transmission line with a resistance _Ro and an adjustable phase rotation, and the adjustable phase rotation can be set to an odd multiple of 90 degrees at the center operating frequency (2 GHz for this simulation). The load impedance is R _o /2. For simulation, the impedance when the peaking amplifier is turned off is given as 20R _o .

可使用諸如可從美國加州Santa Rosa的Keysight Technologies, Inc.取得的Advanced Design System(ADS)的軟體工具，實施本文所說明的模擬電路與電路元件。其他適合的軟體工具，包含但不限於可從美國加州El Segundo的AWR Corporation取得的NI AWR Design Environment，以及可從美國紐約North Syracuse的Sonnet Software取得的Sonnet®軟件工具。The analog circuits and circuit components described herein can be implemented using a software tool such as the Advanced Design System (ADS) available from Keysight Technologies, Inc. of Santa Rosa, California. Other suitable software tools include, but are not limited to, the NI AWR Design Environment available from AWR Corporation of El Segundo, California, USA, and the Sonnet® software tool available from Sonnet Software of North Syracuse, New York, USA.

第 3 圖 圖示杜赫放大器的模擬結果。圖示中繪製的頻率響應曲線310、320、330呈現從主放大器132（例如電流源I_m ）輸出處看進阻抗反相器150所估算的散射參數S(1,1)。頻率響應曲線呈現反射回主放大器的訊號量（例如電壓對駐波比），為對頻率的函數。為了估算放大器性能，可從頻率響應曲線上的-20 dB點之間的頻率差異，來判定放大器的RF部分頻寬（Dw/w_o ），其中往回反射訊號的值低於輸入至阻抗反相器的訊號位準至少20 dB。 FIG 3 illustrates the simulation results of the Doherty amplifier. The frequency response curves 310, 320, 330 plotted in the illustration present the scatter parameter S(1, 1) estimated from the impedance inverter 150 at the output of the main amplifier 132 (eg, current source I _m ). The frequency response curve presents the amount of signal reflected back to the main amplifier (eg, voltage versus standing wave ratio) as a function of frequency. In order to estimate the performance of the amplifier, the RF part bandwidth (Dw/w _o ) of the amplifier can be determined from the frequency difference between the -20 dB points on the frequency response curve. The value of the back-reflected signal is lower than the input-to-impedance inverse. The signal level of the phaser is at least 20 dB.

在阻抗匹配元件142、144被放置在阻抗反相器與結合節點之前時，阻抗反相器150的最小可允許相位旋轉可為270度，由於阻抗匹配元件所增加的額外電性路徑長度。一個這種情況（在方程式1中n=1，虛線）對應於第 3 圖 繪製的頻率響應曲線320。在此情況中，RF部分頻寬為約6%。若阻抗匹配元件142、144引入的增加電性路徑更大，則阻抗反相器150引入的最小可允許相位可提升至450度（n=2），這產生了頻率響應曲線310。對此情況，RF部分頻寬減少至約3%。用於RF通訊系統的習知杜赫放大器，通常操作在少於約4%的RF部分頻寬。另一方面，若阻抗反相器150引入的最小可允許相位為90度，則RF部分頻寬可提升至17%以上，如頻率響應曲線330指示。When the impedance matching components 142, 144 are placed before the impedance inverter and the bonding node, the minimum allowable phase rotation of the impedance inverter 150 can be 270 degrees due to the additional electrical path length added by the impedance matching component. A case (in Equation 1, n = 1, dashed line) in FIG. 3 corresponds to the frequency response curve 320 plotted. In this case, the RF portion has a bandwidth of about 6%. If the increased electrical path introduced by the impedance matching elements 142, 144 is greater, the minimum allowable phase introduced by the impedance inverter 150 can be increased to 450 degrees (n = 2), which produces a frequency response curve 310. In this case, the RF portion bandwidth is reduced to approximately 3%. Conventional Duch amplifiers for RF communication systems typically operate at less than about 4% of the RF portion bandwidth. On the other hand, if the minimum allowable phase introduced by the impedance inverter 150 is 90 degrees, the RF portion bandwidth can be increased to above 17% as indicated by the frequency response curve 330.

發明人已認知並理解到，將阻抗匹配元件142、144從阻抗反相器150與結合節點155之前移除，允許將阻抗反相器引入的補償相位減少至90度或約90度。雖然補償相位角度較佳為90度，但在一些情況中耦合器110可施加85度與95度之間的相位差異而由阻抗反相器補償。The inventors have recognized and appreciated that removing the impedance matching elements 142, 144 from the impedance inverter 150 and the bonding node 155 allows the compensation phase introduced by the impedance inverter to be reduced to 90 degrees or about 90 degrees. Although the compensation phase angle is preferably 90 degrees, in some cases the coupler 110 can apply a phase difference between 85 degrees and 95 degrees to be compensated by the impedance inverter.

第 4 圖 圖示一具體實施例的經修改杜赫放大器400，其中來自主放大器與峰化放大器的訊號先被結合，在結合之後再將阻抗匹配至負載。例如，可在放置在結合節點155之後的輸出阻抗匹配元件420中完成阻抗匹配。根據一些具體實施例，結合節點155可放置在峰化放大器138的輸出處。對阻抗反相器410的輸入，可直接連接至來自主放大器132的輸出。在主放大器的輸出與阻抗反相器410的輸入之間，可不存在例如將主放大器的阻抗匹配或旋轉至50歐姆的阻抗匹配元件。再者，峰化放大器138的輸出與結合節點155之間可不存在阻抗匹配元件。 FIG 4 illustrates a modified embodiment particularly by Doherty amplifier 400, where signals from the main amplifier and the peaking amplifier are combined first, and then after bonding to the load impedance. For example, impedance matching can be done in the output impedance matching component 420 placed after the bonding node 155. According to some embodiments, the bonding node 155 can be placed at the output of the peaking amplifier 138. The input to impedance inverter 410 can be directly coupled to the output from main amplifier 132. Between the output of the main amplifier and the input of the impedance inverter 410, there may be no impedance matching elements such as matching or rotating the impedance of the main amplifier to 50 ohms. Furthermore, there may be no impedance matching components between the output of the peaking amplifier 138 and the bonding node 155.

第 5A 圖 根據一些具體實施例，繪製阻抗反相器410與經修改杜赫放大器400的進一步細節。在一些情況中，阻抗反相器410包含延伸長度L的傳導帶線510（例如微帶線）。長度L可延伸於主放大器132與峰化放大器138的輸出汲極接合墊533之間（並沿著輸出汲極接合墊533延伸）。傳導帶線510可具有寬度W。根據一些具體實施例，傳導帶線的長度可位於約2毫米與約6毫米之間，並可被選擇以對帶線510提供所需的電感。根據一些具體實施例，傳導帶線的寬度可位於約100微米與約1000微米之間，並可被選擇以對帶線提供所需的電感。在一些實施例中，傳導帶線被形成在地導體或地平面上，且藉由介電材料（未圖示）與地導體或地平面隔開。在其他具體實施例中，傳導帶線可並非形成於地平面上，也並非形成為鄰接於地平面。相對的，在圖案化傳導帶線的PCB區域處可移除地平面。在實施在用於RF訊號的阻抗反相器中時，傳導帶線可包含為實質上全電感性的整合分佈式阻抗元件。在一些實施例中，帶線可包含一些寄生電容與電阻。 FIG . 5A depicts further details of the impedance inverter 410 and the modified Duch amplifier 400, in accordance with some embodiments. In some cases, impedance inverter 410 includes a conductive strip line 510 (eg, a microstrip line) that extends an length L. The length L may extend between the main amplifier 132 and the output drain pad 533 of the peaking amplifier 138 (and extend along the output drain pad 533). Conductive strip line 510 can have a width W. According to some embodiments, the length of the conductive strip line can be between about 2 mm and about 6 mm and can be selected to provide the desired inductance to the strip line 510. According to some embodiments, the width of the conductive strip line can be between about 100 microns and about 1000 microns and can be selected to provide the desired inductance to the strip line. In some embodiments, the conductive strip lines are formed on the ground conductor or ground plane and are separated from the ground conductor or ground plane by a dielectric material (not shown). In other embodiments, the conductive strip lines may not be formed on the ground plane nor formed adjacent to the ground plane. In contrast, the ground plane can be removed at the PCB area where the conductive strip lines are patterned. When implemented in an impedance inverter for RF signals, the conductive strip line can comprise an integrated distributed impedance element that is substantially fully inductive. In some embodiments, the strip line can include some parasitic capacitance and resistance.

傳導帶線可被形成在基板505上，可在基板505上製造輸出阻抗匹配元件560。在一些具體實施例中，主放大器132與峰化放大器138可被裝設為鄰接於基板505，且在一或更多個個別的晶粒上。在一些實施例中，傳導帶線510可被整合到其上形成了主放大器132及（或）峰化放大器138的同一基板上。其上形成了傳導帶線的基板505，在一些具體實施例中可包含印刷電路板、在一些具體實施例中可包含能夠承載GHz頻率訊號的高頻層壓結構、陶瓷、或半導體。高頻層壓結構的範例，為可從美國亞利桑那州Chandler的Rogers Corporation獲得的層壓結構型號RO4003®。A conductive strip line can be formed on substrate 505 on which output impedance matching element 560 can be fabricated. In some embodiments, main amplifier 132 and peaking amplifier 138 can be mounted adjacent to substrate 505 and on one or more individual dies. In some embodiments, the conductive strip line 510 can be integrated onto the same substrate on which the main amplifier 132 and/or the peaking amplifier 138 are formed. A substrate 505 having conductive strip lines formed thereon may, in some embodiments, include a printed circuit board, and in some embodiments may include a high frequency laminate structure, ceramic, or semiconductor capable of carrying GHz frequency signals. An example of a high frequency laminate structure is the laminated structure model RO4003® available from Rogers Corporation of Chandler, Arizona, USA.

根據一些具體實施例，阻抗反相器410可進一步包含一或更多個放大器輸出接合線520，在帶線的第一端附近（例如約位於帶線長度的首1/3之內）連接至主放大器的汲極接合墊533與傳導帶線510。此外，可存在一或更多個放大器輸出接合線520，連接在峰化放大器138的汲極接合墊與傳導帶線510的相對端之間。在一些具體實施例中輸出接合線520可沿著帶線實質均勻地間隔設置，但在其他具體實施例中可不均勻地設置。接合線之間的間隔可為約100微米與約800微米之間。接合線520可包含金或任何其他適合的導體，可具有20微米與80微米之間的直徑，並可拱接(arc)或延伸在基板505與基板503上至約50微米與約250微米之間的高度。輸出接合線520包含阻抗反相器410的集總電感性元件。在RF電子學的領域中，這種接合線被認知為「集總電感器」，具有主要由接合線的長度與直徑判定的電感值。可存在放大器輸入接合線540，連接至主放大器132與峰化放大器138的閘點接合墊531。According to some embodiments, the impedance inverter 410 can further include one or more amplifier output bond wires 520 connected to the first end of the strip line (eg, within about the first 1/3 of the length of the strip line) to The main amplifier has a drain bond pad 533 and a conductive strip line 510. Additionally, there may be one or more amplifier output bond wires 520 connected between the drain bond pads of the peaking amplifier 138 and the opposite ends of the conductive strip lines 510. In some embodiments, the output bond wires 520 may be substantially evenly spaced along the strip line, but may be non-uniformly disposed in other embodiments. The spacing between the bond wires can be between about 100 microns and about 800 microns. Bond wire 520 can comprise gold or any other suitable conductor, can have a diameter between 20 microns and 80 microns, and can be arched or extended over substrate 505 and substrate 503 to between about 50 microns and about 250 microns. The height between the two. Output bond wire 520 includes a lumped inductive component of impedance inverter 410. In the field of RF electronics, such bonding wires are known as "lumped inductors" having inductance values that are primarily determined by the length and diameter of the bond wires. There may be an amplifier input bond wire 540 connected to the gate bond pad 531 of the main amplifier 132 and the peaking amplifier 138.

在其中傳導帶線510、主放大器及（或）峰化放大器被整合在同一基板上的一些具體實施例中，可不使用接合線520。相反的，可使用諸如微帶傳輸線或傳導跡線的傳導性互連結構，以將帶線510連接至主放大器與峰化放大器的輸出。在其中傳導帶線510、主放大器及（或）峰化放大器被整合在同一基板上的一些實施例中，一個或兩個汲極接合墊530可被傳導帶線510替換或歸入傳導帶線510，使得阻抗反相器的電感值實質上整體為分散式電感值。In some embodiments in which the conduction strip line 510, the main amplifier, and/or the peaking amplifier are integrated on the same substrate, the bond wires 520 may not be used. Instead, a conductive interconnect structure such as a microstrip transmission line or a conductive trace can be used to connect the strip line 510 to the output of the main amplifier and the peaking amplifier. In some embodiments in which the conductive strip line 510, the main amplifier, and/or the peaking amplifier are integrated on the same substrate, one or both of the drain bond pads 530 can be replaced by conductive strip lines 510 or classified as conductive strip lines. 510, such that the inductance value of the impedance inverter is substantially a distributed inductance value.

根據第 5A 圖 繪製的具體實施例，杜赫放大器400的結合節點可被放置在峰化放大器138的汲極接合墊533處。在這種具體實施例中，阻抗反相器410可包含集總電感性元件（例如主放大器與峰化放大器輸出接合線520）以及包含傳導帶線510的整合分散式電感性元件。為了分析RF性能，阻抗反相器可包含集總電容性元件，集總電容性元件可包含主放大器132與峰化放大器138的汲極對源極電容以及汲極接合墊533的電容。阻抗反相器410可進一步包含傳導帶線510的小型分散式電容。According to a particular embodiment of FIG. 5A drawn conjoin node Doherty amplifier 400 may be placed in a peaking amplifier 138. Drain electrode bonding pad 533. In such a particular embodiment, impedance inverter 410 can include a lumped inductive component (eg, main amplifier and peaking amplifier output bond wire 520) and an integrated decentralized inductive component including conductive stripline 510. To analyze RF performance, the impedance inverter can include a lumped capacitive element that can include the drain-to-source capacitance of the main amplifier 132 and the peaking amplifier 138 and the capacitance of the drain bond pad 533. The impedance inverter 410 can further include a small distributed capacitor that conducts the strip line 510.

在一些實施例中，集總電容元件可被加入並聯至汲極接合墊533及（或）電感性帶線510，以將杜赫放大器的操作頻率調整至所需值，或可被加入串聯以延伸阻抗反相器的長度以用於較高功率的應用。在一些情況中，整合電感性帶線可包含兩個個別的帶線512，兩個帶線512由電容器580（例如表面安裝式電容器）串聯連接，電容器580位於兩個帶線512之間，如第 5C 圖 所示。這種雙帶線設置可延伸兩個放大器之間的總和距離，允許較大的放大器132、138以及較高的功率能力，而不會增加更多電感值。然而，所加入的電感值應被限制，以避免改變阻抗反相器中的相位旋轉超過95度。In some embodiments, a lumped capacitive element can be added in parallel to the drain bond pad 533 and/or the inductive strip line 510 to adjust the operating frequency of the Duch amplifier to a desired value, or can be added in series to Extend the length of the impedance inverter for higher power applications. In some cases, the integrated inductive strip line can include two individual strip lines 512 that are connected in series by capacitors 580 (eg, surface mount capacitors) with capacitor 580 between the two strip lines 512, such as As shown in FIG. 5C. This dual strip line setup extends the summing distance between the two amplifiers, allowing for larger amplifiers 132, 138 and higher power capabilities without adding more inductance values. However, the added inductance value should be limited to avoid changing the phase rotation in the impedance inverter by more than 95 degrees.

在一些情況中，可存在輸出接合線550，輸出接合線550連接於杜赫放大器的峰化放大器138的汲極接合墊533與輸出阻抗匹配元件560之間。輸出阻抗匹配元件560可包含集總及（或）分散式阻抗元件，用於將來自峰化放大器138的汲極接合墊533的阻抗匹配至負載平面570處的負載阻抗（例如50歐姆）。In some cases, there may be an output bond wire 550 that is coupled between the drain bond pad 533 of the peaking amplifier 138 of the Duch amplifier and the output impedance matching component 560. Output impedance matching component 560 can include lumped and/or distributed impedance components for matching the impedance of drain bond pad 533 from peaking amplifier 138 to a load impedance (eg, 50 ohms) at load plane 570.

第 5B 圖 圖示對於一些具體實施例的接近主放大器或峰化放大器的汲極接合墊533的結構的額外細節。主放大器132及（或）峰化放大器138可包含電晶體線性陣列，具有形成在半導體基板503上的閘極導體532、汲極接點534、與源極接點536。對於放大器的汲極接點534可連接至汲極接合墊533，在汲極接合墊533處可接合一或更多個輸出接合線520、550。在一些實施例中，電晶體的主動區域可包含氮化鎵，如前述，可期望將氮化鎵用於高功率、高頻率的RF訊號放大。本文中的詞語「氮化鎵」，是指氮化鎵（GaN）及其任何合金，例如氮化鋁鎵（Al_x Ga_{（ 1-x ）} N）、氮化銦鎵（In_y Ga_{（ 1-y ）} N）、氮化鋁銦鎵（Al_x In_y Ga_{（ 1-x-y ）} N）、氮化鎵砷磷（GaAs_x P_y N_{（ 1-x-y ）} ）、氮化鋁銦鎵砷磷氮化物（Al_x In_y Ga_{（ 1-x-y ）} As_a P_b N_{（ 1-a-b ）} ）等等。在一些情況中，可由其他半導體材料形成電晶體，諸如砷化鎵、碳化矽、矽鍺、矽、磷化銦等等，且本發明並不限於基於氮化鎵的放大器。 FIG 5B illustrates some of the main amplifier or close the drain peaking amplifier particular embodiment of the electrode bonding pad Additional details of the structure 533. Main amplifier 132 and/or peaking amplifier 138 may comprise a linear array of transistors having gate conductor 532, drain contact 534, and source contact 536 formed on semiconductor substrate 503. The drain contact 534 for the amplifier can be connected to the drain bond pad 533, and one or more output bond wires 520, 550 can be bonded at the drain bond pad 533. In some embodiments, the active region of the transistor may comprise gallium nitride, as described above, and it may be desirable to use gallium nitride for high power, high frequency RF signal amplification. The term "gallium nitride" as used herein refers to gallium nitride (GaN) and any alloy thereof, such as aluminum gallium nitride (Al _x Ga _{( 1-x )} N), indium gallium nitride (In _y Ga _{( 1 -y )} N), aluminum indium gallium nitride (Al _x In _y Ga _{( 1-xy )} N), gallium nitride arsenic phosphorus (GaAs _x P _y N _{( 1-xy )} ), aluminum indium gallium arsenide Nitride (Al _x In _y Ga _{( 1-xy )} As _a P _b N _{( 1-ab )} ) or the like. In some cases, a transistor may be formed from other semiconductor materials, such as gallium arsenide, tantalum carbide, tantalum, niobium, indium phosphide, and the like, and the invention is not limited to gallium nitride-based amplifiers.

以阻抗反相器中的傳導帶線510作為電感性阻抗元件的益處，在於傳導帶線510可更輕易地允許杜赫放大器400的功率的可縮放性，相較於僅使用集總電感性元件。例如，杜赫放大器的功率處理能力，可由主放大器132與峰化放大器138中的電晶體尺寸判定。可藉由在主放大器與峰化放大器中提升沿著線性電晶體陣列的電晶體數量（閘極導體、汲極接點、與源極接點），來提升杜赫放大器中的功率。然而，提升陣列的電晶體數量與長度，可需要兩個放大器之間的額外放大器輸出接合線520，以及傳導帶線510上的對應位置，並可需要提升帶線長度。The benefit of using the conduction strip line 510 in the impedance inverter as the inductive impedance element is that the conduction strip line 510 can more easily allow the power of the Duch amplifier 400 to be scalable compared to using only lumped inductive elements. . For example, the power handling capability of the Duch amplifier can be determined by the transistor size in the main amplifier 132 and the peaking amplifier 138. The power in the Duch amplifier can be boosted by boosting the number of transistors along the linear transistor array (gate conductor, gate contact, and source contact) in the main and peaking amplifiers. However, increasing the number and length of transistors in the array may require additional amplifier output bond wires 520 between the two amplifiers, as well as corresponding locations on the conductive strip lines 510, and may require elevated strip line lengths.

增加放大器輸出接合線520並提升帶線長度，正常來說將提升阻抗反相器410的電感值。發明人已認知並理解到，這種電感值的提升，可由降低傳導帶線510的電感值來抵銷。可藉由提升帶線寬度W，來降低帶線510的電感值。藉由選擇帶線的長度與寬度，可將帶線510的分散式電感值調諧至所需的值。根據一些具體實施例，帶線的分散式電感值的總和，可在約250 picoHenries與約1.5 nanoHenries之間。Increasing the amplifier output bond line 520 and increasing the strip line length will normally increase the inductance of the impedance inverter 410. The inventors have recognized and appreciated that this increase in inductance can be offset by reducing the inductance of the conduction strip line 510. The inductance value of the strip line 510 can be reduced by increasing the strip line width W. By selecting the length and width of the strip line, the distributed inductance value of strip line 510 can be tuned to the desired value. According to some embodiments, the sum of the distributed inductance values of the strip lines can be between about 250 picoHenries and about 1.5 nanoHenries.

對於在一些情況中的功率縮放，藉由提升帶線510的寬度W及（或）降低帶線510的長度L，可降低帶線510的電感值。相反的，可藉由降低帶線的寬度W及（或）提升帶線510的長度L，來提升帶線的電感值。這種改變亦將影響帶線的任何電感值與電阻值。傳導帶線510包含用於阻抗反相器410的可調諧式阻抗元件，可在圖案化製造階段調整可調諧式阻抗元件以用於所需的應用。因此，杜赫放大器400的功率可被縮放，同時保持杜赫放大器400的操作頻率與頻寬性能。在使用純集總元件阻抗反相器時（其中主放大器132的汲極接合墊533直接接線接合至峰化放大器138的汲極接合墊），將不可能達成這種可縮放性。For power scaling in some cases, by increasing the width W of the strip line 510 and/or reducing the length L of the strip line 510, the inductance value of the strip line 510 can be reduced. Conversely, the inductance of the strip line can be increased by reducing the width W of the strip line and/or the length L of the lift strip line 510. This change will also affect any inductance and resistance values of the strip. Conductive strip line 510 includes a tunable impedance element for impedance inverter 410 that can be adjusted during the patterning fabrication stage for the desired application. Therefore, the power of the Duch amplifier 400 can be scaled while maintaining the operating frequency and bandwidth performance of the Duch amplifier 400. This scalability is not possible when using a pure lumped element impedance inverter where the gate pad 533 of the main amplifier 132 is directly wired to the pad electrode of the peaking amplifier 138.

加入長度至電晶體陣列，亦將加入電性路徑長度至阻抗反相器410。因此，在如第 5A 圖 所繪製的設置中，對於總和允許電性路徑長度將有限制，且因此限制了杜赫放大器可處理的功率。實質上，電性路徑長度可被提升，直到相位旋轉到達約90度，雖然在耦合器110提供高於90度的相位旋轉的一些情況中，可能存在較高的值（例如上至95度）。因為對於實體路徑長度的相位旋轉將取決於頻率，較低頻率的裝置可允許放大器電晶體陣列長度延伸較多，且因此能處理高功率。初始計算指示如第 5A 圖 所示般配置的杜赫放大器，應能夠將在約500 MHz與約6 GHz之間的頻率範圍中的RF訊號，在500 MHz下放大至約5瓦與約100瓦之間的功率位準，且在6 GHz下放大至約5瓦與約35瓦之間的功率位準。在一些實施例中，功率位準在500 MHz下可高至約20瓦與約100瓦之間，且在6 GHz下可高至約20瓦與約35瓦之間。Adding the length to the transistor array will also add an electrical path length to the impedance inverter 410. Accordingly, as provided in FIG. 5A drawn, for allowing the sum of the electrical path length will be limited, and thus limit the processing power of the Doherty amplifier. In essence, the electrical path length can be increased until the phase rotation reaches approximately 90 degrees, although in some cases where the coupler 110 provides a phase rotation above 90 degrees, there may be a higher value (eg, up to 95 degrees). . Since the phase rotation for the length of the physical path will depend on the frequency, a lower frequency device may allow the amplifier transistor array to extend more in length and thus be able to handle high power. The initial calculations indicate Doherty amplifier configuration as shown in FIG 5A, may be capable of RF signals in the frequency range between about 500 MHz and about 6 GHz is enlarged to about 5 watts and about 100 watts at 500 MHz The power level between them is amplified to a power level between about 5 watts and about 35 watts at 6 GHz. In some embodiments, the power level can be as high as about 20 watts to about 100 watts at 500 MHz and can be as high as about 20 watts to about 35 watts at 6 GHz.

在替代性具體實施例中，杜赫放大器400的功率能力可加倍。再次參照第 5A 圖 ，第二主放大器132可放置在傳導帶線與所圖示說明之第一主放大器132相對的一側。輸出阻抗匹配元件560可被旋轉90度，且被裝設在傳導帶線510末端旁靠近峰化放大器138處。第二峰化放大器138可放置在傳導帶線與所圖示說明的第一峰化放大器138相對的一側上。來自額外的主放大器與峰化放大器的汲極接合墊，可被接線接合至傳導帶線。額外的接合線可被以一些角度從輸出阻抗匹配元件560連接至峰化放大器138的汲極接合墊。In an alternative embodiment, the power capability of the Duch amplifier 400 can be doubled. Referring again to FIG . 5A , the second main amplifier 132 can be placed on the side of the conductive strip line opposite the illustrated first main amplifier 132. Output impedance matching component 560 can be rotated 90 degrees and mounted adjacent to the end of conductive strip line 510 near peaking amplifier 138. The second peaking amplifier 138 can be placed on the side of the conductive strip line opposite the illustrated first peaking amplifier 138. A drain bond pad from an additional main amplifier and peaking amplifier can be wired to the conduction strip line. Additional bond wires can be connected from the output impedance matching component 560 to the drain bond pads of the peaking amplifier 138 at some angle.

執行了對於設置如第 4 圖 所示的杜赫放大器400的數個電路模擬，第 6 圖 圖示模擬的一些結果。在第一模擬中，使用集總等效模型來模型化阻抗反相器410：單一集總電感器以及多個並聯電容器，設置為連接在主放大器132與峰化放大器138之間的pi型網路。電容器可被並聯連接於電感器的任一側。電感器的值為1.04 nH。兩個電容器的值為1.99 pF，這代表汲極對源極電容值（~ 1.6 pF）與汲極接合墊電容值（~ 0.39 pF）的總和。電路設置類似於第 2 圖 圖示的設置，但阻抗反相器150係由集總pi型網路替換，且峰化電流源I_p 由20Ro電阻替換。R_o 的值為22.9歐姆。執行此第一模擬，以分析杜赫放大器400的可行性，其中在阻抗匹配之前先執行結合。Some results for the execution of a plurality of analog circuits Doherty amplifier 400 is provided as shown in FIG. 4, FIG. 6 illustrates simulation. In a first simulation, a lumped equivalent model is used to model the impedance inverter 410: a single lumped inductor and a plurality of shunt capacitors, arranged as a pi-type network connected between the main amplifier 132 and the peaking amplifier 138. road. The capacitor can be connected in parallel to either side of the inductor. The value of the inductor is 1.04 nH. The value of the two capacitors is 1.99 pF, which represents the sum of the drain-to-source capacitance (~ 1.6 pF) and the drain bond capacitance (~ 0.39 pF). Providing a second circuit arrangement is similar to FIG illustrated, but the impedance of the inverter 150 is replaced by a lumped pi-based network type, and the peak of the current source I _p 20Ro replaced by a resistor. The value of R _o is 22.9 ohms. This first simulation is performed to analyze the feasibility of the Duch amplifier 400, where the bonding is performed prior to impedance matching.

在一些具體實施例中，杜赫放大器的操作頻率w_o 與帶線510的電感L_s 的值，部分受限於放大器設計。例如，一放大器設計可具有汲極對源極電容C_ds ，且對於操作電壓V_ds 被額定在最大汲極對源極電流I_max 。可使放大器傳輸最大功率的電阻值R_o ，可大約由下式判定。(方程式2) 其中V_k 為放大器的膝節電壓。一旦R_o 估算出，則期望使並聯電容C_sh 的導納（主要由C_ds 判定，雖然可包含汲極墊電容與任何加入的電容）與阻抗反相器的電感L_c 的阻抗（由接合線520與帶線510判定）匹配對應的R_o 的導納與阻抗值，這得出：(方程式 3 )(方程式 4 ) 因為C_ds 主要係由放大器設計判定並可為主導電容（dominant capacitance），方程式 3 大致限制了放大器的操作頻率，雖然可藉由加入額外的並聯電容將操作頻率下調。根據一些具體實施例，在選定操作頻率時，傳導帶線可經設計以根據方程式 4 提供電感。In some embodiments, the operating frequency w _{o of the} Duch amplifier and the value of the inductance L _s of the strip line 510 are partially limited by the amplifier design. For example, an amplifier design can have a drain-to-source capacitance _Cds and is rated for a maximum drain-to-source current _Imax for the operating voltage _Vds . The resistance value R _{o at} which the amplifier can transmit the maximum power can be determined by approximately the following equation. (Equation 2) where V _k is the knee voltage of the amplifier. Once R _{o is} estimated, it is desirable to make the admittance of the shunt capacitor C _sh (mainly determined by C _ds , although it may include the drain pad capacitance and any added capacitance) and the impedance of the impedance inverter L _c (by the junction) Line 520 and strip line 510 determine) the corresponding admittance and impedance values of R _o , which yields: ( Equation 3 ) ( Equation 4 ) Since C _{ds is} primarily determined by the amplifier design and can be dominant capacitance, Equation 3 roughly limits the operating frequency of the amplifier, although the operating frequency can be lowered by adding an additional shunt capacitor. According to some embodiments, the conduction strip line can be designed to provide inductance according to Equation 4 at a selected operating frequency.

第 6 圖 繪製以集總元件阻抗反相器進行的第一模擬的頻率響應曲線610（點曲線）。圖表呈現看進阻抗反相器（例如看進第一電容性並聯的pi型網路）的散射參數S(1,1)。響應顯示約400 MHz的頻寬，定中心於約3.5 GHz的操作頻率。此頻寬大於11%並代表顯著提升的在RF頻率下的習知杜赫放大器的相較頻寬性能（通常小於4%）。Drawing FIG. 6 a first analog frequency lumped element impedance inverter for the response curve 610 (dotted curve). The graph presents the scattering parameter S(1,1) looking into the impedance inverter (for example, looking into the first capacitively parallel pi-type network). The response shows a bandwidth of approximately 400 MHz centered at an operating frequency of approximately 3.5 GHz. This bandwidth is greater than 11% and represents a significantly improved phase-to-bandwidth performance (typically less than 4%) of conventional Duch amplifiers at RF frequencies.

在第二模擬中，集總電感器被由分散式電感器替換，分散式電感器更精確地模型化第 5A 圖 繪製的整合傳導帶線510。對於此模擬，使用電磁（EM）場模擬工具來執行在由傳導帶線510執行的不同頻率下的電磁波的模型化。在EM模擬中，傳導帶線被模型化為具有對應於接合線520的六個輸入埠。輸入埠寬50 µm，且三個輸入埠每一者的末端彼此間隔開50 µm節距。傳導帶線的長度為3.7 mm，且寬度為300 µm。傳導帶線被模型化為由銅形成（厚17.5 µm）在高頻層壓結構上，高頻層壓結構的介電常數為3.55且損耗正切為0.002。隔開傳導帶線與地平面的層壓結構厚度為305 µm。對於EM模擬，使用在4 GHz下每波長具有50個細胞元的網格。對於帶線510的EM模擬的結果，被使用在阻抗反相器的電路模擬中，其中相同的集總電容值（1.99 pF）被使用且被設置在pi型網路中。電路設置或者相同於用以產生頻率響應曲線610的電路設置。此第二模擬的結果被繪製為頻率響應曲線620（點曲線），指示在阻抗反相器中使用分散式電感性元件在RF部分頻寬中加入最少的減少量，相較於純集總元件阻抗反相器。因此，電感性帶線510致能功率縮放性，同時實質上維持操作頻率與RF部分頻寬性能。In the second simulation, a lumped inductor is replaced by the distributed inductor, the inductor distributed to more accurately model the Drawing FIG. 5A integrated with the conductive line 510. For this simulation, an electromagnetic (EM) field simulation tool is used to perform modeling of the electromagnetic waves at different frequencies performed by the conduction strip line 510. In the EM simulation, the conduction strip lines are modeled to have six input turns corresponding to bond wires 520. The input 埠 is 50 μm wide and the ends of each of the three input 间隔 are spaced 50 μm apart from each other. The conductive strip line has a length of 3.7 mm and a width of 300 μm. The conduction strip line was modeled as being formed of copper (thickness 17.5 μm) on a high frequency laminate structure having a dielectric constant of 3.55 and a loss tangent of 0.002. The laminate structure separating the conductive strip line from the ground plane has a thickness of 305 μm. For EM simulation, a grid of 50 cells per wavelength at 4 GHz was used. The results of the EM simulation with line 510 are used in the circuit simulation of the impedance inverter where the same lumped capacitance value (1.99 pF) is used and placed in the pi-type network. The circuit settings are the same as the circuit settings used to generate the frequency response curve 610. The result of this second simulation is plotted as a frequency response curve 620 (dotted curve) indicating the use of decentralized inductive components in the impedance inverter to add the least amount of reduction in the RF portion bandwidth compared to pure lumped elements Impedance inverter. Thus, the inductive strip line 510 enables power scalability while substantially maintaining the operating frequency and RF portion bandwidth performance.

執行了額外的EM模擬，以更精確地呈現主放大器132與峰化放大器138的輸出接合墊533，並執行電路模擬以呈現連接至接合墊533的接合線520。對於EM模擬，量測的接合墊533約1.8 mm乘以約85微米。接合線被呈現為具有25微米直徑、5x10⁷ Siemens導電率、延伸在約500微米的間隙上並上升至放大器晶粒上方約150微米的最大高度。將EM模擬結果使用在對於杜赫放大器400的電路模型中，並未明顯改變頻率響應曲線620。Additional EM simulations are performed to more accurately present the output bond pads 533 of the main amplifier 132 and the peaking amplifier 138, and perform circuit simulations to present the bond wires 520 that are connected to the bond pads 533. For EM simulations, the measured bond pads 533 were approximately 1.8 mm multiplied by approximately 85 microns. The bond wires were presented as having a 25 micron diameter, 5x10 ⁷ Siemens conductivity, extending over a gap of about 500 microns and rising to a maximum height of about 150 microns above the amplifier die. Using the EM simulation results in the circuit model for the Duch amplifier 400 does not significantly change the frequency response curve 620.

在實際裝置中，阻抗反相器410輸出處的阻抗，可需要被匹配至負載的阻抗（例如50歐姆）。為了進一步估算杜赫放大器400的性能，將輸出阻抗匹配元件560加入電路，並執行模擬以處理所加入的元件。對於這些模擬，使用第 7 圖 繪製的輸出阻抗匹配元件560，但所繪製的元件僅為輸出阻抗匹配元件的一個範例，且發明並不僅受限於此配置。可對其他實施例中的輸出阻抗匹配元件使用其他具體實施例。In an actual device, the impedance at the output of impedance inverter 410 may require an impedance (eg, 50 ohms) that is matched to the load. To further estimate the performance of the Duch amplifier 400, an output impedance matching component 560 is added to the circuit and a simulation is performed to process the added components. For these simulations, using the drawings of the seventh output impedance elements 560, but only one element of the drawn example of output impedance matching element, and the invention is not limited to this configuration. Other embodiments may be used with the output impedance matching elements of other embodiments.

根據一些具體實施例，輸出接合線550可被接合至輸出阻抗匹配元件560的輸出帶線710。並聯電容器712、714可連接在輸出帶線710與墊720之間，墊720被使用通孔與並聯導體730連接至下層接地導體。輸出電容器718可連接在輸出帶線710與輸出接合墊750之間。對於模擬，輸出接合墊750可被由50歐姆電阻性通孔並聯至地，以模擬負載。輸出帶線710的長度與寬度、並聯電容器712、714的值、以及輸出電容器718的值，可被選定以將來自結合節點的阻抗匹配至負載平面570處的阻抗。According to some embodiments, the output bond wires 550 can be bonded to the output strip line 710 of the output impedance matching component 560. Parallel capacitors 712, 714 can be connected between output strip line 710 and pad 720, which is connected to the lower ground conductor using vias and parallel conductors 730. Output capacitor 718 can be coupled between output strip line 710 and output bond pad 750. For the simulation, the output bond pad 750 can be paralleled to ground by a 50 ohm resistive via to simulate the load. The length and width of the output strip line 710, the values of the shunt capacitors 712, 714, and the value of the output capacitor 718 can be selected to match the impedance from the bonding node to the impedance at the load plane 570.

包含如第 7 圖 設置的輸出阻抗匹配元件560的放大器性能模擬的結果，繪製於第 6 圖 中為頻率響應曲線630。對於此模擬，結合節點處的阻抗（約11.45歐姆）被匹配至約50歐姆的負載阻抗。在EM模擬中，帶線710量測為長度約1.4 mm且寬度約350微米，且或者使用了與傳導帶線510所使用的相同的電磁性質。並聯電容器712、714被模型化為每一者具有電容值0.75 pF的表面安裝裝置（SMD）。並聯電容器與傳導通孔730的結合每一者的電阻值為0.15歐姆且電感值為0.3 nH。輸出電容器718也被模型化為電容值為6.8 pF的SMD，此SMD具有結合電阻值0.15歐姆與電感值0.3 nH。The result of the amplifier performance simulation including the output impedance matching component 560 set as in Fig . 7 is plotted in Fig . 6 as the frequency response curve 630. For this simulation, the impedance at the junction node (approximately 11.45 ohms) was matched to a load impedance of approximately 50 ohms. In the EM simulation, the strip line 710 was measured to have a length of about 1.4 mm and a width of about 350 microns, and the same electromagnetic properties as used for the conductive strip line 510 were used. The shunt capacitors 712, 714 are modeled as surface mount devices (SMD) each having a capacitance value of 0.75 pF. The combination of the shunt capacitor and the conductive via 730 has a resistance value of 0.15 ohms and an inductance value of 0.3 nH. The output capacitor 718 is also modeled as an SMD having a capacitance value of 6.8 pF, which has a combined resistance value of 0.15 ohms and an inductance value of 0.3 nH.

包含輸出阻抗匹配元件560且亦包含輸出接合墊533的EM模擬的模擬結果，被繪製於第 6 圖 的頻率響應曲線中。對於所圖示說明的阻抗匹配元件，在約3.5 GHz的操作頻率下，放大器的RF部分頻寬減少至約200 MHz或約6%。即使在此減少之下，經修改的杜赫放大器的RF部分頻寬幾乎為習知杜赫放大器的頻寬的兩倍。此模擬的結果指示，若輸出阻抗匹配並未良好完成或具有窄的RF部分頻寬，則裝置的總和頻寬可受限於輸出阻抗匹配元件560。It includes an output impedance matching element 560 includes an output Qieyi engagement simulation results EM simulation pad 533, and is plotted in Figure 6 of the frequency response curve. For the illustrated impedance matching component, the RF portion bandwidth of the amplifier is reduced to about 200 MHz or about 6% at an operating frequency of about 3.5 GHz. Even with this reduction, the RF portion of the modified Duch amplifier has a bandwidth that is almost twice the bandwidth of a conventional Duch amplifier. The results of this simulation indicate that if the output impedance matching is not well done or has a narrow RF partial bandwidth, the sum bandwidth of the device can be limited to the output impedance matching component 560.

為了回復較廣的頻寬，可使用雙區輸出阻抗匹配元件800，如第 8 圖 所示。雙區阻抗匹配元件可包含加入的電感性帶線850，電感性帶線850連接至輸出接合墊750與電容性並聯結構814。帶線710的尺寸可被重新設計，以對第一區提供所需的電感值。In order to respond to a wide bandwidth, you can double the output impedance matching element region 800, as shown in FIG. 8. The dual zone impedance matching component can include an incorporated inductive stripline 850 that is coupled to the output bond pad 750 and the capacitive parallel structure 814. The size of the strip line 710 can be redesigned to provide the desired inductance value for the first zone.

一些具體實施例可包含包含電感性帶線840的電晶體偏壓部件，電感性帶線840連接至DC偏壓埠830，在DC偏壓埠830可施加用於偏壓放大器132、138中的電晶體的汲極的電壓。並聯電容器816可連接至偏壓埠830。在安裝於裝置中時，可將額外的電容器裝設在板的外部，在此板上阻抗匹配元件800被形成並設置為並聯於並聯電容器816。外部電容器的值可為2微法拉與50微法拉之間。Some embodiments may include a transistor biasing component including an inductive strip line 840 that is coupled to a DC bias voltage 830 that may be applied in the biasing amplifiers 132, 138 at a DC bias voltage 830 The voltage of the drain of the transistor. Parallel capacitor 816 can be coupled to bias 埠 830. When installed in the device, an additional capacitor can be mounted external to the board where the impedance matching component 800 is formed and arranged in parallel with the shunt capacitor 816. The value of the external capacitor can be between 2 microfarads and 50 microfarads.

對雙區阻抗匹配元件執行了進一步的模擬，其中電容值如下：C1 = C2 = 0.7 pF、C3 = 1.2 pF、且C4 = 6.8 pF。在3.5 GHz中心（或載波）頻率附近的RF頻率範圍內，雙區阻抗匹配元件800提供改良的阻抗匹配，相較於第 7 圖 繪製的單區。因此，這移除了相關聯於單區阻抗匹配元件560的頻寬瓶頸，並回復了阻抗反相器可用的RF部分頻寬。模擬顯示所產生的RF部分頻寬回復至約18%。A further simulation was performed on the two-zone impedance matching component with the capacitance values as follows: C1 = C2 = 0.7 pF, C3 = 1.2 pF, and C4 = 6.8 pF. In the RF frequency range around the center frequency of 3.5 GHz (or carrier), two-zone to provide improved impedance matching element 800, as compared to single-zone 7, plotted in FIG. Thus, this removes the bandwidth bottleneck associated with the single-region impedance matching component 560 and restores the RF portion bandwidth available to the impedance inverter. The simulation shows that the RF portion bandwidth produced is restored to approximately 18%.

在一些實施例中，阻抗反相器與負載之間可包含額外的阻抗匹配區。不論包含一區或更多區，輸出阻抗匹配元件較佳地轉換阻抗反相器410輸出處的阻抗，以在載波頻率處（在前述範例中為3.5 GHz，但可使用其他載波頻率）感興趣的頻寬上（例如80 MHz、100 MHz、200 MHz、400 MHz、或任何所需的在此範圍中的RF部分頻寬），匹配（或大致匹配）負載平面570處的阻抗。In some embodiments, an additional impedance matching region may be included between the impedance inverter and the load. Regardless of the inclusion of one or more zones, the output impedance matching component preferably converts the impedance at the output of the impedance inverter 410 to be of interest at the carrier frequency (3.5 GHz in the previous example, but other carrier frequencies may be used) The impedance at load plane 570 is matched (or roughly matched) over the bandwidth (eg, 80 MHz, 100 MHz, 200 MHz, 400 MHz, or any desired RF portion bandwidth in this range).

亦思及了用於操作使用前述設備的杜赫放大器的方法。在一些實施例中，用於操作杜赫放大器400的方法可包含以下步驟：將所接收訊號分成第一訊號與第二訊號，第二訊號具有相對於第一訊號的第一相位；以主放大器132放大第一訊號；以及以峰化放大器138放大第二訊號。方法具體實施例可進一步包含：將主放大器的輸出直接提供至阻抗反相器410的輸入，其中阻抗反相器包含整合分散式電感器；以及由阻抗反相器引入第二相位以補償第一相位。在一些實施例中，用於操作杜赫放大器的方法可進一步包含：將來自阻抗反相器410的輸出與來自峰化放大器138的輸出結合，以產生結合輸出；以及提供結合輸出至阻抗匹配元件560，阻抗匹配元件560將輸出阻抗匹配至負載的阻抗。負載阻抗的值可為50歐姆或約50歐姆。在一些實施例中，負載阻抗可為約25歐姆與約100歐姆之間的一值。杜赫放大器400的作業可進一步包含：提供結合輸出以由蜂巢式基地台傳輸。A method for operating a Duch amplifier using the aforementioned device is also contemplated. In some embodiments, the method for operating the Duch amplifier 400 can include the steps of: dividing the received signal into a first signal and a second signal, the second signal having a first phase relative to the first signal; 132 amplifying the first signal; and amplifying the second signal with the peaking amplifier 138. Method embodiments may further include: providing an output of the main amplifier directly to an input of the impedance inverter 410, wherein the impedance inverter includes an integrated decentralized inductor; and introducing a second phase by the impedance inverter to compensate for the first Phase. In some embodiments, the method for operating the Duch amplifier can further include combining the output from the impedance inverter 410 with the output from the peaking amplifier 138 to produce a combined output; and providing a combined output to the impedance matching component 560, impedance matching component 560 matches the output impedance to the impedance of the load. The value of the load impedance can be 50 ohms or about 50 ohms. In some embodiments, the load impedance can be a value between about 25 ohms and about 100 ohms. The operation of the Duch amplifier 400 can further include providing a combined output for transmission by the cellular base station.

結論in conclusion

用詞「約」與「大約」，在一些具體實施例中可用於表示目標尺寸的正負20%，在一些具體實施例中可用於表示目標尺寸的正負10%，在一些具體實施例中可用於表示目標尺寸的正負5%，且在一些具體實施例中可用於表示目標尺寸的正負2%。用詞「約」與「大約」，可包含目標尺寸。The terms "about" and "about" may be used in some embodiments to mean plus or minus 20% of the target size, and in some embodiments may be used to represent plus or minus 10% of the target size, and in some embodiments may be used in some embodiments. It represents plus or minus 5% of the target size and, in some embodiments, can be used to represent plus or minus 2% of the target size. Use the words "about" and "about" to include the target size.

本文所說明的科技，可被實施為方法，已說明了此方法的至少一些步驟。作為方法部分所執行的步驟，可由任何適合的方式排序。因此，可建置其中以不同於所描述的順序執行步驟的具體實施例，其可包括同時執行某些動作，即使在說明性具體實施例中被描述為循序動作。此外，在一些具體實施例中方法可包含比所說明的步驟更多的步驟，且在其他具體實施例中可包含比所說明的步驟更少的步驟。The techniques described herein can be implemented as methods, and at least some of the steps of the method have been described. The steps performed as part of the method may be ordered in any suitable manner. Thus, specific embodiments may be implemented in which the steps are performed in a different order than described, which may include performing some acts simultaneously, even if described in the illustrative embodiments as a sequential action. Moreover, in some embodiments the method may include more steps than those illustrated, and in other specific embodiments may include fewer steps than those illustrated.

在已說明了發明的至少一個說明性具體實施例之後，在本發明所屬技術領域中具有通常知識者將輕易思及各種變異、修改與改良。此種變異、修改與改良意為在本發明的精神與範圍之內。因此，前述說明目的僅為示例而不為限制。本發明僅受限於下列申請專利範圍所定義之範圍及其均等範圍。Having described at least one illustrative embodiment of the invention, various variations, modifications, and improvements will be readily apparent to those of ordinary skill in the art. Such variations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is intended to be illustrative only and not limiting. The invention is limited only by the scope of the following claims and their equivalents.

100‧‧‧杜赫放大器
110‧‧‧90度耦合器
122‧‧‧阻抗匹配部件
124‧‧‧阻抗匹配部件
132‧‧‧主放大器
138‧‧‧峰化放大器
142‧‧‧阻抗匹配部件
144‧‧‧阻抗匹配部件
150‧‧‧阻抗反相器
155‧‧‧結合節點
160‧‧‧輸出阻抗匹配元件
200‧‧‧低功率電路模型
310‧‧‧頻率響應曲線
320‧‧‧頻率響應曲線
330‧‧‧頻率響應曲線
410‧‧‧阻抗反相器
420‧‧‧輸出阻抗匹配元件
503‧‧‧基板
505‧‧‧基板
510‧‧‧傳導帶線
512‧‧‧帶線
520‧‧‧接合線
530‧‧‧汲極接合墊
531‧‧‧閘點接合墊
532‧‧‧閘極導體
533‧‧‧汲極接合墊
534‧‧‧汲極接點
536‧‧‧源極接點
540‧‧‧輸入接合線
550‧‧‧接合線
560‧‧‧輸出阻抗匹配元件
570‧‧‧負載平面
580‧‧‧電容器
610‧‧‧頻率響應曲線
620‧‧‧頻率響應曲線
630‧‧‧頻率響應曲線
710‧‧‧帶線
712‧‧‧並聯電容器
714‧‧‧並聯電容器
718‧‧‧輸出電容器
720‧‧‧墊
730‧‧‧並聯導體
750‧‧‧輸出接合墊100‧‧‧Duh amplifier
110‧‧90 degree coupler
122‧‧‧Imped matching parts
124‧‧‧Imped matching parts
132‧‧‧Main amplifier
138‧‧‧ Peaking amplifier
142‧‧‧ impedance matching components
144‧‧‧ impedance matching components
150‧‧‧ Impedance inverter
155‧‧‧Combined nodes
160‧‧‧ Output impedance matching components
200‧‧‧Low power circuit model
310‧‧‧frequency response curve
320‧‧‧frequency response curve
330‧‧‧ Frequency response curve
410‧‧‧ Impedance inverter
420‧‧‧ Output impedance matching components
503‧‧‧Substrate
505‧‧‧Substrate
510‧‧‧Transmission line
512‧‧‧With line
520‧‧‧bonding line
530‧‧‧汲pole mat
531‧‧‧Block joint pad
532‧‧ ‧ gate conductor
533‧‧‧汲pole mat
534‧‧‧汲pole contacts
536‧‧‧Source contact
540‧‧‧Input wire
550‧‧‧bonding line
560‧‧‧ Output impedance matching components
570‧‧‧Load plane
580‧‧‧ capacitor
610‧‧‧frequency response curve
620‧‧‧frequency response curve
630‧‧‧frequency response curve
710‧‧‧With line
712‧‧‧Shut capacitor
714‧‧‧Shut capacitor
718‧‧‧ output capacitor
720‧‧‧ pads
730‧‧‧Parallel conductor
750‧‧‧output mat

熟習技藝者將瞭解到，在此所說明的圖式，目的僅為示例說明。應瞭解到，在一些實例中，具體實施例的各種態樣可被誇大（或放大）圖示，以協助瞭解具體實施例。圖式並非必需按比例繪製，而是著重在圖示說明教示內容的原理上。在圖式中，各種圖式中類似的元件符號一般而言代表類似的特徵、功能上類似的元件及（或）結構上類似的元件。對於相關於微型製造電路的圖式，可僅圖示一個裝置及（或）電路以簡化圖式。實際上，可在基板的大面積上或整體基板上並行製造大量的裝置或電路。此外，所繪製的裝置或電路可被整合入較大的電路內。Those skilled in the art will appreciate that the figures illustrated herein are for illustrative purposes only. It will be appreciated that, in some instances, various aspects of the specific embodiments may be The drawings are not necessarily drawn to scale, but rather to illustrate the principles of the teachings. In the drawings, like reference characters in the various figures generally refer to the same features, the functionally similar elements, and/or structurally similar elements. For the drawings relating to the microfabrication circuit, only one device and/or circuit may be illustrated to simplify the drawing. In fact, a large number of devices or circuits can be fabricated in parallel over a large area of the substrate or on the entire substrate. Moreover, the devices or circuits drawn can be integrated into larger circuits.

下面的實施方式中，在參照圖式時，可使用如「頂」、「底」、「上」、「下」、「垂直」、「水平」等等的空間性參照。此種參照係用於教示目的，且因此並非意圖作為對於所實施裝置的絕對性的參照。所實施的裝置可被以任何適合的方式空間性地定向，這些定向可不同於圖式中顯示的定向。圖式並非意圖由任何方式限制本教示內容的範圍。In the following embodiments, spatial references such as "top", "bottom", "upper", "lower", "vertical", "horizontal", etc. may be used when referring to the drawings. Such references are for educational purposes and are therefore not intended as a reference to the absolute nature of the device being implemented. The devices implemented may be spatially oriented in any suitable manner, and these orientations may differ from the orientations shown in the figures. The illustrations are not intended to limit the scope of the teachings in any way.

第 1 圖 繪製杜赫放大器（Doherty Amplifier）的第一設置；Drawing FIG. 1 is provided a first Doherty amplifier (Doherty Amplifier); and

第 2 圖 繪製杜赫放大器的等效電路； A second drawing of the equivalent circuit of the Doherty amplifier;

第 3 圖 圖示根據一些具體實施例的對於不同杜赫放大器設計的不同的頻率響應曲線與RF部分頻寬； FIG 3 illustrates a number of different frequencies for the different response curve Doherty amplifier design bandwidth of the RF portion of the embodiment;

第 4 圖 圖示根據一些具體實施例的經修改杜赫放大器，其中在阻抗被匹配至負載之前，來自主放大器與峰化放大器的訊號被結合； FIG 4 illustrates a modification by the Doherty amplifier in accordance with some embodiments of particular embodiments, wherein prior to the load impedance are matched, the signal from the main amplifier and the peaking amplifier are combined;

第 5A 圖 繪製根據一些具體實施例的包含集總與整合分散式電感的阻抗反相器的元件； 5A according to some of the drawing and the total inductance element integrated distributed impedance inverter comprises a specific set of embodiments;

第 5B 圖 繪製根據一些具體實施例的功率放大器的元件；Drawing FIG. 5B elements in accordance with some embodiments of the particular embodiment of a power amplifier;

第 5C 圖 繪製根據一些具體實施例的包含集總與整合分散式電感與集總電容的阻抗反相器的元件； FIG. 5C draw a number of lumped elements integrated distributed inductance and lumped capacitance impedance inverter comprising the specific embodiment;

第 6 圖 指示不同的杜赫放大器設計的頻寬特性； FIG 6 indicates the bandwidth of the different characteristics of the Doherty amplifier design;

第 7 圖 繪製根據一些具體實施例的在經修改杜赫放大器輸出處的阻抗匹配元件；以及Drawing FIG. 7 Doherty amplifier output impedance matching element of some embodiments in accordance with the modified; and

第 8 圖 繪製根據一些具體實施例的在經修改杜赫放大器輸出處的雙區阻抗匹配元件。Drawing FIG. 8 according to some embodiments of the modified two-zone Doherty amplifier output impedance matching element.

連同圖式來閱讀下面的實施方式，將可更顯然明瞭所圖示說明之具體實施例的特徵與優點。The features and advantages of the specific embodiments illustrated are apparent from the accompanying drawings.

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Claims (17)

一種用於放大訊號的方法，包含以下步驟： 將一所接收的訊號分成一第一訊號與一第二訊號，該第二訊號相對於該第一訊號具有一第一相位； 以一主放大器放大該第一訊號； 以一峰化放大器放大該第二訊號； 將來自該主放大器的一輸出直接提供至一阻抗反相器的一輸入，其中該阻抗反相器包含一整合分散式電感器；以及 由該阻抗反相器引入一第二相位，該第二相位補償該第一相位。A method for amplifying a signal, comprising the steps of: dividing a received signal into a first signal and a second signal, the second signal having a first phase relative to the first signal; and amplifying by a main amplifier The first signal; amplifying the second signal with a peaking amplifier; supplying an output from the main amplifier directly to an input of an impedance inverter, wherein the impedance inverter comprises an integrated distributed inductor; A second phase is introduced by the impedance inverter, the second phase compensating for the first phase. 如請求項1所述之方法，其中該第二相位不超過95度。The method of claim 1, wherein the second phase does not exceed 95 degrees. 如請求項1所述之方法，該方法進一步包含以下步驟： 結合來自該阻抗反相器的一輸出與來自該峰化放大器的一輸出，以產生一經結合輸出；以及 提供該經結合輸出至一阻抗匹配元件。The method of claim 1, the method further comprising the steps of: combining an output from the impedance inverter with an output from the peaking amplifier to generate a combined output; and providing the combined output to a Impedance matching component. 如請求項1至3之任一項所述之方法，其中該結合步驟係於該峰化放大器的一汲極接合墊處完成。The method of any of claims 1 to 3, wherein the bonding step is performed at a drain bond pad of the peaking amplifier. 如請求項1至3之任一項所述之方法，其中該整合分散式電感器包含整合在一基板上的一傳導帶線，該傳導帶線具有一寬度與一長度。The method of any one of claims 1 to 3, wherein the integrated distributed inductor comprises a conductive strip line integrated on a substrate, the conductive strip line having a width and a length. 如請求項5所述之方法，其中該阻抗反相器進一步包含接合線或傳導性互連結構，該等接合線或傳導性互連結構連接在該傳導帶線與該主放大器及該峰化放大器的輸出之間。The method of claim 5, wherein the impedance inverter further comprises a bond wire or a conductive interconnect structure connected to the conductive strip line and the main amplifier and the peaking Between the outputs of the amplifiers. 如請求項5所述之方法，其中該寬度位於約100微米與約1000微米之間。The method of claim 5 wherein the width is between about 100 microns and about 1000 microns. 如請求項5所述之方法，其中該長度位於約2毫米與約6毫米之間。The method of claim 5, wherein the length is between about 2 mm and about 6 mm. 如請求項5所述之方法，其中該主放大器與峰化放大器被整合在與該傳導帶線相同的一基板上。The method of claim 5, wherein the main amplifier and the peaking amplifier are integrated on a same substrate as the conductive strip line. 如請求項5所述之方法，其中該基板包含一高頻層壓結構。The method of claim 5, wherein the substrate comprises a high frequency laminate structure. 如請求項1至3之任一項所述之方法，該方法進一步包含以下步驟：由該阻抗匹配元件將一阻抗匹配至約25歐姆與約100歐姆之間的一值。The method of any of claims 1 to 3, further comprising the step of matching an impedance by the impedance matching element to a value between about 25 ohms and about 100 ohms. 如請求項1至3之任一項所述之方法，其中該所接收的訊號位於約500 MHz與約6 GHz之間的一頻率。The method of any one of claims 1 to 3, wherein the received signal is at a frequency between about 500 MHz and about 6 GHz. 如請求項1至3之任一項所述之方法，其中用於放大該等訊號的一RF部分頻寬，係位於約6 %與約18 %之間。The method of any one of claims 1 to 3, wherein an RF portion bandwidth for amplifying the signals is between about 6% and about 18%. 如請求項1至3之任一項所述之方法，其中該經結合輸出的一功率位準係位於約20瓦與約100瓦之間。The method of any of claims 1 to 3, wherein the combined output power level is between about 20 watts and about 100 watts. 如請求項1至3之任一項所述之方法，該方法進一步包含以下步驟：提供該經結合輸出，以由一蜂巢式基地台傳輸。The method of any of claims 1 to 3, the method further comprising the step of providing the combined output for transmission by a cellular base station. 如請求項1至3之任一項所述之方法，該方法進一步包含以下步驟：在該主放大器與該阻抗反相器之間，不提供將把該主放大器的一輸出阻抗匹配至50歐姆的阻抗匹配元件。The method of any one of claims 1 to 3, further comprising the step of: between the main amplifier and the impedance inverter, not providing an output impedance of the main amplifier to be matched to 50 ohms Impedance matching component. 如請求項1至3之任一項所述之方法，其中該等放大步驟之一者或兩者係由氮化鎵電晶體執行。The method of any one of claims 1 to 3, wherein one or both of the amplification steps are performed by a gallium nitride transistor.