TW201833996A - 在鰭式場效電晶體(finfet)裝置上形成共形磊晶半導體覆層材料之方法 - Google Patents
在鰭式場效電晶體(finfet)裝置上形成共形磊晶半導體覆層材料之方法 Download PDFInfo
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- TW201833996A TW201833996A TW106143536A TW106143536A TW201833996A TW 201833996 A TW201833996 A TW 201833996A TW 106143536 A TW106143536 A TW 106143536A TW 106143536 A TW106143536 A TW 106143536A TW 201833996 A TW201833996 A TW 201833996A
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- 239000000463 material Substances 0.000 title claims abstract description 28
- 238000005253 cladding Methods 0.000 title abstract description 11
- 239000004065 semiconductor Substances 0.000 title abstract description 5
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- YMEKHGLPEFBQCR-UHFFFAOYSA-N 2,2,3,3,5,5-hexachloro-1,4-dioxane Chemical compound ClC1(OC(C(OC1)(Cl)Cl)(Cl)Cl)Cl YMEKHGLPEFBQCR-UHFFFAOYSA-N 0.000 claims 3
- HEDRZPFGACZZDS-UHFFFAOYSA-N Chloroform Chemical compound ClC(Cl)Cl HEDRZPFGACZZDS-UHFFFAOYSA-N 0.000 claims 3
- 229960001701 chloroform Drugs 0.000 claims 3
- IREVRWRNACELSM-UHFFFAOYSA-J ruthenium(4+);tetrachloride Chemical compound Cl[Ru](Cl)(Cl)Cl IREVRWRNACELSM-UHFFFAOYSA-J 0.000 claims 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 abstract 1
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- 229910052735 hafnium Inorganic materials 0.000 description 6
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 6
- 229910052715 tantalum Inorganic materials 0.000 description 5
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- 238000005530 etching Methods 0.000 description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- IEXRMSFAVATTJX-UHFFFAOYSA-N tetrachlorogermane Chemical compound Cl[Ge](Cl)(Cl)Cl IEXRMSFAVATTJX-UHFFFAOYSA-N 0.000 description 1
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- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
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Abstract
本揭露內容大致關於具有共形半導體覆層材料的FINFET裝置與其之形成方法。覆層材料係矽鍺磊晶材料。能夠沉積覆層材料至小於傳統沉積/蝕刻技術所形成之覆層材料的厚度。
Description
本揭露內容的實施例大致關於具有共形半導體覆層材料的鰭式場效電晶體(FINFET)裝置與其之形成方法。
將高移動性應變通道併入鰭-基電晶體中提供期望的應力進入裝置的通道區域中。然而,形成應力材料至裝置的鰭部上的傳統技術會造成裝置在低於設計的水平或更糟情況下作用,這會造成裝置因為應力材料與鰭部不小心的合併(這可造成電短路)而報廢。
需要的是在FINFET裝置上形成共形磊晶半導體覆層材料的方法。
在一個實施例中,形成應變通道層的方法包括暴露基板上的一個或多個三維特徵至含矽前驅物與包含氯的含鍺前驅物,以在一個或多個特徵的橫切表面上形成磊晶矽-鍺通道層,橫切表面具有不同的晶體取向。
在另一個實施例中,形成應變通道層的方法包括暴露基板上的一個或多個垂直鰭部至含矽前驅物與含鍺前驅物,以在一個或多個垂直鰭部的暴露水平與垂直表面上選擇性地形成磊晶矽-鍺應變通道層,暴露水平與垂直表面具有選自<100>與<110>面的不同晶體取向,其中含鍺前驅物包括氯。
在另一個實施例中,裝置包括基板,基板具有複數個垂直鰭部自基板的表面延伸;與磊晶矽-鍺應變通道層,共形地形成於複數個垂直鰭部的表面的水平與垂直表面上,水平與垂直表面具有不同的晶體取向,其中磊晶矽-鍺應變通道層具有均勻鍺濃度與小於五奈米的厚度。
本揭露內容大致關於具有共形半導體覆層材料的FINFET裝置與其之形成方法。覆層材料係矽鍺磊晶材料。能夠沉積覆層材料至小於傳統沉積/蝕刻技術所形成之覆層材料的厚度,同時仍維持期望的均勻性。
第1A-1C圖係根據揭露內容實施例的基板在FINFET形成操作過程中的示意橫剖面圖。第1A圖描繪具有垂直鰭部102與淺溝槽隔離(STI)層104於基板100中的基板100。基板100可為塊矽基板、絕緣體上矽(SOI)基板、鍺基板等等。垂直鰭部102自基板100的上表面垂直地延伸。藉由造成垂直鰭部102的基板100的上表面的遮罩與蝕刻來形成垂直鰭部102。然而,亦可考慮其他形成方法。垂直鰭部102包括透過垂直鰭部102的植入而引進的通道摻雜。STI 104配置在基板100的上表面上且在垂直鰭部102之間。STI 104促進基板100上形成之裝置之間的電隔離。如第1A圖中所描繪,垂直鰭部102延伸高於STI 104的上表面一段距離。在一個實例中,STI 104係由二氧化矽、氮化矽或氮氧化矽的一者或多者所形成。然而,可考慮其他介電材料。
在垂直鰭部102與STI 104形成後,如第1B圖中所示,應變通道層106形成於垂直鰭部102的表面上。應變通道層106在磊晶沉積製程過程中形成,並因此具有對應於垂直鰭部102的晶體取向的晶體取向。在一個實例中,應變通道層106係磊晶矽鍺(Si(1-x)
Gex
)。應變通道層106的存在引發期望的應力進入裝置的通道區域、裝置的源極/汲極區域或兩者。在一個實例中,應變通道層106作為接合材料。
藉由暴露垂直鰭部102至包括一個或多個鍺前驅物與一個或多個矽前驅物的氣體混合物來形成應變通道層106。應變通道層106中的Ge部分在Si(1-x)
Gex
的範圍可為約5%至約75%,例如Si0.95
Ge0.05
至Si0.25
Ge0.75
。一個或多個鍺前驅物可包括四氯化鍺(GeCl4
)、氯鍺烷(GeH3
Cl)、二氯鍺烷(GeH2
Cl2
)、三氯鍺烷(GeHCl3
)、六氯二鍺烷(Ge2
Cl6
)、八氯三鍺烷(Ge3
Cl8
)。一個或多個矽前驅物可包括矽烷(SiH4
)、二矽烷(Si2
H6
)、三矽烷(Si3
H8
)、四矽烷(Si4
H10
)、五矽烷(Si5
H12
)。可利用包括雙原子氫或雙原子氮的選擇性載氣。值得注意的是可考慮其他鍺與矽前驅物。在一個實例中,基板100被維持在約560℃至約700℃範圍中的溫度下。處理腔室中的壓力被維持在約5托至約80托的壓力下。各自在約100 sccm至約1200 sccm的流動速率下提供矽前驅物與鍺前驅物,然而,取決於基板尺寸而可考慮其他流動速率。可利用雙原子氮或雙原子氫的載氣來促進鍺前驅物與矽前驅物的流動。
在垂直鰭部的一個或多個垂直與水平表面上共形地沉積磊晶矽-鍺應變通道層的特定實例中,在約15 sccm至約45sccm的流動速率下提供矽前驅物,並在約100 sccm至約1000 sccm的流動速率下提供鍺前驅物。在上述實例中,矽前驅物與鍺前驅物的比例係約1:2至約1:67。
將上方具有垂直鰭部102的基板100在循環製程(例如,原子層沉積)中暴露至鍺前驅物與矽前驅物或同時地(例如,化學氣相沉積)暴露至鍺前驅物與矽前驅物。在一個實例中,在低壓化學氣相沉積製程(例如,約5托至約80托下)中形成應變通道層106。額外或替代地,離子化或自由基化矽前驅物與/或鍺前驅物以促進材料沉積於垂直鰭部102上。在一個實例中,應變通道層106可被沉積至小於10奈米的厚度,諸如約小於5奈米或者約2奈米或更低。在上述實例中,一旦應變通道層106的厚度與電子波函數的德布羅意(de Broglie)波長大小相同時可發現量子侷限。當材料被沉積至上述厚度時,沉積材料的電子與光學性質偏離於塊材料的那些性質。優點可包括諸如汲極電流的提高、較低的功率消耗與/或較低的電阻器開啟閥值電壓。
在上述實例中,垂直鰭部102作為允許應變通道層106生長於垂直鰭部102上的結構性支撐。由於垂直鰭部102提供結構性支撐,可如上述形成具有相對較小厚度的應變通道層106,藉此透過藉由降低接合寬度而得的較大電流流動來改善裝置效能。
傳統磊晶生成矽鍺被形成帶有歸因於矽鍺的結晶取向(即,面心立方)以及HCl的使用的小面,HCl通常用於FINFET裝置中的傳統矽鍺形成中。包含小面通常造成非均勻的膜沉積。然而,相較於傳統方式,形成的應變通道層106具有顯著降低的小面數目。此外,相對於傳統矽鍺層,應變通道層106亦具有處處均勻的矽與鍺濃度。在傳統矽鍺層中,相較於垂直(例如,<110>)面,鍺濃度通常在水平(例如,<100>)面中較高。此外,材料的生成速率在<100>與<110>面上顯著不同,這造成非均勻厚度。應變通道層106並未遭受與傳統層上相同的濃度與/或厚度非均勻性。
可藉由利用含氯的鍺前驅物來達成本揭露內容的優點。含氯的鍺前驅物(例如,上方描述的那些前驅物)係選擇性抵制氧化物與氮化物材料。因此,利用上述的處理化學物,應變通道層106被形成在垂直鰭部102的暴露表面上,但矽鍺材料通常不沉積於STI 104的暴露表面上。再者,本文所述的處理化學物促進橫跨大範圍製程條件<100>與<110>面兩者上的均勻生長速率。
在一個實例中,可如上述般生成應變通道層106。在約650℃與約10托下,<100>面的生長速率係每分鐘約162埃,而鍺濃度係約27原子百分比。在<110>面中,生長速率係每分鐘約165埃,而鍺濃度係約26原子百分比。在另一個實例中,在約600℃與約15托下,<100>面中的生長速率係每分鐘約87埃,而鍺濃度係約30百分比。在<110>面中,生長速率係每分鐘約92埃,而鍺濃度係約28百分比。在一個實例中,<100>面與<110>面中的生長速率在彼此的3百分比內,諸如彼此的2百分比內、或彼此的1.5百分比內或者彼此的1.0百分比內。
如第1C圖中所描繪,在應變通道層106形成後,在應變通道層上形成閘極介電質108與閘極材料110。閘極介電質108位在應變通道層106與閘極材料110之間以促進兩者之間的電隔離。閘極介電質108可由氧化矽、氮化矽、氧化鉿、氮氧化鉿矽與/或氧化鉿矽所形成。閘極材料110可由聚矽、非晶矽、鍺、矽鍺、金屬與/或金屬合金所形成。
第2A-2D圖描繪根據揭露內容的一個實施例形成在基板100上的應變通道層106的TEM照片。應變通道層106共形地形成於垂直鰭部102上。應變通道層106係具有處處均勻厚度與濃度的磊晶矽鍺層。此外,由於應變通道層106選擇性沉積於垂直鰭部102的暴露表面上而不沉積於STI 104的暴露表面上,自STI移除材料的蝕刻操作便非為必需的。因此,比起傳統方式應變通道層106的形成更有效率。
儘管描繪FINFET的一個實例,但亦可考慮其他裝置。舉例而言,本文的實施例可用於雙閘極、三閘極與相似的FINFET結構以及其他特徵。亦可考慮在FINFET以外的裝置中使用。再者,儘管參照應變通道層來描述本文的實施例,亦可考慮參照非應變通道層來應用所揭露的實施例。
揭露內容的優點包括比起傳統應變閘極通道更均勻地且較小規模地沉積之應變閘極通道的應用。此外,本文所述之應變閘極通道的形成製程利用選擇性沉積製程,藉此藉由排除某些遮罩與蝕刻製程來降低製程時間。
儘管上文針對本揭露內容的實施例,但可在不悖離本揭露內容的基本範圍下設計出揭露內容的其他與進一步實施例,且本揭露內容的範圍係由後續的申請專利範圍所決定。
100‧‧‧基板
102‧‧‧垂直鰭部
104‧‧‧STI
106‧‧‧應變通道層
108 ‧‧‧閘極介電質
110 ‧‧‧閘極材料
為了可詳細地理解本揭露內容的上方記載特徵,可藉由參照實施例(某些描繪於附圖中)而取得揭露內容更特定的描述內容(簡短概述於上)。然而,值得注意的是附圖僅描繪示範性實施例並因此不被視為限制範圍,因為此揭露內容可允許其他等效性實施例。
第1A-1C圖係根據揭露內容實施例的基板在FINFET形成操作過程中的示意橫剖面圖。
第2A-2D圖描繪根據揭露內容實施例的第1B圖的應變通道層的TEM照片。
為了促進理解,已經儘可能利用相同的元件符號來標示圖式中共有的相同元件。預期一個實施例的元件與特徵可有利地併入其他實施例而毋需進一步列舉。
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Claims (20)
- 一種形成一應變通道層的方法,包括以下步驟: 暴露一基板上的一個或多個三維特徵至一含矽前驅物與包含氯的含鍺前驅物,以形成一磊晶矽-鍺通道層於該一個或多個三維特徵的數個橫切表面上,該些橫切表面具有不同的晶體取向。
- 如請求項1所述之方法,其中該基板在暴露過程中被維持在約560℃至約700℃的一範圍中的一溫度下。
- 如請求項1所述之方法,其中該含鍺前驅物包括四氯化鍺(GeCl4 )、氯鍺烷(GeH3 Cl)、二氯鍺烷(GeH2 Cl2 )、三氯鍺烷(GeHCl3 )、六氯二鍺烷(Ge2 Cl6 )與八氯三鍺烷(Ge3 Cl8 )的一者或多者。
- 如請求項1所述之方法,其中該含矽前驅物包括矽烷(SiH4 )、二矽烷(Si2 H6 )、三矽烷(Si3 H8 )與四矽烷(Si4 H10 )的一者或多者。
- 如請求項1所述之方法,其中該含鍺前驅物包括四氯化鍺(GeCl4 )、氯鍺烷(GeH3 Cl)、二氯鍺烷(GeH2 Cl2 )、三氯鍺烷(GeHCl3 )、六氯二鍺烷(Ge2 Cl6 )與八氯三鍺烷(Ge3 Cl8 )的一者或多者,其中該含矽前驅物包括矽烷(SiH4 )、二矽烷(Si2 H6 )、三矽烷(Si3 H8 )與四矽烷(Si4 H10 )的一者或多者。
- 如請求項1所述之方法,其中該磊晶矽-鍺應變通道層被共形地沉積在該一個或多個垂直鰭部上。
- 如請求項1所述之方法,其中該基板進一步包括一淺溝槽隔離層,該淺溝槽隔離層包括一氧化物或一氮化物材料,且其中該磊晶矽-鍺應變通道層選擇性地沉積於該些垂直鰭部上。
- 如請求項7所述之方法,其中該些垂直鰭部包括矽。
- 如請求項1所述之方法,其中該磊晶矽-鍺應變通道層在<100>與<110>面上具有大約相同的沉積速率。
- 如請求項1所述之方法,其中一FINFET裝置形成於該基板上。
- 一種形成一應變通道層的方法,包括以下步驟: 暴露一基板上的一個或多個垂直鰭部至一含矽前驅物與一含鍺前驅物,以選擇性地形成一磊晶矽-鍺應變通道層於該一個或多個垂直鰭部的數個暴露水平與垂直表面上,該些暴露水平與垂直表面具有選自<100>與<110>面的不同晶體取向,其中該含鍺前驅物包括氯。
- 如請求項11所述之方法,其中該含鍺前驅物包括四氯化鍺(GeCl4 )、氯鍺烷(GeH3 Cl)、二氯鍺烷(GeH2 Cl2 )、三氯鍺烷(GeHCl3 )、六氯二鍺烷(Ge2 Cl6 )與八氯三鍺烷(Ge3 Cl8 )的一者或多者。
- 如請求項11所述之方法,其中該含矽前驅物包括矽烷(SiH4 )、二矽烷(Si2 H6 )、三矽烷(Si3 H8 )與四矽烷(Si4 H10 )的一者或多者。
- 如請求項12所述之方法,其中該含矽前驅物包括矽烷(SiH4 )、二矽烷(Si2 H6 )、三矽烷(Si3 H8 )與四矽烷(Si4 H10 )的一者或多者。
- 如請求項11所述之方法,其中該磊晶矽-鍺應變通道層被共形地沉積在該一個或多個垂直鰭部上。
- 如請求項11所述之方法,其中該些垂直鰭部包括矽。
- 如請求項11所述之方法,其中該磊晶矽-鍺應變通道層在<100>與<110>面上具有大約相同的沉積速率。
- 如請求項11所述之方法,進一步包括以下步驟:形成一FINFET裝置於該基板上。
- 一種裝置,包括: 一基板,具有自該基板的一表面延伸的複數個垂直鰭部;及 一磊晶矽-鍺應變通道層,共形地形成於該複數個垂直鰭部的數個水平與垂直表面上,該些水平與垂直表面具有不同的晶體取向,其中該磊晶矽-鍺應變通道層具有一均勻鍺濃度與一小於五奈米的厚度。
- 如請求項19所述之裝置,其中該磊晶矽-鍺應變通道層具有一小於兩奈米的厚度。
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2017
- 2017-12-12 US US15/839,024 patent/US11011635B2/en active Active
- 2017-12-12 TW TW106143536A patent/TWI748021B/zh active
- 2017-12-12 WO PCT/US2017/065791 patent/WO2018111859A1/en active Application Filing
- 2017-12-12 KR KR1020197018520A patent/KR102427152B1/ko active IP Right Grant
- 2017-12-12 TW TW111147542A patent/TW202314792A/zh unknown
- 2017-12-12 TW TW110127685A patent/TWI812984B/zh active
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TW202314792A (zh) | 2023-04-01 |
TW202143294A (zh) | 2021-11-16 |
WO2018111859A1 (en) | 2018-06-21 |
US20180166570A1 (en) | 2018-06-14 |
TWI748021B (zh) | 2021-12-01 |
KR20190086752A (ko) | 2019-07-23 |
KR102427152B1 (ko) | 2022-07-28 |
US11011635B2 (en) | 2021-05-18 |
TWI812984B (zh) | 2023-08-21 |
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