TW201822200A - Memory apparatus - Google Patents

Memory apparatus Download PDF

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Publication number
TW201822200A
TW201822200A TW105140789A TW105140789A TW201822200A TW 201822200 A TW201822200 A TW 201822200A TW 105140789 A TW105140789 A TW 105140789A TW 105140789 A TW105140789 A TW 105140789A TW 201822200 A TW201822200 A TW 201822200A
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current
circuit
coupled
signal
power supply
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TW105140789A
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Chinese (zh)
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TWI615854B (en
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宋宏達
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力晶積成電子製造股份有限公司
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Priority to CN201611204597.7A priority patent/CN108231117B/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

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Abstract

A memory apparatus is provided. A current adjustment circuit controls a reference current generation circuit generating a reference current corresponding to a power voltage according to the power voltage, so as to make a sensing amplifier generate a sensing signal corresponding to the power voltage. A processing circuit determines a state of a memory cell unit according to the sensing signal.

Description

記憶體裝置Memory device

本發明是有關於一種電子裝置，且特別是有關於一種記憶體裝置。The present invention relates to an electronic device, and more particularly to a memory device.

在各種記憶體產品中，非揮發性記憶體(non-volatile記憶體)允許多次的資料程式化(programming)、讀取(reading)以及抹除(erasing)操作，且甚至在記憶體的電源中斷之後還能夠保存儲存於其中的資料。由於這些優點，非揮發性記憶體已成為個人電腦與電子設備中廣泛使用的記憶體。一般來說，非揮發性記憶體的操作需要外加電源電壓來進行，而對應不同的電源電壓，對於程式化以及抹除等記憶體狀態作讀取操作時所對應的記憶胞電流亦會不同。如此一來，當電源電壓出現變化時，感測放大器依據記憶胞電流及參考電流所產生的感測信號亦會隨電源電壓的波動而產生變化，然而記憶胞電流與參考電流對於電源電壓變化而產生的變動並不相同，如此將可能出現記憶胞的記憶體狀態誤判的情形。Among various memory products, non-volatile memory (non-volatile memory) allows multiple data programming, reading, and erasing operations, and even in the power supply of the memory The data stored in it can be saved after the interruption. Because of these advantages, non-volatile memory has become a widely used memory in personal computers and electronic devices. In general, the operation of non-volatile memory requires an external power supply voltage, and corresponding to different power supply voltages, the corresponding memory cell currents for reading operations on memory states such as programming and erasing will also be different. In this way, when the power supply voltage changes, the sensing signal generated by the sense amplifier based on the memory cell current and the reference current also changes with the fluctuation of the power supply voltage. However, the memory cell current and the reference current change with the power supply voltage. The resulting changes are not the same, so there may be cases where the memory state of the memory cell is misjudged.

本發明提供一種記憶體裝置，可避免因電源電壓的改變而產生對記憶胞的記憶體狀態誤判的情形。The invention provides a memory device, which can avoid the situation that the memory state of the memory cell is misjudged due to the change of the power supply voltage.

本發明的記憶體裝置包括記憶體陣列、感測放大器、參考電流產生電路、電流調整電路以及處理電路。記憶體陣列包括至少一記憶胞單元，其耦接電源電壓，依據字元線選擇信號、位元線選擇信號以及控制信號輸出記憶胞電流。參考電流產生電路耦接電源電壓，產生參考電流。感測放大器耦接記憶體陣列與參考電流產生電路，依據記憶胞電流及參考電流產生感測信號。感測放大器包括電流比較電路。電流比較電路耦接記憶胞單元與參考電流產生電路，比較記憶胞電流與參考電流，以產生感測信號。電流調整電路耦接電源電壓與參考電流產生電路，依據電源電壓控制參考電流產生電路產生對應電源電壓的參考電流。處理電路耦接電流比較電路，依據感測信號判斷記憶胞單元的記憶體狀態。The memory device of the present invention includes a memory array, a sense amplifier, a reference current generation circuit, a current adjustment circuit, and a processing circuit. The memory array includes at least one memory cell unit, which is coupled to a power voltage and outputs a memory cell current according to a word line selection signal, a bit line selection signal, and a control signal. The reference current generating circuit is coupled to the power supply voltage to generate a reference current. The sense amplifier is coupled to the memory array and the reference current generating circuit, and generates a sensing signal according to the memory cell current and the reference current. The sense amplifier includes a current comparison circuit. The current comparison circuit is coupled to the memory cell unit and the reference current generating circuit, and compares the memory cell current and the reference current to generate a sensing signal. The current adjustment circuit is coupled to the power supply voltage and the reference current generation circuit, and controls the reference current generation circuit to generate a reference current corresponding to the power supply voltage according to the power supply voltage. The processing circuit is coupled to the current comparison circuit, and judges the memory state of the memory cell unit according to the sensing signal.

在本發明的一實施例中，上述的電流比較電路包括第一電流鏡電路以及第二電流鏡電路。第一電流鏡電路的輸入端與輸出端分別耦接記憶體胞單元以及電流比較電路的輸出端，依據記憶胞電流於第一電流鏡電路的輸出端產生第一電流鏡信號。第二電流鏡電路的輸入端與輸出端分別耦接參考電流產生電路以及電流比較電路的輸出端，依據參考電流產生第二電流鏡信號，根據第一電流鏡信號與第二電流鏡信號反應電流比較電路的偏壓狀態，而於電流比較電路的輸出端產生感測信號。In an embodiment of the present invention, the current comparison circuit includes a first current mirror circuit and a second current mirror circuit. The input terminal and the output terminal of the first current mirror circuit are respectively coupled to the memory cell unit and the output terminal of the current comparison circuit, and a first current mirror signal is generated at the output terminal of the first current mirror circuit according to the memory cell current. The input terminal and the output terminal of the second current mirror circuit are respectively coupled to the output terminals of the reference current generating circuit and the current comparison circuit, and generate a second current mirror signal according to the reference current, and react to the current according to the first current mirror signal and the second current mirror signal. The bias state of the comparison circuit generates a sensing signal at the output of the current comparison circuit.

在本發明的一實施例中，上述的參考電流產生電路包括多個電流源，其並聯於第二電流鏡電路的輸入端與接地之間，分別受控於電流調整電路產生電流，以於第二電流鏡電路的輸入端產生對應電源電壓的參考電流。In an embodiment of the present invention, the above-mentioned reference current generating circuit includes a plurality of current sources, which are connected in parallel between the input terminal of the second current mirror circuit and the ground, and are respectively controlled by the current adjustment circuit to generate a current. The input terminal of the two current mirror circuit generates a reference current corresponding to the power supply voltage.

在本發明的一實施例中，上述的各個電流源包括電阻與開關。電阻耦接第二電流鏡電路的輸入端。開關耦接於電阻與接地之間，開關受控於電流調整電路改變其導通狀態，以於第二電流鏡電路的輸入端產生對應電源電壓的參考電流。In an embodiment of the present invention, each of the current sources includes a resistor and a switch. The resistor is coupled to the input terminal of the second current mirror circuit. The switch is coupled between the resistor and the ground. The switch is controlled by the current adjustment circuit to change its conducting state, so that the input terminal of the second current mirror circuit generates a reference current corresponding to the power supply voltage.

在本發明的一實施例中，上述的電流調整電路包括分壓電路、類比數位轉換電路以及第一編碼器。分壓電路耦接於電源電壓，分壓電源電壓以產生分壓電壓。類比數位轉換電路耦接分壓電路，將分壓電壓轉換為數位控制信號。第一編碼器耦接類比數位轉換電路與上述多個開關，依據數位控制信號產生開關控制信號，以控制上述多個開關的導通狀態，而於第二電流鏡電路的輸入端產生對應電源電壓的參考電流。In an embodiment of the present invention, the current adjusting circuit includes a voltage dividing circuit, an analog-to-digital conversion circuit, and a first encoder. The voltage dividing circuit is coupled to the power voltage, and divides the power voltage to generate a divided voltage. The analog digital conversion circuit is coupled to the voltage dividing circuit and converts the divided voltage into a digital control signal. The first encoder is coupled to the analog digital conversion circuit and the plurality of switches, and generates a switch control signal according to the digital control signal to control the conduction states of the plurality of switches, and generates a corresponding power supply voltage at the input end of the second current mirror circuit. Reference current.

在本發明的一實施例中，上述的分壓電路包括第一電阻以及第二電阻，第二電阻與第一電阻串接於電源電壓與接地之間，第一電阻與第二電阻的共同接點產生分壓電壓。In an embodiment of the present invention, the voltage dividing circuit includes a first resistor and a second resistor. The second resistor and the first resistor are connected in series between the power voltage and the ground. The first resistor and the second resistor are in common. The contact generates a divided voltage.

在本發明的一實施例中，上述的類比數位轉換電路包括多個分壓電阻、多個比較器以及第二編碼器。多個分壓電阻串接於參考電壓與接地之間，以產生多個子參考電壓。各個比較器的第一輸入端耦接分壓電壓，各個比較器的第二輸入端分別耦接對應的子參考電壓，以於比較器的輸出端產生熱碼(thermometer code)信號。第二編碼器耦接上述多個比較器，對熱碼信號進行編碼以產生數位控制信號。In an embodiment of the present invention, the analog-to-digital conversion circuit includes a plurality of voltage dividing resistors, a plurality of comparators, and a second encoder. A plurality of voltage dividing resistors are connected in series between the reference voltage and the ground to generate a plurality of sub-reference voltages. The first input terminal of each comparator is coupled to the divided voltage, and the second input terminal of each comparator is respectively coupled to the corresponding sub-reference voltage, so as to generate a thermometer code signal at the output terminal of the comparator. The second encoder is coupled to the plurality of comparators, and encodes the hot code signal to generate a digital control signal.

在本發明的一實施例中，上述的數位控制信號為二進碼(binary code)信號，開關控制信號為單一熱碼(one-hot code)信號。In one embodiment of the present invention, the digital control signal is a binary code signal, and the switch control signal is a one-hot code signal.

在本發明的一實施例中，上述的第一編碼器更儲存查找表，並依據查找表將熱碼信號轉換為單一熱碼信號。In an embodiment of the present invention, the first encoder further stores a lookup table, and converts the hot code signal into a single hot code signal according to the lookup table.

基於上述，本發明的實施例依據電源電壓控制參考電流產生電路產生對應電源電壓的較佳的參考電流，以使感測放大器產生對應電源電壓的感測信號，避免因電源電壓的改變而產生記憶胞的記憶體狀態誤判的情形。Based on the above, the embodiment of the present invention controls the reference current generating circuit to generate a better reference current corresponding to the power supply voltage according to the power supply voltage, so that the sense amplifier generates a sensing signal corresponding to the power supply voltage, and avoids generating memory due to a change in power supply voltage Misjudgment of the memory state of the cell.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

圖1是依照本發明的實施例的一種記憶體裝置的示意圖，請參照圖1。記憶體裝置包括記憶體陣列102、感測放大器SA1、參考電流產生電路104、電流調整電路108以及處理電路110，感測放大器SA1耦接記憶體陣列102、參考電流產生電路104與處理電路110。其中處理電路110可例如為中央處理單元，記憶體陣列102可例如為快閃記憶體陣列，然不以此為限，記憶體陣列102包括至少一記憶體胞單元112，其耦接電源電壓VDD，並依據字元線選擇信號SWL、位元線選擇信號SGD以及控制信號FWL輸出記憶胞電流IC1。參考電流產生電路104耦接電流比較電路106以及電流調整電路108。參考電流產生電路104可用以產生參考電流Iref。感測放大器SA1可依據記憶胞電流IC1以及參考電流Iref產生感測信號S1，進一步來說，感測放大電路SA1可包括電流比較電路106，電流比較電路106可比較記憶胞電流IC1與參考電流Iref，以產生感測信號S1，電流調整電路108可依據電源電壓VDD控制參考電流產生電路產生對應電源電壓VDD的參考電流Iref。FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention. Please refer to FIG. 1. The memory device includes a memory array 102, a sense amplifier SA1, a reference current generation circuit 104, a current adjustment circuit 108, and a processing circuit 110. The sense amplifier SA1 is coupled to the memory array 102, the reference current generation circuit 104, and the processing circuit 110. The processing circuit 110 may be, for example, a central processing unit, and the memory array 102 may be, for example, a flash memory array, but is not limited thereto. The memory array 102 includes at least one memory cell unit 112, which is coupled to the power supply voltage VDD. And output the memory cell current IC1 according to the word line selection signal SWL, the bit line selection signal SGD, and the control signal FWL. The reference current generation circuit 104 is coupled to the current comparison circuit 106 and the current adjustment circuit 108. The reference current generating circuit 104 can be used to generate a reference current Iref. The sense amplifier SA1 can generate a sensing signal S1 according to the memory cell current IC1 and the reference current Iref. Further, the sense amplifier circuit SA1 can include a current comparison circuit 106, and the current comparison circuit 106 can compare the memory cell current IC1 and the reference current Iref. In order to generate the sensing signal S1, the current adjustment circuit 108 can control the reference current generation circuit to generate the reference current Iref corresponding to the power supply voltage VDD according to the power supply voltage VDD.

另外，處理電路110則可依據感測信號S1判斷記憶胞單元112的記憶體狀態，進一步來說，處理電路110可依據感測信號S1得知記憶胞電流IC1與參考電流Iref的大小比較結果，進而判斷記憶胞單元112的記憶體狀態，例如當記憶胞電流IC1大於參考電流Iref時，可判斷記憶胞單元112為抹除狀態，而當記憶胞電流IC1未大於參考電流Iref時，可判斷記憶胞單元112為程式化狀態。In addition, the processing circuit 110 can determine the memory state of the memory cell unit 112 according to the sensing signal S1. Furthermore, the processing circuit 110 can obtain the comparison result between the memory cell current IC1 and the reference current Iref according to the sensing signal S1. Furthermore, the memory state of the memory cell unit 112 can be determined. For example, when the memory cell current IC1 is greater than the reference current Iref, the memory cell unit 112 can be judged to be in an erased state, and when the memory cell current IC1 is not greater than the reference current Iref, the memory can be judged The cell unit 112 is in a stylized state.

由於本實施例的電流調整電路108可依據電源電壓VDD控制參考電流產生電路104產生對應電源電壓VDD的參考電流Iref。例如當提供至記憶胞單元112的電源電壓VDD的電壓值降低時，電流調整電路108可依據電源電壓VDD控制參考電流產生電路104產生較佳的參考電流Iref，以避免在記憶胞電流IC1因電源電壓VDD降低而變小時，變小幅度較小參考電流Iref與變小幅度較大的記憶胞電流IC1作比較，而將抹除狀態的記憶胞單元112誤判為程式化狀態的記憶胞單元112。Because the current adjustment circuit 108 of this embodiment can control the reference current generation circuit 104 to generate the reference current Iref corresponding to the power supply voltage VDD according to the power supply voltage VDD. For example, when the voltage value of the power supply voltage VDD provided to the memory cell unit 112 decreases, the current adjustment circuit 108 may control the reference current generation circuit 104 to generate a better reference current Iref according to the power supply voltage VDD, so as to prevent the IC1 from being damaged by the power supply. The voltage VDD decreases and becomes smaller. The reference current Iref which becomes smaller and smaller is compared with the memory cell current IC1 which becomes larger and smaller, and the memory cell unit 112 in the erased state is misjudged as the memory cell unit 112 in the stylized state.

圖2是依照本發明另一實施例的一種記憶體裝置的示意圖，請參照圖2。在本實施例中，記憶體胞單元112可包括字元線選擇電晶體M1、記憶體電晶體M2以及位元線選擇電晶體M3，字元線選擇電晶體M1、記憶體電晶體M2以及位元線選擇電晶體M3串接於電源電壓VDD與電流比較電路106之間，字元線選擇電晶體M1、記憶體電晶體M2以及位元線選擇電晶體M3的閘極分別接收字元線選擇信號SWL、控制信號FWL以及位元線選擇信號SGD。其中記憶體電晶體M2具有儲存資料電荷的浮動閘極，可反應控制信號提供記憶胞電流IC1。FIG. 2 is a schematic diagram of a memory device according to another embodiment of the present invention. Please refer to FIG. 2. In this embodiment, the memory cell unit 112 may include a word line selection transistor M1, a memory transistor M2, and a bit line selection transistor M3. A word line selection transistor M1, a memory transistor M2, and a bit The element line selection transistor M3 is connected in series between the power supply voltage VDD and the current comparison circuit 106. The gates of the word line selection transistor M1, the memory transistor M2, and the bit line selection transistor M3 respectively receive the word line selection. The signal SWL, the control signal FWL, and the bit line selection signal SGD. The memory transistor M2 has a floating gate for storing data charges, and can provide a memory cell current IC1 in response to a control signal.

另外，電流比較電路106可包括電流鏡電路202以及電流鏡電路204，參考電流產生電路104則可包括多個電流源I1~IN，其中N為正整數。多個電流源I1~IN並聯於電流鏡電路204的輸入端與接地之間，分別受控於電流調整電路108產生電流，以於電流鏡電路204的輸入端產生對應電源電壓VDD的參考電流Iref。電流鏡電路202的輸入端與輸出端分別耦接記憶體胞單元112以及電流比較電路106的輸出端，電流鏡電路204輸入端與輸出端分別耦接參考電流產生電路104以及電流比較電路106的輸出端。電流鏡電路202依據記憶胞電流IC1於電流鏡電路202的輸出端產生電流鏡信號IM1。電流鏡電路204依據參考電流Iref產生電流鏡信號IM2，由於電流鏡信號IM1與電流鏡信號IM2分別為依據記憶胞電流IC1與參考電流Iref所產生，而感測信號S1為電流鏡信號IM1與電流鏡信號IM2反應電流比較電路106的偏壓狀態所產生，因此處理電路110亦可依據感測信號S1得知記憶胞電流IC1與參考電流Iref的大小比較結果，進而判斷記憶胞單元112的記憶體狀態。其中由於參考電流Iref可反應電源電壓VDD的變化而作較佳的改變，因此可避免因電源電壓VDD的改變而產生記憶胞的記憶體狀態誤判的情形。In addition, the current comparison circuit 106 may include a current mirror circuit 202 and a current mirror circuit 204, and the reference current generation circuit 104 may include a plurality of current sources I1 ~ IN, where N is a positive integer. Multiple current sources I1 ~ IN are connected in parallel between the input terminal of the current mirror circuit 204 and the ground, and are respectively controlled by the current adjustment circuit 108 to generate a current, so that the input terminal of the current mirror circuit 204 generates a reference current Iref corresponding to the power supply voltage VDD. . The input and output of the current mirror circuit 202 are respectively coupled to the memory cell 112 and the output of the current comparison circuit 106. The input and output of the current mirror circuit 204 are respectively coupled to the reference current generation circuit 104 and the current comparison circuit 106. Output. The current mirror circuit 202 generates a current mirror signal IM1 at the output terminal of the current mirror circuit 202 according to the memory cell current IC1. The current mirror circuit 204 generates a current mirror signal IM2 according to the reference current Iref. The current mirror signal IM1 and the current mirror signal IM2 are generated based on the memory cell current IC1 and the reference current Iref, and the sensing signal S1 is the current mirror signal IM1 and the current. The mirror signal IM2 is generated by the bias state of the current comparison circuit 106, so the processing circuit 110 can also learn the comparison result between the memory cell current IC1 and the reference current Iref according to the sensing signal S1, and then judge the memory of the memory cell unit 112. status. Among them, the reference current Iref can make a better change in response to the change in the power supply voltage VDD, so that the situation of misjudgment of the memory state of the memory cell due to the change in the power supply voltage VDD can be avoided.

圖3是依照本發明另一實施例的一種記憶體裝置的示意圖，請參照圖3。進一步來說，電流鏡電路202可例如包括電晶體M4與電晶體M5，而電流鏡電路204可包括電晶體Q1與電晶體Q2，其中電晶體M4耦接於記憶體胞單元112與接地之間，電晶體M4的汲極與源極相耦接，電晶體M4的閘極更耦接電晶體M5的閘極。電晶體M5的汲極與源極分別耦接電晶體Q1的汲極與接地。電晶體Q1的源極耦接電源電壓VDD，電晶體Q1的閘極耦接電晶體Q2的閘極，電晶體Q2的源極與汲極分別耦接電源電壓VDD以及參考電流產生電路104。電晶體M4與電晶體M5可依據記憶胞電流IC1於電晶體M5的汲極產生電流鏡信號IM1，而電晶體Q1與電晶體Q2可依據參考電流Iref於電晶體Q2的汲極產生電流鏡信號IM2，電流鏡信號IM1與電流鏡信號IM2則可反應電晶體M5汲極端的偏壓狀態而產生感測信號S1，以供處理電路110判斷記憶胞單元112的記憶體狀態。FIG. 3 is a schematic diagram of a memory device according to another embodiment of the present invention. Please refer to FIG. 3. Further, the current mirror circuit 202 may include, for example, a transistor M4 and a transistor M5, and the current mirror circuit 204 may include a transistor Q1 and a transistor Q2, where the transistor M4 is coupled between the memory cell unit 112 and the ground The drain and the source of the transistor M4 are coupled, and the gate of the transistor M4 is more coupled to the gate of the transistor M5. The drain and source of transistor M5 are respectively coupled to the drain and ground of transistor Q1. The source of the transistor Q1 is coupled to the power supply voltage VDD, the gate of the transistor Q1 is coupled to the gate of the transistor Q2, and the source and the drain of the transistor Q2 are respectively coupled to the power supply voltage VDD and the reference current generating circuit 104. Transistor M4 and transistor M5 can generate a current mirror signal IM1 at the drain of transistor M5 according to the memory cell current IC1, and transistors Q1 and Q2 can generate a current mirror signal at the drain of transistor Q2 according to the reference current Iref IM2, the current mirror signal IM1 and the current mirror signal IM2 can respond to the bias state of the transistor M5 to generate a sensing signal S1 for the processing circuit 110 to determine the memory state of the memory cell unit 112.

在本實施例中，圖3的電流源I1~IN可例如分別以串接於電流鏡電路的輸入端204與接地間的電阻與開關來實施，例如串接於電流鏡電路的輸入端204與接地間的電阻R1與開關SW1、電阻R2與開關SW2…電阻RN與開關SWN，其中N為正整數。開關SW1~SWN可例如以電晶體開關來實施，然不以此為限，個個開關SW1~SWN可接收來自電流調整電路108的開關控制信號SC1，而改變其導通狀態，進而改變參考電流Iref的電流值。電流調整電路108可例如包括分壓電路302、類比數位轉換電路304以及編碼器306，類比數位轉換電路304耦接分壓電路302以及編碼器306，編碼器306更耦接參考電流產生電路104。In this embodiment, the current sources I1 to IN of FIG. 3 may be implemented by, for example, resistors and switches connected in series between the input terminal 204 and the ground of the current mirror circuit, for example, connected in series with the input terminal 204 of the current mirror circuit and The resistor R1 and the switch SW1, the resistor R2 and the switch SW2, ... the resistor RN and the switch SWN between the grounds, where N is a positive integer. The switches SW1 to SWN can be implemented by, for example, transistor switches, but not limited to this. Each of the switches SW1 to SWN can receive the switching control signal SC1 from the current adjustment circuit 108 to change its conducting state, thereby changing the reference current Iref. The current value. The current adjustment circuit 108 may include, for example, a voltage dividing circuit 302, an analog digital conversion circuit 304, and an encoder 306. The analog digital conversion circuit 304 is coupled to the voltage dividing circuit 302 and the encoder 306. The encoder 306 is further coupled to a reference current generating circuit. 104.

分壓電路302可分壓電源電壓VDD以產生分壓電壓VD1，在本實施例中，分壓電路302可例如包括串接於電源電壓VDD與接地間的電阻RD1與電阻RD2，電阻RD1與電阻RD2的共同接點耦接類比數位轉換電路304，用以產生分壓電壓VD1。類比數位轉換電路304將分壓電壓VD1轉換為數位控制信號SD1，編碼器306則可依據數位控制信號SD1產生開關控制信號SC1，以控制開關SW1~SWN的導通狀態，而於電流鏡電路204的輸入端產生對應電源電壓VDD的參考電流Iref。The voltage dividing circuit 302 can divide the power supply voltage VDD to generate a divided voltage VD1. In this embodiment, the voltage dividing circuit 302 can include, for example, a resistor RD1 and a resistor RD2, and a resistor RD1 connected in series between the power voltage VDD and the ground. The common contact with the resistor RD2 is coupled to the analog-to-digital conversion circuit 304 for generating a divided voltage VD1. The analog digital conversion circuit 304 converts the divided voltage VD1 into a digital control signal SD1. The encoder 306 can generate a switching control signal SC1 according to the digital control signal SD1 to control the conduction state of the switches SW1 to SWN. The input terminal generates a reference current Iref corresponding to the power supply voltage VDD.

進一步來說，類比數位轉換電路304可例如以圖4所示的實施方式來實施，在圖4實施例中，類比數位轉換電路304包括多個分壓電阻RD、多個比較器A1以及編碼器402，多個分壓電阻RD串接於參考電壓Vref與接地之間，並於分壓電阻RD間的接點上的產生多個子參考電壓。各個比較器A1的一輸入端耦接分壓電壓VD1，另一輸入端則分別耦接對應的子參考電壓，各個比較器A1分別將其對應的子參考電壓與分壓電壓VD1進行比較，並依據比較結果產生對應的位元值，進而於此些比較器A1的輸出端產生熱碼(thermometer code)信號，例如在本實施例中，多個比較器A1可反應分壓電壓VD1產生位元資料為“0001111”的熱碼信號。編碼器402可對熱碼信號進行編碼以產生數位控制信號SC1，其中數位控制信號SC1可為二進碼(binary code)信號。例如在本實施例中，可將位元資料為“0001111”的熱碼信號轉換為位元資料為“101”的二進碼信號，值得注意的是本實施例的熱碼信號以及二進碼信號的位元值僅為示範性的實施例，熱碼信號以及二進碼信號的位元值可隨子參考電壓與分壓電壓VD1的變化而有所改變，實際應用上並不以此為限。Further, the analog-to-digital conversion circuit 304 can be implemented, for example, with the implementation shown in FIG. 4. In the embodiment of FIG. 4, the analog-to-digital conversion circuit 304 includes a plurality of voltage dividing resistors RD, a plurality of comparators A1, and an encoder. 402. A plurality of voltage dividing resistors RD are connected in series between the reference voltage Vref and the ground, and a plurality of sub-reference voltages are generated at the contacts between the voltage dividing resistors RD. One input terminal of each comparator A1 is coupled to the divided voltage VD1, and the other input terminal is respectively coupled to the corresponding sub-reference voltage. Each comparator A1 compares its corresponding sub-reference voltage with the divided voltage VD1, and Corresponding bit values are generated according to the comparison results, and then a thermometer code signal is generated at the output ends of these comparators A1. For example, in this embodiment, multiple comparators A1 can generate bit bits in response to the divided voltage VD1 The data is a hot code signal of "0001111". The encoder 402 may encode the hot code signal to generate a digital control signal SC1, where the digital control signal SC1 may be a binary code signal. For example, in this embodiment, a hot code signal whose bit data is "0001111" can be converted into a binary code signal whose bit data is "101". It is worth noting that the hot code signal and the binary code of this embodiment The bit value of the signal is only an exemplary embodiment, and the bit value of the hot code signal and the binary code signal may change with the change of the sub-reference voltage and the divided voltage VD1, which is not used in practice. limit.

圖3實施例的編碼器306則可將類比數位轉換電路304輸出的二進碼信號轉換為單一熱碼(one-hot code)信號，並將其作為開關控制信號SC1。舉例來說，編碼器306可儲存查找表，依據查找表將二進碼信號轉換為單一熱碼信號，查找表可例如表1所示： 表1The encoder 306 in the embodiment of FIG. 3 can convert a binary code signal output by the analog-to-digital conversion circuit 304 into a one-hot code signal and use it as a switch control signal SC1. For example, the encoder 306 may store a lookup table and convert a binary code signal into a single hot code signal according to the lookup table. The lookup table may be as shown in Table 1: Table 1

如圖3所示，假設參考電流產生電路104包括開關SW1~SW3(亦即參考電流產生電路104具有3個電流源)，編碼器306輸出的單一熱碼信號的各個位元可分別控制一個開關，以進行參考電流Iref的調整。值得注意的是，表1所列舉的二進碼信號與單一熱碼信號(開關控制信號SC1)為3位元的位元信號，然不以此為限，在其它實施例中，二進碼信號與單一熱碼信號亦可為具有不同位元數的位元信號，此外，二進碼信號與單一熱碼信號間的轉換關係亦不以表1為限，其可根據使用者對於參考電流Iref的需求進行調整，以使感測信號S1可正確地反應出記憶胞單元112的記憶體狀態，而避免誤判的情形發生。As shown in FIG. 3, it is assumed that the reference current generating circuit 104 includes switches SW1 to SW3 (that is, the reference current generating circuit 104 has three current sources), and each bit of a single hot code signal output by the encoder 306 can control one switch respectively. To adjust the reference current Iref. It is worth noting that the binary code signal and the single hot code signal (switch control signal SC1) listed in Table 1 are 3-bit bit signals, but not limited to this. In other embodiments, the binary code The signal and the single hot code signal can also be bit signals with different numbers of bits. In addition, the conversion relationship between the binary code signal and the single hot code signal is not limited to Table 1. It can be based on the user's reference current. The requirements of Iref are adjusted so that the sensing signal S1 can correctly reflect the memory state of the memory cell unit 112 to avoid misjudgment.

綜上所述，本發明的實施例依據電源電壓控制參考電流產生電路產生對應電源電壓的較佳的參考電流，以使感測放大器產生對應電源電壓的感測信號，避免處理電路因電源電壓的改變而出現記憶胞的記憶體狀態誤判的情形。In summary, the embodiment of the present invention controls the reference current generating circuit to generate a better reference current corresponding to the power supply voltage according to the power supply voltage, so that the sense amplifier generates a sensing signal corresponding to the power supply voltage, and avoids the processing circuit from being damaged due to the power supply voltage. The situation that the memory state of the memory cell is misjudged by the change.

102‧‧‧記憶體陣列102‧‧‧Memory Array

104‧‧‧參考電流產生電路104‧‧‧Reference current generating circuit

106‧‧‧電流比較電路106‧‧‧Current comparison circuit

108‧‧‧電流調整電路108‧‧‧Current adjustment circuit

110‧‧‧處理電路110‧‧‧Processing circuit

112‧‧‧記憶體胞單元112‧‧‧Memory Cell Unit

202、204‧‧‧電流鏡電路202, 204‧‧‧ current mirror circuit

302‧‧‧分壓電路302‧‧‧Divided voltage circuit

304‧‧‧類比數位轉換電路304‧‧‧ Analog Digital Conversion Circuit

306‧‧‧編碼器306‧‧‧ Encoder

402‧‧‧編碼器402‧‧‧Encoder

SA1‧‧‧感測放大器SA1‧‧‧Sense Amplifier

VDD‧‧‧電源電壓VDD‧‧‧ supply voltage

SWL‧‧‧字元線選擇信號SWL‧‧‧Word line selection signal

SGD‧‧‧位元線選擇信號SGD‧‧‧Bit line selection signal

FWL‧‧‧控制信號FWL‧‧‧Control signal

IC1‧‧‧記憶胞電流IC1‧‧‧Memory cell current

S1‧‧‧感測信號S1‧‧‧sensing signal

Iref‧‧‧參考電流Iref‧‧‧Reference current

M1‧‧‧字元線選擇電晶體M1‧‧‧Word line selection transistor

M2‧‧‧記憶體電晶體M2‧‧‧Memory Transistor

M3‧‧‧位元線選擇電晶體M3‧‧‧bit line selection transistor

I1~IN‧‧‧電流源I1 ~ IN‧‧‧current source

IM1、IM2‧‧‧電流鏡信號IM1, IM2‧‧‧ current mirror signal

M4、M5、Q1、Q2‧‧‧電晶體M4, M5, Q1, Q2 ‧‧‧ Transistors

R1~RN、RD1、RD2‧‧‧電阻R1 ~ RN, RD1, RD2‧‧‧ resistance

SW1~SWN‧‧‧開關SW1 ~ SWN‧‧‧Switch

SC1‧‧‧開關控制信號SC1‧‧‧Switch control signal

VD1‧‧‧分壓電壓VD1‧‧‧ divided voltage

SD1‧‧‧數位控制信號SD1‧‧‧Digital control signal

RD‧‧‧分壓電阻RD‧‧‧Voltage Divider

A1‧‧‧比較器A1‧‧‧ Comparator

Vref‧‧‧參考電壓Vref‧‧‧Reference voltage

圖1是依照本發明的實施例的一種記憶體裝置的示意圖。 圖2是依照本發明另一實施例的一種記憶體裝置的示意圖。 圖3是依照本發明另一實施例的一種記憶體裝置的示意圖。 圖4是依照本發明的實施例的一種類比數位轉換電路的示意圖。FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a memory device according to another embodiment of the invention. FIG. 3 is a schematic diagram of a memory device according to another embodiment of the invention. FIG. 4 is a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the present invention.

Claims (9)

一種記憶體裝置，包括： 一記憶體陣列，包括： 至少一記憶胞單元，耦接一電源電壓，依據字元線選擇信號、位元線選擇信號以及一控制信號輸出一記憶胞電流； 一參考電流產生電路，耦接該電源電壓，產生一參考電流； 一感測放大器，耦接該記憶體陣列與該參考電流產生電路，依據該記憶胞電流及該參考電流產生一感測信號，該感測放大器包括： 一電流比較電路，耦接該記憶胞單元與該參考電流產生電路，比較該記憶胞電流與該參考電流，以產生該感測信號； 一電流調整電路，耦接該電源電壓與該參考電流產生電路，依據該電源電壓控制該參考電流產生電路產生對應該電源電壓的該參考電流；以及 一處理電路，耦接該電流比較電路，依據該感測信號判斷該記憶胞單元的記憶體狀態。A memory device includes: a memory array including: at least one memory cell unit coupled to a power voltage, and outputting a memory cell current according to a word line selection signal, a bit line selection signal, and a control signal; a reference A current generating circuit is coupled to the power voltage to generate a reference current; a sense amplifier is coupled to the memory array and the reference current generating circuit, and a sensing signal is generated according to the memory cell current and the reference current, and the sensing The sense amplifier includes: a current comparison circuit coupled to the memory cell unit and the reference current generating circuit, comparing the memory cell current and the reference current to generate the sensing signal; a current adjustment circuit, coupled to the power supply voltage and The reference current generation circuit controls the reference current generation circuit to generate the reference current corresponding to the power supply voltage according to the power supply voltage; and a processing circuit coupled to the current comparison circuit to judge the memory of the memory cell unit based on the sensing signal Body status. 如申請專利範圍第1項所述的記憶體裝置，其中該電流比較電路包括： 一第一電流鏡電路，其輸入端與輸出端分別耦接該記憶體胞單元以及該電流比較電路的輸出端，依據該記憶胞電流於該第一電流鏡電路的輸出端產生一第一電流鏡信號；以及 一第二電流鏡電路，其輸入端與輸出端分別耦接該參考電流產生電路以及該電流比較電路的輸出端，依據該參考電流產生一第二電流鏡信號，該第一電流鏡信號與該第二電流鏡信號反應該電流比較電路的偏壓狀態而於該電流比較電路的輸出端產生該感測信號。The memory device according to item 1 of the patent application scope, wherein the current comparison circuit comprises: a first current mirror circuit, the input end and the output end of the current comparison circuit are respectively coupled to the memory cell unit and the output end of the current comparison circuit Generating a first current mirror signal at the output terminal of the first current mirror circuit according to the memory cell current; and a second current mirror circuit whose input terminal and output terminal are respectively coupled to the reference current generating circuit and the current comparison The output end of the circuit generates a second current mirror signal according to the reference current, and the first current mirror signal and the second current mirror signal reflect the bias state of the current comparison circuit and generate the current comparison circuit output. Sense the signal. 如申請專利範圍第2項所述的記憶體裝置，其中該參考電流產生電路包括： 多個電流源，並聯於該第二電流鏡電路的輸入端與一接地之間，分別受控於該電流調整電路產生電流，以於該第二電流鏡電路的輸入端產生對應該電源電壓的該參考電流。The memory device according to item 2 of the scope of patent application, wherein the reference current generating circuit includes: a plurality of current sources connected in parallel between an input terminal of the second current mirror circuit and a ground, respectively controlled by the current The adjusting circuit generates a current, so that the input terminal of the second current mirror circuit generates the reference current corresponding to the power supply voltage. 如申請專利範圍第3項所述的記憶體裝置，其中各該電流源包括： 一電阻，耦接該第二電流鏡電路的輸入端；以及 一開關，耦接於該電阻與該接地之間，該開關受控於該電流調整電路改變其導通狀態，以於該第二電流鏡電路的輸入端產生對應該電源電壓的該參考電流。According to the memory device in claim 3, each of the current sources includes: a resistor coupled to the input terminal of the second current mirror circuit; and a switch coupled between the resistor and the ground. The switch is controlled by the current adjustment circuit to change its conducting state, so that the input terminal of the second current mirror circuit generates the reference current corresponding to the power supply voltage. 如申請專利範圍第4項所述的記憶體裝置，其中該電流調整電路包括： 一分壓電路，耦接於該電源電壓，分壓該電源電壓以產生一分壓電壓； 一類比數位轉換電路，耦接該分壓電路，將該分壓電壓轉換為一數位控制信號；以及 一第一編碼器，耦接該類比數位轉換電路與該些開關，依據該數位控制信號產生一開關控制信號，以控制該些開關的導通狀態，而於該第二電流鏡電路的輸入端產生對應該電源電壓的該參考電流。The memory device according to item 4 of the scope of patent application, wherein the current adjustment circuit includes: a voltage dividing circuit coupled to the power supply voltage, and dividing the power supply voltage to generate a divided voltage; an analog digital conversion A circuit coupled to the voltage dividing circuit to convert the divided voltage into a digital control signal; and a first encoder coupled to the analog digital conversion circuit and the switches to generate a switch control according to the digital control signal Signals to control the on-states of the switches, and the reference current corresponding to the power supply voltage is generated at the input terminal of the second current mirror circuit. 如申請專利範圍第5項所述的記憶體裝置，其中該分壓電路包括： 一第一電阻；以及 一第二電阻，與該第一電阻串接於該電源電壓與該接地之間，該第一電阻與該第二電阻的共同接點產生該分壓電壓。The memory device according to item 5 of the scope of patent application, wherein the voltage dividing circuit includes: a first resistor; and a second resistor connected in series with the first resistor between the power supply voltage and the ground, A common contact point of the first resistor and the second resistor generates the divided voltage. 如申請專利範圍第5項所述的記憶體裝置，其中該類比數位轉換電路包括： 多個分壓電阻，串接於一參考電壓與該接地之間，以產生多個子參考電壓； 多個比較器，各該比較器的第一輸入端耦接該分壓電壓，各該比較器的第二輸入端分別耦接對應的該些子參考電壓，以於該些比較器的輸出端產生一熱碼(thermometer code)信號；以及 一第二編碼器，耦接該些比較器，對該熱碼信號進行編碼以產生該數位控制信號。The memory device according to item 5 of the patent application scope, wherein the analog digital conversion circuit includes: a plurality of voltage dividing resistors connected in series between a reference voltage and the ground to generate a plurality of sub-reference voltages; a plurality of comparisons A first input terminal of each of the comparators is coupled to the divided voltage, and a second input terminal of each of the comparators is respectively coupled to the corresponding sub-reference voltages so that a heat is generated at the output terminals of the comparators A thermometer code signal; and a second encoder coupled to the comparators to encode the hot code signal to generate the digital control signal. 如申請專利範圍第7項所述的記憶體裝置，其中該數位控制信號為一二進碼(binary code)信號，該開關控制信號為一單一熱碼(one-hot code)信號。The memory device according to item 7 of the patent application scope, wherein the digital control signal is a binary code signal, and the switch control signal is a one-hot code signal. 如申請專利範圍第8項所述的記憶體裝置，該第一編碼器更儲存一查找表，並依據該查找表將該二進碼信號轉換為該單一熱碼信號。According to the memory device described in item 8 of the patent application scope, the first encoder further stores a lookup table, and converts the binary code signal into the single hot code signal according to the lookup table.
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