TW201810617A - Memory device and method of manufacturing the same - Google Patents
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Description
本發明實施例係有關於記憶體裝置及其製造方法，且特別係有關於一種非揮發性記憶體裝置及其製造方法。 Embodiments of the present invention relate to a memory device and a method of fabricating the same, and in particular to a non-volatile memory device and a method of fabricating the same.
現代電子裝置如筆記型電腦包含多種記憶體以儲存資訊。記憶電路包含非揮發性記憶體。非揮發性記憶體在未接電時仍維持其儲存資料。非揮發性記憶體包含多種分類如唯讀記憶體(ROM)、電子可抹除式可程式化唯讀記憶體(EEPROM)、與快閃記憶體。 Modern electronic devices such as notebook computers contain a variety of memories to store information. The memory circuit contains non-volatile memory. Non-volatile memory retains its stored data when it is not connected. Non-volatile memory contains a variety of categories such as read-only memory (ROM), electronic erasable programmable read-only memory (EEPROM), and flash memory.
然而，目前的非揮發性記憶體裝置並非各方面皆令人滿意。因此，業界仍須一種可更進一步降低資料寫入電壓、提升資料寫入速度、且可增加資料保存時間的非揮發性記憶體裝置及其製造方法。 However, current non-volatile memory devices are not satisfactory in all respects. Therefore, the industry still needs a non-volatile memory device that can further reduce the data write voltage, increase the data writing speed, and increase the data storage time, and a manufacturing method thereof.
本發明實施例提供一種記憶體裝置，包括：基板；第一堆疊結構，設於基板之上表面上，且具有相反之第一側及第二側，其中第一堆疊結構包括：穿隧層，設於基板之上表面上，其中穿隧層包括SixOyNz，且x：y為1：0.1至1：10，而x：z為1：0.1至1：10；電荷層，設於穿隧層之上；第一氧化矽層，設於電荷層之上；及第一閘極線，設於第一氧化矽層之上；源 極線摻雜區，設於基板中，且位於第一堆疊結構之第一側：以及位元線摻雜區，設於基板中，且位於第一堆疊結構之第二側。 An embodiment of the present invention provides a memory device, including: a substrate; a first stacked structure disposed on an upper surface of the substrate and having opposite first and second sides, wherein the first stacked structure includes: a tunneling layer, Provided on the upper surface of the substrate, wherein the tunneling layer comprises Si x O y N z , and x:y is 1:0.1 to 1:10, and x:z is 1:0.1 to 1:10; Above the tunneling layer; a first yttria layer disposed over the charge layer; and a first gate line disposed over the first ruthenium oxide layer; a source line doped region disposed in the substrate, and Located on a first side of the first stacked structure: and a bit line doped region disposed in the substrate and located on a second side of the first stacked structure.
本發明實施例更提供一種記憶體裝置之製造方法，包括：提供基板；形成第一堆疊結構於基板之上表面上，第一堆疊結構具有相反之第一側及第二側，其中第一堆疊結構包括：穿隧層，設於基板之上表面上，其中穿隧層包括SixOyNz，且x：y為1：0.1至1：10，而x：z為1：0.1至1：10；電荷層，設於穿隧層之上；第一氧化矽層，設於電荷層之上；及第一閘極線，設於第一氧化矽層之上；形成源極線摻雜區於基板中，且位於第一堆疊結構之第一側：以及形成位元線摻雜區於基板中，且位於第一堆疊結構之第二側。 The embodiment of the present invention further provides a method for manufacturing a memory device, comprising: providing a substrate; forming a first stacked structure on an upper surface of the substrate, the first stacked structure having opposite first sides and second sides, wherein the first stack The structure comprises: a tunneling layer disposed on an upper surface of the substrate, wherein the tunneling layer comprises Si x O y N z , and x:y is 1:0.1 to 1:10, and x:z is 1:0.1 to 1 a charge layer disposed on the tunneling layer; a first yttria layer disposed over the charge layer; and a first gate line disposed over the first ruthenium oxide layer; forming a source line doping The region is in the substrate and is located on the first side of the first stacked structure: and the bit line doped region is formed in the substrate and is located on the second side of the first stacked structure.
為讓本發明實施例之特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下。 The features and advantages of the embodiments of the present invention will become more apparent and understood.
100‧‧‧記憶體裝置 100‧‧‧ memory device
102‧‧‧基板 102‧‧‧Substrate
102S‧‧‧上表面 102S‧‧‧ upper surface
104A‧‧‧第一堆疊結構 104A‧‧‧First stacking structure
104AS‧‧‧底面 104AS‧‧‧ bottom
104B‧‧‧第二堆疊結構 104B‧‧‧Second stacking structure
104BS‧‧‧底面 104BS‧‧‧ bottom
104C‧‧‧第三堆疊結構 104C‧‧‧ third stack structure
104CS‧‧‧底面 104CS‧‧‧ bottom
106‧‧‧穿隧層 106‧‧‧Through tunnel
108‧‧‧電荷層 108‧‧‧Charge layer
110A‧‧‧第一氧化矽層 110A‧‧‧First ruthenium oxide layer
110B‧‧‧第二氧化矽層 110B‧‧‧Second ruthenium oxide layer
110C‧‧‧第三氧化矽層 110C‧‧‧ Third ruthenium oxide layer
112A‧‧‧第一閘極線 112A‧‧‧First Gate Line
112B‧‧‧第二閘極線 112B‧‧‧second gate line
112C‧‧‧第三閘極線 112C‧‧‧third gate line
114‧‧‧源極線摻雜區 114‧‧‧Source line doped area
114A‧‧‧輕摻雜區 114A‧‧‧Lightly doped area
114B‧‧‧重摻雜區 114B‧‧‧ heavily doped area
114BE1‧‧‧邊緣 114BE1‧‧‧ edge
114BE2‧‧‧邊緣 114BE2‧‧‧ edge
116‧‧‧位元線摻雜區 116‧‧‧ bit line doped area
116A‧‧‧輕摻雜區 116A‧‧‧Lightly doped area
116B‧‧‧重摻雜區 116B‧‧‧ heavily doped area
116BE1‧‧‧邊緣 116BE1‧‧‧ edge
116BE2‧‧‧邊緣 116BE2‧‧‧ edge
118‧‧‧源極線摻雜區 118‧‧‧ source line doped area
118A‧‧‧輕摻雜區 118A‧‧‧Lightly doped area
118B‧‧‧重摻雜區 118B‧‧‧ heavily doped area
118BE1‧‧‧邊緣 118BE1‧‧‧ edge
120‧‧‧位元線摻雜區 120‧‧‧ bit line doped area
120A‧‧‧輕摻雜區 120A‧‧‧lightly doped area
120B‧‧‧重疊之重摻雜區 120B‧‧‧Overlapped heavily doped areas
120BE1‧‧‧邊緣 120BE1‧‧‧ edge
200‧‧‧記憶體裝置 200‧‧‧ memory device
300‧‧‧記憶體裝置 300‧‧‧ memory device
S1‧‧‧第一側 S1‧‧‧ first side
S2‧‧‧第二側 S2‧‧‧ second side
S3‧‧‧第三側 S3‧‧‧ third side
S4‧‧‧第四側 S4‧‧‧ fourth side
S5‧‧‧第五側 S5‧‧‧ fifth side
S6‧‧‧第六側 S6‧‧‧ sixth side
E1‧‧‧第一邊緣 E1‧‧‧ first edge
E2‧‧‧第二邊緣 E2‧‧‧ second edge
E3‧‧‧第三邊緣 E3‧‧‧ third edge
E4‧‧‧第四邊緣 E4‧‧‧ fourth edge
E5‧‧‧第五邊緣 E5‧‧‧ fifth edge
E6‧‧‧第六邊緣 E6‧‧‧ sixth edge
第1圖係本發明一些實施例之記憶體裝置之剖面圖。 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view of a memory device in accordance with some embodiments of the present invention.
第2圖係本發明一些實施例之記憶體裝置之剖面圖。 Figure 2 is a cross-sectional view of a memory device in accordance with some embodiments of the present invention.
第3圖係本發明一些實施例之記憶體裝置之剖面圖。 Figure 3 is a cross-sectional view of a memory device in accordance with some embodiments of the present invention.
以下針對本發明一些實施例之記憶體裝置及其製造方法作詳細說明。應了解的是，以下之敘述提供許多不同的實施例或例子，用以實施本發明一些實施例之不同樣態。以下所述特定的元件及排列方式僅為簡單清楚描述本發明一些實 施例。當然，這些僅用以舉例而非本發明一些實施例之限定。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明一些實施例，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸之情形。或者，亦可能間隔有一或更多其它材料層之情形，在此情形中，第一材料層與第二材料層之間可能不直接接觸。 The memory device and the method of manufacturing the same according to some embodiments of the present invention are described in detail below. It will be appreciated that the following description provides many different embodiments or examples for implementing the various embodiments of the invention. The specific elements and arrangements described below are only for the sake of simplicity and clarity. Example. Of course, these are only by way of example and not by the definition of some embodiments of the invention. Moreover, repeated numbers or labels may be used in different embodiments. These repetitive examples are merely illustrative of some embodiments of the invention, and are not intended to represent any of the various embodiments and/or structures discussed. Furthermore, when a first material layer is on or above a second material layer, the first material layer is in direct contact with the second material layer. Alternatively, it is also possible to have one or more layers of other materials interposed, in which case there may be no direct contact between the first layer of material and the second layer of material.
此外，實施例中可能使用相對性的用語，例如「較低」或「底部」及「較高」或「頂部」，以描述圖式的一個元件對於另一元件的相對關係。能理解的是，如果將圖式的裝置翻轉使其上下顛倒，則所敘述在「較低」側的元件將會成為在「較高」側的元件。 In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element of the drawing to another. It will be understood that if the device of the drawing is flipped upside down, the component described on the "lower" side will become the component on the "higher" side.
在此，「約」、「大約」、「大抵」之用語通常表示在一給定值或範圍的20%之內，較佳是10%之內，且更佳是5%之內，或3%之內，或2%之內，或1%之內，或0.5%之內。在此給定的數量為大約的數量，亦即在沒有特定說明「約」、「大約」、「大抵」的情況下，仍可隱含「約」、「大約」、「大抵」之含義。 Here, the terms "about", "about" and "major" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. The quantity given here is an approximate quantity, that is, in the absence of specific descriptions of "about", "about" and "major", the meanings of "about", "about" and "major" may still be implied.
能理解的是，雖然在此可使用用語「第一」、「第二」、「第三」等來敘述各種元件、組成成分、區域、層、及/或部分，這些元件、組成成分、區域、層、及/或部分不應被這些用語限定，且這些用語僅是用來區別不同的元件、組成成分、區域、層、及/或部分。因此，以下討論的一第一元件、組成成分、區域、層、及/或部分可在不偏離本發明一些實施 例之教示的情況下被稱為一第二元件、組成成分、區域、層、及/或部分。 It will be understood that the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or portions, such elements, components, and regions. The layers, and/or parts are not to be limited by the terms, and the terms are used to distinguish different elements, components, regions, layers, and/or parts. Thus, a first element, component, region, layer, and/or portion discussed below can be implemented without departing from the practice of the invention. The teachings of the examples are referred to as a second element, component, region, layer, and/or portion.
除非另外定義，在此使用的全部用語(包括技術及科學用語)具有與此篇發明所屬之一般技藝者所通常理解的相同涵義。能理解的是，這些用語，例如在通常使用的字典中定義的用語，應被解讀成具有與相關技術及本發明的背景或上下文一致的意思，而不應以一理想化或過度正式的方式解讀，除非在本發明一些實施例有特別定義。 Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning meaning It will be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the related art and the context or context of the present invention, and should not be in an idealized or overly formal manner. The interpretation is unless specifically defined in some embodiments of the invention.
本發明一些實施例可配合圖式一併理解，本發明一些實施例之圖式亦被視為發明說明之一部分。需了解的是，本發明一些實施例之圖式並未以實際裝置及元件之比例繪示。在圖式中可能誇大實施例的形狀與厚度以便清楚表現出本發明之特徵。此外，圖式中之結構及裝置係以示意之方式繪示，以便清楚表現出本發明之特徵。 Some embodiments of the invention may be understood in conjunction with the drawings, and the drawings of some embodiments of the invention are also considered as part of the description of the invention. It is to be understood that the drawings of the embodiments of the invention are not The shapes and thicknesses of the embodiments may be exaggerated in the drawings in order to clearly illustrate the features of the invention. In addition, the structures and devices in the drawings are schematically illustrated in order to clearly illustrate the features of the invention.
在本發明一些實施例中，相對性的用語例如「下」、「上」、「水平」、「垂直」、「之下」、「之上」、「頂部」、「底部」等等應被理解為該段以及相關圖式中所繪示的方位。此相對性的用語僅是為了方便說明之用，其並不代表其所敘述之裝置需以特定方位來製造或運作。而關於接合、連接之用語例如「連接」、「互連」等，除非特別定義，否則可指兩個結構係直接接觸，或者亦可指兩個結構並非直接接觸，其中有其它結構設於此兩個結構之間。且此關於接合、連接之用語亦可包括兩個結構都可移動，或者兩個結構都固定之情況。 In some embodiments of the present invention, relative terms such as "lower", "upper", "horizontal", "vertical", "lower", "above", "top", "bottom", etc. should be It is understood to be the orientation depicted in this paragraph and related figures. This relative term is used for convenience of description only, and does not mean that the device described therein is to be manufactured or operated in a particular orientation. Terms such as "joining" and "interconnecting", etc., unless otherwise defined, may mean that two structures are in direct contact, or that two structures are not in direct contact, and other structures are provided here. Between the two structures. The term "joining and joining" may also include the case where both structures are movable or both structures are fixed.
應注意的是，在後文中「基板」一詞可包括半導 體晶圓上已形成的元件與覆蓋在晶圓上的各種膜層，其上方可以已形成任何所需的半導體元件，不過此處為了簡化圖式，僅以平整的基板表示之。此外，「基板表面」係包括半導體晶圓上最上方且暴露之膜層，例如一矽表面、一絕緣層及/或金屬線。 It should be noted that the term "substrate" may include semi-conductive in the following text. The formed components on the bulk wafer and the various film layers overlying the wafer may have formed any desired semiconductor components thereon, but for the sake of simplicity of the drawing, only the flat substrate is shown. In addition, the "substrate surface" includes the uppermost and exposed film layer on the semiconductor wafer, such as a germanium surface, an insulating layer, and/or metal lines.
本發明一些實施例之資料儲存結構包括具有穿隧層、電荷層及氧化矽層之三層結構，且此穿隧層包括特定材料，故本發明一些實施例之記憶體裝置(例如非揮發性記憶體裝置)可更進一步降低資料寫入電壓、提升資料寫入速度、且可增加資料保存時間。 The data storage structure of some embodiments of the present invention includes a three-layer structure having a tunneling layer, a charge layer, and a ruthenium oxide layer, and the tunneling layer includes a specific material, so the memory device of some embodiments of the present invention (for example, non-volatile) The memory device can further reduce the data write voltage, increase the data writing speed, and increase the data storage time.
參見第1圖，該圖係本發明一些實施例之記憶體裝置100之剖面圖。在本發明一些實施例中，此記憶體裝置100可包括非揮發性記憶體裝置。此外，在本發明一些實施例中，此記憶體裝置100可藉由下述步驟形成。 Referring to Figure 1, there is shown a cross-sectional view of a memory device 100 in accordance with some embodiments of the present invention. In some embodiments of the invention, the memory device 100 can include a non-volatile memory device. Moreover, in some embodiments of the invention, the memory device 100 can be formed by the following steps.
首先，基板102可為半導體基板，例如矽基板。此外，上述半導體基板亦可為元素半導體，包括鍺(germanium)；化合物半導體，包括氮化鎵(gallium nitride，GaN)、碳化矽(silicon carbide)、砷化鎵(gallium arsenide)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)及/或銻化銦(indium antimonide)；合金半導體，包括矽鍺合金(SiGe)、磷砷鎵合金(GaAsP)、砷鋁銦合金(AlInAs)、砷鋁鎵合金(AlGaAs)、砷銦鎵合金(GaInAs)、磷銦鎵合金(GaInP)及/或磷砷銦鎵合金(GaInAsP)或上述材料之組合。此外，基板102也可以是絕緣層上覆半導體(semiconductor on insulator)。在一實 施例中，基板102可為輕摻雜第一導電型摻質之基板，例如輕摻雜之P型或N型基板。 First, the substrate 102 can be a semiconductor substrate, such as a germanium substrate. In addition, the semiconductor substrate may also be an elemental semiconductor, including germanium; a compound semiconductor including gallium nitride (GaN), silicon carbide, gallium arsenide, gallium phosphide ( Gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; alloy semiconductors including bismuth alloy (SiGe), phosphorus gallium arsenide (GaAsP), arsenic Aluminum indium alloy (AlInAs), arsenic aluminum gallium alloy (AlGaAs), arsenic gallium alloy (GaInAs), indium gallium alloy (GaInP) and/or phosphorus indium gallium alloy (GaInAsP) or a combination thereof. Further, the substrate 102 may be a semiconductor on insulator. In a real In an embodiment, the substrate 102 can be a substrate that is lightly doped with a first conductivity type dopant, such as a lightly doped P-type or N-type substrate.
在所述實施例中，“輕摻雜”意指約1011-1013/cm3的摻雜濃度，例如為約1012/cm3的摻雜濃度。然而，本領域具有通常知識者可瞭解的是，“輕摻雜”的定義亦可依照特定裝置型態、技術世代、最小元件尺寸等所決定。因此，“輕摻雜”的定義當可視技術內容重新評估，而不受限於在此所舉之實施例。 In the embodiment, "lightly doped" means a doping concentration of about 10 11 -10 13 /cm 3 , for example, a doping concentration of about 10 12 /cm 3 . However, it will be appreciated by those of ordinary skill in the art that the definition of "lightly doped" can also be determined by the particular device type, technology generation, minimum component size, and the like. Thus, the definition of "lightly doped" is re-evaluated as visual technology content and is not limited by the embodiments presented herein.
接著，形成第一堆疊結構104A於基板102之上表面102S上，此第一堆疊結構104A係作為記憶體裝置100之資料儲存結構。此第一堆疊結構104A具有相反之第一側S1及第二側S2，且於第一側S1具有一第一邊緣E1，於第二側S2具有一第二邊緣E2。 Next, a first stacked structure 104A is formed on the upper surface 102S of the substrate 102. The first stacked structure 104A serves as a data storage structure of the memory device 100. The first stack structure 104A has opposite first side S1 and second side S2, and has a first edge E1 on the first side S1 and a second edge E2 on the second side S2.
第一堆疊結構104A包括設於基板102之上表面102S上之穿隧層106、設於此穿隧層106上之電荷層108、設於此電荷層108上之第一氧化矽層110A、及設於第一氧化矽層110A上之第一閘極線112A。上述電荷層108係用以儲存資料(亦即電子或電洞)，而上述第一氧化矽層110A係用以防止電荷層108中的電子或電洞進入第一閘極線112A。在本發明之一些實施例中，電荷層108可為氮化矽層。 The first stacked structure 104A includes a tunneling layer 106 disposed on the upper surface 102S of the substrate 102, a charge layer 108 disposed on the tunneling layer 106, a first germanium oxide layer 110A disposed on the charge layer 108, and The first gate line 112A is disposed on the first tantalum oxide layer 110A. The charge layer 108 is used to store data (ie, electrons or holes), and the first ruthenium oxide layer 110A is used to prevent electrons or holes in the charge layer 108 from entering the first gate line 112A. In some embodiments of the invention, the charge layer 108 can be a tantalum nitride layer.
上述穿隧層106之材料包括SixOyNz，且x：y約為1：0.1至1：10，例如為約1：0.5至1：8，或約1：1至1：5，或約1：2至1：3。而x：z為約1：0.1至1：10，例如為約1：0.5至1：8，或約1：1至1：5，或約1：2至1：3。在本發明一些實施例中，y為0，且x：y約為3：4。亦即，此時穿隧層106之材料包括Si3N4。 The material of the tunneling layer 106 includes Si x O y N z and x:y is about 1:0.1 to 1:10, for example, about 1:0.5 to 1:8, or about 1:1 to 1:5. Or about 1:2 to 1:3. And x:z is from about 1:0.1 to 1:10, for example from about 1:0.5 to 1:8, or from about 1:1 to 1:5, or from about 1:2 to 1:3. In some embodiments of the invention, y is zero and x:y is about 3:4. That is, the material of the tunneling layer 106 at this time includes Si 3 N 4 .
在本發明一些實施例中，電荷層108之材料包括SiaNb，且a：b為1：0.1至1：10，例如為約1：0.5至1：8，或約1：1至1：5，或約1：2至1：3。在本發明一些實施例中，a：b約為3：4。亦即，此時電荷層108之材料包括Si3N4。 In some embodiments of the invention, the material of charge layer 108 comprises Si a N b and a:b is from 1:0.1 to 1:10, for example from about 1:0.5 to 1:8, or from about 1:1 to 1 : 5, or about 1:2 to 1:3. In some embodiments of the invention, a:b is about 3:4. That is, the material of the charge layer 108 at this time includes Si 3 N 4 .
此外，上述穿隧層106與電荷層108為獨立且不同之兩個層，且穿隧層106與電荷層108之間具有一界面。例如，在本發明一些實施例中，上述y為0，此時穿隧層106為SixNz，電荷層108為SiaNb，且x：z不等於a：b。 In addition, the tunneling layer 106 and the charge layer 108 are independent and different layers, and the tunneling layer 106 has an interface with the charge layer 108. For example, in some embodiments of the invention, y is zero, where tunneling layer 106 is Si x N z , charge layer 108 is Si a N b , and x:z is not equal to a:b.
當資料寫入此時，載子(例如電子或電洞)會穿過穿隧層106進入並停留於電荷層108內。而上述第一氧化矽層110A係用以避免此載子進入第一閘極線112A。由於本發明一些實施例之穿隧層106包括能隙(band gap)較小之SixOyNz，故可使載子於寫入資料時容易穿過此穿隧層106而進入電荷層108內，故可降低記憶體裝置100之資料寫入電壓，並提升資料寫入速度。此外，由於電荷層108與穿隧層106之間具有界面，故可防止已進入電荷層108中的載子於資料保存期間內穿過穿隧層106回到基板102中，故可增加記憶體裝置100之資料保存時間。 When the data is written at this time, a carrier (eg, an electron or a hole) enters through the tunneling layer 106 and stays in the charge layer 108. The first ruthenium oxide layer 110A is used to prevent the carrier from entering the first gate line 112A. Since the tunneling layer 106 of some embodiments of the present invention includes Si x O y N z having a small band gap, the carrier can easily pass through the tunneling layer 106 and enter the charge layer when writing data. In 108, the data writing voltage of the memory device 100 can be reduced, and the data writing speed can be improved. In addition, since the interface between the charge layer 108 and the tunneling layer 106 is provided, the carrier that has entered the charge layer 108 can be prevented from returning to the substrate 102 through the tunneling layer 106 during the data storage period, thereby increasing the memory. The data retention time of the device 100.
在本發明一些實施例中，上述第一氧化矽層110A之材料包括二氧化矽，且上述第一閘極線112A之材料包括複晶矽、非晶矽、一或多種金屬、金屬氮化物、導電金屬氧化物、或上述之組合。上述金屬可包括但不限於鉬(molybdenum)、鎢(tungsten)、鈦(titanium)、鉭(tantalum)、鉑(platinum)或鉿(hafnium)。上述金屬氮化物可包括但不限於氮化鉬(molybdenum nitride)、氮化鎢(tungsten nitride)、氮化鈦 (titanium nitride)以及氮化鉭(tantalum nitride)。上述導電金屬氧化物可包括但不限於釕金屬氧化物(ruthenium oxide)以及銦錫金屬氧化物(indium tin oxide)。 In some embodiments of the present invention, the material of the first ruthenium oxide layer 110A includes ruthenium dioxide, and the material of the first gate line 112A includes a polycrystalline germanium, an amorphous germanium, one or more metals, a metal nitride, A conductive metal oxide, or a combination thereof. The above metals may include, but are not limited to, molybdenum, tungsten, titanium, tantalum, platinum or hafnium. The above metal nitride may include, but is not limited to, molybdenum nitride, tungsten nitride, titanium nitride (titanium nitride) and tantalum nitride. The above conductive metal oxide may include, but is not limited to, ruthenium oxide and indium tin oxide.
在本發明一些實施例中，穿隧層106之厚度可為約2nm至約200nm，例如為約5nm至約150nm，或約10nm至約100nm，或約30nm至約80nm。且穿隧層106可直接接觸電荷層108。 In some embodiments of the invention, the tunneling layer 106 may have a thickness of from about 2 nm to about 200 nm, such as from about 5 nm to about 150 nm, or from about 10 nm to about 100 nm, or from about 30 nm to about 80 nm. And the tunneling layer 106 can directly contact the charge layer 108.
在本發明一些實施例中，電荷層108之厚度可為約2nm至約200nm，例如為約5nm至約150nm，或約10nm至約100nm，或約30nm至約80nm。且電荷層108可直接接觸第一氧化矽層110A。 In some embodiments of the invention, the charge layer 108 may have a thickness of from about 2 nm to about 200 nm, such as from about 5 nm to about 150 nm, or from about 10 nm to about 100 nm, or from about 30 nm to about 80 nm. And the charge layer 108 can directly contact the first tantalum oxide layer 110A.
在本發明一些實施例中，第一氧化矽層110A之厚度可為約2nm至約200nm，例如為約5nm至約150nm，或約10nm至約100nm，或約30nm至約80nm。且第一氧化矽層110A可直接接觸第一閘極線112A。在本發明一些實施例中，此第一閘極線112A之厚度可為約50nm至約2000nm，例如為約100nm至約500nm，且此第一閘極線112A之厚度大於穿隧層106之厚度、電荷層108之厚度或第一氧化矽層110A之厚度。 In some embodiments of the invention, the first hafnium oxide layer 110A may have a thickness of from about 2 nm to about 200 nm, such as from about 5 nm to about 150 nm, or from about 10 nm to about 100 nm, or from about 30 nm to about 80 nm. And the first hafnium oxide layer 110A can directly contact the first gate line 112A. In some embodiments of the present invention, the first gate line 112A may have a thickness of about 50 nm to about 2000 nm, for example, about 100 nm to about 500 nm, and the thickness of the first gate line 112A is greater than the thickness of the tunneling layer 106. The thickness of the charge layer 108 or the thickness of the first tantalum oxide layer 110A.
在本發明一些實施例中，第一堆疊結構104A可藉由下述步驟形成。首先，藉由化學氣相沉積法(CVD)或旋轉塗佈法於基板102之上表面102S上依序毯覆性沈積穿隧材料層(用以形成穿隧層106)、電荷材料層(用以形成電荷層108)、及第一氧化矽材料層(用以形成第一氧化矽層110A)。此化學氣相沉積法例如可為低壓化學氣相沉積法(low pressure chemical vapor deposition，LPCVD)、低溫化學氣相沉積法(low temperature chemical vapor deposition，LTCVD)、快速升溫化學氣相沉積法(rapid thermal chemical vapor deposition，RTCVD)、電漿輔助化學氣相沉積法(plasma enhanced chemical vapor deposition，PECVD)、原子層化學氣相沉積法之原子層沉積法(atomic layer deposition，ALD)或其它常用的方法。 In some embodiments of the invention, the first stack structure 104A can be formed by the following steps. First, a tunneling material layer (to form the tunneling layer 106) and a layer of charge material are sequentially deposited on the upper surface 102S of the substrate 102 by chemical vapor deposition (CVD) or spin coating. To form a charge layer 108), and a first layer of ruthenium oxide material (to form the first ruthenium oxide layer 110A). The chemical vapor deposition method can be, for example, low pressure chemical vapor deposition (low pressure chemical) Vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (plasma enhanced) Chemical vapor deposition (PECVD), atomic layer deposition (ALD) or other commonly used methods.
在本發明一些實施例中，可藉由於上述化學氣相沉積步驟中調控各氣體之比例，以調控穿隧材料層(用以形成穿隧層106)中SixOyNz之x、y、z比例，亦即調控穿隧層106中矽、氧及氮之比例。此外，亦可藉由於上述化學氣相沉積步驟中調控各氣體之比例，以調控電荷材料層(用以形成電荷層108)中SiaNb之a、b比例，亦即調控電荷層108中矽及氮之比例。 In some embodiments of the present invention, the ratio of each gas in the chemical vapor deposition step may be adjusted to adjust the x, y of the Si x O y N z in the tunneling material layer (to form the tunneling layer 106). The z ratio, that is, the ratio of enthalpy, oxygen, and nitrogen in the tunneling layer 106. In addition, by adjusting the ratio of each gas in the chemical vapor deposition step to adjust the ratio of a and b of Si a N b in the charge material layer (to form the charge layer 108 ), that is, to regulate the charge layer 108 The ratio of strontium to nitrogen.
接著，再於第一氧化矽材料層上毯覆性沈積第一閘極線材料層(用以形成第一閘極線112A)。可藉由前述之化學氣相沉積法(CVD)、濺鍍法、電阻加熱蒸鍍法、電子束蒸鍍法、或其它任何適合的沈積方式形成此第一閘極線材料層，例如，在一實施例中，可用低壓化學氣相沈積法(LPCVD)在525~650℃之間沈積而製得複晶矽導電材料層，其厚度範圍可為約1000Å至約10000Å。 Next, a first gate line material layer is formed on the first yttria material layer (to form the first gate line 112A). The first gate line material layer may be formed by the aforementioned chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition method, for example, In one embodiment, a polycrystalline germanium conductive material layer may be deposited by low pressure chemical vapor deposition (LPCVD) at a temperature between 525 and 650 ° C, and may have a thickness ranging from about 1000 Å to about 10,000 Å.
接著，藉由一或多道蝕刻步驟蝕刻上述第一閘極線材料層、第一氧化矽材料層、電荷材料層、及穿隧材料層以形成第一閘極線112A、第一氧化矽層110A、電荷層108、及穿隧層106。 Then, the first gate line material layer, the first hafnium oxide material layer, the charge material layer, and the tunneling material layer are etched by one or more etching steps to form the first gate line 112A and the first hafnium oxide layer. 110A, charge layer 108, and tunneling layer 106.
上述蝕刻步驟包括乾蝕刻、濕蝕刻或上述之組 合。此濕蝕刻可包括浸洗蝕刻(immersion etching)、噴洗蝕刻(spray etching)、上述之組合、或其它適合之乾蝕刻。此乾蝕刻步驟包括電容耦合電漿蝕刻、感應耦合型電漿蝕刻、螺旋電漿蝕刻、電子迴旋共振電漿蝕刻、上述之組合、或其它適合之乾蝕刻。此乾蝕刻步驟使用的氣體可包括惰性氣體、含氟氣體、含氯氣體、含溴氣體、含碘氣體、上述氣體之組合或其它任何適合的氣體。在一些實施例中，此乾蝕刻步驟使用的氣體包括Ar、CF4、SF6、CH2F2、CHF3、C2F6、Cl2、CHCl3、CCl4、HBr、CHBr3、BF3、BCl3、上述氣體之組合或其它任何適合的氣體。 The above etching steps include dry etching, wet etching, or a combination thereof. This wet etch can include immersion etching, spray etching, combinations of the above, or other suitable dry etch. The dry etching step includes capacitively coupled plasma etching, inductively coupled plasma etching, spiral plasma etching, electron cyclotron resonance plasma etching, combinations of the foregoing, or other suitable dry etching. The gas used in this dry etching step may include an inert gas, a fluorine-containing gas, a chlorine-containing gas, a bromine-containing gas, an iodine-containing gas, a combination of the above gases, or any other suitable gas. In some embodiments, the gas used in the dry etching step includes Ar, CF 4 , SF 6 , CH 2 F 2 , CHF 3 , C 2 F 6 , Cl 2 , CHCl 3 , CCl 4 , HBr, CHBr 3 , BF. 3. BCl 3 , a combination of the above gases or any other suitable gas.
接著，繼續參見第1圖，形成源極線摻雜區114於基板102中，且此源極線摻雜區114位於第一堆疊結構104A之第一側S1。此源極線摻雜區114具有第二導電型，且此第二導電型與基板102之第一導電型不同。例如，在本發明一些實施例中，第一導電型為P型，而第二導電型為N型。然而，在本發明其它一些實施例中，第一導電型為N型，而第二導電型為P型。 Next, referring to FIG. 1, a source line doping region 114 is formed in the substrate 102, and the source line doping region 114 is located on the first side S1 of the first stacked structure 104A. The source line doping region 114 has a second conductivity type, and the second conductivity type is different from the first conductivity type of the substrate 102. For example, in some embodiments of the invention, the first conductivity type is a P type and the second conductivity type is an N type. However, in other embodiments of the invention, the first conductivity type is an N type and the second conductivity type is a P type.
繼續參見第1圖，此源極線摻雜區114包括設於基板102中之輕摻雜區114A，以及與此輕摻雜區114A部分重疊之重摻雜區114B。 Continuing to refer to FIG. 1, the source line doped region 114 includes a lightly doped region 114A disposed in the substrate 102, and a heavily doped region 114B partially overlapping the lightly doped region 114A.
在本發明一些實施例中，此輕摻雜區114A之摻雜濃度為約1011-1013/cm3，例如為約1012/cm3。而此重摻雜區114B之摻雜濃度超過約1013/cm3，例如為約1015/cm3至約1017/cm3。 In some embodiments of the invention, the lightly doped region 114A has a doping concentration of about 10 11 -10 13 /cm 3 , for example about 10 12 /cm 3 . The doping concentration of the heavily doped region 114B exceeds about 10 13 /cm 3 , for example, from about 10 15 /cm 3 to about 10 17 /cm 3 .
在本發明一些實施例中，此源極線摻雜區114可藉由離子佈植步驟形成。例如，當此第二導電型為N型時，可於 預定形成源極線摻雜區114之區域佈植磷離子或砷離子以形成源極線摻雜區114。而當此第二導電型為P型時，可於預定形成源極線摻雜區114之區域佈植硼離子、銦離子或二氟化硼離子(BF2 +)以形成源極線摻雜區114。 In some embodiments of the invention, the source line doping region 114 can be formed by an ion implantation step. For example, when the second conductivity type is an N-type, phosphorus ions or arsenic ions may be implanted in a region where the source line doping region 114 is predetermined to form the source line doping region 114. When the second conductivity type is a P-type, boron ions, indium ions or boron difluoride ions (BF 2 + ) may be implanted in a region where the source line doping region 114 is to be formed to form a source line doping. Area 114.
繼續參見第1圖，在本發明一些實施例中，輕摻雜區114A延伸至第一堆疊結構104A之底面104AS下，且直接接觸此第一堆疊結構104A之底面104AS。在本發明一些實施例中，而重摻雜區114B與此輕摻雜區114A部分重疊，且重摻雜區114B之深度大於輕摻雜區114A之深度。 Continuing to refer to FIG. 1, in some embodiments of the invention, the lightly doped region 114A extends under the bottom surface 104AS of the first stacked structure 104A and directly contacts the bottom surface 104AS of the first stacked structure 104A. In some embodiments of the invention, the heavily doped region 114B partially overlaps the lightly doped region 114A, and the depth of the heavily doped region 114B is greater than the depth of the lightly doped region 114A.
此外，在本發明一些實施例中，重摻雜區114B不延伸至第一堆疊結構104A之底面104AS下，亦言之，重摻雜區114B不接觸第一堆疊結構104A之底面104AS。此外，在本發明一些實施例中，重摻雜區114B之一邊緣114BE1與第一堆疊結構104A之第一邊緣E1對齊。 Moreover, in some embodiments of the invention, the heavily doped regions 114B do not extend under the bottom surface 104AS of the first stacked structure 104A, and in other words, the heavily doped regions 114B do not contact the bottom surface 104AS of the first stacked structure 104A. Moreover, in some embodiments of the invention, one of the edges 114BE1 of the heavily doped region 114B is aligned with the first edge E1 of the first stacked structure 104A.
接著，繼續參見第1圖，形成位元線摻雜區116於基板102中，且此位元線摻雜區116位於第一堆疊結構104A之第二側S2。此位元線摻雜區116具有第二導電型，且此第二導電型與基板102之第一導電型不同。例如，在本發明一些實施例中，第一導電型為P型，而第二導電型為N型。然而，在本發明其它一些實施例中，第一導電型為N型，而第二導電型為P型。 Next, referring to FIG. 1, a bit line doped region 116 is formed in the substrate 102, and the bit line doped region 116 is located on the second side S2 of the first stacked structure 104A. The bit line doping region 116 has a second conductivity type, and the second conductivity type is different from the first conductivity type of the substrate 102. For example, in some embodiments of the invention, the first conductivity type is a P type and the second conductivity type is an N type. However, in other embodiments of the invention, the first conductivity type is an N type and the second conductivity type is a P type.
繼續參見第1圖，此位元線摻雜區116包括設於基板102中之輕摻雜區116A，以及與此輕摻雜區116A部分重疊之重摻雜區116B。 Continuing to refer to FIG. 1, the bit line doped region 116 includes a lightly doped region 116A disposed in the substrate 102, and a heavily doped region 116B partially overlapping the lightly doped region 116A.
在本發明一些實施例中，此輕摻雜區116A之摻雜 濃度為約1011-1013/cm3，例如為約1012/cm3。而此重摻雜區116B之摻雜濃度超過約1013/cm3，例如為約1015/cm3至約1017/cm3。 In some embodiments of the invention, the lightly doped region 116A has a doping concentration of about 10 11 -10 13 /cm 3 , for example about 10 12 /cm 3 . The doping concentration of the heavily doped region 116B exceeds about 10 13 /cm 3 , for example, from about 10 15 /cm 3 to about 10 17 /cm 3 .
在本發明一些實施例中，此位元線摻雜區116可藉由離子佈植步驟形成。例如，當此第二導電型為N型時，可於預定形成位元線摻雜區116之區域佈植磷離子或砷離子以形成位元線摻雜區116。而當此第二導電型為P型時，可於預定形成位元線摻雜區116之區域佈植硼離子、銦離子或二氟化硼離子(BF2 +)以形成位元線摻雜區116。此外，在本發明一些實施例中，此位元線摻雜區116與上述源極線摻雜區114可於同一道製程步驟中形成。 In some embodiments of the invention, the bit line doped region 116 can be formed by an ion implantation step. For example, when the second conductivity type is N-type, phosphorus ions or arsenic ions may be implanted in a region where the bit line doping region 116 is predetermined to form a bit line doping region 116. When the second conductivity type is P-type, boron ions, indium ions or boron difluoride ions (BF 2 + ) may be implanted in a region where the bit line doping region 116 is predetermined to form a bit line doping. Area 116. In addition, in some embodiments of the present invention, the bit line doping region 116 and the source line doping region 114 may be formed in the same process step.
繼續參見第1圖，在本發明一些實施例中，輕摻雜區116A延伸至第一堆疊結構104A之底面104AS下，且直接接觸此第一堆疊結構104A之底面104AS。在本發明一些實施例中，而重摻雜區116B與此輕摻雜區116A部分重疊，且重摻雜區116B之深度大於輕摻雜區116A之深度。 Continuing to refer to FIG. 1, in some embodiments of the invention, the lightly doped region 116A extends under the bottom surface 104AS of the first stacked structure 104A and directly contacts the bottom surface 104AS of the first stacked structure 104A. In some embodiments of the invention, the heavily doped region 116B partially overlaps the lightly doped region 116A, and the depth of the heavily doped region 116B is greater than the depth of the lightly doped region 116A.
此外，在本發明一些實施例中，重摻雜區116B不延伸至第一堆疊結構104A之底面104AS下，亦言之，重摻雜區116B不接觸第一堆疊結構104A之底面104AS。此外，在本發明一些實施例中，重摻雜區116B之一邊緣116BE1與第一堆疊結構104A之第二邊緣E2對齊。 Moreover, in some embodiments of the invention, the heavily doped regions 116B do not extend under the bottom surface 104AS of the first stacked structure 104A, and in other words, the heavily doped regions 116B do not contact the bottom surface 104AS of the first stacked structure 104A. Moreover, in some embodiments of the invention, one of the edges 116BE1 of the heavily doped region 116B is aligned with the second edge E2 of the first stacked structure 104A.
第2圖係本發明另外一些實施例之記憶體裝置200之剖面圖。如第2圖所示，可於基板102之上表面102S上更進一步形成一第二堆疊結構104B，且此第二堆疊結構104B位於第一堆疊結構104A之第一側S1。 Figure 2 is a cross-sectional view of a memory device 200 in accordance with still other embodiments of the present invention. As shown in FIG. 2, a second stacked structure 104B may be further formed on the upper surface 102S of the substrate 102, and the second stacked structure 104B is located on the first side S1 of the first stacked structure 104A.
如第2圖所示，此第二堆疊結構104B包括設於基板102之上表面102S上之第二氧化矽層110B，以及設於第二氧化矽層110B上之第二閘極線112B。此第二氧化矽層110B及第二閘極線112B可藉由類似前述之步驟形成。亦即，在本發明一些實施例中，第二氧化矽層110B可藉由化學氣相沉積法(CVD)或旋轉塗佈法形成，而第二閘極線112B可藉由化學氣相沉積法(CVD)、濺鍍法、電阻加熱蒸鍍法、電子束蒸鍍法、或其它任何適合的沈積方式形成。 As shown in FIG. 2, the second stack structure 104B includes a second hafnium oxide layer 110B disposed on the upper surface 102S of the substrate 102, and a second gate line 112B disposed on the second hafnium oxide layer 110B. The second hafnium oxide layer 110B and the second gate line 112B can be formed by steps similar to those described above. That is, in some embodiments of the present invention, the second hafnium oxide layer 110B may be formed by chemical vapor deposition (CVD) or spin coating, and the second gate line 112B may be formed by chemical vapor deposition. (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition method.
此外，在本發明一些實施例中，此第二氧化矽層110B之厚度大抵上與第一堆疊結構104A之穿隧層106、電荷層108、及第一氧化矽層110A之總厚度相同。 In addition, in some embodiments of the present invention, the thickness of the second hafnium oxide layer 110B is substantially the same as the total thickness of the tunneling layer 106, the charge layer 108, and the first hafnium oxide layer 110A of the first stacked structure 104A.
此外，此第二堆疊結構104B具有相反之第三側S3及第四側S4，且此第三側S3係面對第一堆疊結構104A之第一側S1。此第二堆疊結構104B於第三側S3具有一第三邊緣E3，於第四側S4具有一第四邊緣E4。 In addition, the second stack structure 104B has opposite third side S3 and fourth side S4, and the third side S3 faces the first side S1 of the first stack structure 104A. The second stack structure 104B has a third edge E3 on the third side S3 and a fourth edge E4 on the fourth side S4.
此外，在本發明一些實施例中，如第2圖所示，位於第一堆疊結構104A之第一側S1的源極線摻雜區114由第一堆疊結構104A之底面104AS延伸至第二堆疊結構104B之底面104BS。因此，在本發明一些實施例中，此源極線摻雜區114亦是作為第二堆疊結構104B之位元線摻雜區。 Moreover, in some embodiments of the present invention, as shown in FIG. 2, the source line doping region 114 on the first side S1 of the first stacked structure 104A extends from the bottom surface 104AS of the first stacked structure 104A to the second stack. The bottom surface 104BS of the structure 104B. Therefore, in some embodiments of the invention, the source line doping region 114 is also a bit line doping region of the second stack structure 104B.
詳細而言，源極線摻雜區114之輕摻雜區114A由第一堆疊結構104A鄰近第一側S1的底面104AS延伸至第二堆疊結構104B鄰近第三側S3的底面104BS。且此輕摻雜區114A直接接觸第一堆疊結構104A之底面104AS及第二堆疊結構104B之 底面104BS。 In detail, the lightly doped region 114A of the source line doping region 114 extends from the bottom surface 104AS of the first stack structure 104A adjacent to the first side S1 to the bottom surface 104BS of the second stack structure 104B adjacent to the third side S3. The lightly doped region 114A directly contacts the bottom surface 104AS of the first stacked structure 104A and the second stacked structure 104B. The bottom surface 104BS.
此外，源極線摻雜區114之重摻雜區114B不延伸至第一堆疊結構104A之底面104AS下及第二堆疊結構104B之底面104BS下。亦言之，重摻雜區114B不接觸第一堆疊結構104A之底面104AS及第二堆疊結構104B之底面104BS。此外，在本發明一些實施例中，重摻雜區114B之一邊緣114BE1與第一堆疊結構104A之第一邊緣E1對齊，而另一邊緣114BE2與第二堆疊結構104B之第三邊緣E3對齊。 In addition, the heavily doped region 114B of the source line doping region 114 does not extend under the bottom surface 104AS of the first stacked structure 104A and under the bottom surface 104BS of the second stacked structure 104B. In other words, the heavily doped region 114B does not contact the bottom surface 104AS of the first stacked structure 104A and the bottom surface 104BS of the second stacked structure 104B. Moreover, in some embodiments of the invention, one edge 114BE1 of heavily doped region 114B is aligned with first edge E1 of first stacked structure 104A, while the other edge 114BE2 is aligned with third edge E3 of second stacked structure 104B.
此外，記憶體裝置200可更包括設於基板102中的源極線摻雜區118，且此源極線摻雜區118位於第二堆疊結構104B之第四側S4。此源極線摻雜區118具有第二導電型，且此第二導電型與基板102之第一導電型不同。例如，在本發明一些實施例中，第一導電型為P型，而第二導電型為N型。然而，在本發明其它一些實施例中，第一導電型為N型，而第二導電型為P型。 In addition, the memory device 200 may further include a source line doping region 118 disposed in the substrate 102, and the source line doping region 118 is located on the fourth side S4 of the second stack structure 104B. The source line doping region 118 has a second conductivity type, and the second conductivity type is different from the first conductivity type of the substrate 102. For example, in some embodiments of the invention, the first conductivity type is a P type and the second conductivity type is an N type. However, in other embodiments of the invention, the first conductivity type is an N type and the second conductivity type is a P type.
繼續參見第1圖，此源極線摻雜區118包括設於基板102中之輕摻雜區118A，以及與此輕摻雜區118A部分重疊之重摻雜區118B。 Continuing to refer to FIG. 1, the source line doped region 118 includes a lightly doped region 118A disposed in the substrate 102 and a heavily doped region 118B partially overlapping the lightly doped region 118A.
在本發明一些實施例中，此輕摻雜區118A之摻雜濃度為約1011-1013/cm3，例如為約1012/cm3。而此重摻雜區118B之摻雜濃度超過約1013/cm3，例如為約1015/cm3至約1017/cm3。 In some embodiments of the invention, the lightly doped region 118A has a doping concentration of about 10 11 -10 13 /cm 3 , for example about 10 12 /cm 3 . The doping concentration of the heavily doped region 118B exceeds about 10 13 /cm 3 , for example, from about 10 15 /cm 3 to about 10 17 /cm 3 .
在本發明一些實施例中，此源極線摻雜區118可藉由離子佈植步驟形成。例如，當此第二導電型為N型時，可於預定形成源極線摻雜區118之區域佈植磷離子或砷離子以形成 源極線摻雜區118。而當此第二導電型為P型時，可於預定形成源極線摻雜區118之區域佈植硼離子、銦離子或二氟化硼離子(BF2 +)以形成源極線摻雜區118。 In some embodiments of the invention, the source line doping region 118 can be formed by an ion implantation step. For example, when the second conductivity type is N-type, phosphorus ions or arsenic ions may be implanted in a region where the source line doping region 118 is to be formed to form the source line doping region 118. When the second conductivity type is a P-type, boron ions, indium ions or boron difluoride ions (BF 2 + ) may be implanted in a region where the source line doping region 118 is to be formed to form a source line doping. District 118.
繼續參見第1圖，在本發明一些實施例中，輕摻雜區118A延伸至第二堆疊結構104B之底面104BS下，且直接接觸此第二堆疊結構104B之底面104BS。在本發明一些實施例中，而重摻雜區118B與此輕摻雜區118A部分重疊，且重摻雜區118B之深度大於輕摻雜區118A之深度。 Continuing to refer to FIG. 1, in some embodiments of the invention, the lightly doped region 118A extends below the bottom surface 104BS of the second stacked structure 104B and directly contacts the bottom surface 104BS of the second stacked structure 104B. In some embodiments of the invention, the heavily doped region 118B partially overlaps the lightly doped region 118A, and the depth of the heavily doped region 118B is greater than the depth of the lightly doped region 118A.
此外，在本發明一些實施例中，重摻雜區118B不延伸至第二堆疊結構104B之底面104BS下，亦言之，重摻雜區118B不接觸第二堆疊結構104B之底面104BS。此外，在本發明一些實施例中，重摻雜區118B之一邊緣118BE1與第二堆疊結構104B之第四邊緣E4對齊。 Moreover, in some embodiments of the invention, the heavily doped region 118B does not extend under the bottom surface 104BS of the second stacked structure 104B, and in other words, the heavily doped region 118B does not contact the bottom surface 104BS of the second stacked structure 104B. Moreover, in some embodiments of the invention, one edge 118BE1 of heavily doped region 118B is aligned with a fourth edge E4 of second stacked structure 104B.
在此實施例中，藉由形成此第二堆疊結構104B，可增加流經第一堆疊結構104A之電流量，故可使周邊電路更容易被驅動。 In this embodiment, by forming the second stack structure 104B, the amount of current flowing through the first stack structure 104A can be increased, so that the peripheral circuits can be driven more easily.
第3圖係本發明另外一些實施例之記憶體裝置300之剖面圖。如第3圖所示，可於基板102之上表面102S上更進一步形成一第三堆疊結構104C，且此第三堆疊結構104C位於第一堆疊結構104A之第二側S2。 Figure 3 is a cross-sectional view of a memory device 300 in accordance with still other embodiments of the present invention. As shown in FIG. 3, a third stacked structure 104C may be further formed on the upper surface 102S of the substrate 102, and the third stacked structure 104C is located on the second side S2 of the first stacked structure 104A.
如第3圖所示，此第三堆疊結構104C包括設於基板102之上表面102S上之第三氧化矽層110C，以及設於第三氧化矽層110C上之第三閘極線112C。此第三氧化矽層110C及第三閘極線112C可藉由類似前述之步驟形成。亦即，在本發明一些 實施例中，第三氧化矽層110C可藉由化學氣相沉積法(CVD)或旋轉塗佈法形成，而第三閘極線112C可藉由化學氣相沉積法(CVD)、濺鍍法、電阻加熱蒸鍍法、電子束蒸鍍法、或其它任何適合的沈積方式形成。 As shown in FIG. 3, the third stack structure 104C includes a third hafnium oxide layer 110C disposed on the upper surface 102S of the substrate 102, and a third gate line 112C disposed on the third hafnium oxide layer 110C. The third hafnium oxide layer 110C and the third gate line 112C can be formed by steps similar to those described above. That is, in the present invention In an embodiment, the third hafnium oxide layer 110C may be formed by chemical vapor deposition (CVD) or spin coating, and the third gate line 112C may be formed by chemical vapor deposition (CVD) or sputtering. Formed by resistance heating evaporation, electron beam evaporation, or any other suitable deposition method.
且在本發明一些實施例中，此第三氧化矽層110C之厚度大抵上與第一堆疊結構104A之穿隧層106、電荷層108、及第一氧化矽層110A之總厚度相同。 In some embodiments of the present invention, the thickness of the third hafnium oxide layer 110C is substantially the same as the total thickness of the tunneling layer 106, the charge layer 108, and the first hafnium oxide layer 110A of the first stacked structure 104A.
此外，此第三堆疊結構104C具有相反之第五側S5及第六側S6，且此第五側S5係面對第一堆疊結構104A之第二側S2。此第三堆疊結構104C於第五側S5具有一第五邊緣E5，於第六側S6具有一第六邊緣E6。 In addition, the third stack structure 104C has opposite fifth side S5 and sixth side S6, and the fifth side S5 faces the second side S2 of the first stack structure 104A. The third stack structure 104C has a fifth edge E5 on the fifth side S5 and a sixth edge E6 on the sixth side S6.
此外，在本發明一些實施例中，如第3圖所示，位於第一堆疊結構104A之第二側S2的位元線摻雜區116由第一堆疊結構104A之底面104AS延伸至第三堆疊結構104C之底面104CS。因此，在本發明一些實施例中，此位元線摻雜區116亦是作為第三堆疊結構104C之源極線摻雜區。 Moreover, in some embodiments of the present invention, as shown in FIG. 3, the bit line doped region 116 on the second side S2 of the first stacked structure 104A extends from the bottom surface 104AS of the first stacked structure 104A to the third stack. The bottom surface 104CS of the structure 104C. Thus, in some embodiments of the invention, the bit line doped region 116 is also the source line doped region of the third stacked structure 104C.
詳細而言，位元線摻雜區116之輕摻雜區116A由第一堆疊結構104A鄰近第二側S2的底面104AS延伸至第三堆疊結構104C鄰近第五側S5的底面104CS。且此輕摻雜區116A直接接觸第一堆疊結構104A之底面104AS及第三堆疊結構104C之底面104CS。 In detail, the lightly doped region 116A of the bit line doped region 116 extends from the bottom surface 104AS of the first stack structure 104A adjacent to the second side S2 to the bottom surface 104CS of the third stack structure 104C adjacent to the fifth side S5. The lightly doped region 116A directly contacts the bottom surface 104AS of the first stacked structure 104A and the bottom surface 104CS of the third stacked structure 104C.
此外，位元線摻雜區116之重摻雜區116B不延伸至第一堆疊結構104A之底面104AS下及第三堆疊結構104C之底面104CS下。亦言之，重摻雜區116B不接觸第一堆疊結構104A 之底面104AS及第三堆疊結構104C之底面104CS。此外，在本發明一些實施例中，重摻雜區116B之一邊緣116BE1與第一堆疊結構104A之第一邊緣E1對齊，而另一邊緣116BE2與第三堆疊結構104C之第五邊緣E5對齊。 In addition, the heavily doped region 116B of the bit line doped region 116 does not extend under the bottom surface 104AS of the first stacked structure 104A and under the bottom surface 104CS of the third stacked structure 104C. In other words, the heavily doped region 116B does not contact the first stacked structure 104A. The bottom surface 104AS and the bottom surface 104CS of the third stack structure 104C. Moreover, in some embodiments of the invention, one edge 116BE1 of heavily doped region 116B is aligned with first edge E1 of first stacked structure 104A, while the other edge 116BE2 is aligned with fifth edge E5 of third stacked structure 104C.
此外，記憶體裝置300可更包括設於基板102中的位元線摻雜區120，且此位元線摻雜區120位於第三堆疊結構104C之第六側S6。此位元線摻雜區120具有第二導電型，且此第二導電型與基板102之第一導電型不同。例如，在本發明一些實施例中，第一導電型為P型，而第二導電型為N型。然而，在本發明其它一些實施例中，第一導電型為N型，而第二導電型為P型。 In addition, the memory device 300 may further include a bit line doping region 120 disposed in the substrate 102, and the bit line doping region 120 is located on the sixth side S6 of the third stacked structure 104C. The bit line doping region 120 has a second conductivity type, and the second conductivity type is different from the first conductivity type of the substrate 102. For example, in some embodiments of the invention, the first conductivity type is a P type and the second conductivity type is an N type. However, in other embodiments of the invention, the first conductivity type is an N type and the second conductivity type is a P type.
繼續參見第1圖，此位元線摻雜區120包括設於基板102中之輕摻雜區120A，以及與此輕摻雜區120A部分重疊之重摻雜區120B。 Continuing to refer to FIG. 1, the bit line doped region 120 includes a lightly doped region 120A disposed in the substrate 102, and a heavily doped region 120B partially overlapping the lightly doped region 120A.
在本發明一些實施例中，此輕摻雜區120A之摻雜濃度為約1011-1013/cm3，例如為約1012/cm3。而此重摻雜區120B之摻雜濃度超過約1013/cm3，例如為約1015/cm3至約1017/cm3。 In some embodiments of the invention, the lightly doped region 120A has a doping concentration of about 10 11 -10 13 /cm 3 , such as about 10 12 /cm 3 . The doping concentration of the heavily doped region 120B exceeds about 10 13 /cm 3 , for example, from about 10 15 /cm 3 to about 10 17 /cm 3 .
在本發明一些實施例中，此位元線摻雜區120可藉由離子佈植步驟形成。例如，當此第二導電型為N型時，可於預定形成位元線摻雜區120之區域佈植磷離子或砷離子以形成位元線摻雜區120。而當此第二導電型為P型時，可於預定形成位元線摻雜區120之區域佈植硼離子、銦離子或二氟化硼離子(BF2 +)以形成位元線摻雜區120。 In some embodiments of the invention, the bit line doped region 120 can be formed by an ion implantation step. For example, when the second conductivity type is N-type, phosphorus ions or arsenic ions may be implanted in a region where the bit line doping region 120 is predetermined to form a bit line doping region 120. When the second conductivity type is P-type, boron ions, indium ions or boron difluoride ions (BF 2 + ) may be implanted in a region where the bit line doping region 120 is predetermined to form a bit line doping. Area 120.
繼續參見第1圖，在本發明一些實施例中，輕摻雜 區120A延伸至第三堆疊結構104C之底面104CS下，且直接接觸此第三堆疊結構104C之底面104CS。在本發明一些實施例中，而重摻雜區120B與此輕摻雜區120A部分重疊，且重摻雜區120B之深度大於輕摻雜區120A之深度。 With continued reference to Figure 1, in some embodiments of the invention, lightly doped The region 120A extends below the bottom surface 104CS of the third stacked structure 104C and directly contacts the bottom surface 104CS of the third stacked structure 104C. In some embodiments of the invention, the heavily doped region 120B partially overlaps the lightly doped region 120A, and the depth of the heavily doped region 120B is greater than the depth of the lightly doped region 120A.
此外，在本發明一些實施例中，重摻雜區120B不延伸至第三堆疊結構104C之底面104CS下，亦言之，重摻雜區120B不接觸第三堆疊結構104C之底面104CS。此外，在本發明一些實施例中，重摻雜區120B之一邊緣120BE1與第三堆疊結構104C之第六邊緣E6對齊。 Moreover, in some embodiments of the invention, the heavily doped region 120B does not extend under the bottom surface 104CS of the third stacked structure 104C, and in other words, the heavily doped region 120B does not contact the bottom surface 104CS of the third stacked structure 104C. Moreover, in some embodiments of the invention, one edge 120BE1 of heavily doped region 120B is aligned with a sixth edge E6 of third stacked structure 104C.
在此實施例中，藉由形成此第三堆疊結構104C，可更進一步增加流經第一堆疊結構104A之電流量，故可使周邊電路更容易被驅動。 In this embodiment, by forming the third stacked structure 104C, the amount of current flowing through the first stacked structure 104A can be further increased, so that the peripheral circuits can be more easily driven.
繼續參見第1-3圖，記憶體裝置100-300可包括基板102，與設於基板102之上表面102S上之第一堆疊結構104A。此第一堆疊結構104A具有相反之第一側S1及第二側S2，且包括設於基板102之上表面102S上之穿隧層106，且此穿隧層106包括SixOyNz，且x：y為1：0.1至1：10，而x：z為1：0.1至1：10。此第一堆疊結構104A更包括設於穿隧層106上之電荷層108、設於電荷層108上之第一氧化矽層110A、及設於第一氧化矽層110A上之第一閘極線112A。此外，記憶體裝置100-300更包括設於基板102中且位於第一堆疊結構104A之第一側S1之源極線摻雜區114，以及設於基板102中且位於第一堆疊結構104A之第二側S2之位元線摻雜區116。 Continuing to Figures 1-3, the memory device 100-300 can include a substrate 102 and a first stack structure 104A disposed on the upper surface 102S of the substrate 102. The first stacked structure 104A has opposite first side S1 and second side S2, and includes a tunneling layer 106 disposed on the upper surface 102S of the substrate 102, and the tunneling layer 106 includes Si x O y N z , And x:y is 1:0.1 to 1:10, and x:z is 1:0.1 to 1:10. The first stacked structure 104A further includes a charge layer 108 disposed on the tunneling layer 106, a first germanium oxide layer 110A disposed on the charge layer 108, and a first gate line disposed on the first germanium oxide layer 110A. 112A. In addition, the memory device 100-300 further includes a source line doping region 114 disposed in the substrate 102 and located on the first side S1 of the first stacked structure 104A, and disposed in the substrate 102 and located in the first stacked structure 104A. The bit line doped region 116 of the second side S2.
此外，記憶體裝置200-300更包括設於基板102之上 表面102S上，且位於第一堆疊結構104A之第一側S1之第二堆疊結構104B。此第二堆疊結構104B包括設於基板102之上表面102S上之第二氧化矽層110B，以及設於第二氧化矽層110B上之第二閘極線112B。 In addition, the memory device 200-300 further includes a substrate 102 On the surface 102S, and located in the second stack structure 104B of the first side S1 of the first stacked structure 104A. The second stack structure 104B includes a second hafnium oxide layer 110B disposed on the upper surface 102S of the substrate 102, and a second gate line 112B disposed on the second hafnium oxide layer 110B.
此外，記憶體裝置300更包括設於基板102之上表面102S上，且位於第一堆疊結構104A之第二側S2之第三堆疊結構104C。此第三堆疊結構104C包括設於基板102之上表面102S上之第三氧化矽層110C，以及設於第三氧化矽層110C上之第三閘極線112C。 In addition, the memory device 300 further includes a third stacked structure 104C disposed on the upper surface 102S of the substrate 102 and located on the second side S2 of the first stacked structure 104A. The third stack structure 104C includes a third hafnium oxide layer 110C disposed on the upper surface 102S of the substrate 102, and a third gate line 112C disposed on the third hafnium oxide layer 110C.
綜上所述，本發明一些實施例之記憶體裝置的資料儲存結構包括具有穿隧層、電荷層及氧化矽層之三層結構，且此穿隧層包括特定材料，故本發明一些實施例之記憶體裝置(例如非揮發性記憶體裝置)可更進一步降低資料寫入電壓、提升資料寫入速度、且可增加資料保存時間。 In summary, the data storage structure of the memory device of some embodiments of the present invention includes a three-layer structure having a tunneling layer, a charge layer, and a ruthenium oxide layer, and the tunneling layer includes a specific material, so some embodiments of the present invention The memory device (for example, a non-volatile memory device) can further reduce the data write voltage, increase the data writing speed, and increase the data storage time.
此外，應注意的是，熟習本技術領域之人士均深知，本發明實施例所述之位元線與源極線可互換，因其定義係與本身所連接的電壓位準有關。 In addition, it should be noted that those skilled in the art are well aware that the bit line and source line described in the embodiments of the present invention are interchangeable because their definition is related to the voltage level to which they are connected.
值得注意的是，以上所述之元件尺寸、元件參數、以及元件形狀皆非為本發明實施例之限制條件。此技術領域中具有通常知識者可以根據不同需要調整這些設定值。另外，本發明實施例之記憶體裝置及其製造方法並不僅限於第1-3圖所圖示之狀態。本發明實施例可以僅包括第1-3圖之任何一或複數個實施例之任何一或複數項特徵。換言之，並非所有圖示之特徵均須同時實施於本發明實施例之記憶體裝置及其製造方 法中。 It should be noted that the above-mentioned component sizes, component parameters, and component shapes are not limitations of the embodiments of the present invention. Those of ordinary skill in the art can adjust these settings according to different needs. Further, the memory device and the method of manufacturing the same according to the embodiments of the present invention are not limited to the state illustrated in FIGS. 1-3. The embodiments of the present invention may include only one or more of the features of any one or a plurality of embodiments of Figures 1-3. In other words, not all of the illustrated features must be simultaneously implemented in the memory device and its manufacturer of the embodiments of the present invention. In the law.
此外，雖然前文舉出各個摻雜區於一些實施例之摻雜濃度。然而，本領域具有通常知識者可瞭解的是，各個摻雜區之摻雜濃度可依照特定裝置型態、技術世代、最小元件尺寸等所決定。因此，各個摻雜區之摻雜濃度可依照技術內容重新評估，而不受限於在此所舉之實施例。 In addition, although the doping concentrations of the various doped regions in some embodiments are set forth above. However, it will be understood by those of ordinary skill in the art that the doping concentration of each doped region can be determined according to a particular device type, technology generation, minimum component size, and the like. Thus, the doping concentration of each doped region can be re-evaluated in accordance with the technical content without being limited to the embodiments presented herein.
雖然本發明的實施例及其優點已揭露如上，但應該瞭解的是，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。此外，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明實施例揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大抵相同功能或獲得大抵相同結果皆可根據本發明實施例使用。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。 Although the embodiments of the present invention and its advantages are disclosed above, it should be understood that those skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of the invention. In addition, the scope of the present invention is not limited to the processes, machines, manufactures, compositions, devices, methods and steps in the specific embodiments described in the specification, and any one of ordinary skill in the art can. The present disclosure understands the processes, machines, manufactures, compositions, devices, methods, and procedures that are presently or in the future, as long as they can perform substantially the same function or achieve substantially the same results in the embodiments described herein. The examples were used. Accordingly, the scope of the invention includes the above-described processes, machines, manufactures, compositions, devices, methods, and steps. In addition, the scope of each of the claims constitutes an individual embodiment, and the scope of the invention also includes the combination of the scope of the application and the embodiments.
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