TW201810458A - Package substrate and the manufacture thereof - Google Patents
Package substrate and the manufacture thereof Download PDFInfo
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- TW201810458A TW201810458A TW105115936A TW105115936A TW201810458A TW 201810458 A TW201810458 A TW 201810458A TW 105115936 A TW105115936 A TW 105115936A TW 105115936 A TW105115936 A TW 105115936A TW 201810458 A TW201810458 A TW 201810458A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
Abstract
Description
本發明係有關一種封裝基板，尤指一種具導電凸塊之封裝基板及其製法。 The invention relates to a packaging substrate, in particular to a packaging substrate with conductive bumps and a manufacturing method thereof.
隨著電子產業的發達，現今的電子產品已趨向輕薄短小與功能多樣化的方向設計，半導體封裝技術亦隨之開發出不同的封裝型態，其中，球柵陣列式(Ball grid array，簡稱BGA)封裝，為一種先進的半導體封裝技術，其特點在於採用一封裝基板來安置半導體元件，並於該封裝基板背面植置多數個成柵狀陣列排列之焊球(Solder ball)，並藉該些焊球將整個封裝單元銲結並電性連接至外部電子裝置，使相同單位面積之承載件上可容納更多輸入/輸出連接端(I/O connection)以符合高度集積化(Integration)之半導體晶片之需求。 With the development of the electronics industry, today's electronic products have tended to be light, thin, short, and functionally diversified. Semiconductor packaging technology has also developed different packaging types. Among them, ball grid array (BGA) ) Packaging is an advanced semiconductor packaging technology, which is characterized by using a packaging substrate to place semiconductor devices, and a plurality of solder balls arranged in a grid array are placed on the back of the packaging substrate, and these Solder balls solder the entire package unit and electrically connect it to an external electronic device, so that the same unit area of the carrier can accommodate more input/output connections (I/O connections) to meet the requirements of highly integrated semiconductors Demand for chips.
再者，為了符合半導體封裝件輕薄短小、多功能、高速度及高頻化的開發方向，晶片已朝向細線路及小孔徑發展。 Furthermore, in order to comply with the development direction of semiconductor packages that are light, thin, short, multi-functional, high-speed, and high-frequency, chips have been developed toward thin circuits and small apertures.
如第1圖所示，習知半導體封裝件1係將一半導體晶 片10與被動元件10’覆晶設於一封裝基板11上側，再於該封裝基板11下側植設複數焊球14。具體地，該半導體晶片10上設有銅凸塊(Cu pillar)101與焊錫凸塊100，以結合至該封裝基板11之電性連接墊110，再以底膠12包覆該銅凸塊101，且該被動元件10’藉由焊錫凸塊100結合至該封裝基板11之電性連接墊110。亦即，習知半導體封裝件1中需於該半導體晶片10上進行銅凸塊101之電鍍製程，以利於與該封裝基板11進行細線路間距(Fine bump pitch)之連接。 As shown in FIG. 1, the conventional semiconductor package 1 uses a semiconductor crystal The chip 10 and the passive element 10' flip chip are provided on the upper side of a package substrate 11, and a plurality of solder balls 14 are implanted on the lower side of the package substrate 11. Specifically, the semiconductor wafer 10 is provided with copper bumps 101 and solder bumps 100 for bonding to the electrical connection pads 110 of the packaging substrate 11, and then the copper bumps 101 are coated with the primer 12 And, the passive element 10' is bonded to the electrical connection pad 110 of the package substrate 11 through the solder bump 100. That is to say, in the conventional semiconductor package 1, an electroplating process of copper bumps 101 needs to be performed on the semiconductor chip 10 to facilitate fine bump pitch connection with the packaging substrate 11.
然而，於該半導體晶片10上製作該銅凸塊101之製程成本高，不利於生產。 However, the manufacturing cost of manufacturing the copper bump 101 on the semiconductor wafer 10 is high, which is not conducive to production.
再者，於半導體晶片10之表面上電鍍形成該些銅凸塊101時，由於該些銅凸塊101之高度控制不易，若該些銅凸塊101之高度彼此不同，將使該些銅凸塊101所排列成之柵狀陣列(grid array)產生共面性(coplanarity)不良問題，導致接點應力(stress)不平衡而造成該半導體晶片10損壞。 Furthermore, when the copper bumps 101 are formed by electroplating on the surface of the semiconductor wafer 10, since the height control of the copper bumps 101 is not easy, if the heights of the copper bumps 101 are different from each other, the copper bumps 101 The grid array in which the blocks 101 are arranged has a problem of poor coplanarity, resulting in unbalanced contact stress and damage to the semiconductor chip 10.
因此，如何避免習知技術中之種種缺失，實已成為目前亟欲解決的課題。 Therefore, how to avoid the various shortcomings in the conventional technology has become an urgent issue to be solved.
鑑於上述習知技術之種種缺失，本發明提供一種封裝基板，係包括：一絕緣層，係具有相對之第一表面與第二表面，且該第一表面上具有至少一凹部；複數導電凸塊，係設於該凹部中並包含一體成形之柱體與電性連接墊，其中該柱體係外露於該絕緣層之第一表面，該電性連接墊係 嵌埋於該絕緣層中，且該柱體之寬度係小於該電性連接墊之寬度；以及複數導電柱，係結合於該些電性連接墊上且嵌埋於該絕緣層中。 In view of the above-mentioned defects of the prior art, the present invention provides a package substrate including: an insulating layer having opposing first and second surfaces, and the first surface having at least one concave portion; a plurality of conductive bumps , Which is located in the concave portion and includes an integrally formed pillar and an electrical connection pad, wherein the pillar system is exposed on the first surface of the insulating layer, the electrical connection pad is It is embedded in the insulating layer, and the width of the pillar is smaller than the width of the electrical connection pad; and a plurality of conductive pillars are combined on the electrical connection pads and embedded in the insulation layer.
前述之封裝基板中，復包括形成於該柱體上之阻障層，以令該阻障層外露於該絕緣層之第一表面。 In the aforementioned packaging substrate, a barrier layer formed on the pillar is included to expose the barrier layer to the first surface of the insulating layer.
本發明亦提供一種封裝基板之製法，係包括：形成導體層於一承載件上，且該導體層具有複數開孔；形成複數導電凸塊於該導體層上，該導電凸塊包含形成於該些開孔中之柱體及設於該導體層上之電性連接墊，且該柱體與該電性連接墊係一體成形，其中，該柱體之寬度係小於該電性連接墊之寬度；形成複數導電柱於該些電性連接墊上；形成絕緣層於該承載件上，以令該絕緣層包覆該些導電凸塊與該些導電柱；移除該承載件；以及移除全部該導體層，以令該絕緣層對應該導體層處形成凹部，且使該導電凸塊之柱體凸出該凹部之底面。 The invention also provides a method for manufacturing a packaging substrate, comprising: forming a conductive layer on a carrier, and the conductive layer has a plurality of openings; forming a plurality of conductive bumps on the conductive layer, the conductive bumps including The pillars in the openings and the electrical connection pads provided on the conductor layer, and the pillars are integrally formed with the electrical connection pads, wherein the width of the pillars is smaller than the width of the electrical connection pads Forming a plurality of conductive posts on the electrical connection pads; forming an insulating layer on the carrier, so that the insulating layer covers the conductive bumps and the conductive posts; removing the carrier; and removing all In the conductor layer, a recess is formed at the insulating layer corresponding to the conductor layer, and the pillar of the conductive bump protrudes from the bottom surface of the recess.
前述之製法中，復包括於形成該些導電凸塊於該導體層上之前，形成阻障層於該導體層上及該些開孔中。 In the aforementioned manufacturing method, before forming the conductive bumps on the conductive layer, forming a barrier layer on the conductive layer and in the openings.
於一實施例中，該阻障層復形成於該承載件上，且於移除全部該導體層之後，移除全部該阻障層。 In one embodiment, the barrier layer is formed on the carrier, and after removing all the conductor layers, all the barrier layers are removed.
於一實施例中，復包括形成另一阻障層於該阻障層上，且於移除全部該導體層之後，移除全部該阻障層與該另一阻障層。 In one embodiment, the method further includes forming another barrier layer on the barrier layer, and after removing all of the conductor layer, removing all of the barrier layer and the other barrier layer.
於一實施例中，該阻障層僅形成於該導電凸塊與該導體層之間，且於移除全部該導體層之後，以令該阻障層外 露於該絕緣層之第一表面。 In one embodiment, the barrier layer is only formed between the conductive bump and the conductor layer, and after removing all of the conductor layer, to make the barrier layer outside Exposed on the first surface of the insulating layer.
前述之封裝基板及其製法中，該柱體係凸出該絕緣層之第一表面。 In the aforementioned packaging substrate and its manufacturing method, the pillar system protrudes from the first surface of the insulating layer.
前述之封裝基板及其製法中，於移除全部該導體層後，以令該絕緣層對應該導體層處形成凹部，使該些導電凸塊位於該凹部中，且使該導電凸塊之柱體凸出該凹部之底面。 In the aforementioned packaging substrate and its manufacturing method, after removing all of the conductive layer, the insulating layer is formed to correspond to the conductive layer to form a recess, so that the conductive bumps are located in the recess and the pillars of the conductive bump The body protrudes from the bottom surface of the recess.
前述之封裝基板及其製法中，復包括形成第一線路結構於該承載件上，以令該絕緣層復包覆該第一線路結構，且該第一線路結構外露於該絕緣層之第一表面與第二表面。 In the aforementioned packaging substrate and its manufacturing method, the method includes forming a first circuit structure on the carrier, so that the insulating layer overcoats the first circuit structure, and the first circuit structure is exposed to the first of the insulating layer Surface and second surface.
前述之封裝基板及其製法中，復包括形成第二線路結構於該絕緣層上；以及於該絕緣層上形成包覆該第二線路結構之另一絕緣層，且令部分該第二線路結構外露於該另一絕緣層。 In the aforementioned package substrate and its manufacturing method, it includes forming a second circuit structure on the insulating layer; and forming another insulating layer covering the second circuit structure on the insulating layer, and making part of the second circuit structure Exposed to the other insulating layer.
由上可知，本發明之封裝基板及其製法，主要藉由將該些導電凸塊形成於該封裝基板上，故相較於習知在半導體晶片上製作銅凸塊之製程，本發明之封裝基板及其製法之成本較低，因而有利於生產。 It can be seen from the above that the package substrate and the manufacturing method thereof of the present invention are mainly formed by forming the conductive bumps on the package substrate, so compared with the conventional manufacturing process of making copper bumps on a semiconductor wafer, the package of the present invention The cost of the substrate and its manufacturing method is low, which is conducive to production.
再者，本發明係於承載件之表面上藉由該導體層之限制而向內電鍍該些導電凸塊，使該些柱體之端面之高度位置之平整性極佳，因而容易達到細間距的要求。例如，該些柱體之端面之高度位置相同，使該些柱體所排列成之柵狀陣列之共面性良好，故接點應力能保持平衡，避免該封 裝基板或其上電子元件之損壞。 Furthermore, the present invention is to plate the conductive bumps inwards on the surface of the carrier by the restriction of the conductor layer, so that the flatness of the height positions of the end surfaces of the pillars is excellent, and thus it is easy to achieve a fine pitch Requirements. For example, the height positions of the end faces of the pillars are the same, so that the grid-like array of the pillars has a good coplanarity, so the contact stress can be balanced to avoid the sealing Damage to the mounting substrate or electronic components on it.
1‧‧‧半導體封裝件 1‧‧‧Semiconductor package
10‧‧‧半導體晶片 10‧‧‧Semiconductor chip
10’‧‧‧被動元件 10’‧‧‧Passive components
100‧‧‧焊錫凸塊 100‧‧‧Solder bump
101‧‧‧銅凸塊 101‧‧‧Copper bump
11,2,3,6,6’‧‧‧封裝基板 11,2,3,6,6’‧‧‧‧Package substrate
110,241‧‧‧電性連接墊 110,241‧‧‧Electrical connection pad
12,50‧‧‧底膠 12,50‧‧‧ Primer
14,44‧‧‧焊球 14,44‧‧‧solder ball
20‧‧‧承載件 20‧‧‧Carrier
21‧‧‧導體層 21‧‧‧Conductor layer
210‧‧‧開孔 210‧‧‧opening
22,23,32,32’‧‧‧阻障層 22,23,32,32’‧‧‧ barrier layer
24‧‧‧導電凸塊 24‧‧‧conductive bump
240‧‧‧柱體 240‧‧‧pillar
25‧‧‧第一線路結構 25‧‧‧ First line structure
250‧‧‧第一線路層 250‧‧‧ First circuit layer
251‧‧‧第一導電柱 251‧‧‧The first conductive column
26‧‧‧導電柱 26‧‧‧conductive column
27,29‧‧‧絕緣層 27,29‧‧‧Insulation
27a‧‧‧第一表面 27a‧‧‧First surface
27b‧‧‧第二表面 27b‧‧‧Second surface
270‧‧‧凹部 270‧‧‧recess
270a‧‧‧底面 270a‧‧‧Bottom
28‧‧‧第二線路結構 28‧‧‧ Second line structure
280‧‧‧第二線路層 280‧‧‧ Second circuit layer
281‧‧‧第二導電柱 281‧‧‧Second conductive column
4,4’,5‧‧‧電子封裝件 4,4’,5‧‧‧Electronic package
40,40’‧‧‧電子元件 40,40’‧‧‧Electronic components
400‧‧‧焊錫材料 400‧‧‧Solder material
41‧‧‧線路層 41‧‧‧ Line layer
42‧‧‧導電體 42‧‧‧Conductor
43‧‧‧封裝層 43‧‧‧Encapsulation layer
45‧‧‧電子組件 45‧‧‧Electronic components
450‧‧‧導電元件 450‧‧‧Conducting element
46‧‧‧封裝膠體 46‧‧‧Packing colloid
d,r‧‧‧寬度 d,r‧‧‧Width
第1圖係為習知半導體封裝件的剖視示意圖；第2A至2G圖係為本發明之封裝基板之製法之第一實施例之剖視示意圖，其中該第2A’圖係為對應第2A’圖之其它實施態樣示意圖，該第2F’及2F”圖係為對應第2F圖之其它實施態樣示意圖；第3A至3E圖係為本發明之封裝基板之製法之第二實施例之剖視示意圖；第4A及4B圖係為第2G圖之封裝基板之後續應用之剖視示意圖；第5圖係為第3E圖之封裝基板之後續應用之剖視示意圖；以及第6A至6E圖係為本發明之封裝基板之製法之第二實施例之剖視示意圖，其中該第6E’圖係為對應第6E圖之其它實施態樣示意圖。 Fig. 1 is a schematic cross-sectional view of a conventional semiconductor package; Figs. 2A to 2G are schematic cross-sectional views of a first embodiment of a method for manufacturing a package substrate of the present invention, where the 2A' figure corresponds to the 2A 'Simple schematic diagrams of other implementation forms of the figure, the 2F' and 2F" drawings are schematic views of other implementation forms corresponding to the 2F chart; Figs. 3A to 3E are the second embodiment of the manufacturing method of the package substrate of the present invention 4A and 4B are sectional views of the subsequent applications of the package substrate of FIG. 2G; FIG. 5 is a sectional views of the subsequent applications of the package substrate of FIG. 3E; and FIGS. 6A to 6E It is a schematic cross-sectional view of a second embodiment of the method for manufacturing a package substrate of the present invention, where the 6E' figure is a schematic diagram of other implementations corresponding to the 6E figure.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following describes the implementation of the present invention by specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例 關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It should be noted that the structure, ratio, size, etc. shown in the drawings of this specification are only used to match the content disclosed in the specification, for those who are familiar with this skill to understand and read, not to limit the implementation of the present invention The limited conditions, so it does not have the technical significance, any structural modification, proportion The change of the relationship or the adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effect and the aim of the present invention. At the same time, the terms such as "on", "first", "second", and "one" cited in this specification are only for the convenience of description, not to limit the scope of the invention, Changes or adjustments in the relative relationship are considered to be within the scope of the invention without substantial changes in the technical content.
請參閱第2A至2G圖，係為本發明之封裝基板2之第一實施例之製法之剖視示意圖。 Please refer to FIGS. 2A to 2G, which are schematic cross-sectional views of the manufacturing method of the first embodiment of the package substrate 2 of the present invention.
如第2A圖所示，藉由圖案化製程於一承載件20上形成一導體層21，且該導體層21具有複數開孔210。接著，形成一阻障層22於該承載件20、該導體層21上及該些開孔210中。 As shown in FIG. 2A, a conductive layer 21 is formed on a carrier 20 by a patterning process, and the conductive layer 21 has a plurality of openings 210. Next, a barrier layer 22 is formed on the carrier 20, the conductive layer 21 and the openings 210.
於本實施例中，該承載件20係為基材，例如銅箔基板或其它板體，並無特別限制，且該導體層21係以電鍍方式形成於該承載件20上。 In this embodiment, the carrier 20 is a base material, such as a copper foil substrate or other plates, and is not particularly limited, and the conductor layer 21 is formed on the carrier 20 by electroplating.
再者，該導體層21與該阻障層22互為不同材質。具體地，該導體層21係為金屬層，如銅層，且該阻障層22係為金屬層，如鎳層、金層或鈦層等。 Furthermore, the conductive layer 21 and the barrier layer 22 are made of different materials. Specifically, the conductor layer 21 is a metal layer, such as a copper layer, and the barrier layer 22 is a metal layer, such as a nickel layer, a gold layer, or a titanium layer.
於另一實施例中，如第2A’圖所示，形成另一阻障層23於該阻障層22上，且該阻障層22與該另一阻障層23互為不同材質，例如，該另一阻障層23係為銅層。 In another embodiment, as shown in FIG. 2A′, another barrier layer 23 is formed on the barrier layer 22, and the barrier layer 22 and the other barrier layer 23 are different materials from each other, for example The other barrier layer 23 is a copper layer.
如第2B圖所示，接續第2A圖之製程，係形成複數導電凸塊24於該導體層21上之阻障層22上，各該導電凸塊 24係包含一形成於該些開孔210中之柱體240及一設於該導體層21上之電性連接墊241，且該柱體240與該電性連接墊241係一體成形，其中，該柱體240之寬度d係小於該電性連接墊241之寬度r。 As shown in FIG. 2B, following the process of FIG. 2A, a plurality of conductive bumps 24 are formed on the barrier layer 22 on the conductor layer 21, and each of the conductive bumps 24 includes a pillar 240 formed in the openings 210 and an electrical connection pad 241 provided on the conductor layer 21, and the pillar 240 and the electrical connection pad 241 are integrally formed, wherein, The width d of the pillar 240 is smaller than the width r of the electrical connection pad 241.
於本實施例中，係以電鍍銅方式形成該些導電凸塊24，且復以電鍍銅方式一同形成一第一線路層250於該承載件20上之阻障層22上。 In this embodiment, the conductive bumps 24 are formed by copper electroplating, and a first circuit layer 250 is formed on the barrier layer 22 on the carrier 20 by copper electroplating.
如第2C圖所示，形成複數導電柱26於該些電性連接墊241上，且形成複數第一導電柱251於該第一線路層250上，以令該第一導電柱251與該第一線路層250作為第一線路結構25，使該第一線路結構25形成於該承載件20上。 As shown in FIG. 2C, a plurality of conductive pillars 26 are formed on the electrical connection pads 241, and a plurality of first conductive pillars 251 are formed on the first circuit layer 250, so that the first conductive pillars 251 and the first A circuit layer 250 serves as the first circuit structure 25 so that the first circuit structure 25 is formed on the carrier 20.
於本實施例中，係以電鍍銅方式形成該些導電柱26與第一導電柱251。 In this embodiment, the conductive pillars 26 and the first conductive pillars 251 are formed by electroplating copper.
如第2D圖所示，形成一絕緣層27於該阻障層22上，以令該絕緣層27包覆該些導電凸塊24、該第一線路結構25與該些導電柱26。 As shown in FIG. 2D, an insulating layer 27 is formed on the barrier layer 22 so that the insulating layer 27 covers the conductive bumps 24, the first circuit structure 25 and the conductive pillars 26.
於本實施例中，該絕緣層27具有相對之第一表面27a及第二表面27b，以藉其第一表面27a結合至該阻障層22上，且令該些導電柱26與該第一線路結構25之第一導電柱251外露於該絕緣層27之第二表面27b。具體地，該第一線路層250之表面係齊平該絕緣層27之第一表面27a，且該些導電柱26之端面及該些第一導電柱251之端面係齊平該絕緣層27之第二表面27b。應可理解地，該絕緣層27之第二表面27b亦可形成開孔，以外露該該些導電柱26 之端面及該些第一導電柱251之端面。 In this embodiment, the insulating layer 27 has opposite first surface 27a and second surface 27b, so that the first surface 27a is bonded to the barrier layer 22, and the conductive pillars 26 and the first surface The first conductive pillar 251 of the circuit structure 25 is exposed on the second surface 27b of the insulating layer 27. Specifically, the surface of the first circuit layer 250 is flush with the first surface 27a of the insulating layer 27, and the end surfaces of the conductive pillars 26 and the end surfaces of the first conductive pillars 251 are flush with the insulating layer 27 Second surface 27b. It should be understood that the second surface 27b of the insulating layer 27 may also form an opening, exposing the conductive pillars 26 And the end surfaces of the first conductive pillars 251.
再者，該絕緣層27係以壓合或鑄模(molding)方式製作，且該絕緣層27係為鑄模化合物(molding compound)、乾膜材(dry film)、環氧樹脂(Epoxy)、聚醯亞胺(Polyimide，簡稱PI)、感光或非感光性材料等之有機樹脂。 Furthermore, the insulating layer 27 is made by pressing or molding, and the insulating layer 27 is a molding compound, a dry film, an epoxy, or a polyimide Organic resins such as polyimide (PI), photosensitive or non-photosensitive materials, etc.
如第2E圖所示，於該絕緣層27之第二表面27b上形成一第二線路結構28。接著，於該絕緣層27之第二表面27b上形成一用以包覆該第二線路結構28之另一絕緣層29，且令部分該第二線路結構28外露於該另一絕緣層29。 As shown in FIG. 2E, a second circuit structure 28 is formed on the second surface 27b of the insulating layer 27. Next, another insulating layer 29 for covering the second circuit structure 28 is formed on the second surface 27b of the insulating layer 27, and part of the second circuit structure 28 is exposed to the other insulating layer 29.
於本實施例中，第二線路結構28復包括一形成於該絕緣層27之第二表面27b上的第二線路層280及複數形成於該第二線路層22之第二導電柱281。 In this embodiment, the second circuit structure 28 includes a second circuit layer 280 formed on the second surface 27 b of the insulating layer 27 and a plurality of second conductive pillars 281 formed on the second circuit layer 22.
於本實施例中，該第二線路層280係直接連接該些第一導電柱251與導電柱26。 In this embodiment, the second circuit layer 280 directly connects the first conductive pillars 251 and the conductive pillars 26.
再者，該第二導電柱281係為銅柱，其端面外露於該另一絕緣層29。 Furthermore, the second conductive pillar 281 is a copper pillar, and its end surface is exposed to the other insulating layer 29.
又，該另一絕緣層29係以壓合或鑄模(molding)方式製作，且該另一絕緣層29係為鑄模化合物(molding compound)、乾膜材(dry film)、環氧樹脂(Epoxy)、聚醯亞胺(Polyimide，簡稱PI)、感光或非感光性材料等之有機樹脂。 Moreover, the other insulating layer 29 is made by pressing or molding, and the other insulating layer 29 is a molding compound, a dry film, or an epoxy resin , Polyimide (Polyimide, referred to as PI), organic resins such as photosensitive or non-photosensitive materials.
如第2F圖所示，移除該承載件20，以外露該導體層21與該阻障層22。 As shown in FIG. 2F, the carrier 20 is removed, and the conductor layer 21 and the barrier layer 22 are exposed.
如第2G圖所示，移除全部該導體層21與全部該阻障層22，以令該絕緣層27之第一表面27a上形成有凹部270，並使該些導電凸塊24之柱體240凸出該凹部270之底面270a。 As shown in FIG. 2G, all of the conductor layer 21 and all of the barrier layer 22 are removed, so that a concave portion 270 is formed on the first surface 27a of the insulating layer 27, and the pillars of the conductive bumps 24 are made 240 protrudes from the bottom surface 270a of the concave portion 270.
於本實施例中，該第一線路層250之表面係外露於該絕緣層27之第一表面27a。 In this embodiment, the surface of the first circuit layer 250 is exposed on the first surface 27a of the insulating layer 27.
再者，係以蝕刻方式移除全部該導體層21與全部該阻障層22，故先以該阻障層22作為止蝕層，移除全部該導體層21，再移除全部該阻障層22。 Furthermore, all of the conductor layer 21 and all of the barrier layer 22 are removed by etching, so first use the barrier layer 22 as an etch stop layer, remove all of the conductor layer 21, and then remove all of the barrier Layer 22.
又，如第2F’及2F”圖所示，若接續第2A’圖之製程，係以該另一阻障層23作為止蝕層，蝕刻移除全部該導體層21及全部該阻障層22，再移除全部該另一阻障層23，以得到如第2G圖所示之封裝基板2。 In addition, as shown in FIGS. 2F′ and 2F”, if the process of FIG. 2A′ is continued, the other barrier layer 23 is used as an etch stop layer, and all the conductor layers 21 and all the barrier layers are etched and removed. 22, and then remove all the other barrier layers 23 to obtain the package substrate 2 as shown in FIG. 2G.
復請參閱第3A至3E圖，係為本發明之封裝基板3之第二實施例之製法之剖視示意圖。本實施例與第一實施例的差異在於阻障層之佈設，其它製程大致相同，故以下僅說明相異處，而不再贅述相同處。 Please also refer to FIGS. 3A to 3E, which are schematic cross-sectional views of the manufacturing method of the second embodiment of the package substrate 3 of the present invention. The difference between this embodiment and the first embodiment lies in the layout of the barrier layer, and other processes are approximately the same. Therefore, only the differences will be described below, and the similarities will not be repeated.
如第3A圖所示，藉由圖案化製程於一承載件20上形成一導體層21，且該導體層21具有複數開孔210。接著，藉由圖案化製程形成一阻障層32,32’於該導體層21之部分表面上、該些開孔210中、以及該承載件20之部分表面。 As shown in FIG. 3A, a conductive layer 21 is formed on a carrier 20 by a patterning process, and the conductive layer 21 has a plurality of openings 210. Next, a barrier layer 32, 32' is formed on the part of the surface of the conductor layer 21, the openings 210, and the part of the surface of the carrier 20 by a patterning process.
如第3B圖所示，形成複數導電凸塊24與一第一線路層250於該阻障層32,32’上，使結合該導電凸塊24之阻障層32僅形成於該導電凸塊24與該導體層21之間，且結 合於該承載件20上之阻障層32’僅形成於該承載件20與該第一線路層250之間。 As shown in FIG. 3B, a plurality of conductive bumps 24 and a first circuit layer 250 are formed on the barrier layers 32, 32' so that the barrier layer 32 combining the conductive bumps 24 is formed only on the conductive bumps 24 and the conductor layer 21, and the junction The barrier layer 32' joined to the carrier 20 is only formed between the carrier 20 and the first circuit layer 250.
如第3C圖所示，係進行如第2C至2E圖所示之製程。 As shown in Figure 3C, the process shown in Figures 2C to 2E is performed.
如第3D圖所示，移除該承載件20，以外露該絕緣層27之第一表面27a、該導體層21與該阻障層32,32’。 As shown in FIG. 3D, the carrier 20 is removed to expose the first surface 27a of the insulating layer 27, the conductor layer 21 and the barrier layers 32, 32'.
如第3E圖所示，移除全部該導體層21，以令該絕緣層27之第一表面27a上形成一凹部270，使該些導電凸塊24之柱體240凸出該凹部270之底面270a。 As shown in FIG. 3E, all of the conductor layer 21 is removed, so that a concave portion 270 is formed on the first surface 27a of the insulating layer 27, so that the pillars 240 of the conductive bumps 24 protrude from the bottom surface of the concave portion 270 270a.
於本實施例中，該些導電凸塊24上之阻障層32係外露於該凹部270中，且該第一線路層250上之阻障層32’係外露於該絕緣層27之第一表面27a。 In this embodiment, the barrier layer 32 on the conductive bumps 24 is exposed in the concave portion 270, and the barrier layer 32' on the first circuit layer 250 is exposed on the first of the insulating layer 27 Surface 27a.
本發明之製法中，係將該些導電凸塊24形成於該封裝基板2,3上，故相較於習知半導體晶片上製作銅凸塊之製程，本發明之製法之成本較低，因而有利於生產。 In the manufacturing method of the present invention, the conductive bumps 24 are formed on the packaging substrates 2 and 3, so compared with the conventional manufacturing process of copper bumps on semiconductor wafers, the manufacturing method of the present invention has a lower cost, so Good for production.
再者，於承載件20之表面上藉由導體層21之限制而向內(意指由該封裝基板2,3之外側向內側製作)電鍍該些導電凸塊24，使該些柱體240之端面之高度位置之平整性極佳，達到細間距線路的要求。亦即，該些柱體240之端面之高度位置相同，使該些柱體240所排列成之柵狀陣列(grid array)之共面性(coplanarity)良好，故接點應力(stress)能保持平衡，避免該封裝基板2,3或其上電子元件40(如後所述)之損壞。 Furthermore, the conductive bumps 24 are electroplated inwards on the surface of the carrier 20 by the restriction of the conductor layer 21 (meaning the outer side of the package substrates 2 and 3 are made), so that the pillars 240 The flatness of the height position of the end face is excellent, meeting the requirements of fine-pitch lines. That is, the height positions of the end surfaces of the pillars 240 are the same, so that the grid array of the pillars 240 is arranged with a good coplanarity, so the stress of the contacts can be maintained Balance to avoid damage to the packaging substrates 2, 3 or the electronic components 40 (as described later).
第4A、4B及5圖係為應用本發明之封裝基板2,3所形成之電子封裝件4,4’,5之剖面示意圖。 FIGS. 4A, 4B and 5 are schematic cross-sectional views of electronic packages 4, 4', 5 formed by using the package substrates 2 and 3 of the present invention.
如第4A圖所示之電子封裝件4，係以第2G圖之封裝基板2為例，對應其凹部270位置，將至少一電子元件40藉由焊錫材料400結合至該些柱體240，使該電子元件40電性連接該些導電凸塊24，且該第一線路層250亦可藉由焊錫材料400結合另一電子元件40’。 The electronic package 4 shown in FIG. 4A takes the package substrate 2 in FIG. 2G as an example, corresponding to the position of the concave portion 270, at least one electronic component 40 is bonded to the pillars 240 by the solder material 400, so that The electronic component 40 is electrically connected to the conductive bumps 24, and the first circuit layer 250 can also be combined with another electronic component 40' through a solder material 400.
於本實施例中，該電子元件40,40’係為主動元件、被動元件或其二者之組合，其中，該主動元件係例如半導體晶片，該被動元件係例如電阻、電容及電感。具體地，該些柱體240上之電子元件40係為主動元件，且該第一線路層250上之電子元件40’係為被動元件。 In this embodiment, the electronic components 40, 40' are active components, passive components, or a combination of the two, wherein the active components are, for example, semiconductor chips, and the passive components are, for example, resistors, capacitors, and inductors. Specifically, the electronic components 40 on the pillars 240 are active components, and the electronic components 40' on the first circuit layer 250 are passive components.
再者，該電子封裝件4包括一封裝層43，其形成於該絕緣層27之第一表面27a上，以令該封裝層43包覆該些柱體240、該些電子元件40,40’與該焊錫材料400，且形成複數焊球44於該絕緣層27之第二表面27b上，以令該些焊球44電性連接該些第二導電柱281，俾供結合一如電路板之電子裝置(圖略)。 Furthermore, the electronic package 4 includes an encapsulation layer 43 formed on the first surface 27a of the insulating layer 27 so that the encapsulation layer 43 covers the pillars 240 and the electronic components 40, 40' And the solder material 400, and a plurality of solder balls 44 are formed on the second surface 27b of the insulating layer 27, so that the solder balls 44 are electrically connected to the second conductive pillars 281 for bonding like a circuit board Electronic device (figure omitted).
又，該電子封裝件4復包括一形成於該封裝層43上之線路層41及複數形成於該封裝層43中之導電體42，以令該線路層41藉由該些導電體42電性連接該第一線路層250。 In addition, the electronic package 4 includes a circuit layer 41 formed on the packaging layer 43 and a plurality of conductors 42 formed in the packaging layer 43 so that the circuit layer 41 is electrically conductive through the conductors 42 Connect the first circuit layer 250.
另外，藉由該些導電體42與該線路層41之設計，以堆疊至少一電子組件45，如第4B圖所示，故本發明之電子封裝件4無需使用習知矽中介板(Si interposer)作為轉接結構，因而能降低該電子封裝件4之整體結構之高度，以 達到薄化及降低成本之需求。 In addition, through the design of the conductors 42 and the circuit layer 41, at least one electronic component 45 is stacked, as shown in FIG. 4B, so the electronic package 4 of the present invention does not need to use a conventional silicon interposer (Si interposer) ) As a transition structure, which can reduce the height of the overall structure of the electronic package 4 to To achieve the demand for thinning and cost reduction.
於本實施例中，於該線路層41上藉由複數導電元件450堆疊結合及電性連接該電子組件45。具體地，該些導電元件450係如焊球、焊錫凸塊、銅凸塊等，且該電子組件45係為主動元件、被動元件、封裝元件或其三者之組合，其中，該封裝元件係包含晶片及包覆該晶片之封裝膠體，另可選擇性地形成一封裝膠體46於該封裝層43上，以令該封裝膠體46包覆該電子組件45。 In this embodiment, a plurality of conductive elements 450 are stacked and electrically connected to the electronic component 45 on the circuit layer 41. Specifically, the conductive elements 450 are such as solder balls, solder bumps, copper bumps, etc., and the electronic component 45 is an active element, a passive element, a package element, or a combination of the three, wherein the package element is The chip and the encapsulating glue covering the chip can also selectively form an encapsulating glue 46 on the encapsulation layer 43 so that the encapsulating glue 46 covers the electronic component 45.
另一方面，如第5圖所示之電子封裝件5，係以第3E圖之封裝基板3為例，該些柱體240藉由阻障層32結合該電子元件40之焊錫材料400，且該電子元件40電性連接該些導電凸塊24，並於該電子元件40與該凹部270之間形成底膠50，以包覆該些柱體240、阻障層32與該焊錫材料400，而該第一線路層250上之阻障層32’亦可藉由焊錫材料400結合另一電子元件40’。 On the other hand, the electronic package 5 shown in FIG. 5 takes the package substrate 3 in FIG. 3E as an example, the pillars 240 are combined with the solder material 400 of the electronic component 40 through the barrier layer 32, and The electronic component 40 is electrically connected to the conductive bumps 24, and a primer 50 is formed between the electronic component 40 and the recess 270 to cover the pillars 240, the barrier layer 32 and the solder material 400, The barrier layer 32 ′ on the first circuit layer 250 can also be combined with another electronic component 40 ′ by the solder material 400.
於本實施例中，該阻障層32(尤其是鎳層)與該焊錫材料400具有較好的結合性，使該封裝基板3能更穩固地結合該電子元件40。 In this embodiment, the barrier layer 32 (especially the nickel layer) has good bonding with the solder material 400, so that the package substrate 3 can more firmly bond the electronic component 40.
再請參閱第6A至6E圖，係為本發明之封裝基板6之第三實施例之製法之剖視示意圖。本實施例與上述實施例的差異在於省略製作第一線路結構25，其它製程大致相同，故以下僅說明相異處，而不再贅述相同處。 Please refer to FIGS. 6A to 6E again, which are schematic cross-sectional views of the manufacturing method of the third embodiment of the package substrate 6 of the present invention. The difference between this embodiment and the above-mentioned embodiment lies in that the first circuit structure 25 is omitted, and the other processes are substantially the same. Therefore, only the differences are described below, and the similarities are not repeated.
如第6A至6B圖所示，依據第二實施例的製法，省略製作第一線路結構25。 As shown in FIGS. 6A to 6B, according to the manufacturing method of the second embodiment, the manufacturing of the first circuit structure 25 is omitted.
如第6C圖所示，係進行如第3C圖所示之製程，使該第二線路結構28之第二線路層280直接連接該些導電柱26。 As shown in FIG. 6C, the process shown in FIG. 3C is performed, so that the second circuit layer 280 of the second circuit structure 28 is directly connected to the conductive pillars 26.
如第6D圖所示，移除該承載件20，以外露該絕緣層27之第一表面27a、該導體層21與該阻障層32。 As shown in FIG. 6D, the carrier 20 is removed to expose the first surface 27 a of the insulating layer 27, the conductor layer 21 and the barrier layer 32.
如第6E圖所示，移除全部該導體層21，以令該些導電凸塊24之柱體240凸出該絕緣層27之第一表面27a。 As shown in FIG. 6E, all the conductor layers 21 are removed so that the pillars 240 of the conductive bumps 24 protrude from the first surface 27a of the insulating layer 27.
於本實施例中，應可理解地，亦可依據第一實施例的製法，以獲得如第6E’圖所示之封裝基板6’。 In this embodiment, it should be understood that the packaging substrate 6'shown in FIG. 6E' may also be obtained according to the manufacturing method of the first embodiment.
再者，應可理解地，本實施例之封裝基板6,6’於後續應用中亦可以如第4A及5圖之方式形成電子封裝件。 Furthermore, it should be understood that the packaging substrates 6, 6'of this embodiment can also be used in subsequent applications to form electronic packages as shown in FIGS. 4A and 5.
本發明提供一種封裝基板2,3,6,6’，係包括：一絕緣層27、複數導電凸塊24以及複數導電柱26。 The invention provides a packaging substrate 2, 3, 6, 6', which comprises: an insulating layer 27, a plurality of conductive bumps 24 and a plurality of conductive pillars 26.
所述之絕緣層27係具有相對之第一表面27a與第二表面27b，且該第一表面27a上具有一凹部270。 The insulating layer 27 has opposing first surface 27a and second surface 27b, and a recess 270 is formed on the first surface 27a.
所述之導電凸塊24係結合該絕緣層27之第一表面27a並包含一體成形之柱體240與電性連接墊241，且各該柱體240係外露於該絕緣層27之第一表面27a，而該些電性連接墊241係嵌埋於該絕緣層27中，其中，該柱體240之寬度d係小於該電性連接墊241之寬度r。 The conductive bump 24 is combined with the first surface 27a of the insulating layer 27 and includes an integrally formed post 240 and an electrical connection pad 241, and each post 240 is exposed on the first surface of the insulating layer 27 27a, and the electrical connection pads 241 are embedded in the insulating layer 27, wherein the width d of the pillar 240 is smaller than the width r of the electrical connection pad 241.
所述之導電柱26係嵌埋於該絕緣層27中且外露於第二表面27b，並電性連接至該些電性連接墊241。 The conductive pillar 26 is embedded in the insulating layer 27 and exposed on the second surface 27b, and is electrically connected to the electrical connection pads 241.
於一實施例之封裝基板6,6’中，各該柱體240係凸出該絕緣層27之第一表面27a。 In one embodiment of the package substrates 6, 6', each of the pillars 240 protrudes from the first surface 27a of the insulating layer 27.
於一實施例之封裝基板2,3中，該絕緣層27之第一表面27a上形成有至少一凹部270，以令該些導電凸塊24位於該凹部270中，且各該柱體240係凸出單一該凹部270之底面270a。 In the package substrates 2 and 3 of one embodiment, at least one concave portion 270 is formed on the first surface 27a of the insulating layer 27 so that the conductive bumps 24 are located in the concave portion 270, and each of the pillars 240 is The bottom surface 270a of the single concave portion 270 protrudes.
於一實施例中，該封裝基板2,3復包括一形成於該絕緣層27中之第一線路結構25，且該第一線路結構25外露於該絕緣層27之第一表面27a與第二表面27b。 In one embodiment, the packaging substrates 2 and 3 include a first circuit structure 25 formed in the insulating layer 27, and the first circuit structure 25 is exposed on the first surface 27a and the second of the insulating layer 27 Surface 27b.
於一實施例中，該封裝基板2,3,6,6’復包括一第二線路結構28，係形成於該絕緣層27之第二表面27b上。又包括一包覆該第二線路結構28之另一絕緣層29，且令部分該第二線路結構28係外露於該另一絕緣層29。 In one embodiment, the package substrates 2, 3, 6, 6'include a second circuit structure 28 formed on the second surface 27b of the insulating layer 27. A second insulating layer 29 covering the second circuit structure 28 is also included, and part of the second circuit structure 28 is exposed to the other insulating layer 29.
於一實施例中，該封裝基板3,6復包括一形成於各該柱體240上之阻障層32，以令該阻障層32外露於該絕緣層27之第一表面27a。 In one embodiment, the packaging substrates 3, 6 include a barrier layer 32 formed on each of the pillars 240, so that the barrier layer 32 is exposed on the first surface 27a of the insulating layer 27.
綜上所述，本發明之封裝基板及其製法，係藉由將該些導電凸塊形成於該封裝基板上而非形成於半導體晶片上，故本發明之製法之成本低，因而有利於生產。 In summary, the packaging substrate and the manufacturing method of the present invention are formed by forming the conductive bumps on the packaging substrate instead of the semiconductor wafer, so the manufacturing method of the present invention has low cost and is therefore beneficial to production .
再者，本發明利用在該承載件表面上藉由導體層之限制而向內電鍍該些導電凸塊，使該些柱體之端面之高度位置之平整性極佳，以達到細間距線路的要求。 Furthermore, the present invention utilizes the electroplating of the conductive bumps on the surface of the carrier by the restriction of the conductor layer, so that the flatness of the height positions of the end surfaces of the pillars is excellent, so as to achieve the fine pitch circuit Claim.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。 The above embodiments are used to exemplify the principles and effects of the present invention, rather than to limit the present invention. Anyone who is familiar with this skill can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be as follows Listed.
2‧‧‧封裝基板 2‧‧‧Package substrate
24‧‧‧導電凸塊 24‧‧‧conductive bump
240‧‧‧柱體 240‧‧‧pillar
241‧‧‧電性連接墊 241‧‧‧Electrical connection pad
25‧‧‧第一線路結構 25‧‧‧ First line structure
250‧‧‧第一線路層 250‧‧‧ First circuit layer
251‧‧‧第一導電柱 251‧‧‧The first conductive column
26‧‧‧導電柱 26‧‧‧conductive column
27,29‧‧‧絕緣層 27,29‧‧‧Insulation
27a‧‧‧第一表面 27a‧‧‧First surface
27b‧‧‧第二表面 27b‧‧‧Second surface
270‧‧‧凹部 270‧‧‧recess
270a‧‧‧底面 270a‧‧‧Bottom
28‧‧‧第二線路結構 28‧‧‧ Second line structure
280‧‧‧第二線路層 280‧‧‧ Second circuit layer
281‧‧‧第二導電柱 281‧‧‧Second conductive column
Claims (20)
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| TW105115936A TWI567843B (en) | 2016-05-23 | 2016-05-23 | Package substrate and the manufacture thereof |
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| TW105115936A TWI567843B (en) | 2016-05-23 | 2016-05-23 | Package substrate and the manufacture thereof |
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| TWI567843B TWI567843B (en) | 2017-01-21 |
| TW201810458A true TW201810458A (en) | 2018-03-16 |
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| TWI808639B (en) * | 2021-05-13 | 2023-07-11 | 台灣積體電路製造股份有限公司 | Package structure and method for forming the same |
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| TWI570856B (en) * | 2014-11-10 | 2017-02-11 | 恆勁科技股份有限公司 | Package structure and method of manufacture |
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