TW201810431A - Semiconductor devices and methods for manufacturing the same - Google Patents
Semiconductor devices and methods for manufacturing the same Download PDFInfo
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本發明是關於半導體裝置,特別是關於使用快速熱退火製程之半導體裝置及其製造方法。 The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a rapid thermal annealing process and a method of fabricating the same.
在傳統半導體裝置的製程中,藉由擴散製程使得形成在半導體基底表面的摻質由高濃度區向低濃度區移動,以驅入半導體基底內形成不同導電類型(P或N型)的井區,雖然擴散製程具有可批次製作且低成本的優勢,但對於井區側向邊緣的擴散較不容易控制,隨著半導體裝置的尺寸持續地縮減,如何精準地控制井區的側向擴散將是目前需努力的方向。 In a conventional semiconductor device process, a dopant formed on a surface of a semiconductor substrate is moved from a high concentration region to a low concentration region by a diffusion process to drive a well region of a different conductivity type (P or N type) into the semiconductor substrate. Although the diffusion process has the advantage of being batch-produced and low-cost, the diffusion of the lateral edge of the well is less controllable. As the size of the semiconductor device continues to shrink, how to accurately control the lateral diffusion of the well will It is the direction that needs to be worked out now.
本揭露提供了半導體裝置的實施例及其形成方法,特別是以整合式的雙載子-互補式金氧半導體-擴散金氧半導體(bipolar-CMOS-DMOS,BCD)製程製造的蕭特基二極體(Schottky diode)。本揭露利用快速熱退火製程(rapid thermal annealing,RTA)取代傳統的擴散製程,可精準地控制半導體基底內井區的側向擴散,以縮小井區與井區之間的距離,例如縮小至0.6微米至1.2微米的範圍內,在上述蕭特基二極體的實施例中,可減少蕭特基接觸面積(Schottky contact area),進而縮 小蕭特基二極體的整體尺寸、降低室溫和高溫時蕭特基二極體的反向漏電流(reverse leakage current),也無需在製程中使用額外的離子植入或遮罩。 The present disclosure provides an embodiment of a semiconductor device and a method of forming the same, and in particular, a Schottky II process fabricated by an integrated bipolar-CMOS-DMOS (BCD) process. Schottky diode. The present disclosure utilizes rapid thermal annealing (RTA) instead of the conventional diffusion process to accurately control the lateral diffusion of the well region within the semiconductor substrate to reduce the distance between the well region and the well region, for example, to 0.6. In the range of micrometers to 1.2 micrometers, in the above embodiment of the Schottky diode, the Schottky contact area can be reduced, and the Schottky contact area can be reduced. The overall size of the small Schottky diode, the reverse leakage current of the Schottky diode at room temperature and high temperature, does not require the use of additional ion implantation or masking in the process.
根據一些實施例,提供半導體裝置的製造方法。半導體裝置的製造方法包含形成第一井區於半導體基底內,形成隔離結構於半導體基底上,形成複數個第二井區和第三井區於第一井區內,其中第二井區係藉由隔離結構與第三井區分隔,且兩個相鄰的第二井區之間具有第一距離。半導體裝置的製造方法更包含實施快速熱退火製程,縮短第一距離為第二距離,形成第一阻障金屬層於第一井區上且覆蓋第二井區,形成第二阻障金屬層於第一井區上且覆蓋第三井區,形成第一電極於第一阻障金屬層上,以及形成第二電極於第二阻障金屬層上。 According to some embodiments, a method of fabricating a semiconductor device is provided. A method of fabricating a semiconductor device includes forming a first well region in a semiconductor substrate, forming an isolation structure on the semiconductor substrate, forming a plurality of second well regions and a third well region in the first well region, wherein the second well region is borrowed Separated from the third well region by the isolation structure and having a first distance between two adjacent second well regions. The manufacturing method of the semiconductor device further comprises performing a rapid thermal annealing process, shortening the first distance to a second distance, forming a first barrier metal layer on the first well region and covering the second well region, forming a second barrier metal layer The first well region covers the third well region, the first electrode is formed on the first barrier metal layer, and the second electrode is formed on the second barrier metal layer.
根據一些實施例,提供半導體裝置。半導體裝置包含設置於半導體基底內的第一井區,設置於該半導體基底上的隔離結構,設置於第一井區內的複數個第二井區和第三井區,其中第二井區係藉由隔離結構與第三井區分隔,且兩個相鄰的第二井區之間的距離在0.6微米至1.2微米的範圍內,設置於第一井區上且覆蓋第二井區的第一阻障金屬層,設置於第一井區上且覆蓋第三井區的第二阻障金屬層,設置於第一阻障金屬層上的複數個第一電極,以及設置於第二阻障金屬層上的第二電極。 According to some embodiments, a semiconductor device is provided. The semiconductor device includes a first well region disposed in the semiconductor substrate, and the isolation structure disposed on the semiconductor substrate is disposed in the plurality of second well regions and the third well region in the first well region, wherein the second well region is Separating from the third well region by the isolation structure, and the distance between the two adjacent second well regions is in the range of 0.6 micrometer to 1.2 micrometer, and is disposed on the first well region and covering the second well region a barrier metal layer disposed on the first well region and covering the second barrier metal layer of the third well region, a plurality of first electrodes disposed on the first barrier metal layer, and being disposed on the second barrier a second electrode on the metal layer.
本揭露的半導體裝置可應用於多種類型的半導體裝置,以精準地控制半導體裝置內井區的側向擴散,為讓本揭 露之特徵和優點能更明顯易懂,下文特舉出應用於蕭特基二極體之實施例,並配合所附圖式,作詳細說明如下。 The disclosed semiconductor device can be applied to various types of semiconductor devices to precisely control the lateral diffusion of the well region in the semiconductor device, The features and advantages of the dew can be more clearly understood. The following is an example of an embodiment applied to the Schottky diode, and is described in detail below in conjunction with the drawings.
100‧‧‧半導體裝置 100‧‧‧Semiconductor device
101‧‧‧半導體基底 101‧‧‧Semiconductor substrate
103‧‧‧第一井區 103‧‧‧First Well Area
105a、105b‧‧‧隔離結構 105a, 105b‧‧‧ isolation structure
107a、107a’、107b、107b’‧‧‧第二井區 107a, 107a’, 107b, 107b’‧‧‧ second well area
109、109’‧‧‧第三井區 109, 109’‧‧‧ Third Well Area
111‧‧‧第一摻雜區 111‧‧‧First doped area
113‧‧‧第二摻雜區 113‧‧‧Second doped area
115‧‧‧第一阻障金屬層 115‧‧‧First barrier metal layer
117‧‧‧第二阻障金屬層 117‧‧‧Second barrier metal layer
119‧‧‧第一電極 119‧‧‧first electrode
121‧‧‧第二電極 121‧‧‧second electrode
150‧‧‧快速熱退火製程 150‧‧‧Quick thermal annealing process
d1‧‧‧第一距離 D1‧‧‧first distance
d2‧‧‧第二距離 D2‧‧‧Second distance
d3‧‧‧第三距離 D3‧‧‧ third distance
d4‧‧‧第四距離 D4‧‧‧fourth distance
藉由以下的詳述配合所附圖式,我們能更加理解本揭露的觀點。值得注意的是,根據工業上的標準慣例,一些特徵部件(feature)可能沒有按照比例繪製。事實上,為了能清楚地討論,不同特徵部件的尺寸可能被增加或減少。 We can better understand the point of view of the disclosure by the following detailed description in conjunction with the accompanying drawings. It is worth noting that some features may not be drawn to scale according to industry standard practice. In fact, the dimensions of different features may be increased or decreased for clarity of discussion.
第1-7圖是根據本揭露的一些實施例,顯示形成半導體裝置不同階段的剖面示意圖。 1-7 are schematic cross-sectional views showing different stages of forming a semiconductor device in accordance with some embodiments of the present disclosure.
以下揭露提供了很多不同的實施例或範例,用於實施所提供的半導體裝置之不同元件。各元件和其配置的具體範例描述如下,以簡化本揭露。當然,這些僅僅是範例,並非用以限定本揭露。舉例而言,敘述中若提及第一元件形成在第二元件之上,可能包含第一和第二元件直接接觸的實施例,也可能包含額外的元件形成在第一和第二元件之間,使得它們不直接接觸的實施例。此外,本揭露可能在不同的範例中重複參考數字及/或字母。如此重複是為了簡明和清楚,而非用以表示所討論的不同實施例及/或形態之間的關係。 The following disclosure provides many different embodiments or examples for implementing the various components of the semiconductor device provided. Specific examples of the components and their configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to limit the disclosure. For example, reference to a first element formed above a second element in the description may include embodiments in which the first and second elements are in direct contact, and may also include additional elements formed between the first and second elements. Embodiments that make them in direct contact. Furthermore, the disclosure may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of clarity and clarity, and is not intended to represent the relationship of the various embodiments and/
以下描述實施例的一些變化。在不同圖式和說明的實施例中,相似的參考數字被用來標明相似的元件。可以理解的是,在方法的前、中、後可以提供額外的操作,且一些敘述的操作可為了該方法的其他實施例被取代或刪除。 Some variations of the embodiments are described below. In the various figures and illustrated embodiments, like reference numerals are used to design It will be appreciated that additional operations may be provided before, during, and after the method, and that some of the recited operations may be substituted or deleted for other embodiments of the method.
第1-7圖是根據本揭露的一些實施例,顯示形成第 7圖所示之半導體裝置100不同階段的剖面示意圖。 1-7 are diagrams showing formation according to some embodiments of the present disclosure 7 is a schematic cross-sectional view of the semiconductor device 100 at different stages.
根據一些實施例,如第1圖所示,提供半導體基底101。一些實施例中,半導體基底101可由矽或其他半導體材料製成,或者,半導體基底101可包含其他元素半導體材料,例如鍺(Ge)。一些實施例中,半導體基底101由化合物半導體製成,例如碳化矽、氮化鎵、砷化鎵、砷化銦或磷化銦。一些實施例中,半導體基底101由合金半導體製成,例如矽鍺、碳化矽鍺、磷化砷鎵或磷化銦鎵。一些實施例中,半導體基底101包含絕緣層上覆矽(silicon-on-insulator,SOI)基底。一些實施例中,半導體基底101包含磊晶層,例如半導體基底101有覆蓋在塊材半導體之上的磊晶層。本實施例之半導體基底101為輕摻雜之P型基底,在其他實施例中,半導體基底101可為輕摻雜之N型基底。 According to some embodiments, as shown in FIG. 1, a semiconductor substrate 101 is provided. In some embodiments, the semiconductor substrate 101 can be made of germanium or other semiconductor material, or the semiconductor substrate 101 can comprise other elemental semiconductor materials, such as germanium (Ge). In some embodiments, the semiconductor substrate 101 is made of a compound semiconductor such as tantalum carbide, gallium nitride, gallium arsenide, indium arsenide or indium phosphide. In some embodiments, the semiconductor substrate 101 is made of an alloy semiconductor such as germanium, tantalum carbide, gallium arsenide or indium gallium phosphide. In some embodiments, the semiconductor substrate 101 comprises a silicon-on-insulator (SOI) substrate. In some embodiments, the semiconductor substrate 101 includes an epitaxial layer, such as the semiconductor substrate 101 having an epitaxial layer overlying the bulk semiconductor. The semiconductor substrate 101 of the present embodiment is a lightly doped P-type substrate. In other embodiments, the semiconductor substrate 101 can be a lightly doped N-type substrate.
接續前述,如第2圖所示,在半導體基底101內形成第一井區103。一些實施例中,第一井區103是藉由離子植入(ion implantation)製程所形成,可在半導體基底101內植入N型摻雜物,例如磷(P)或砷(As),或P型摻雜物,例如硼(B)。本實施例之第一井區103為高壓N型井區(high voltage N well,HVNW),在其他實施例中,第一井區103可為高壓P型井區(HVPW)。 Following the foregoing, as shown in FIG. 2, a first well region 103 is formed in the semiconductor substrate 101. In some embodiments, the first well region 103 is formed by an ion implantation process, and an N-type dopant such as phosphorus (P) or arsenic (As) may be implanted in the semiconductor substrate 101, or P-type dopant, such as boron (B). The first well region 103 of the present embodiment is a high voltage N well (HVNW). In other embodiments, the first well region 103 may be a high pressure P-type well region (HVPW).
根據一些實施例,如第3圖所示,在半導體基底101上形成一些隔離結構105a和105b,且這些隔離結構105a和105b具有一部份位於半導體基底101內。本實施例包括四個隔離結構105a和105b,其中兩個隔離結構105a位於半導體 基底101與第一井區103的交界處之上,定義出半導體裝置100的主動區(active region),另外兩個隔離結構105b位於第一井區103上,具有一部分位於第一井區103內,前述四個隔離結構105a和105b共同定義出半導體裝置100中的三個陽/陰極電極區。 According to some embodiments, as shown in FIG. 3, some isolation structures 105a and 105b are formed on the semiconductor substrate 101, and a portion of the isolation structures 105a and 105b are located within the semiconductor substrate 101. This embodiment includes four isolation structures 105a and 105b, wherein the two isolation structures 105a are located in the semiconductor Above the interface of the substrate 101 and the first well region 103, an active region of the semiconductor device 100 is defined, and the other two isolation structures 105b are located on the first well region 103 with a portion located in the first well region 103. The aforementioned four isolation structures 105a and 105b collectively define three anode/cathode electrode regions in the semiconductor device 100.
一些實施例中,前述之隔離結構105a和105b可為淺溝槽隔離(shallow trench isolation,STI)或矽局部氧化(local oxidation of silicon,LOCOS)隔離。一些實施例中,隔離結構105a和105b可由熱氧化(thermal oxidation)製程、化學氣相沉積(chemical vapor deposition,CVD)製程或前述之組合形成,視其隔離種類而定。 In some embodiments, the aforementioned isolation structures 105a and 105b may be shallow trench isolation (STI) or local oxidation of silicon (LOCOS) isolation. In some embodiments, the isolation structures 105a and 105b may be formed by a thermal oxidation process, a chemical vapor deposition (CVD) process, or a combination of the foregoing, depending on the type of isolation.
根據一些實施例,如第4圖所示,在第一井區103內形成第二井區107a和107b。一些實施例中,包括四個第二井區107a和107b,其中任一隔離結構105a和與之相鄰的隔離結構105b之間具有兩個第二井區107a和107b,第二井區107a具有一部份位於隔離結構105a下,而第二井區107b具有一部份位於隔離結構105b下,第二井區107a和107b之間具有第一距離d1。一些實施例中,第二井區107a和107b係由離子植入製程所形成,其中P型或N型之摻雜物可藉由圖案化的遮罩,利用傾斜的角度被植入半導體基底101內。本實施例之第二井區107a和107b為P型井區,在其他實施例中,第二井區107a和107b可為N型井區。 According to some embodiments, as shown in FIG. 4, second well regions 107a and 107b are formed in the first well region 103. In some embodiments, there are four second well regions 107a and 107b, wherein there is two second well regions 107a and 107b between any of the isolation structures 105a and the isolation structure 105b adjacent thereto, and the second well region 107a has A portion is located below the isolation structure 105a, and a portion of the second well region 107b is located below the isolation structure 105b, and a second distance d1 between the second well regions 107a and 107b. In some embodiments, the second well regions 107a and 107b are formed by an ion implantation process in which a P-type or N-type dopant is implanted into the semiconductor substrate 101 by a tilted angle by a patterned mask. Inside. The second well regions 107a and 107b of the present embodiment are P-type well regions. In other embodiments, the second well regions 107a and 107b may be N-type well regions.
接續前述,如第4圖所示,在第一井區103內形成第三井區109。一些實施例中,第三井區109位於相鄰的兩 隔離結構105b之間,且具有一部份位於兩隔離結構105b下。 一些實施例中,第三井區109的範圍與第二井區107a和107b的範圍相比較深且寬。一些實施例中,第三井區109和相鄰的第二井區107b之間具有第三距離d3。一些實施例中,第三井區109係由離子植入製程所形成,其中P型或N型之摻雜物可藉由傾斜的角度被植入。本實施例之第三井區109為N型井區,在其他實施例中,第三井區109可為P型井區。 Following the foregoing, as shown in FIG. 4, a third well region 109 is formed in the first well region 103. In some embodiments, the third well region 109 is located adjacent to the two Between the isolation structures 105b, and a portion is located under the two isolation structures 105b. In some embodiments, the extent of the third well region 109 is deeper and wider than the extent of the second well region 107a and 107b. In some embodiments, the third well region 109 and the adjacent second well region 107b have a third distance d3 therebetween. In some embodiments, the third well region 109 is formed by an ion implantation process in which a P-type or N-type dopant can be implanted by oblique angles. The third well region 109 of the present embodiment is an N-type well region. In other embodiments, the third well region 109 may be a P-type well region.
根據一些實施例,如第5圖所示,對第4圖所示之結構實施快速熱退火製程150,使得第二井區107a、107b和第三井區109的摻雜物向外擴散,藉由快速熱退火製程150形成範圍較大的第二井區107a’、107b’和第三井區109’。第5圖顯示了井區內之摻雜物的側向擴散,其中第二井區107a和107b之間的第一距離d1在實施快速熱退火製程150之後縮短為第二距離d2,而第三井區109和相鄰的第二井區107b之間的第三距離d3在實施快速熱退火製程150之後縮短為第四距離d4。 According to some embodiments, as shown in FIG. 5, the rapid thermal annealing process 150 is performed on the structure shown in FIG. 4, so that the dopants of the second well regions 107a, 107b and the third well region 109 are outwardly diffused. A second well region 107a', 107b' and a third well region 109' having a larger range are formed by the rapid thermal annealing process 150. Figure 5 shows the lateral diffusion of dopants in the well region, wherein the first distance d1 between the second well regions 107a and 107b is shortened to a second distance d2 after performing the rapid thermal annealing process 150, and the third The third distance d3 between the well region 109 and the adjacent second well region 107b is shortened to a fourth distance d4 after the rapid thermal annealing process 150 is implemented.
一些實施例中,實施快速熱退火製程150之時間在20秒至60秒的範圍內。一些實施例中,快速熱退火製程150之溫度在900℃至1100℃的範圍內。一些實施例中,第二距離d2和第四距離d4在約0.6微米至約1.2微米的範圍內。 In some embodiments, the time to perform the rapid thermal annealing process 150 is in the range of 20 seconds to 60 seconds. In some embodiments, the temperature of the rapid thermal annealing process 150 is in the range of 900 °C to 1100 °C. In some embodiments, the second distance d2 and the fourth distance d4 are in a range from about 0.6 microns to about 1.2 microns.
接續前述,如第6圖所示,在第二井區107a’和107b’內形成第一摻雜區111,在第三井區109’內形成第二摻雜區113。一些實施例中,任一第二井區107a’內僅具有一第一摻雜區111,且第一摻雜區111具有一部份位於相鄰的隔離結 構105a或105b下。本實施例之第一摻雜區111為P型重摻雜區,且第二摻雜區113為N型重摻雜區,在其他實施例中,第一摻雜區111可為N型重摻雜區,且第二摻雜區113為P型重摻雜區。 Following the foregoing, as shown in Fig. 6, a first doping region 111 is formed in the second well regions 107a' and 107b', and a second doping region 113 is formed in the third well region 109'. In some embodiments, any of the second well regions 107a' has only one first doped region 111, and the first doped region 111 has a portion located adjacent to the isolation junction. Under the structure 105a or 105b. The first doped region 111 of the present embodiment is a P-type heavily doped region, and the second doped region 113 is an N-type heavily doped region. In other embodiments, the first doped region 111 can be an N-type heavily doped region. The doped region, and the second doped region 113 is a P-type heavily doped region.
根據一些實施例,如第7圖所示,在第一井區103上形成位於同一水平方向上的數個第一阻障金屬層115。一些實施例中,第一阻障金屬層115覆蓋隔離結構105a和相鄰的隔離結構105b之間的區域,即半導體裝置100,例如蕭特基二極體的陽/陰極電極區。換言之,第一阻障金屬層115覆蓋一部份相鄰的兩個第一摻雜區111、一部分相鄰的兩個第二井區107a’、107b’和前述兩者之間的第一井區103。 According to some embodiments, as shown in FIG. 7, a plurality of first barrier metal layers 115 in the same horizontal direction are formed on the first well region 103. In some embodiments, the first barrier metal layer 115 covers the area between the isolation structure 105a and the adjacent isolation structure 105b, ie, the semiconductor device 100, such as the male/cathode electrode region of the Schottky diode. In other words, the first barrier metal layer 115 covers a portion of the adjacent two first doped regions 111, a portion of the adjacent two second well regions 107a', 107b', and the first well between the two Area 103.
一些實施例中,在第一井區103上形成第二阻障金屬層117,其中第二阻障金屬層117覆蓋兩個相鄰的隔離結構105b之間的區域,即半導體裝置100,例如蕭特基二極體的陽/陰極電極區。換言之,第二阻障金屬層117覆蓋第二摻雜區113。一些實施例中,第二阻障金屬層117完全覆蓋第二摻雜區113以及一部份第二摻雜區113周圍的第三井區109’。 In some embodiments, a second barrier metal layer 117 is formed over the first well region 103, wherein the second barrier metal layer 117 covers a region between two adjacent isolation structures 105b, ie, a semiconductor device 100, such as Xiao The anode/cathode electrode region of the stellate diode. In other words, the second barrier metal layer 117 covers the second doping region 113. In some embodiments, the second barrier metal layer 117 completely covers the second doped region 113 and a third well region 109' around a portion of the second doped region 113.
此外,第一阻障金屬層115和第二阻障金屬層117係使用化學氣相沉積(CVD)、物理氣相沉積(physical vapor deposition,PVD)、原子層沉積(atomic layer deposition,ALD)、電鍍(electroplating)、濺鍍(sputtering)或其他合適的方法形成。一些實施例中,在藉由整合式的雙載子-互補式金氧半導體-擴散金氧半導體(BCD)製程製造的半導體裝置,例如蕭特基二極體中,第一阻障金屬層115和第二阻障金屬層117係由自 對準金屬矽化物(silicide)製程形成。 In addition, the first barrier metal layer 115 and the second barrier metal layer 117 are formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), Electroplating, sputtering, or other suitable method is formed. In some embodiments, in a semiconductor device fabricated by an integrated bi-carrier-complementary MOS-diffusion metal oxide semiconductor (BCD) process, such as a Schottky diode, the first barrier metal layer 115 And the second barrier metal layer 117 is derived from Aligned with a metal silicide process.
接著,如第7圖所示,在第一金屬阻障層115上形成第一電極119,在第二金屬阻障層117上形成第二電極121。一些實施例中,第一電極119和第二電極121係使用化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、電鍍、濺鍍或其他合適的方法形成。一些實施例中,在藉由整合式的雙載子-互補式金氧半導體-擴散金氧半導體(BCD)製程製造的半導體裝置,例如蕭特基二極體中,第一電極119和第二電極121係由鋁製成。本實施例之半導體裝置100,例如蕭特基二極體具有兩個作為陽極的第一電極119和一個作為陰極的第二電極121,在其他實施例中,可具有不同的陽/陰極組合。 Next, as shown in FIG. 7, a first electrode 119 is formed on the first metal barrier layer 115, and a second electrode 121 is formed on the second metal barrier layer 117. In some embodiments, the first electrode 119 and the second electrode 121 are formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, sputtering, or other suitable methods. In some embodiments, in a semiconductor device fabricated by an integrated bi-carrier-complementary MOS-diffusion metal oxide semiconductor (BCD) process, such as a Schottky diode, the first electrode 119 and the second The electrode 121 is made of aluminum. The semiconductor device 100 of the present embodiment, for example, a Schottky diode has two first electrodes 119 as anodes and one second electrode 121 as a cathode, and in other embodiments, may have different anode/cathode combinations.
上述係以藉由整合式的雙載子-互補式金氧半導體-擴散金氧半導體(BCD)製程製造的蕭特基二極體為實施例來說明本揭露的概念,本揭露的半導體裝置之製造方法也可應用於其他類型的半導體裝置,以精確控制並縮短井區之間的距離。 The above description is based on the Schottky diode manufactured by the integrated bi-carrier-complementary MOS-diffusion metal oxide semiconductor (BCD) process, and the concept of the present disclosure is described. The semiconductor device of the present disclosure The fabrication method can also be applied to other types of semiconductor devices to precisely control and shorten the distance between well regions.
由於蕭特基二極體具有金屬-半導體接面的蕭特基能障(Schottky barrier),使其在順向偏壓下具有低導通電壓(turn-on voltage)以及提高切換速率的優勢,常被用於電源管理積體電路中以提高電源轉換效率。然而,蕭特基二極體在逆向偏壓下具有漏電流偏大的問題,且逆向漏電流容易隨著溫度升高而急遽變大,特別是使用整合式的雙載子-互補式金氧半導體-擴散金氧半導體(BCD)製程製造的蕭特基二極體。 Due to the Schottky barrier of the Schottky diode with a metal-semiconductor junction, it has the advantage of low turn-on voltage and improved switching rate under forward bias. It is used in power management integrated circuits to improve power conversion efficiency. However, the Schottky diode has a problem of large leakage current under reverse bias, and the reverse leakage current tends to become larger as the temperature increases, especially using the integrated bi-carrier-complementary metal oxygen. Schottky diodes fabricated by semiconductor-diffused metal oxide semiconductor (BCD) processes.
本揭露之半導體裝置的實施例,蕭特基二極體係 利用快速熱退火製程(RTA)取代傳統的擴散製程,以精準地控制半導體基底內井區的側向擴散,以縮小井區與井區之間的距離,舉例而言,以往使用擴散製程形成的井區與井區之間的距離在約2微米至約4微米的範圍內,但本揭露使用快速熱退火製程形成的井區與井區之間的距離在約0.6微米至約1.2微米的範圍內,如此可減少蕭特基接觸面積,進而縮小蕭特基二極體的整體尺寸至以往使用擴散製程的70%至80%。 Embodiment of the semiconductor device of the present disclosure, Schottky diode system Replacing the traditional diffusion process with a rapid thermal annealing process (RTA) to precisely control the lateral diffusion of the well region within the semiconductor substrate to reduce the distance between the well and the well region, for example, previously formed using a diffusion process The distance between the well region and the well region is in the range of from about 2 microns to about 4 microns, but the distance between the well region and the well region formed using the rapid thermal annealing process is in the range of from about 0.6 microns to about 1.2 microns. This reduces the Schottky contact area and reduces the overall size of the Schottky diode to 70% to 80% of the previous diffusion process.
再者,由於本揭露之半導體裝置的實施例,蕭特基二極體具有較小的蕭特基接觸面積,在室溫和高溫(至約150℃)皆能具有極低的反向漏電流,也無需在製程中使用額外的離子植入或遮罩,可降低製程的成本。 Moreover, due to the embodiment of the semiconductor device of the present disclosure, the Schottky diode has a small Schottky contact area and can have a very low reverse leakage current at room temperature and high temperature (to about 150 ° C). There is also no need to use additional ion implantation or masking in the process to reduce the cost of the process.
以上概述數個實施例為特徵,以便在本發明所屬技術領域中具有通常知識者可以更理解本揭露的觀點。在發明所屬技術領域中具有通常知識者應該理解他們能以本揭露為基礎,設計或修改其他製程和結構以達到與在此介紹的實施例相同之目的及/或優勢。在發明所屬技術領域中具有通常知識者也應該理解到,此類等效的結構並無悖離本揭露的精神與範圍,且他們能在不違背本揭露之精神和範圍之下,做各式各樣的改變、取代和替換。 The above summary of the several embodiments is characterized in that the subject matter of the present disclosure can be more fully understood by those of ordinary skill in the art. Those having ordinary skill in the art should understand that they can design or modify other processes and structures based on the present disclosure to achieve the same objects and/or advantages as the embodiments described herein. It is also to be understood by those of ordinary skill in the art that the present invention is not limited to the spirit and scope of the disclosure, and that they can be practiced without departing from the spirit and scope of the disclosure. Various changes, substitutions and substitutions.
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