TW201806018A - 引入較低蝕刻速率的材料以形成ｔ形ｓｄｂ ｓｔｉ結構 - Google Patents

引入較低蝕刻速率的材料以形成ｔ形ｓｄｂ ｓｔｉ結構 Download PDF

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TW201806018A
TW201806018A TW106105272A TW106105272A TW201806018A TW 201806018 A TW201806018 A TW 201806018A TW 106105272 A TW106105272 A TW 106105272A TW 106105272 A TW106105272 A TW 106105272A TW 201806018 A TW201806018 A TW 201806018A
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shallow trench
trench isolation
single diffusion
sdb
sti
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彭建偉
吳旭昇
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格羅方德半導體公司
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Abstract

本發明提供一種在形成t形單擴散中斷的淺溝槽隔離(SDB STI)結構期間引入具有較低蝕刻速率的單擴散中斷(SDB)材料的方法。實施例包括在矽(Si)基板中設置淺溝槽隔離(STI)區域；在該STI區域及該矽基板上方形成硬遮罩；穿過該STI區域上方的該硬遮罩形成腔體，該腔體具有大於該STI區域的寬度的寬度；在該腔體中沉積具有低於高密度電漿(HDP)氧化物的蝕刻速率的單擴散中斷材料，以形成t形SDB STI結構；以及移除該硬遮罩。

Description

引入較低蝕刻速率的材料以形成T形SDB STI結構
本發明關於包括單擴散中斷(single diffusion break；SDB)的半導體裝置的製造。本發明尤其適用于14奈米(nm)技術節點及以下的t形單擴散中斷的淺溝槽隔離(SDB STI)結構的製造。
在半導體製造期間使用隔離結構來隔離設於半導體基板上的眾多材料。在這些隔離結構中，採用淺溝槽隔離(shallow trench isolation；STI)結構，因為所得溝槽可很好地適應小裝置隔離面積。該淺溝槽隔離(STI)區域通過在矽(Si)基板中蝕刻淺溝槽並接著用介電材料(例如氧化物)填充該溝槽來形成。類似地，單擴散中斷(SDB)是一種用於技術擴展以在較小設計面積上獲得相同功能的積體電路的技術。SDB可用以縮小電路面積，從而支持高密度積體電路的形成。通過使用位於該STI區域上方的高密度電漿(high density plasma；HDP)氧化物來使該STI區域具有t形，從而形成該SDB。不過，當前的SDB製程因鄰近該STI區域形成源/汲(S/D)腔體以後，保留于單 擴散中斷的淺溝槽隔離(SDB STI)側壁上的有限矽(Si)而具有嚴重的刻面(facet)嵌入矽鍺(eSiGe)及矽磷(eSiP)的問題。
因此，需要在PFET腔體蝕刻期間能夠保護該SDB STI側壁上的矽的方法以及所得裝置。
本發明的一個態樣是一種方法，其包括使用與高密度電漿(HDP)氧化物相比具有較低蝕刻速率的單擴散中斷(SDB)材料。
本發明的另一個態樣是一種裝置，其包括單擴散中斷(SDB)材料以防止源/汲(S/D)腔體接觸淺溝槽隔離(STI)。
本發明的額外態樣以及其它特徵將在下面的說明中闡述，且本領域的普通技術人員在檢查下文以後將在某種程度上清楚該些額外態樣以及其它特徵，或者該些額外態樣以及其它特徵可自本發明的實施中獲知。本發明的優點可如所附申請專利範圍中所特別指出的那樣來實現和獲得。
依據本發明，一些技術效果可通過一種方法在某種程度上實現，該方法包括：在矽(Si)基板中設置淺溝槽隔離(STI)區域；在該STI區域及該矽基板上方形成硬遮罩；穿過該STI區域上方的該硬遮罩形成腔體，該腔體具有大於該STI區域的寬度的寬度；在該腔體中沉積具有低於高密度電漿(HDP)氧化物的蝕刻速率的單擴散 中斷(SDB)材料，以形成t形單擴散中斷的淺溝槽隔離(SDB STI)結構；以及移除該硬遮罩。
另一個態樣包括由氮(N)改性(modifying)的二氧化矽(SiO2)形成該SDB材料。其它態樣包括該SDB材料具有在純氧化物與氮化矽(SiN)的蝕刻速率之間的蝕刻速率比。又一個態樣包括用10至40%的N改性該SiO2。另一個態樣包括由碳(C)改性的SiO2形成該SDB材料。又一個態樣包括該SDB材料具有在純氧化物與碳化矽(SiC)的蝕刻速率之間的蝕刻速率比。另一個態樣包括用1至15%的C改性該SiO2。
另一個態樣包括在垂直於該STI區域的該矽基板中設置用STI材料填充的溝槽；在移除該硬遮罩以後，凹入該STI材料以形成矽鰭片，其中，凹入該STI材料以後，SDB的寬度大於該STI區域的寬度。其它態樣包括該SDB層具有35奈米至90奈米(nm)的寬度。
另一個態樣包括在鄰近該STI的各側的該矽基板中形成腔體；以及在該腔體中磊晶生長矽鍺(eSiGe)或矽磷(eSiP)。其它態樣包括該SDB層防止該腔體接觸該STI。
本發明的另一個態樣是一種裝置，其包括：具有鰭片(FINs)的矽基板；位於該些鰭片之間的該基板中的淺溝槽隔離(STI)材料；位於鰭片中並延伸進入下方矽基板中的STI區域；具有低於高密度電漿(HDP)氧化物的蝕刻速率的單擴散中斷(SDB)材料，位於該STI上方以形成t形單擴散中斷的淺溝槽隔離(SDB STI)結構； 以及源/汲(S/D)區，位於該STI區域的相對側上，該S/D通過矽與該STI區域隔開。
該裝置的態樣包括該SDB層具有35奈米至90奈米的寬度。其它態樣包括該SDB包括用N改性的SiO2，且該SDB具有在純氧化物與SiN的蝕刻速率之間的蝕刻速率比。
又一個態樣包括該SiO2通過10至40%的N改性。另一個態樣包括該SDB包括用C改性的SiO2，且該SDB材料具有在純氧化物與SiC的蝕刻速率之間的蝕刻速率比。又一個態樣包括該SiO2通過1至15%的C改性。另一個態樣包括該SDB材料包括純氮化物。
本發明的另一個態樣是一種方法，其包括：在矽(Si)基板中設置淺溝槽隔離(STI)區域；在該STI區域及該矽基板上方沉積硬遮罩氮化矽(HM SiN)材料以形成硬遮罩；在該硬遮罩的上表面上形成光阻；移除該硬遮罩的中心部分以形成開口；移除該光阻；通過該開口蝕刻該STI區域及該矽基板，以在該STI區域上方形成腔體，該腔體具有大於該STI區域的寬度的寬度；在該腔體中沉積包括用氮(N)或碳(C)改性的二氧化矽(SiO2)或純氮化物的單擴散中斷(SDB)材料；向下平坦化該SDB材料至該硬遮罩，以形成t形單擴散中斷的淺溝槽隔離(SDB STI)結構；以及移除該硬遮罩；在垂直於該STI區域的該矽基板中設置用STI材料填充的溝槽；在移除該硬遮罩以後，凹入該STI材料以形成矽鰭片。
本領域的技術人員從下面的詳細說明中將很容易瞭解額外的態樣以及技術效果，在該詳細說明中，通過示例擬執行本發明的最佳模式來簡單說明本發明的實施例。本領域的技術人員將意識到，本發明支持其它及不同的實施例，且其數個細節支持在各種顯而易見的方面的修改，所有這些都不背離本發明。相應地，附圖及說明將被看作示例性質而非限制。
101‧‧‧矽部分
103、204‧‧‧淺溝槽隔離(STI)區域
105‧‧‧硬遮罩
107、203、205‧‧‧腔體
109、201‧‧‧單擴散中斷(SDB)材料
207、209‧‧‧矽
211、213‧‧‧矽鍺或矽磷(eSiGe/eSiP)
附圖中的圖形示例顯示(而非限制)本發明，附圖中類似的附圖標記表示類似的元件，且其中：第1A至1G圖示意依據一個示例實施例顯示用具有低於高密度電漿(HDP)氧化物的蝕刻速率的單擴散中斷(SDB)材料形成t形單擴散中斷的淺溝槽隔離(SDB STI)結構的製程的序列步驟；以及第2A至2B圖示意依據一個示例實施例顯示單擴散中斷(SDB)材料防止源/汲(S/D)腔體接觸淺溝槽隔離(STI)側壁。
在下面的說明中，出於解釋目的，闡述許多具體細節來提供有關示例實施例的充分理解。不過，應當很清楚，可在不具有這些具體細節或者具有等同佈置的情況下實施示例實施例。在其它情況下，以方塊圖形式顯示已知的結構及裝置，以避免不必要地模糊示例實施例。此外，除非另外指出，否則說明書及申請專利範圍中所使用 的表示組分的量、比例及數值屬性、反應條件等的所有數字將被理解為通過術語“大約”在所有情況下被修飾。
本發明處理並解決當前利用高密度電漿(HDP)氧化物形成單擴散中斷(SDB)所伴隨的嚴重的刻面磊晶(epitaxial；EPI)生長的問題。依據本發明的實施例，通過用具有顯著較低蝕刻速率的SDB材料替代該HDP氧化物來獲得t形單擴散中斷的淺溝槽隔離(SDB STI)結構。由於該SDB材料具有較慢的蝕刻速率，因此剩餘SDB材料具有較大的橫向寬度並能夠在該源/汲(S/D)腔體蝕刻期間保護該淺溝槽隔離(STI)側壁上的矽，其相應為後續S/D磊晶生長提供更加對稱的種子層(seed layer)。
依據本發明的實施例的方法包括在矽(Si)基板中設置淺溝槽隔離(STI)區域以及在該STI區域及該矽基板上方形成硬遮罩。然後，穿過該STI區域上方的該硬遮罩形成腔體，該腔體具有大於該STI區域的寬度的寬度。接著，在該腔體中沉積具有低於高密度電漿(HDP)氧化物的蝕刻速率的單擴散中斷(SDB)材料，以形成t形單擴散中斷的淺溝槽隔離(SDB STI)結構。然後，移除該硬遮罩。
本領域的技術人員從下面的詳細說明中將很容易瞭解其它態樣、特徵以及技術效果，在該詳細說明中，簡單地通過示例所考慮的最佳模式來顯示並說明優選實施例。本發明支持其它及不同的實施例，且其數個細節支持在各種顯而易見的方面的修改。相應地，附圖及說明將被看作示例性質而非限制。
第1A至1G圖示意依據一個示例實施例顯示用具有低於密度電漿(HDP)氧化物的蝕刻速率的單擴散中斷(SDB)材料形成t形單擴散中斷的淺溝槽隔離(SDB STI)結構的製程的序列步驟。請參照第1A圖，矽基板包括位於該矽基板上的交替的矽部分(包括矽部分101)與STI部分(出於說明方便未顯示)。例如由二氧化矽(SiO2)形成的淺溝槽隔離(STI)區域103垂直於並嵌入該矽部分101及該STI部分中，且第1A圖顯示沿一個矽部分101的長度的剖視圖。然後，在矽部分101及STI區域103上方形成硬遮罩105(例如由氮化矽(SiN)形成)。在第1B圖中，在硬遮罩105的上表面上形成光阻(出於說明方便未顯示)。接著，在位於STI區域103上方中心的硬遮罩105中形成例如具有35奈米至90奈米的寬度的開口。隨後，移除該光阻。接著，通過該開口蝕刻矽部分101及STI區域103，以在STI區域103上方形成腔體107。腔體107具有大於該STI區域的寬度的寬度。
在第1C圖中，在硬遮罩105及腔體107上方沉積單擴散中斷(SDB)材料109。該SDB可由用10至40%的N(氮)改性的二氧化矽(SiO2)形成，其中，該SDB材料具有在純氧化物與氮化矽(SiN)的蝕刻速率之間的蝕刻速率比。或者，該SDB可由用1至15%的C(碳)改性的SiO2形成，其中，該SDB材料具有在純氧化物與碳化矽(SiC)的蝕刻速率之間的蝕刻速率比。SDB材料109也可由純氮形成。接著，例如通過化學機械拋光(chemical mechanical polishing；CMP)將SDB材料109向下平坦化至硬遮罩105，如第1D圖中所示。然後，移除硬遮罩105並形成所得t形SDB STI結構，如第1E圖中所示。
請參照第1F及1G圖，在移除硬遮罩105以後，凹入未顯示的該STI區域以形成矽鰭片(在矽部分1E)。該STI材料通過乾式蝕刻而凹入(第1F圖)，例如通過使用徑向線縫隙天線(radial line slot antenna；RLSA)工具進行蝕刻，接著執行濕式蝕刻(第1G圖)，例如Siconi蝕刻。在各該乾式蝕刻及該濕式蝕刻期間，可降低材料109的厚度，但因該慢蝕刻速率而使寬度保持不變。這樣，與HDP氧化物(其最終為STI區域103的寬度)不同，SDB材料109突出於STI區域103的邊緣之上。
第2A至2B圖示意依據一個示例實施例顯示單擴散中斷(SDB)材料防止腔體接觸該淺溝槽隔離(STI)。在當前的實施中，連續的腔體蝕刻以獲得優化接近導致該腔體接觸該STI氧化物並且在該STI側壁上沒有留下矽。在第2A圖中，單擴散中斷(SDB)材料201突出於淺溝槽隔離(STI)區域204的側壁之上，從而在分別形成腔體203及腔體205時保護該側壁上的矽，並在該STI側壁上保留一層矽207及209。請參照第2B圖，在腔體203及腔體205中磊晶生長矽鍺或矽磷(eSiGe/eSiP)211及213。保留于該t形單擴散中斷的淺溝槽隔離(SDB STI)側壁上的矽207及209為該矽鍺或矽磷(eSiGe/eSiP)提供種子層，其導致最小刻面磊晶(minumum facet EPI)。
本發明的實施例可實現數個技術效果，例如改善結 磊晶刻面(junction EPI facet)問題以提升裝置性能。依據本發明的實施例所形成的裝置適於各種工業應用，例如微處理器、智慧型電話、行動電話、蜂窩手機、機上盒、DVD記錄器及播放器、汽車導航、印表機及周邊設備、網路及電信設備、遊戲系統、以及數位相機。因此，本發明對於任意各種類型的高度積體finFET半導體裝置具有工業適用性，尤其是14奈米技術節點及以下。
在前面的說明中，參照本發明的具體示例實施例來說明本發明。不過，顯然，可對其作各種修改及變更，而不背離如申請專利範圍中所闡述的本發明的較廣泛的精神及範圍。相應地，說明書及附圖將被看作示例性質而非限制。應當理解，本發明能夠使用各種其它組合及實施例，且支持在本文所表示的發明性概念的範圍內的任意修改或變更。
101‧‧‧矽部分
103‧‧‧淺溝槽隔離(STI)區域
105‧‧‧硬遮罩

Claims (20)

  1. 一種方法，包括：在矽(Si)基板中設置淺溝槽隔離(STI)區域；在該淺溝槽隔離區域及該矽基板上方形成硬遮罩；穿過該淺溝槽隔離區域上方的該硬遮罩形成腔體，該腔體具有大於該淺溝槽隔離區域的寬度的寬度；在該腔體中沉積具有低於高密度電漿(HDP)氧化物的蝕刻速率的單擴散中斷(SDB)氧化物材料，以形成t形單擴散中斷的淺溝槽隔離(SDB STI)結構；以及移除該硬遮罩。
  2. 如申請專利範圍第1項所述的方法，包括由氮(N)改性的二氧化矽(SiO2)形成該單擴散中斷材料。
  3. 如申請專利範圍第2項所述的方法，其中，該單擴散中斷材料具有在純氧化物與氮化矽(SiN)的蝕刻速率之間的蝕刻速率比。
  4. 如申請專利範圍第2項所述的方法，包括用10至40%的氮改性該二氧化矽。
  5. 如申請專利範圍第1項所述的方法，包括由碳(C)改性的二氧化矽(SiO2)形成該單擴散中斷材料。
  6. 如申請專利範圍第5項所述的方法，其中，該單擴散中斷材料具有在純氧化物與碳化矽(SiC)的蝕刻速率之間的蝕刻速率比。
  7. 如申請專利範圍第5項所述的方法，包括用1至15% 的碳改性該二氧化矽。
  8. 如申請專利範圍第1項所述的方法，包括由純氮化物形成該單擴散中斷材料。
  9. 如申請專利範圍第1項所述的方法，還包括：在垂直於該淺溝槽隔離區域的該矽基板中設置用淺溝槽隔離材料填充的溝槽；在移除該硬遮罩以後，凹入該淺溝槽隔離材料以形成矽鰭片，其中，凹入該淺溝槽隔離材料以後，單擴散中斷層的寬度大於該淺溝槽隔離區域的寬度。
  10. 如申請專利範圍第9項所述的方法，其中，該單擴散中斷層的寬度為35至90奈米(nm)。
  11. 如申請專利範圍第1項所述的方法，還包括：在鄰近該淺溝槽隔離的各側的該矽基板中形成腔體；以及在該腔體中磊晶生長矽鍺(eSiGe)或矽磷(eSiP)。
  12. 如申請專利範圍第11項所述的方法，其中，該單擴散中斷層防止該腔體接觸該淺溝槽隔離。
  13. 一種裝置，包括：矽(Si)基板，具有鰭片(FINs)；淺溝槽隔離(STI)材料，位於所述鰭片之間的該基板中；淺溝槽隔離區域，位於鰭片中並延伸進入下方該矽基板中； 具有低於高密度電漿(HDP)氧化物的蝕刻速率的單擴散中斷(SDB)氧化物材料，位於該淺溝槽隔離上方以形成t形單擴散中斷的淺溝槽隔離(SDB STI)結構；以及源/汲(S/D)區，位於該淺溝槽隔離區域的相對側上，該源/汲通過矽與該淺溝槽隔離區域隔開。
  14. 如申請專利範圍第13項所述的裝置，其中，該單擴散中斷層具有35至90奈米(nm)的寬度。
  15. 如申請專利範圍第13項所述的裝置，其中，該單擴散中斷包括用氮(N)改性的二氧化矽(SiO2)，且該單擴散中斷具有在純氧化物與氮化矽(SiN)的蝕刻速率之間的蝕刻速率比。
  16. 如申請專利範圍第15項所述的裝置，其中，該二氧化矽通過10至40%的氮改性。
  17. 如申請專利範圍第13項所述的裝置，其中，該單擴散中斷包括用碳(C)改性的二氧化矽(SiO2)，且該單擴散中斷材料具有在純氧化物與碳化矽(SiC)的蝕刻速率之間的蝕刻速率比。
  18. 如申請專利範圍第17項所述的裝置，其中，該二氧化矽通過1至15%的碳改性。
  19. 如申請專利範圍第13項所述的裝置，其中，該單擴散中斷材料包括純氮化物。
  20. 一種方法，包括：在矽(Si)基板中設置淺溝槽隔離(STI)區域； 在該淺溝槽隔離區域及該矽基板上方沉積硬遮罩氮化矽(HM SiN)材料以形成硬遮罩；在該硬遮罩的上表面上形成光阻；移除該硬遮罩的中心部分以形成開口；移除該光阻；通過該開口蝕刻該淺溝槽隔離區域及該矽基板，以在該淺溝槽隔離區域上方形成腔體，該腔體具有大於該淺溝槽隔離區域的寬度的寬度；沉積包括用氮(N)或碳(C)改性的二氧化矽(SiO2)或純氮化物的單擴散中斷(SDB)材料，該單擴散中斷材料位於該腔體中；向下平坦化該單擴散中斷材料至該硬遮罩，以形成t形單擴散中斷的淺溝槽隔離(SDB STI)結構；以及移除該硬遮罩；在垂直於該淺溝槽隔離區域的該矽基板中設置用淺溝槽隔離材料填充的溝槽；在移除該硬遮罩以後，凹入該淺溝槽隔離材料以形成矽鰭片，其中，凹入該淺溝槽隔離材料以後，單擴散中斷層的寬度大於該淺溝槽隔離區域的寬度。
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