TW201804454A - Output buffer apparatus - Google Patents
Output buffer apparatus Download PDFInfo
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- TW201804454A TW201804454A TW105124036A TW105124036A TW201804454A TW 201804454 A TW201804454 A TW 201804454A TW 105124036 A TW105124036 A TW 105124036A TW 105124036 A TW105124036 A TW 105124036A TW 201804454 A TW201804454 A TW 201804454A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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Abstract
Description
本發明是有關於一種電子裝置，且特別是有關於一種輸出緩衝裝置。The present invention relates to an electronic device, and more particularly, to an output buffer device.
隨著光電與半導體元件之進步，平面顯示器諸如液晶顯示器（liquid crystal display, LCD）在近幾年蓬勃地發展。液晶顯示器因具有多項優點，例如低功率消耗、無輻射與高空間利用率，而逐漸地成為市場的主流。源極驅動器為液晶顯示器中相當重要的元件，其能轉換顯示影像之數位資料信號為類比信號，且輸出此類比信號至顯示面板的每個像素。一般來說，源極驅動器包含多個驅動通道來傳送類比信號至每一資料線上的像素，且其亦包含多個輸出緩衝器來提升信號傳輸強度。為了滿足可輸出不同極性的驅動電壓，一般會在緩衝器的輸出端配置傳輸閘來切換輸出至資料線的驅動電壓，此方式雖可滿足切換驅動電壓極性的需求，然由於傳輸閘本身具有一定的電阻，因此將會影響輸出緩衝器對畫素電容的充放電速度與特性，進而降低顯示品質。With the advancement of optoelectronics and semiconductor components, flat-panel displays such as liquid crystal displays (LCDs) have flourished in recent years. Liquid crystal displays have gradually become the mainstream of the market due to their many advantages, such as low power consumption, no radiation, and high space utilization. The source driver is a very important element in the liquid crystal display. It can convert the digital data signal of the displayed image into an analog signal, and output the analog signal to each pixel of the display panel. Generally, a source driver includes multiple driving channels to transmit analog signals to pixels on each data line, and it also includes multiple output buffers to improve signal transmission strength. In order to meet the requirements of driving voltages with different polarities, a transmission gate is usually configured at the output end of the buffer to switch the driving voltage output to the data line. Although this method can meet the needs of switching the driving voltage polarity, the transmission gate itself has a certain The resistance of the output buffer will affect the charging and discharging speed and characteristics of the pixel capacitor of the output buffer, thereby reducing the display quality.
本發明提供一種輸出緩衝裝置，可滿足輸出不同電壓範圍的輸出電壓的需求，同時有效地提高輸出緩衝裝置的驅動能力。The invention provides an output buffer device, which can meet the requirements for outputting output voltages in different voltage ranges, and effectively improve the driving capability of the output buffer device.
本發明的輸出緩衝裝置包括第一運算放大器、第一輸出級電路、第二輸出級電路、第一開關電路以及第二開關電路。第一運算放大器的正輸入端用以接收第一輸入信號。第一輸出級電路依據第一運算放大器的輸出端的輸出電壓提供落於第一電壓範圍內的輸出電壓。第二輸出級電路依據第一運算放大器的輸出端的輸出電壓提供落於第二電壓範圍內的輸出電壓，其中第一輸出級電路耦接第二輸出級電路的輸出端相互耦接且耦接至第一運算放大器的負輸入端。第一開關電路耦接於第一運算放大器的輸出端與第一輸出級電路之間。第二開關電路耦接於第一運算放大器的輸出端與第二輸出級電路之間，第一開關電路與第二開關電路分別受控於一第一控制信號與一第二控制信號，以決定是否將第一運算放大器的輸出端連接至第一輸出級電路或將第一運算放大器的輸出端連接至第二輸出級電路。The output buffer device of the present invention includes a first operational amplifier, a first output stage circuit, a second output stage circuit, a first switching circuit, and a second switching circuit. The positive input terminal of the first operational amplifier is used to receive a first input signal. The first output stage circuit provides an output voltage falling within a first voltage range according to an output voltage of an output terminal of the first operational amplifier. The second output stage circuit provides an output voltage falling within a second voltage range according to the output voltage of the output terminal of the first operational amplifier, wherein the output ends of the first output stage circuit coupled to the second output stage circuit are coupled to each other and are coupled to The negative input terminal of the first operational amplifier. The first switching circuit is coupled between the output terminal of the first operational amplifier and the first output stage circuit. The second switch circuit is coupled between the output terminal of the first operational amplifier and the second output stage circuit. The first switch circuit and the second switch circuit are respectively controlled by a first control signal and a second control signal to determine Whether to connect the output terminal of the first operational amplifier to the first output stage circuit or the output terminal of the first operational amplifier to the second output stage circuit.
在本發明的一實施例中，上述的第一輸出級電路包括第一P型電晶體以及第一N型電晶體。第一P型電晶體耦接於第一電源電壓與第一輸出級電路的輸出端之間，第一P型電晶體的閘極耦接第一開關電路。第一N型電晶體耦接於第一輸出級電路的輸出端與第二電源電壓之間，第一N型電晶體的閘極耦接第一開關電路。According to an embodiment of the present invention, the first output stage circuit includes a first P-type transistor and a first N-type transistor. The first P-type transistor is coupled between the first power supply voltage and the output terminal of the first output stage circuit, and the gate of the first P-type transistor is coupled to the first switching circuit. The first N-type transistor is coupled between the output terminal of the first output stage circuit and the second power voltage, and the gate of the first N-type transistor is coupled to the first switch circuit.
在本發明的一實施例中，上述的第一控制信號包括第一切換控制信號與第一反相切換控制信號，第一開關電路包括第一傳輸閘、第二傳輸閘、第二P型電晶體以及第二N型電晶體。第一傳輸閘耦接於第一運算放大器的輸出端與第一P型電晶體的閘極之間。第二傳輸閘耦接於第一運算放大器的輸出端與第一N型電晶體的閘極之間，第一傳輸閘與第二傳輸閘受控於第一切換控制信號與第一反相切換控制信號而同時被導通或關閉。第二P型電晶體耦接於第一電源電壓與第一P型電晶體的閘極之間，第二P型電晶體的閘極接收第一切換控制信號。第二N型電晶體耦接於第一N型電晶體的閘極與第二電源電壓之間，第二N型電晶體的閘極接收第一反相切換控制信號。In an embodiment of the present invention, the above-mentioned first control signal includes a first switching control signal and a first inverted switching control signal, and the first switching circuit includes a first transmission gate, a second transmission gate, and a second P-type circuit. A crystal and a second N-type transistor. The first transmission gate is coupled between the output terminal of the first operational amplifier and the gate of the first P-type transistor. The second transmission gate is coupled between the output terminal of the first operational amplifier and the gate of the first N-type transistor. The first transmission gate and the second transmission gate are controlled by the first switching control signal and the first inversion switching. The control signal is turned on or off at the same time. The second P-type transistor is coupled between the first power voltage and the gate of the first P-type transistor. The gate of the second P-type transistor receives the first switching control signal. The second N-type transistor is coupled between the gate of the first N-type transistor and the second power supply voltage, and the gate of the second N-type transistor receives a first inverted switching control signal.
在本發明的一實施例中，上述的第二輸出級電路包括第二P型電晶體以及第二N型電晶體。第二P型電晶體耦接於第三電源電壓與第二輸出級電路的輸出端之間，第二P型電晶體的閘極耦接第二開關電路。第二N型電晶體耦接於第二輸出級電路的輸出端與第四電源電壓之間，第二N型電晶體的閘極耦接第二開關電路。In an embodiment of the present invention, the second output stage circuit includes a second P-type transistor and a second N-type transistor. The second P-type transistor is coupled between the third power supply voltage and the output terminal of the second output stage circuit, and the gate of the second P-type transistor is coupled to the second switching circuit. The second N-type transistor is coupled between the output terminal of the second output stage circuit and the fourth power voltage, and the gate of the second N-type transistor is coupled to the second switch circuit.
在本發明的一實施例中，上述的第二控制信號包括第二切換控制信號與第二反相切換控制信號，第二開關電路包括第一傳輸閘、第二傳輸閘、第三P型電晶體以及第三N型電晶體。第一傳輸閘耦接於第一運算放大器的輸出端與第二P型電晶體的閘極之間。第二傳輸閘耦接於第一運算放大器的輸出端與第二N型電晶體的閘極之間，第一傳輸閘與第二傳輸閘受控於第二切換控制信號與第二反相切換控制信號而同時被導通或關閉。第三P型電晶體耦接於第三電源電壓與第二P型電晶體的閘極之間，第三P型電晶體的閘極接收第二切換控制信號。第三N型電晶體耦接於第二N型電晶體的閘極與第四電源電壓之間，第三N型電晶體的閘極接收第二反相切換控制信號。In an embodiment of the present invention, the above-mentioned second control signal includes a second switching control signal and a second inversion switching control signal, and the second switching circuit includes a first transmission gate, a second transmission gate, and a third P-type electric current. Crystal and a third N-type transistor. The first transmission gate is coupled between the output terminal of the first operational amplifier and the gate of the second P-type transistor. The second transmission gate is coupled between the output terminal of the first operational amplifier and the gate of the second N-type transistor. The first transmission gate and the second transmission gate are controlled by the second switching control signal and the second inversion switching. The control signal is turned on or off at the same time. The third P-type transistor is coupled between the third power supply voltage and the gate of the second P-type transistor, and the gate of the third P-type transistor receives the second switching control signal. The third N-type transistor is coupled between the gate of the second N-type transistor and the fourth power supply voltage, and the gate of the third N-type transistor receives a second inverted switching control signal.
在本發明的一實施例中，上述的第一電源電壓大於第二電源電壓，第三電源電壓大於第四電源電壓。In an embodiment of the present invention, the first power supply voltage is greater than the second power supply voltage, and the third power supply voltage is greater than the fourth power supply voltage.
在本發明的一實施例中，上述的輸出緩衝裝置更包括第二運算放大器、切換電路、第三輸出級電路、第四輸出級電路、第三開關電路以及第四開關電路。切換電路耦接第一運算放大器與第二運算放大器的正輸入端，接收第一輸入信號與第二輸入信號，受控於選擇信號切換輸出至第一運算放大器與第二運算放大器的正輸入端的信號。第三輸出級電路依據第二運算放大器的輸出端的輸出電壓提供落於第一電壓範圍內的輸出電壓。第四輸出級電路，依據第二運算放大器的輸出端的輸出電壓提供落於第二電壓範圍內的輸出電壓，其中第三輸出級電路耦接第四輸出級電路的輸出端相互耦接且耦接至第二運算放大器的負輸入端。第三開關電路耦接於第二運算放大器的輸出端與第三輸出級電路之間。第四開關電路耦接於第二運算放大器的輸出端與第四輸出級電路之間，第三開關電路與第四開關電路分別受控於第三控制信號與第四控制信號，以決定是否將第二運算放大器的輸出端連接至第三輸出級電路或將第二運算放大器的輸出端連接至第四輸出級電路。In an embodiment of the present invention, the output buffer device further includes a second operational amplifier, a switching circuit, a third output stage circuit, a fourth output stage circuit, a third switching circuit, and a fourth switching circuit. The switching circuit is coupled to the positive input terminals of the first operational amplifier and the second operational amplifier, receives the first input signal and the second input signal, and is controlled by the selection signal to switch and output to the positive input terminals of the first operational amplifier and the second operational amplifier. signal. The third output stage circuit provides an output voltage falling within the first voltage range according to the output voltage of the output terminal of the second operational amplifier. The fourth output stage circuit provides an output voltage falling within the second voltage range according to the output voltage of the output terminal of the second operational amplifier, wherein the third output stage circuit is coupled to the output terminals of the fourth output stage circuit and is coupled to each other. To the negative input terminal of the second operational amplifier. The third switch circuit is coupled between the output terminal of the second operational amplifier and the third output stage circuit. The fourth switch circuit is coupled between the output terminal of the second operational amplifier and the fourth output stage circuit. The third switch circuit and the fourth switch circuit are controlled by the third control signal and the fourth control signal, respectively, to determine whether to switch the The output terminal of the second operational amplifier is connected to the third output stage circuit or the output terminal of the second operational amplifier is connected to the fourth output stage circuit.
基於上述，本發明實施例的第一開關電路與第二開關電路耦接運算放大器的輸出端、第一輸出級電路與第二輸出級電路之間，第一開關電路與第二開關電路分別受控於第一控制信號與第二控制信號，而決定使第一輸出級電路依據運算放大器的輸出端的輸出電壓提供落於第一電壓範圍內的輸出電壓，或使第二輸出級電路依據運算放大器的輸出端的輸出電壓提供落於第二電壓範圍內的輸出電壓，進而滿足輸出不同電壓範圍的輸出電壓的需求，同時有效地提高輸出緩衝裝置的驅動能力。Based on the above, the first switch circuit and the second switch circuit of the embodiment of the present invention are coupled to the output end of the operational amplifier, between the first output stage circuit and the second output stage circuit, and the first switch circuit and the second switch circuit are respectively affected. Controlled by the first control signal and the second control signal, and decided to make the first output stage circuit provide an output voltage falling within the first voltage range according to the output voltage of the output terminal of the operational amplifier, or make the second output stage circuit according to the operational amplifier The output voltage of the output terminal provides an output voltage falling within the second voltage range, thereby meeting the demand for outputting output voltages in different voltage ranges, and effectively improving the driving capability of the output buffer device.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.
圖1是依照本發明一實施例的一種輸出緩衝裝置的示意圖，請參照圖1。輸出緩衝裝置包括運算放大器102、輸出級電路104、輸出級電路106、開關電路108以及開關電路110。其中運算放大器102的正輸入端用以接收輸入信號VIN，運算放大器102的負輸入端耦接輸出級電路104與輸出級電路106的輸出端TO，以接收來自輸出級電路104與輸出級電路106的回授信號。開關電路108耦接於運算放大器102的輸出端與輸出級電路104的輸入端之間，開關電路110耦接於運算放大器102的輸出端與輸出級電路106的輸入端之間。此外，輸出級電路104與輸出級電路106的輸出端TO連接至負載112，在本實施例中負載可例如為液晶顯示面板，然不以此為限，液晶顯示面板可包括等效電阻RL1以及液晶電容CL1。FIG. 1 is a schematic diagram of an output buffer device according to an embodiment of the present invention. Please refer to FIG. 1. The output buffer device includes an operational amplifier 102, an output stage circuit 104, an output stage circuit 106, a switching circuit 108, and a switching circuit 110. The positive input terminal of the operational amplifier 102 is used to receive the input signal VIN, and the negative input terminal of the operational amplifier 102 is coupled to the output terminal TO of the output stage circuit 104 and the output stage circuit 106 to receive the output stage circuit 104 and the output stage circuit 106. Feedback signal. The switching circuit 108 is coupled between the output of the operational amplifier 102 and the input of the output stage circuit 104, and the switching circuit 110 is coupled between the output of the operational amplifier 102 and the input of the output stage circuit 106. In addition, the output stage TO of the output stage circuit 104 and the output stage circuit 106 is connected to the load 112. In this embodiment, the load may be, for example, a liquid crystal display panel, but is not limited thereto. The liquid crystal display panel may include an equivalent resistance RL1 and Liquid crystal capacitor CL1.
運算放大器102可依據輸入信號VIN以及輸出級電路104與輸出級電路106的輸出端TO所提供的回授信號於其輸出端產生輸出電壓，而輸出級電路104、輸出級電路106則可分別依據運算放大器102的輸出端所提供的輸出電壓產生不同電壓範圍的輸出電壓至負載112，另外開關電路108以及開關電路110則可分別受控於控制信號SC1與控制信號SC2，以決定是否將運算放大器102的輸出端連接至輸出級電路104或將運算放大器102的輸出端連接至第二輸出級電路106，亦即決定由輸出級電路104或輸出級電路106輸出電壓至負載112。The operational amplifier 102 can generate an output voltage at its output terminal according to the input signal VIN and the feedback signal provided by the output terminal TO of the output stage circuit 104 and the output stage circuit 106, and the output stage circuit 104 and the output stage circuit 106 can respectively The output voltage provided by the output terminal of the operational amplifier 102 generates output voltages of different voltage ranges to the load 112. In addition, the switching circuit 108 and the switching circuit 110 can be controlled by the control signal SC1 and the control signal SC2, respectively, to determine whether to use the operational amplifier. The output end of 102 is connected to the output stage circuit 104 or the output end of the operational amplifier 102 is connected to the second output stage circuit 106, that is, it is determined that the output stage circuit 104 or the output stage circuit 106 outputs a voltage to the load 112.
舉例來說，假設本實施例的輸出緩衝裝置為應用於液晶顯示面板，而有輸出不同極性的驅動電壓至負載112的需求，此時可設計使輸出級電路104負責輸出正極性的輸出電壓以驅動負載112，對液晶電容CL1進行充電，而輸出級電路106則負責輸出負極性的輸出電壓對液晶電容CL1進行充電。另外開關電路108以及開關電路110則分別受控於控制信號SC1與控制信號SC2，以決定輸出級電路104與輸出級電路106依據運算放大器102的輸出端電壓提供正極性輸出電壓與負極性輸出電壓的時點。For example, assuming that the output buffer device of this embodiment is applied to a liquid crystal display panel, and there is a need to output driving voltages of different polarities to the load 112, at this time, the output stage circuit 104 can be designed to output a positive output voltage to The load 112 is driven to charge the liquid crystal capacitor CL1, and the output stage circuit 106 is responsible for outputting a negative-polarity output voltage to charge the liquid crystal capacitor CL1. In addition, the switching circuit 108 and the switching circuit 110 are controlled by the control signal SC1 and the control signal SC2, respectively, to determine the output stage circuit 104 and the output stage circuit 106 to provide a positive output voltage and a negative output voltage according to the output terminal voltage of the operational amplifier 102. Time.
如此藉由在各個資料驅動通道的運算放大器的輸出端配置具有出不同電壓範圍的輸出級電路，並透過開關電路控制輸出級電路的輸出，除了可滿足輸出不同極性的輸出電壓的需求外，亦不會如先前技術般，因輸出至液晶顯示面板的輸出電壓須經過傳輸閘而降低了輸出緩衝裝置的驅動能力，進而影響液晶顯示面板的顯示品質。In this way, by arranging output stage circuits having different voltage ranges at the output ends of the operational amplifiers of each data driving channel, and controlling the output of the output stage circuit through the switching circuit, in addition to meeting the needs of outputting output voltages of different polarities, It will not reduce the driving capability of the output buffer device because the output voltage output to the liquid crystal display panel must pass through the transmission gate as in the prior art, thereby affecting the display quality of the liquid crystal display panel.
圖2是依照本發明另一實施例的一種輸出緩衝裝置的示意圖，請參照圖2。在本實施例中，運算放大器102包括電晶體P1~P9以及電晶體N1~N9，其中電晶體P1~P9為P型電晶體而電晶體N1~N9為N型電晶體。電晶體P1~P3以及電晶體N1~N3可構成差動對電路，以進行差動放大，電晶體P4~P7以及電晶體N4~N7可分別構成電流鏡電路而作為主動負載，另外電晶體P8~P9以及電晶體N8~N9則用以構成偏壓電路進行偏壓，其中電晶體P3、N3、P8、N8、P9、N9的閘極接收偏壓電壓VB1、VB2、VB5、VB6、VB7、VB8，電晶體P6、P7的閘極接收偏壓電壓VB3，電晶體N6、N7的閘極接收偏壓電壓VB4，以分別提供適當的電阻。另外，本實施例的輸出級電路104包括電晶體P10、N10，輸出級電路106包括電晶體P11、N11，開關電路108包括電晶體P12、N12以及傳輸閘TS1、TS2，開關電路110則包括電晶體P13、N13以及傳輸閘TS3、TS4，其中電晶體P10~P13為P型電晶體，電晶體N10~N13為N型電晶體，另外傳輸閘TS1~TS4可例如以一個P型電晶體與一個N型電晶體來實施，然不以此為限。FIG. 2 is a schematic diagram of an output buffer device according to another embodiment of the present invention. Please refer to FIG. 2. In this embodiment, the operational amplifier 102 includes transistors P1 to P9 and transistors N1 to N9, where the transistors P1 to P9 are P-type transistors and the transistors N1 to N9 are N-type transistors. Transistors P1 ~ P3 and transistors N1 ~ N3 can form a differential pair circuit for differential amplification. Transistors P4 ~ P7 and transistors N4 ~ N7 can respectively form a current mirror circuit as an active load. In addition, transistor P8 ~ P9 and transistors N8 ~ N9 are used to form a bias circuit for biasing. The gates of transistors P3, N3, P8, N8, P9, and N9 receive bias voltages VB1, VB2, VB5, VB6, and VB7. , VB8, the gates of the transistors P6 and P7 receive the bias voltage VB3, and the gates of the transistors N6 and N7 receive the bias voltage VB4 to provide appropriate resistances, respectively. In addition, the output stage circuit 104 of this embodiment includes transistors P10 and N10, the output stage circuit 106 includes transistors P11 and N11, the switching circuit 108 includes transistors P12 and N12 and the transmission gates TS1 and TS2, and the switching circuit 110 includes a transistor The crystals P13 and N13 and the transmission gates TS3 and TS4, among which the transistors P10 to P13 are P-type transistors, the transistors N10 to N13 are N-type transistors, and the transmission gates TS1 to TS4 can be, for example, one P-type transistor and one N-type transistors are implemented, but not limited to this.
傳輸閘TS1的一端耦接運算放大器102的輸出端TO1(亦即電晶體P7與電晶體P9的共同接點)，另一端則耦接電晶體P10的閘極，電晶體P12耦接於電源電壓VDD1與電晶體P10的閘極之間，電晶體P10耦接於電源電壓VDD1與輸出端TO之間。另外，傳輸閘TS2的一端耦接運算放大器102的輸出端TO2(亦即電晶體N7與電晶體N9的共同接點)，另一端則耦接電晶體N10的閘極，電晶體N12耦接於電源電壓VDD2與電晶體N10的閘極之間，電晶體N10耦接於電源電壓VDD2與輸出端TO之間。其中傳輸閘TS1、TS2受控於切換控制信號SW1與反相切換控制信號SW1B而改變其導通狀態，電晶體P12與電晶體N12分別受控於切換控制信號SW1與反相切換控制信號SW1B而改變其導通狀態，其中切換控制信號SW1與反相切換控制信號SW1B為反相信號。One end of the transmission gate TS1 is coupled to the output terminal TO1 of the operational amplifier 102 (that is, the common connection point of the transistor P7 and the transistor P9), and the other end is coupled to the gate of the transistor P10, and the transistor P12 is coupled to the power supply voltage. Between VDD1 and the gate of transistor P10, transistor P10 is coupled between the power supply voltage VDD1 and the output terminal TO. In addition, one end of the transmission gate TS2 is coupled to the output terminal TO2 of the operational amplifier 102 (that is, a common junction of the transistor N7 and the transistor N9), and the other end is coupled to the gate of the transistor N10, and the transistor N12 is coupled to Between the power supply voltage VDD2 and the gate of the transistor N10, the transistor N10 is coupled between the power supply voltage VDD2 and the output terminal TO. The transmission gates TS1 and TS2 are controlled by the switching control signal SW1 and the inversion switching control signal SW1B to change their conduction states. The transistor P12 and the transistor N12 are controlled by the switching control signal SW1 and the inversion switching control signal SW1B respectively. In its conducting state, the switching control signal SW1 and the inverted switching control signal SW1B are inverted signals.
另外，傳輸閘TS3的一端耦接運算放大器102的輸出端TO1，另一端則耦接電晶體P11的閘極，電晶體P13耦接於電源電壓VDD3與電晶體P11的閘極之間，電晶體P11耦接於電源電壓VDD3與輸出端TO之間。傳輸閘TS4的一端耦接運算放大器102的輸出端TO2，另一端則耦接電晶體N11的閘極，電晶體N13耦接於電源電壓VDD4與電晶體N11的閘極之間，電晶體N11耦接於電源電壓VDD4與輸出端TO之間。其中傳輸閘TS3、TS4受控於切換控制信號SW2與反相切換控制信號SW2B而改變其導通狀態，電晶體P13與電晶體N13分別受控於切換控制信號SW2與反相切換控制信號SW2B而改變其導通狀態，其中切換控制信號SW2與反相切換控制信號SW2B為反相信號。另外，上述的電源電壓VDD1大於電源電壓VDD2，電源電壓VDD3大於電源電壓VDD4，亦即電源電壓VDD2與電源電壓VDD3介於電源電壓VDD1與電源電壓VDD4之間。In addition, one end of the transmission gate TS3 is coupled to the output terminal TO1 of the operational amplifier 102, and the other end is coupled to the gate of the transistor P11. The transistor P13 is coupled between the power supply voltage VDD3 and the gate of the transistor P11. P11 is coupled between the power supply voltage VDD3 and the output terminal TO. One end of the transmission gate TS4 is coupled to the output terminal TO2 of the operational amplifier 102, and the other end is coupled to the gate of the transistor N11. The transistor N13 is coupled between the power supply voltage VDD4 and the gate of the transistor N11, and the transistor N11 is coupled Connected between the power supply voltage VDD4 and the output terminal TO. The transmission gates TS3 and TS4 are controlled by the switching control signal SW2 and the inverted switching control signal SW2B to change their conduction states. The transistor P13 and the transistor N13 are controlled by the switching control signal SW2 and the inverted switching control signal SW2B, respectively. In its conducting state, the switching control signal SW2 and the inverted switching control signal SW2B are inverted signals. In addition, the power supply voltage VDD1 is greater than the power supply voltage VDD2, and the power supply voltage VDD3 is greater than the power supply voltage VDD4, that is, the power supply voltage VDD2 and the power supply voltage VDD3 are between the power supply voltage VDD1 and the power supply voltage VDD4.
圖3是依照本發明一實施例的切換控制信號與反相切換控制信號的波形示意圖，請參照圖3。以下將以圖3為例配合圖2說明輸出緩衝裝置的作動方式，且在圖3實施例中，輸出緩衝裝置為用以驅動液晶顯示面板。須注意的是，圖3所示的切換控制信號與反相切換控制信號僅為一示範性的實施例，圖2的輸出緩衝裝置並不限定須配合圖3所示的切換控制信號與反相切換控制信號來進行作動，在其它實施例中，圖2的輸出緩衝裝置亦可依實際需求配合不同的切換控制信號與反相切換控制信號進行作動。FIG. 3 is a waveform diagram of a switching control signal and an inverted switching control signal according to an embodiment of the present invention. Please refer to FIG. 3. The operation of the output buffer device will be described with reference to FIG. 3 as an example in conjunction with FIG. 2. In the embodiment of FIG. 3, the output buffer device is used to drive a liquid crystal display panel. It should be noted that the switching control signal and the inversion switching control signal shown in FIG. 3 are only exemplary embodiments, and the output buffer device of FIG. 2 is not limited to cooperate with the switching control signal and the inversion shown in FIG. 3. The switching control signal is used for operation. In other embodiments, the output buffer device of FIG. 2 may also be operated with different switching control signals and reverse switching control signals according to actual needs.
如圖3所示，在第N個畫框期間FN，傳輸閘TS1、TS2受控於切換控制信號SW1與反相切換控制信號SW1B而被導通，電晶體P12與電晶體N12分別受控於切換控制信號SW1與反相切換控制信號SW1B而被關閉。同時傳輸閘TS3、TS4受控於切換控制信號SW2與反相切換控制信號SW2B而被關閉，電晶體P13與電晶體N13分別受控於切換控制信號SW2與反相切換控制信號SW2B而被導通。因此，輸出級電路104的電晶體P10與N10可分別透過傳輸閘TS1與TS2接收來自運算放大器102的輸出電壓，而輸出具有第一電壓範圍的電壓(例如正極性電壓)。另一方面，在輸出級電路106中，電晶體P11與N11的閘極可分別透過電晶體P13與N13接收電源電壓VDD3與VDD4而被關閉。As shown in FIG. 3, during the FN frame N, the transmission gates TS1 and TS2 are turned on by the switching control signal SW1 and the inverted switching control signal SW1B, and the transistor P12 and the transistor N12 are respectively controlled by switching. The control signal SW1 and the inverted switching control signal SW1B are turned off. At the same time, the transmission gates TS3 and TS4 are closed by the switching control signal SW2 and the inversion switching control signal SW2B, and the transistor P13 and the transistor N13 are controlled by the switching control signal SW2 and the inversion switching control signal SW2B and turned on. Therefore, the transistors P10 and N10 of the output stage circuit 104 can receive the output voltage from the operational amplifier 102 through the transmission gates TS1 and TS2, respectively, and output a voltage having a first voltage range (for example, a positive polarity voltage). On the other hand, in the output stage circuit 106, the gates of the transistors P11 and N11 can be turned off by receiving the power supply voltages VDD3 and VDD4 through the transistors P13 and N13, respectively.
在第N個空白期間BN，將切換控制信號SW1與反相切換控制信號SW1B進行反相，以停止對顯示面板的液晶電容充電，並進行顯示。假設在第N+1個畫框期間FN+1未改變輸出電壓的極性，在第N+1個畫框期間FN+1，控制信號SW1、SW2與反相切換控制信號SW1B、SW2B的電壓準位將被切換為與第N個畫框期間FN相同。類似地，在第N+1個空白期間BN+1，亦將切換控制信號SW1與反相切換控制信號SW1B進行反相，以停止對顯示面板的液晶電容充電，並進行顯示。假設在第N+2個畫框期間FN+2改變輸出電壓的極性，在第N+2個畫框期間FN+2，控制信號SW1、SW2與反相切換控制信號SW1B、SW2B的電壓準位將被切換為與第N+1個畫框期間FN+1相反。In the N-th blank period BN, the switching control signal SW1 and the inverted switching control signal SW1B are inverted to stop charging the liquid crystal capacitor of the display panel and perform display. Assuming that FN + 1 does not change the polarity of the output voltage during the N + 1 frame, during the FN + 1 frame, the voltage levels of the control signals SW1, SW2 and the inversion switching control signals SW1B, SW2B are accurate. The bits will be switched to be the same as FN during the Nth frame. Similarly, during the N + 1th blank period BN + 1, the switching control signal SW1 and the inverted switching control signal SW1B are also inverted to stop charging the liquid crystal capacitor of the display panel and perform display. Suppose that during the N + 2 frame, FN + 2 changes the polarity of the output voltage. During the N + 2 frame, FN + 2, the voltage levels of the control signals SW1, SW2 and the inverted switching control signals SW1B, SW2B. Will be switched to the opposite of FN + 1 during the N + 1th frame.
此時，傳輸閘TS1、TS2受控於切換控制信號SW1與反相切換控制信號SW1B而被關閉，電晶體P12與電晶體N12分別受控於切換控制信號SW1與反相切換控制信號SW1B而被導通。同時傳輸閘TS3、TS4受控於切換控制信號SW2與反相切換控制信號SW2B而被導通，電晶體P13與電晶體N13分別受控於切換控制信號SW2與反相切換控制信號SW2B而被關閉。因此，輸出級電路106的電晶體P11與N11可分別透過傳輸閘TS3與TS4接收來自運算放大器102的輸出電壓，而輸出具有第二電壓範圍的電壓(例如負極性電壓)。另一方面，在輸出級電路104中，電晶體P10與N10的閘極可分別透過電晶體P12與N12接收電源電壓VDD1與VDD2而被關閉。At this time, the transmission gates TS1 and TS2 are closed by the switching control signal SW1 and the inverted switching control signal SW1B, and the transistor P12 and the transistor N12 are controlled by the switching control signal SW1 and the inverted switching control signal SW1B, respectively. Continuity. At the same time, the transmission gates TS3 and TS4 are turned on by the switching control signal SW2 and the inversion switching control signal SW2B, and the transistor P13 and the transistor N13 are controlled by the switching control signal SW2 and the inversion switching control signal SW2B and turned off. Therefore, the transistors P11 and N11 of the output stage circuit 106 can receive the output voltage from the operational amplifier 102 through the transmission gates TS3 and TS4, respectively, and output a voltage having a second voltage range (for example, a negative polarity voltage). On the other hand, in the output stage circuit 104, the gates of the transistors P10 and N10 can be turned off by receiving the power supply voltages VDD1 and VDD2 through the transistors P12 and N12, respectively.
圖4是依照本發明另一實施例的一種輸出緩衝裝置的示意圖，請參照圖4。相較於圖1實施例的輸出緩衝裝置，本實施例的輸出緩衝裝置可更包括運算放大器202、輸出級電路204、輸出級電路06、開關電路208、開關電路210以及切換電路212。其中切換電路212耦接運算放大器102與運算放大器202的正輸入端，切換電路212可接收輸入信號VIN1與輸入信號VIN2，受控於選擇信號SL1切換輸出至運算放大器102與運算放大器202的正輸入端的信號，亦即受控於選擇信號SL1決定將輸入信號VIN1與輸入信號VIN2分別提供給運算放大器102與運算放大器202的正輸入端，或將輸入信號VIN1與輸入信號VIN2分別提供給運算放大器202與運算放大器102的正輸入端。如圖4所示，切換電路212可例如以4個切換開關來實施，然不以此為限。FIG. 4 is a schematic diagram of an output buffer device according to another embodiment of the present invention. Please refer to FIG. 4. Compared with the output buffer device in the embodiment of FIG. 1, the output buffer device in this embodiment may further include an operational amplifier 202, an output stage circuit 204, an output stage circuit 06, a switching circuit 208, a switching circuit 210, and a switching circuit 212. The switching circuit 212 is coupled to the positive inputs of the operational amplifier 102 and the operational amplifier 202. The switching circuit 212 can receive the input signal VIN1 and the input signal VIN2, and is controlled by the selection signal SL1 to switch and output to the positive inputs of the operational amplifier 102 and the operational amplifier 202. Signals, that is, controlled by the selection signal SL1, decide to provide the input signals VIN1 and VIN2 to the positive inputs of the operational amplifier 102 and the operational amplifier 202, respectively, or provide the input signals VIN1 and VIN2 to the operational amplifier 202, respectively. And the positive input of the operational amplifier 102. As shown in FIG. 4, the switching circuit 212 may be implemented by, for example, four switching switches, but is not limited thereto.
運算放大器202的負輸入端耦接輸出級電路204與輸出級電路206的輸出端TO’，以接收來自輸出級電路204與輸出級電路206的回授信號。開關電路208耦接於運算放大器202的輸出端與輸出級電路204的輸入端之間，開關電路210耦接於運算放大器202的輸出端與輸出級電路206的輸入端之間。輸出級電路204與輸出級電路206的輸出端TO’連接至負載214。在本實施例中輸出緩衝裝置為應用於液晶顯示面板，負載214可包括等效電阻RL2以及液晶電容CL2。此外，運算放大器102、輸出級電路104、輸出級電路106、開關電路108、開關電路110以及負載112間的關係與圖1相同，因此在此不再贅述。The negative input terminal of the operational amplifier 202 is coupled to the output terminal TO 'of the output stage circuit 204 and the output stage circuit 206 to receive a feedback signal from the output stage circuit 204 and the output stage circuit 206. The switching circuit 208 is coupled between the output of the operational amplifier 202 and the input of the output stage circuit 204, and the switching circuit 210 is coupled between the output of the operational amplifier 202 and the input of the output stage circuit 206. An output terminal TO 'of the output stage circuit 204 and the output stage circuit 206 is connected to the load 214. In this embodiment, the output buffer device is applied to a liquid crystal display panel. The load 214 may include an equivalent resistor RL2 and a liquid crystal capacitor CL2. In addition, the relationships among the operational amplifier 102, the output stage circuit 104, the output stage circuit 106, the switch circuit 108, the switch circuit 110, and the load 112 are the same as those in FIG. 1, and therefore will not be repeated here.
其中，運算放大器202、輸出級電路204、輸出級電路06、開關電路208、開關電路210以及切換電路212所構成的輸出緩衝電路的作動方式與上述實施例類似，本領域具通常知識者應可依據上述實施例推得其作動方式以及進一步的實施細節，因此在此亦不再贅述。在本案實施例中，藉由切換電路212選擇將輸入信號VIN1與輸入信號VIN2分別提供給運算放大器102與運算放大器202的正輸入端，或將輸入信號VIN1與輸入信號VIN2分別提供給運算放大器202與運算放大器102的正輸入端，可使輸出緩衝裝置具有更多樣的輸出電壓選擇方式來配合液晶顯示面板對於驅動信號的需求。Among them, the operation mode of the output buffer circuit composed of the operational amplifier 202, the output stage circuit 204, the output stage circuit 06, the switching circuit 208, the switching circuit 210, and the switching circuit 212 is similar to the above embodiment, and those skilled in the art should The operation mode and further implementation details are deduced according to the above embodiments, and therefore will not be repeated here. In the embodiment of the present case, the switching circuit 212 is used to select to provide the input signals VIN1 and VIN2 to the positive inputs of the operational amplifier 102 and the operational amplifier 202, respectively, or to provide the input signals VIN1 and VIN2 to the operational amplifier 202, respectively. With the positive input terminal of the operational amplifier 102, the output buffer device can have a variety of output voltage selection methods to meet the needs of the LCD display panel for driving signals.
綜上所述，本發明的實施例藉由在運算放大器的輸出端配置具有出不同電壓範圍的輸出級電路，並透過開關電路控制輸出級電路的輸出。如此除了可滿足輸出不同極性的輸出電壓的需求外，亦不會如先前技術般，需藉由在緩衝器的輸出端配置傳輸閘來切換輸出至資料線的電壓極性，而造成輸出緩衝裝置的驅動能力降低，進而影響液晶顯示面板的顯示品質。In summary, in the embodiment of the present invention, output stage circuits having different voltage ranges are arranged at the output end of the operational amplifier, and the output of the output stage circuit is controlled through the switch circuit. In addition to meeting the requirements of outputting output voltages of different polarities, it will not be necessary to switch the voltage polarity of the output to the data line by configuring a transmission gate at the output end of the buffer as in the prior art, which will cause the output buffer device to fail. The driving ability is reduced, which further affects the display quality of the liquid crystal display panel.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.
102、202‧‧‧運算放大器
104、106、204、206‧‧‧輸出級電路
108、110、208、210‧‧‧開關電路
112、214‧‧‧負載
212‧‧‧切換電路
VIN、VIN1、VIN2‧‧‧輸入信號
TO、TO1、TO2、TO’‧‧‧輸出端
RL1、RL2‧‧‧等效電阻
CL1、CL2‧‧‧液晶電容
SC1、SC2‧‧‧控制信號
P1~P13、N1~N13‧‧‧電晶體
VB1~VB8‧‧‧偏壓電壓
TS1~TS4‧‧‧傳輸閘
VDD1~VDD4‧‧‧電源電壓
SW1、SW2‧‧‧切換控制信號
SW1B、SW2B‧‧‧反相切換控制信號
SL1‧‧‧選擇信號
FN、FN+1、FN+2‧‧‧畫框期間
BN、BN+1‧‧‧空白期間102, 202‧‧‧ Operational Amplifiers
104, 106, 204, 206‧‧‧‧ output stage circuits
108, 110, 208, 210‧‧‧ switch circuits
112, 214‧‧‧ load
212‧‧‧switching circuit
VIN, VIN1, VIN2‧‧‧ input signals
TO, TO1, TO2, TO'‧‧‧ output terminals
RL1, RL2‧‧‧ equivalent resistance
CL1, CL2‧‧‧LCD Capacitors
SC1, SC2‧‧‧Control signal
P1 ~ P13, N1 ~ N13‧‧‧Transistors
VB1 ~ VB8‧‧‧ bias voltage
TS1 ~ TS4‧‧‧Transmission gate
VDD1 ~ VDD4‧‧‧‧Voltage
SW1, SW2‧‧‧‧ Switching control signal
SW1B, SW2B‧‧‧ Inverted switching control signal
SL1‧‧‧Selection signal
FN, FN + 1, FN + 2‧‧‧frame period
BN, BN + 1‧‧‧‧ Blank period
圖1是依照本發明一實施例的一種輸出緩衝裝置的示意圖。 圖2是依照本發明另一實施例的一種輸出緩衝裝置的示意圖。 圖3是依照本發明一實施例的切換控制信號與反相切換控制信號的波形示意圖。 圖4是依照本發明另一實施例的一種輸出緩衝裝置的示意圖。FIG. 1 is a schematic diagram of an output buffer device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of an output buffer device according to another embodiment of the present invention. 3 is a waveform diagram of a switching control signal and an inverted switching control signal according to an embodiment of the present invention. FIG. 4 is a schematic diagram of an output buffer device according to another embodiment of the present invention.
102‧‧‧運算放大器 102‧‧‧Operational Amplifier
104、106‧‧‧輸出級電路 104, 106‧‧‧ output stage circuit
108、110‧‧‧開關電路 108, 110‧‧‧ switch circuit
112‧‧‧負載 112‧‧‧Load
VIN‧‧‧輸入信號 VIN‧‧‧ input signal
TO‧‧‧輸出端 TO‧‧‧ Output
RL1‧‧‧等效電阻 RL1‧‧‧ equivalent resistance
CL1‧‧‧液晶電容 CL1‧‧‧LCD Capacitor
SC1、SC2‧‧‧控制信號 SC1, SC2‧‧‧Control signal
Claims (7)
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| TW105124036A TWI594227B (en) | 2016-07-29 | 2016-07-29 | Output buffer apparatus |
| CN201610903064.1A CN107666310A (en) | 2016-07-29 | 2016-10-17 | Output buffer device |
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| TW105124036A TWI594227B (en) | 2016-07-29 | 2016-07-29 | Output buffer apparatus |
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| TWI594227B TWI594227B (en) | 2017-08-01 |
| TW201804454A true TW201804454A (en) | 2018-02-01 |
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| CN110473505B (en) * | 2018-05-09 | 2021-06-22 | 奇景光电股份有限公司 | Output buffer and source driver |
| CN109903730B (en) * | 2019-02-13 | 2021-04-06 | 奕力科技(开曼)股份有限公司 | Buffer circuit |
| US11393375B2 (en) * | 2020-09-30 | 2022-07-19 | Himax Technologies Limited | Source driver and polarity inversion control circuit |
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| JP5328461B2 (en) * | 2009-04-21 | 2013-10-30 | ルネサスエレクトロニクス株式会社 | Operational amplifier |
| KR101147354B1 (en) * | 2010-07-19 | 2012-05-23 | 매그나칩 반도체 유한회사 | Slew rate boost circuit for output buffer and output buffer having the same |
| TWI454057B (en) * | 2011-03-31 | 2014-09-21 | Raydium Semiconductor Corp | Output buffer of source driver |
| CN103825567B (en) * | 2012-11-16 | 2017-09-22 | 联咏科技股份有限公司 | Operation amplifier circuit |
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