TW201801261A - Lead frame and method of manufacturing semiconductor package - Google Patents
Lead frame and method of manufacturing semiconductor package Download PDFInfo
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- TW201801261A TW201801261A TW106105459A TW106105459A TW201801261A TW 201801261 A TW201801261 A TW 201801261A TW 106105459 A TW106105459 A TW 106105459A TW 106105459 A TW106105459 A TW 106105459A TW 201801261 A TW201801261 A TW 201801261A
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- Prior art keywords
- encapsulating resin
- lead frame
- end portion
- base end
- resin
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 78
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 229920005989 resin Polymers 0.000 claims description 144
- 239000011347 resin Substances 0.000 claims description 144
- 238000004806 packaging method and process Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 8
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 238000005530 etching Methods 0.000 description 6
- 239000011342 resin composition Substances 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 6
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
本揭示係關於一種導線架、及半導體封裝之製造方法。 The present disclosure relates to a method for manufacturing a lead frame and a semiconductor package.
半導體封裝係具備：導線架；搭載在該導線架上之半導體晶片；以及將半導體晶片予以封裝之封裝樹脂。在MAP(Molded Array Packaging)型導線架之情形時，各端子(導線)係以繫桿(tie bar)連接。利用該種導線架來製造半導體封裝時，係在以樹脂封裝導線架及搭載在該導線架上之半導體晶片而獲得樹脂封裝體之後，以切割刀對該樹脂封裝體進行切削並予以個片化。如上述方式製造半導體封裝。 The semiconductor package includes: a lead frame; a semiconductor wafer mounted on the lead frame; and an encapsulating resin that encapsulates the semiconductor wafer. In the case of a MAP (Molded Array Packaging) type lead frame, each terminal (lead) is connected with a tie bar. When manufacturing a semiconductor package using such a lead frame, the resin package is obtained by encapsulating the lead frame and the semiconductor wafer mounted on the lead frame with a resin, and then the resin package is cut and divided into pieces by a dicing knife. . The semiconductor package is manufactured as described above.
在日本特開2001-320007號公報(專利文獻1)中，提出一種為了抑制金屬之切割毛邊之發生與切割刀之磨耗，而藉由以半蝕刻形成之溝部將切割部設為薄壁的技術內容。再者，又提出一種將該溝部之寬度設為比切割刀之寬度大或小而可順暢地進行切斷的技術內容。 Japanese Patent Laid-Open No. 2001-320007 (Patent Document 1) proposes a technique of making the cutting portion thinner by forming a groove portion by half etching in order to suppress the occurrence of metal cutting burrs and the abrasion of the cutting blade content. Furthermore, there is proposed a technical content in which the width of the groove portion is larger or smaller than the width of the cutting blade and can be smoothly cut.
當利用具有比切割刀之寬度更大之溝部的導線架來製造半導體封裝時，在由溝部而來之端子的薄壁部，係形成有厚度較小之薄壁樹脂部。該薄壁樹脂部與覆蓋半導體晶片上之厚度較大之樹脂部相比較，由於容易從導線架之表面剝離，因此必須具有優異之密接性。近年來，由於會有使導線架變薄而使半導體封裝小型化之傾向，因此要求薄壁樹脂部進一步提升密接性。 When manufacturing a semiconductor package using a lead frame having a groove portion larger than the width of the dicing blade, a thin-walled resin portion having a small thickness is formed in the thin-walled portion of the terminal from the groove portion. The thin-walled resin portion is more easily peeled from the surface of the lead frame than the resin portion covering a larger thickness on the semiconductor wafer, and therefore must have excellent adhesion. In recent years, the lead frame has become thinner and the semiconductor package tends to be miniaturized. Therefore, the thin-walled resin portion is required to further improve adhesion.
在本發明的一種態樣中，其目的在於提供一種於製造半導體封裝之際可抑制封裝樹脂之剝離的導線架。本發明在其他樣態中，其目的在於提供一種可抑制封裝樹脂之剝離的半導體封裝之製造方法。 In one aspect of the present invention, an object of the present invention is to provide a lead frame capable of suppressing peeling of a packaging resin when manufacturing a semiconductor package. In another aspect of the present invention, an object of the present invention is to provide a method for manufacturing a semiconductor package that can suppress peeling of the packaging resin.
本發明係在一種態樣中，提供一種導線架，該導線架具備一對端子、及設置在其間且端子在基端部所連結之繫桿，其中，端子之基端部係比前端部薄，基端部係具有朝厚度方向貫通之貫通孔、及使寬度比前端部更狹窄之缺口部的至少一者。 In one aspect, the present invention provides a lead frame including a pair of terminals and a tie bar disposed between the terminals and connected at the base end portion, wherein the base end portion of the terminal is thinner than the front end portion The base end portion has at least one of a through hole penetrating in the thickness direction and a notch portion having a narrower width than the tip portion.
該導線架係在以樹脂進行封裝時，能以貫通孔內之封裝樹脂或缺口部內之封裝樹脂連接形成在基端部之一面上的封裝樹脂、及設置在另一面上之封裝樹脂。因此，在進行切割來製作半導體封裝之際，即使形成在基端部之一面或另一面上之封裝樹脂的厚度變薄，亦可抑制該封裝樹脂之剝離。 When the lead frame is encapsulated with resin, the encapsulating resin formed on one surface of the base end and the encapsulating resin provided on the other surface can be connected by the encapsulating resin in the through hole or the encapsulating resin in the notch. Therefore, when a semiconductor package is manufactured by dicing, even if the thickness of the encapsulating resin formed on one surface or the other surface of the base end portion becomes thin, peeling of the encapsulating resin can be suppressed.
當上述基端部具有貫通孔時，貫通孔係較佳為延伸至繫桿，且在一對端子各者之基端部與其間的繫桿連通。如此，藉由在一對端子之基端部與其間的繫桿中設置成為一體之貫通孔，可使切割時之切削部的體積充分地變小。藉此，即便增大導線架之厚度，亦可順暢地進行切削。再者，還可減低切割刀之負荷，並且可減低導線架之構成材料。 When the base end portion has a through hole, the through hole system preferably extends to the tie bar, and the base end portion of each of the pair of terminals communicates with the tie bar therebetween. In this way, by providing a through hole integrally formed between the base end portions of the pair of terminals and the tie bar between them, the volume of the cutting portion during cutting can be sufficiently reduced. Thereby, even if the thickness of the lead frame is increased, cutting can be performed smoothly. Furthermore, the load of the cutting blade can be reduced, and the material of the lead frame can be reduced.
上述導線架亦可具備：在上表面側搭載有半導體晶片之襯墊；以及連結在繫桿，且支持襯墊之支撐桿；端子之基端部的下表面亦可位於比端子之前端部的下表面更上方之處。當對該導線架進行樹脂封裝時，在端子之基端部的下表面側形成有厚度較薄之封裝樹脂(薄壁樹脂部)。該薄壁樹脂部係藉由貫通基端部之貫通孔內之封裝樹脂，而與端子之基端部的上表面側之封裝樹脂連接。因此，在進行切割而製作半導體封裝之際，可抑制薄壁樹脂部之封裝樹脂之剝離。並且，還可抑制封裝樹脂從所獲得之半導體封裝之剝離。 The lead frame may also include: a pad on which the semiconductor chip is mounted on the upper surface side; and a support rod connected to the tie bar and supporting the pad; and the lower surface of the base end portion of the terminal may be located more than the front end of the terminal Above the lower surface. When the lead frame is resin-encapsulated, a thin-thick encapsulating resin (thin-walled resin portion) is formed on the lower surface side of the base end portion of the terminal. The thin-walled resin portion is connected to the encapsulating resin on the upper surface side of the base end portion of the terminal by the encapsulating resin penetrating through the through hole of the base end portion. Therefore, when the semiconductor package is manufactured by cutting, peeling of the packaging resin of the thin-walled resin portion can be suppressed. Moreover, peeling of the encapsulating resin from the obtained semiconductor package can also be suppressed.
當上述基端部具有缺口部時，缺口部係較佳為以朝基端部之寬度方向相對向之方式成對設置。當以樹脂將該種導線架進行封裝時，可使介設於鄰接之端子間的封裝樹脂增大。藉此，可穩固地連接形成在基端部之一面上之封裝樹脂、與設置在另一面上之封裝樹脂。因此，在進行切割來製作半導體封裝之際，即使形成在基端部之一面或另一面上之封裝樹脂的厚度變薄，亦可抑制該封裝樹 脂之剝離。 When the base end portion has a notch portion, the notch portions are preferably provided in pairs so as to face the width direction of the base end portion. When this kind of lead frame is encapsulated with resin, the encapsulation resin interposed between adjacent terminals can be increased. Thereby, the encapsulating resin formed on one surface of the base end and the encapsulating resin provided on the other surface can be firmly connected. Therefore, when making a semiconductor package by cutting, even if the thickness of the encapsulating resin formed on one side or the other side of the base end portion becomes thin, the package tree can be suppressed Fat peeling.
本發明係在其他樣態中，提供一種半導體封裝之製造方法，係具有：搭載步驟，在導線架上搭載半導體晶片；封裝步驟，封裝半導體晶片，覆蓋導線架之一對主面之至少一部分，並且在貫通孔內設置封裝樹脂；切割步驟，沿著繫桿，將繫桿、和貫通孔內及/或缺口部內之封裝樹脂的一部分進行切削，而獲得該封裝樹脂連接一方之主面上之封裝樹脂與另一方之主面上之封裝樹脂的半導體封裝。 In another aspect, the present invention provides a method for manufacturing a semiconductor package, including: a mounting step of mounting a semiconductor chip on a lead frame; a packaging step of packaging a semiconductor chip to cover at least a portion of a pair of main surfaces of the lead frame, And encapsulating resin is provided in the through hole; cutting step, along the tie bar, the tying rod, and a part of the encapsulating resin in the through hole and / or the notch is cut to obtain the main surface of the side where the encapsulating resin is connected A semiconductor package of encapsulating resin and encapsulating resin on the other main surface.
在上述半導體封裝之製造方法中，貫通孔內及/或缺口部內之封裝樹脂係連接形成在雙方之主面上之各個封裝樹脂。因此，在製造半導體封裝之際，即使形成在一方(或另一方)之主面上的封裝樹脂之厚度變薄，亦可抑制該封裝樹脂之剝離。再者，亦可抑制封裝樹脂從所獲得之半導體封裝之剝離。 In the above-mentioned method of manufacturing a semiconductor package, the encapsulating resin in the through hole and / or the notch is connected to the encapsulating resin formed on the main surfaces of both sides. Therefore, when manufacturing a semiconductor package, even if the thickness of the encapsulating resin formed on the main surface of one (or the other) becomes thin, peeling of the encapsulating resin can be suppressed. Furthermore, peeling of the encapsulating resin from the obtained semiconductor package can also be suppressed.
在本發明的一種樣態中，提供一種在製造半導體封裝之際可抑制封裝樹脂之剝離的導線架。本發明係在其他樣態中，提供一種可抑制封裝樹脂之剝離的半導體封裝之製造方法。 In one aspect of the present invention, there is provided a lead frame that can suppress peeling of a packaging resin when manufacturing a semiconductor package. In another aspect, the present invention provides a method for manufacturing a semiconductor package that can suppress peeling of the packaging resin.
10‧‧‧襯墊 10‧‧‧Padding
12‧‧‧端子 12‧‧‧terminal
12A‧‧‧前端部 12A‧‧‧Front end
12B‧‧‧基端部 12B‧‧‧Base end
12D‧‧‧基端部 12D‧‧‧Base end
14‧‧‧支撐桿 14‧‧‧support rod
15‧‧‧缺口部 15‧‧‧Notch
16‧‧‧繫桿 16‧‧‧tie
17‧‧‧貫通孔 17‧‧‧Through hole
18‧‧‧貫通孔 18‧‧‧Through hole
19‧‧‧凹部 19‧‧‧recess
40‧‧‧切削部 40‧‧‧Cutting Department
70‧‧‧半導體晶片 70‧‧‧Semiconductor chip
72‧‧‧接合線 72‧‧‧bond wire
80、84、86‧‧‧封裝樹脂 80, 84, 86 ‧‧‧ encapsulating resin
82‧‧‧薄壁樹脂部 82‧‧‧Thin Wall Resin Department
100‧‧‧單位架 100‧‧‧Unit rack
100a、100b、200a、200b‧‧‧主面 100a, 100b, 200a, 200b
110‧‧‧樹脂封裝體 110‧‧‧Resin package
150‧‧‧半導體封裝 150‧‧‧Semiconductor packaging
200‧‧‧導線架 200‧‧‧ Lead frame
II‧‧‧區域 II‧‧‧Region
第1圖係一實施形態之導線架的俯視圖。 Fig. 1 is a plan view of a lead frame according to an embodiment.
第2圖(A)係將第1圖中之區域II予以放大顯示之俯視圖。第2圖(B)係第2圖(A)中之b-b線剖視圖。 Figure 2 (A) is a plan view showing the area II in Figure 1 enlarged. Figure 2 (B) is a sectional view taken along line b-b in Figure 2 (A).
第3圖(A)係將一實施形態之變形例之導線架的一部分予以放大顯示之俯視圖。第3圖(B)係第3圖(A)中之b-b線剖視圖。 FIG. 3 (A) is a plan view showing an enlarged view of a part of a lead frame according to a modification of the embodiment. Figure 3 (B) is a cross-sectional view taken along line b-b in Figure 3 (A).
第4圖(A)係將其他實施形態之導線架的一部分予以放大顯示之俯視圖。第4圖(B)係第4圖(A)中之b-b線剖視圖。 Fig. 4 (A) is a plan view showing an enlarged view of a part of the lead frame of another embodiment. Figure 4 (B) is a cross-sectional view taken along the line b-b in Figure 4 (A).
第5圖係具備第1圖之導線架的樹脂封裝體之剖視圖。 Fig. 5 is a cross-sectional view of a resin package provided with the lead frame of Fig. 1;
第6圖係一實施形態之半導體封裝之剖視圖。 FIG. 6 is a cross-sectional view of a semiconductor package according to an embodiment.
第7圖係第6圖之半導體封裝的側視圖。 Figure 7 is a side view of the semiconductor package of Figure 6.
第8圖係其他實施形態之半導體封裝的側視圖。 Fig. 8 is a side view of a semiconductor package of another embodiment.
以下，依情況參照圖式，說明本發明之實施形態。然而，以下之實施形態係用以說明本發明之例示，其目的並非將本發明限定在以下之內容。在說明中，對於同一要素或具有同一功能之要素係採用相同符號，並視情況省略重複之說明。再者，上下左右等之位置關係，若無特別說明，係設為依據圖式所示之位置關係者。再者，圖式之尺寸比率並不限於圖示之比率。 Hereinafter, an embodiment of the present invention will be described with reference to the drawings as appropriate. However, the following embodiments are examples for explaining the present invention, and its purpose is not to limit the present invention to the following content. In the description, the same symbol is used for the same element or the element having the same function, and repeated description is omitted as appropriate. In addition, the positional relationship of up, down, left, right, etc., unless otherwise specified, is assumed to be based on the positional relationship shown in the drawings. Furthermore, the size ratio of the drawings is not limited to the ratio shown.
第1圖係導線架200之俯視圖。導線架200係單位架100之集合體。第1圖雖係顯示9個(3個×3個)之單位架100，但單位架100之數量並無特別限定。單位架100係經由繫桿16與鄰接之單位架100連結。 FIG. 1 is a top view of the lead frame 200. The lead frame 200 is an assembly of unit frames 100. Although FIG. 1 shows 9 (3 × 3) unit racks 100, the number of unit racks 100 is not particularly limited. The unit rack 100 is connected to the adjacent unit rack 100 via the tie bar 16.
導線架200係具備：在各個單位架100中配置於中央部之襯墊10；配置在襯墊10之周圍，且被稱為 內導線之複數個端子12；及支持襯墊10之支撐桿14。支撐桿14之前端係連結在襯墊10，支撐桿14之後端係連結在配置於端子12之周圍的繫桿16。支撐桿14係藉由從大致矩形狀之襯墊10的四角落放射狀地延伸而連結在繫桿16，以支援襯墊10。 The lead frame 200 includes: a spacer 10 disposed in the center of each unit frame 100; it is disposed around the spacer 10 and is called A plurality of terminals 12 of the inner conductor; and a support rod 14 supporting the pad 10. The front end of the support rod 14 is connected to the spacer 10, and the rear end of the support rod 14 is connected to the tie rod 16 disposed around the terminal 12. The support rod 14 is connected to the tie rod 16 by extending radially from the four corners of the substantially rectangular cushion 10 to support the cushion 10.
導線架200係在一方之主面200a側(上表面)中，在襯墊10上搭載有半導體晶片。相對於襯墊10之各邊排列配設4個端子12，其前端部12A係相隔預定之間隔與襯墊10之各邊相對向。端子12之基端部12B係連結在繫桿16。 The lead frame 200 is on one main surface 200a side (upper surface), and a semiconductor wafer is mounted on the pad 10. Four terminals 12 are arranged in line with each side of the pad 10, and the front end portion 12A is opposed to each side of the pad 10 at a predetermined interval. The base end portion 12B of the terminal 12 is connected to the tie rod 16.
第2圖(A)係將第1圖之區域II予以放大顯示之俯視圖。第2圖(B)係第2圖(A)之b-b線剖視圖。以隔著繫桿16之方式，使一對端子12設置成相對向。一對端子12之各者係如第1圖所示，分別包含在彼此鄰接之單位架100。 FIG. 2 (A) is a plan view showing the area II of FIG. 1 enlarged. Figure 2 (B) is a cross-sectional view taken along line b-b of Figure 2 (A). The pair of terminals 12 are arranged to face each other with the tie bar 16 interposed therebetween. Each of the pair of terminals 12 is included in the unit rack 100 adjacent to each other as shown in FIG. 1.
回到第2圖(A)，在一對端子12及繫桿16，形成有朝厚度方向貫通之貫通孔17。貫通孔17係延伸至一對端子12之各個基端部12B與被夾持於其間的繫桿16。亦即，貫通孔17係在一對端子12之各個基端部12B與被夾持於其間的繫桿16中連通，而成為一體。 Returning to FIG. 2 (A), a pair of terminals 12 and tie bars 16 are formed with through holes 17 penetrating in the thickness direction. The through hole 17 extends to each base end portion 12B of the pair of terminals 12 and the tie bar 16 sandwiched therebetween. That is, the through-hole 17 is connected to each base end portion 12B of the pair of terminals 12 and the tie bar 16 sandwiched therebetween, and is integrated.
藉由作成為第2圖(A)之構造，可使貫通孔17之尺寸充分增大。因此，可容易地將樹脂組成物充填在貫通孔17內。再者，當貫通孔17之尺寸較大時，可藉由蝕刻而容易地形成貫通孔17。 With the structure shown in FIG. 2 (A), the size of the through hole 17 can be sufficiently increased. Therefore, the through hole 17 can be easily filled with the resin composition. Furthermore, when the size of the through-hole 17 is large, the through-hole 17 can be easily formed by etching.
如第2圖(B)所示，基端部12B及繫桿16之厚度係比端子12之前端部12A的厚度更薄。如第2圖(B)所示，在通過一對端子12及繫桿16且與一對端子12相對向之方向平行並與主面200b垂直之剖面中，在一對端子12之基端部12B與其間的繫桿16中，係於主面200b側(下表面側)形成有凹部19。 As shown in FIG. 2 (B), the thickness of the base end portion 12B and the tie bar 16 is thinner than the thickness of the front end portion 12A of the terminal 12. As shown in FIG. 2 (B), in the cross section that passes through the pair of terminals 12 and the tie bar 16 in a direction parallel to the pair of terminals 12 and perpendicular to the main surface 200b, at the base end of the pair of terminals 12 12B and the tie bar 16 therebetween, a recess 19 is formed on the main surface 200b side (lower surface side).
藉由使基端部12B及繫桿16之厚度變薄，而可順暢地進行切割時之導線架200的切削。再者，還可減輕切割刀之負荷。端子12之基端部12B係可藉由例如半蝕刻而變得比前端部12A更薄。 By making the thickness of the base end portion 12B and the tie bar 16 thin, the cutting of the lead frame 200 at the time of cutting can be performed smoothly. Furthermore, the load of the cutting blade can be reduced. The base end portion 12B of the terminal 12 can be made thinner than the front end portion 12A by, for example, half-etching.
在端子12之基端部12B的主面200b側中，係於製造半導體封裝之際，在封裝步驟中形成有薄壁樹脂部。該薄壁樹脂部係藉由貫通孔17內之封裝樹脂而與主面200a側之封裝樹脂連接。之後，在切割步驟中被切削之切削部40係在第2圖(B)中以虛線所包圍之區域。沿著一對端子12之相對向方向的切削部40之長度係比沿著該相對向方向之凹部19的長度更短。凹部19相對於切削部40之長度的比係為例如1.1至1.5。 On the main surface 200b side of the base end portion 12B of the terminal 12, when manufacturing a semiconductor package, a thin-walled resin portion is formed in the packaging step. The thin-walled resin portion is connected to the encapsulating resin on the main surface 200 a side by the encapsulating resin in the through hole 17. After that, the cutting portion 40 cut in the cutting step is the area surrounded by the broken line in FIG. 2 (B). The length of the cutting portion 40 along the opposing direction of the pair of terminals 12 is shorter than the length of the recess 19 along the opposing direction. The ratio of the length of the concave portion 19 to the length of the cutting portion 40 is, for example, 1.1 to 1.5.
在切割步驟中被切削之後，在端子12之基端部12B的殘存部分之下表面(主面200b)側，殘存有薄壁樹脂部。該薄壁樹脂部係藉由貫通孔17內之封裝樹脂的殘存部分而與上表面(主面200a)側之封裝樹脂連接。藉此，可抑制封裝樹脂從薄壁樹脂部之剝離。 After being cut in the cutting step, a thin-walled resin portion remains on the lower surface (main surface 200b) side of the remaining portion of the base end portion 12B of the terminal 12. The thin-walled resin portion is connected to the encapsulating resin on the upper surface (main surface 200a) side by the remaining portion of the encapsulating resin in the through hole 17. With this, peeling of the encapsulating resin from the thin-walled resin portion can be suppressed.
貫通孔17之尺寸雖無特別限定，但其寬度(第 2圖(A)中之上下方向的長度)較佳為例如以端子12之前端部12A的厚度為基準在80至120%。藉此，可充分容易地進行利用蝕刻所為之貫通孔17的形成。端子12之基端部12B及繫桿16之厚度無需相同，繫桿16之厚度亦可為與端子12之前端部12A相同。 Although the size of the through hole 17 is not particularly limited, its width (No. 2 The length in the vertical direction in FIG. (A) is preferably 80 to 120% based on the thickness of the front end portion 12A of the terminal 12, for example. Thereby, the formation of the through-hole 17 by etching can be performed sufficiently easily. The thickness of the base end portion 12B of the terminal 12 and the tie bar 16 need not be the same, and the thickness of the tie bar 16 may be the same as the front end portion 12A of the terminal 12.
第3圖(A)係將上述實施形態之變形例之導線架的一部分予以放大顯示之俯視圖。第3圖(B)係第3圖(A)之b-b線剖視圖。第3圖(A)及第3圖(B)係將與第2圖(A)及第2圖(B)相同之位置予以放大顯示。在本變形例中，貫通孔18之形狀係與上述實施形態不同。其他構成係與上述實施形態相同。 FIG. 3 (A) is a plan view showing an enlarged view of a part of a lead frame according to a modification of the above embodiment. Figure 3 (B) is a cross-sectional view taken along line b-b of Figure 3 (A). Figure 3 (A) and Figure 3 (B) show the same position as Figure 2 (A) and Figure 2 (B) in enlarged view. In this modification, the shape of the through hole 18 is different from the above-mentioned embodiment. The other configuration is the same as the above-mentioned embodiment.
在本變形例中，並未在繫桿16形成有貫通孔。並且，在一對端子12之基端部12B之各者，隔離地形成有貫通孔18。因此，一對端子12之基端部12B中之貫通孔18並未連通，而分別地獨立。 In this modification, no through hole is formed in the tie bar 16. In addition, a through hole 18 is formed in each of the base end portions 12B of the pair of terminals 12 in isolation. Therefore, the through-holes 18 in the base end portions 12B of the pair of terminals 12 are not connected, but are independent.
如第3圖(B)所示，基端部12B及繫桿16之厚度係比端子12之前端部12A的厚度更薄。如此，藉由使基端部12B及繫桿16之厚度變薄，而可順暢地進行導線架200之切割。再者，還可減輕切割刀之負荷。在該變形例之情形時，亦可抑制封裝樹脂從薄壁樹脂部之剝離。 As shown in FIG. 3 (B), the thickness of the base end portion 12B and the tie bar 16 is thinner than the thickness of the front end portion 12A of the terminal 12. In this way, by making the thickness of the base end portion 12B and the tie bar 16 thin, the lead frame 200 can be cut smoothly. Furthermore, the load of the cutting blade can be reduced. In the case of this modification, peeling of the sealing resin from the thin-walled resin portion can also be suppressed.
第4圖(A)係將其他實施形態之導線架之一部分予以放大顯示之俯視圖。第4圖(B)係第4圖(A)中之b-b線剖視圖。第4圖(A)及第4圖(B)係將與第2圖(A)及第2圖(B)相同之位置予以放大顯示。在本實施形態中，係取 而代之為端子12之基端部12D分別具有使基端部12D之寬度比前端部12A之寬度更狹窄之一對缺口部15，而未在端子12之基端部12B形成有貫通孔。一對缺口部15係設置在基端部12D之側部，且與基端部12D之寬度方向相對向。基端部12D係由於具有缺口部15，因此基端部12D之寬度(沿著第4圖(A)中之上下方向的長度)係比端子12之前端部12A的寬度小。 Fig. 4 (A) is a plan view showing an enlarged view of a part of the lead frame of another embodiment. Figure 4 (B) is a cross-sectional view taken along the line b-b in Figure 4 (A). Figure 4 (A) and Figure 4 (B) show the same positions as Figure 2 (A) and Figure 2 (B) in enlarged view. In this embodiment, Instead, the base end portion 12D of the terminal 12 has a pair of notch portions 15 that make the width of the base end portion 12D narrower than the width of the front end portion 12A, and no through hole is formed in the base end portion 12B of the terminal 12. A pair of notch parts 15 are provided in the side part of the base end part 12D, and are opposed to the width direction of the base end part 12D. Since the base end portion 12D has the notch portion 15, the width of the base end portion 12D (the length in the vertical direction in FIG. 4 (A)) is smaller than the width of the front end portion 12A of the terminal 12.
缺口部15之大小及形狀並無特別限定。例如，亦可僅設置在基端部12D之一方側部，來取代使缺口部15以成對之方式設置在兩側部。藉由使基端部12D之厚度比端子12之前端部12A薄，並且使基端部12D之寬度比端子12之前端部12A小，即可順暢地進行導線架之切割。再者，還可減輕切割刀之負荷。 The size and shape of the notch 15 are not particularly limited. For example, it may be provided only on one side of the base end portion 12D instead of providing the notch portions 15 on both sides in pairs. By making the thickness of the base end portion 12D thinner than the front end portion 12A of the terminal 12, and making the width of the base end portion 12D smaller than the front end portion 12A of the terminal 12, the lead frame can be cut smoothly. Furthermore, the load of the cutting blade can be reduced.
在端子12之基端部12D的主面200b側，係於製造半導體封裝之際，在封裝步驟中形成有薄壁樹脂部。該薄壁樹脂部係藉由介設在相鄰之端子12、12間的封裝樹脂，而與主面200a側之封裝樹脂連接。在切割步驟中將切削部40予以切削之後，於端子12之基端部12D的殘存部分之下表面(主面200b)側，殘存有薄壁樹脂部。該薄壁樹脂部係藉由介設在相鄰之端子12、12間的封裝樹脂，而與上表面(主面200a)側之封裝樹脂連接。由於基端部12D具有缺口部15，因此可使介設在相鄰之端子12、12間的封裝樹脂之體積增大。藉此，可抑制封裝樹脂從薄壁樹脂部之剝離。 On the main surface 200b side of the base end portion 12D of the terminal 12, when a semiconductor package is manufactured, a thin-walled resin portion is formed in the packaging step. The thin-walled resin portion is connected to the encapsulating resin on the main surface 200a side by the encapsulating resin interposed between the adjacent terminals 12, 12. After the cutting portion 40 is cut in the cutting step, a thin-walled resin portion remains on the lower surface (main surface 200b) side of the remaining portion of the base end portion 12D of the terminal 12. The thin-walled resin portion is connected to the encapsulating resin on the upper surface (main surface 200a) side by the encapsulating resin interposed between the adjacent terminals 12 and 12. Since the base end portion 12D has the notch portion 15, the volume of the encapsulating resin interposed between the adjacent terminals 12, 12 can be increased. With this, peeling of the encapsulating resin from the thin-walled resin portion can be suppressed.
端子12之基端部12D之寬度尺寸雖無特別限定，但較佳為例如以端子12之前端部12A的厚度為基準在80至120%。藉此，可充分容易地進行利用蝕刻所為之基端部12D的形成。端子12之基端部12D及繫桿16的厚度無需相同，繫桿16之厚度亦可為與端子12之前端部12A相同。 Although the width dimension of the base end portion 12D of the terminal 12 is not particularly limited, it is preferably, for example, 80 to 120% based on the thickness of the front end portion 12A of the terminal 12. This makes it possible to sufficiently form the base end portion 12D by etching. The thickness of the base end portion 12D of the terminal 12 and the tie bar 16 need not be the same, and the thickness of the tie bar 16 may be the same as the front end portion 12A of the terminal 12.
接著，說明本發明一實施形態之半導體封裝的製造方法。本實施形態之製造方法係具有：在導線架上搭載半導體晶片之搭載步驟；封裝半導體晶片，覆蓋導線架之一對主面的至少一部分，並且在貫通孔內設置封裝樹脂之封裝步驟；沿著繫桿而將繫桿、端子之基端部的一部分及貫通孔內之封裝樹脂的一部分予以切削，以獲得該封裝樹脂連接一方主面上之封裝樹脂與另一方之主面上之封裝樹脂的半導體封裝之切割步驟。以下，說明利用導線架200時之半導體封裝的製造方法。 Next, a method of manufacturing a semiconductor package according to an embodiment of the present invention will be described. The manufacturing method of this embodiment includes: a mounting step of mounting a semiconductor wafer on a lead frame; a step of encapsulating a semiconductor wafer, covering at least a part of a pair of main surfaces of the lead frame, and providing a encapsulating resin in the through hole; Tie bar, cutting a part of the base end of the tie bar, the terminal, and a part of the encapsulating resin in the through hole to obtain the encapsulating resin connecting the encapsulating resin on one main surface with the encapsulating resin on the other main surface Cutting step of semiconductor package. Hereinafter, a method of manufacturing a semiconductor package when using the lead frame 200 will be described.
第1圖之導線架200係以例如下述之順序而形成。首先，藉由進行作為母材之帶狀金屬板的蝕刻或衝壓(stamping)，而形成導線架，該導線架係以繫桿連接有具備襯墊、配置在襯墊周圍之端子、及支持襯墊之支撐桿的單位架。此時，如第2圖或第3圖所示，設置貫通孔17(18)，並且使端子12之基端部12B及繫桿16的厚度比其他部分更薄。然後，進行導線架之表面處理，且依需要進行彎曲加工。如此，可獲得第1圖所示之導線架200。 The lead frame 200 of FIG. 1 is formed in the following order, for example. First, a lead frame is formed by etching or stamping a strip-shaped metal plate as a base material, and the lead frame is connected with a tie bar, a terminal provided with a spacer, arranged around the spacer, and a support spacer The unit frame of the support rod of the pad. At this time, as shown in FIG. 2 or FIG. 3, through holes 17 (18) are provided, and the thickness of the base end portion 12B of the terminal 12 and the tie bar 16 are made thinner than other portions. Then, the surface treatment of the lead frame is performed, and bending processing is performed as needed. In this way, the lead frame 200 shown in FIG. 1 can be obtained.
在搭載步驟中，係在包含於導線架200之單 位架100的襯墊10，利用例如銀膏等金屬膏來固定半導體晶片。接著，利用接合線(bonding wire)來連接半導體晶片之電極襯墊與端子12。如此，在導線架200之一方主面200a上搭載半導體晶片。 In the mounting step, the order is included in the lead frame 200 The pad 10 of the pedestal 100 fixes the semiconductor wafer with a metal paste such as silver paste. Next, the bonding pads are used to connect the electrode pads of the semiconductor wafer and the terminals 12. In this way, the semiconductor wafer is mounted on one main surface 200 a of the lead frame 200.
在封裝步驟中，將搭載有半導體晶片之導線架200配置在模具內。然後，將樹脂組成物(例如環氧樹脂等熱硬化性樹脂組成物)供給至模具內。此時，樹脂組成物係注入成為：覆蓋具有半導體晶片之一方主面200a的至少一部分，並且亦覆蓋導線架200之另一方之主面的至少一部分。此時，在第2圖或第3圖所示之貫通孔17或貫通孔18，填充有樹脂組成物。然後，進行加熱而在模具內使樹脂組成物硬化，以形成封裝樹脂而獲得樹脂封裝體。 In the packaging step, the lead frame 200 on which the semiconductor wafer is mounted is placed in the mold. Then, a resin composition (for example, a thermosetting resin composition such as epoxy resin) is supplied into the mold. At this time, the resin composition is injected so as to cover at least a part of one main surface 200 a having the semiconductor wafer and also cover at least a part of the other main surface of the lead frame 200. At this time, the through hole 17 or the through hole 18 shown in FIG. 2 or FIG. 3 is filled with the resin composition. Then, heating is performed to harden the resin composition in the mold to form an encapsulating resin to obtain a resin package.
第5圖係在導線架200之一方主面200a上，藉由封裝樹脂80而將半導體晶片70予以封裝之樹脂封裝體110的剖視圖。封裝樹脂80係在一方主面200a側中，覆蓋半導體晶片70，並且覆蓋襯墊10及端子12。如第5圖所示，端子12之基端部12B側係比前端部12A更薄。亦即，基端部12B之下表面係位於比前端部12A之下表面更上方之處。藉此，而在導線架之主面200b形成有凹部19。 FIG. 5 is a cross-sectional view of the resin package 110 that encapsulates the semiconductor wafer 70 with the encapsulating resin 80 on one main surface 200 a of the lead frame 200. The encapsulating resin 80 covers the semiconductor wafer 70 on one side of the main surface 200 a, and covers the pad 10 and the terminal 12. As shown in FIG. 5, the base 12B side of the terminal 12 is thinner than the tip 12A. That is, the lower surface of the base end portion 12B is located above the lower surface of the front end portion 12A. As a result, the recess 19 is formed on the main surface 200b of the lead frame.
在凹部19填充有封裝樹脂80，在凹部19中形成薄壁樹脂部82。導線架之主面200b係在凹部19設置有封裝樹脂80、亦即薄壁樹脂部82。設置在主面200b上之薄壁樹脂部82係藉由第5圖中未顯示之貫通孔內的封 裝樹脂，而與設置在主面200a上之封裝樹脂80相連接。因此，即使在切割步驟時將切削部40予以切削，亦可抑制薄壁樹脂部82從凹部19(端子12)剝離。 The concave portion 19 is filled with encapsulating resin 80, and a thin-walled resin portion 82 is formed in the concave portion 19. The main surface 200b of the lead frame is provided with the encapsulating resin 80, that is, the thin-walled resin portion 82 in the concave portion 19. The thin-walled resin portion 82 provided on the main surface 200b is sealed by a through hole not shown in FIG. 5 It is filled with resin and connected to the encapsulating resin 80 provided on the main surface 200a. Therefore, even if the cutting portion 40 is cut during the cutting step, the thin-walled resin portion 82 can be suppressed from peeling off from the concave portion 19 (terminal 12).
在切割步驟中，沿著繫桿16將如第5圖所示之樹脂封裝體110進行切削。藉由將由單位架100於縱橫方向連接成之導線架200沿著繫桿16進行切削，而個片化成單位架100。此時，繫桿16、一對端子12之基端部12B的一部分、及貫通孔內之封裝樹脂的一部分會被切削。藉此，依第1圖之每個單位架100個片化，而獲得半導體封裝。 In the cutting step, the resin package 110 shown in FIG. 5 is cut along the tie bar 16. By cutting the lead frame 200 connected by the unit frame 100 in the vertical and horizontal directions along the tie bar 16, the individual frames are converted into the unit frame 100. At this time, a portion of the tie bar 16, a portion of the base end portion 12B of the pair of terminals 12, and a portion of the encapsulating resin in the through hole are cut. With this, 100 pieces of each unit frame according to FIG. 1 are sliced to obtain a semiconductor package.
半導體封裝之製造方法並不限定於上述方法。例如在上述實施形態中，雖利用具有第2圖之構造的導線架100，用但亦可利用具有第3圖或第4圖之構造的導線架來取代。即使在利用具有第3圖之構造的導線架之情形時，亦藉由充填在貫通孔18之封裝樹脂80而連接主面200a側之封裝樹脂80及薄壁樹脂部82。藉此，可抑制封裝樹脂從薄壁樹脂部82剝離。在利用具有第4圖之構造的導線架時，係藉由設置在缺口部15之封裝樹脂80而連接主面200a側之封裝樹脂80與薄壁樹脂部82。藉此，可抑制封裝樹脂從薄壁樹脂部82剝離。 The manufacturing method of the semiconductor package is not limited to the above method. For example, in the above embodiment, although the lead frame 100 having the structure of FIG. 2 is used, a lead frame having the structure of FIG. 3 or FIG. 4 may be used instead. Even when the lead frame having the structure of FIG. 3 is used, the encapsulating resin 80 and the thin-walled resin portion 82 on the main surface 200 a side are connected by the encapsulating resin 80 filled in the through hole 18. With this, peeling of the encapsulating resin from the thin-walled resin portion 82 can be suppressed. When the lead frame having the structure of FIG. 4 is used, the encapsulating resin 80 and the thin-walled resin portion 82 on the main surface 200 a side are connected by the encapsulating resin 80 provided in the notch 15. With this, peeling of the encapsulating resin from the thin-walled resin portion 82 can be suppressed.
說明由上述製造方法所製造之半導體封裝的一例。第6圖係半導體封裝150之剖視圖。半導體封裝150係具備：屬於單位架之導線架100；搭載在導線架100之一方主面100a上的半導體晶片70；連接半導體晶片70與 端子12之接合線72；以及封裝半導體晶片70及接合線72且覆蓋導線架100之一對主面100a、100b之至少一部分的封裝樹脂80。 An example of the semiconductor package manufactured by the above manufacturing method will be described. FIG. 6 is a cross-sectional view of the semiconductor package 150. The semiconductor package 150 includes: a lead frame 100 belonging to a unit frame; a semiconductor wafer 70 mounted on one main surface 100a of the lead frame 100; and connecting the semiconductor wafer 70 to The bonding wire 72 of the terminal 12; and the encapsulating resin 80 that encapsulates the semiconductor chip 70 and the bonding wire 72 and covers at least a part of the pair of main surfaces 100 a and 100 b of the lead frame 100.
封裝樹脂80係在導線架100之主面100a側，以覆蓋半導體晶片70且覆蓋端子12之方式設置。封裝樹脂80係在導線架100之主面100b側，以覆蓋端子12之基端部12B的方式設置。設置在該端子12之基端部12B之下側的封裝樹脂80係形成薄壁樹脂部82。薄壁樹脂部82係藉由充填在貫通孔17之封裝樹脂80，而與設置在主面100a上之封裝樹脂80連接。因此，可抑制薄壁樹脂部82從端子12之基端部12B剝離。 The encapsulating resin 80 is provided on the main surface 100 a side of the lead frame 100 so as to cover the semiconductor wafer 70 and the terminal 12. The encapsulating resin 80 is provided on the main surface 100 b side of the lead frame 100 so as to cover the base end portion 12B of the terminal 12. The encapsulating resin 80 provided below the base end portion 12B of the terminal 12 forms a thin-walled resin portion 82. The thin-walled resin portion 82 is connected to the encapsulating resin 80 provided on the main surface 100 a by the encapsulating resin 80 filled in the through hole 17. Therefore, peeling of the thin-walled resin portion 82 from the base end portion 12B of the terminal 12 can be suppressed.
第7圖係半導體封裝150之側視圖。端子12(基端部12B)係由封裝樹脂80所包圍，且其端面會在半導體封裝150之側面中露出。在端子12之基端部12B的下方、亦即主面100b側，係形成有薄壁樹脂部82。薄壁樹脂部82係藉由形成在貫通孔17內之封裝樹脂86，而與主面100a側之封裝樹脂80連接。藉此，可抑制薄壁樹脂部82從端子12剝離。 FIG. 7 is a side view of the semiconductor package 150. The terminal 12 (base end portion 12B) is surrounded by the encapsulating resin 80, and its end surface is exposed in the side surface of the semiconductor package 150. Below the base end portion 12B of the terminal 12, that is, on the main surface 100 b side, a thin-walled resin portion 82 is formed. The thin-walled resin portion 82 is connected to the encapsulating resin 80 on the main surface 100 a side by the encapsulating resin 86 formed in the through hole 17. With this, the thin resin portion 82 can be suppressed from peeling off from the terminal 12.
第8圖係其他例之半導體封裝的側視圖。該半導體封裝係利用具有基端部12D之導線架而製造者，該基端部12D係具有如第4圖所示之缺口部15。端子12(基端部12D)係由封裝樹脂80所包圍，其端面會在該半導體封裝之側面中露出。在端子12之基端部12D的下方、亦即主面100b側，係形成有薄壁樹脂部82。薄壁樹脂部82 係藉由形成在缺口部15內之封裝樹脂86而與主面100a側之封裝樹脂80連接。亦即，由於基端部12D具有缺口部15，因此寬度(第8圖之橫方向的長度)會比前端部12A更小。因此，可使介設在鄰接之端子12間(基端部12D間)的封裝樹脂84之尺寸變大。 Fig. 8 is a side view of a semiconductor package of another example. The semiconductor package is manufactured using a lead frame having a base end portion 12D, and the base end portion 12D has a notch portion 15 as shown in FIG. 4. The terminal 12 (base end portion 12D) is surrounded by the encapsulating resin 80, and its end surface is exposed in the side surface of the semiconductor package. Below the base end portion 12D of the terminal 12, that is, on the main surface 100 b side, a thin-walled resin portion 82 is formed. Thin-walled resin part 82 The encapsulating resin 86 formed in the notch portion 15 is connected to the encapsulating resin 80 on the main surface 100 a side. That is, since the base end portion 12D has the notch portion 15, the width (the length in the horizontal direction in FIG. 8) is smaller than the front end portion 12A. Therefore, the size of the encapsulating resin 84 interposed between the adjacent terminals 12 (between the base end portions 12D) can be increased.
薄壁樹脂部82係藉由介設在鄰接之端子12間(基端部12D間)的封裝樹脂84，而與主面100a側之封裝樹脂80連接。藉此，可抑制薄壁樹脂部82從端子12剝離。 The thin-walled resin portion 82 is connected to the encapsulating resin 80 on the main surface 100a side by the encapsulating resin 84 interposed between the adjacent terminals 12 (between the base end portions 12D). With this, the thin resin portion 82 can be suppressed from peeling off from the terminal 12.
以上，雖說明了本發明之實施形態，但本發明並不限定在上述任一實施形態。例如，在第6圖中，襯墊10與端子12之前端部12A雖會在主面100b側露出，但並不限定於該種襯墊露出型之導線架。例如，亦可在主面100b側以覆蓋襯墊10之方式設置封裝樹脂。雖分別說明在端子之基端部具有貫通孔之導線架的實施形態、在端子之基端部具有缺口部之導線架的實施形態，但並不限定於該等實施形態。亦即，亦可在端子之基端部設置貫通孔與缺口部雙方。 Although the embodiments of the present invention have been described above, the present invention is not limited to any of the above embodiments. For example, in FIG. 6, although the front end 12A of the pad 10 and the terminal 12 is exposed on the main surface 100b side, it is not limited to this type of pad exposed lead frame. For example, the sealing resin may be provided on the main surface 100b side so as to cover the gasket 10. Although the embodiments of the lead frame having a through hole at the base end of the terminal and the lead frame having a notch at the base end of the terminal are described separately, they are not limited to these embodiments. That is, both the through hole and the notch portion may be provided at the base end portion of the terminal.
在上述實施形態中，前端部12A及基端部12B、12D各者之厚度雖均一，但並不限定於此。亦即，若前端部12A具有厚度比基端部12B、12D更大之部分，則前端部12A及基端部12B、12D各者之厚度亦可為不均一。例如，前端部12A之外緣部之至少一部分亦可比該外緣部之內側的本體部之厚度更薄。 In the above embodiment, although the thickness of each of the front end portion 12A and the base end portions 12B and 12D is uniform, it is not limited to this. That is, if the front end portion 12A has a larger thickness than the base end portions 12B and 12D, the thickness of each of the front end portion 12A and the base end portions 12B and 12D may not be uniform. For example, at least a part of the outer edge portion of the front end portion 12A may be thinner than the thickness of the body portion inside the outer edge portion.
10‧‧‧襯墊 10‧‧‧Padding
12‧‧‧端子 12‧‧‧terminal
12A‧‧‧前端部 12A‧‧‧Front end
12B‧‧‧基端部 12B‧‧‧Base end
14‧‧‧支撐桿 14‧‧‧support rod
16‧‧‧繫桿 16‧‧‧tie
100‧‧‧單位架 100‧‧‧Unit rack
200‧‧‧導線架 200‧‧‧ Lead frame
200a‧‧‧主面 200a‧‧‧Main
II‧‧‧區域 II‧‧‧Region
Claims (9)
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|---|---|---|---|
| JP2016032421A JP6695166B2 (en) | 2016-02-23 | 2016-02-23 | Lead frame and method for manufacturing semiconductor package |
| JP2016-032421 | 2016-02-23 |
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| Publication Number | Publication Date |
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| TW201801261A true TW201801261A (en) | 2018-01-01 |
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| JP2001320007A (en) * | 2000-05-09 | 2001-11-16 | Dainippon Printing Co Ltd | Frame for resin sealed semiconductor device |
| JP4417541B2 (en) * | 2000-10-23 | 2010-02-17 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
| KR20020093250A (en) * | 2001-06-07 | 2002-12-16 | 삼성전자 주식회사 | ELP type leadframe and ELP using the same |
| JP2009302209A (en) * | 2008-06-11 | 2009-12-24 | Nec Electronics Corp | Lead frame, semiconductor device, manufacturing method of lead frame, and manufacturing method of semiconductor device |
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| JP2017152496A (en) | 2017-08-31 |
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