TW201742279A - Resistive random access memory - Google Patents
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本發明是有關於一種非揮發性記憶體,且特別是有關於一種電阻式隨機存取記憶體。This invention relates to a non-volatile memory, and more particularly to a resistive random access memory.
電阻式隨機存取記憶體(Resistive random access memory,RRAM)屬於非揮發性記憶體的一種。因電阻式隨機存取記憶體具有結構簡單、操作電壓低、操作時間快速、可多位元記憶、成本低、耐久性佳等優點,故目前被廣泛地研究中。電阻式隨機存取記憶體常用的基本結構是以一個電晶體加上一個電阻(1T1R)所組成。藉由改變外加偏壓的方式改變電阻的電阻值,使元件處於高電阻態(High resistance state)或低電阻態(Low resistance state),並藉此判讀數位訊號的0或1。Resistive random access memory (RRAM) is a type of non-volatile memory. Resistive random access memory is widely studied because of its simple structure, low operating voltage, fast operation time, multi-bit memory, low cost and good durability. The basic structure commonly used in resistive random access memory is composed of a transistor plus a resistor (1T1R). The resistance value of the resistor is changed by changing the applied bias voltage, so that the component is in a high resistance state or a low resistance state, and thereby 0 or 1 of the bit signal is judged.
本發明提供一種電阻式隨機存取記憶體,能縮小電阻式隨機存取記憶體元件的尺寸,提高元件集積度。The present invention provides a resistive random access memory capable of reducing the size of a resistive random access memory device and improving component accumulation.
本發明的一種電阻式隨機存取記憶體,包括:記憶體單元,設置於第一導線與第二導線的交點之間。記憶體單元包括以任意順序串聯下述三元件:選擇器結構、第一限流器結構與電阻結構。A resistive random access memory according to the present invention includes: a memory unit disposed between an intersection of a first wire and a second wire. The memory unit includes three elements in series connected in any order: a selector structure, a first current limiter structure, and a resistance structure.
在本發明的一實施例中,上述的電阻式隨機存取記憶體,其中選擇器結構依序包括第一導電層、選擇材料層與第二導電層。In an embodiment of the invention, the resistive random access memory, wherein the selector structure comprises a first conductive layer, a selected material layer and a second conductive layer in sequence.
在本發明的一實施例中,上述的電阻式隨機存取記憶體,其中第一限流器結構依序包括第三導電層、第一金屬層、第一限流材料層與第四導電層。In an embodiment of the present invention, the resistive random access memory, wherein the first current limiter structure sequentially includes a third conductive layer, a first metal layer, a first current limiting material layer, and a fourth conductive layer. .
在本發明的一實施例中,上述的電阻式隨機存取記憶體,其中電阻結構依序包括第五導電層、可變電阻層與第六導電層。In an embodiment of the invention, the resistive random access memory, wherein the resistor structure sequentially includes a fifth conductive layer, a variable resistance layer, and a sixth conductive layer.
在本發明的一實施例中,上述的電阻式隨機存取記憶體,其中第五導電層或第六導電層的其中之一者的氧親和力高於另外一者的氧親和力。In an embodiment of the invention, the resistive random access memory, wherein one of the fifth conductive layer or the sixth conductive layer has an oxygen affinity higher than that of the other one.
在本發明的一實施例中,上述的電阻式隨機存取記憶體,其中記憶體單元更包括第二限流器結構,與三元件串聯。In an embodiment of the invention, the resistive random access memory, wherein the memory unit further comprises a second current limiter structure in series with the three elements.
在本發明的一實施例中,上述的電阻式隨機存取記憶體,其中第二限流器結構更包括第七導電層、第二限流材料層與第八導電層。In an embodiment of the invention, the resistive random access memory, wherein the second current limiter structure further comprises a seventh conductive layer, a second current limiting material layer and an eighth conductive layer.
在本發明的一實施例中,上述的電阻式隨機存取記憶體,其中第一導電層與第二導電層的材料包括氮化鈦、氮化鉭、鈦、鉭或氧化銦錫。In an embodiment of the invention, the resistive random access memory, wherein the material of the first conductive layer and the second conductive layer comprises titanium nitride, tantalum nitride, titanium, tantalum or indium tin oxide.
在本發明的一實施例中,上述的電阻式隨機存取記憶體,其中選擇材料層的材料包括矽或二氧化鈦或非晶系硫屬化合物。In an embodiment of the invention, the resistive random access memory, wherein the material of the selected material layer comprises tantalum or titanium dioxide or an amorphous chalcogen compound.
在本發明的一實施例中,上述的電阻式隨機存取記憶體,其中第三導電層與第四導電層的材料包括氮化鈦、氮化鉭、鈦、鉭或氧化銦錫。In an embodiment of the invention, the resistive random access memory, wherein the materials of the third conductive layer and the fourth conductive layer comprise titanium nitride, tantalum nitride, titanium, tantalum or indium tin oxide.
在本發明的一實施例中,上述的電阻式隨機存取記憶體,其中第一限流材料層的材料包括矽或二氧化鈦。In an embodiment of the invention, the resistive random access memory, wherein the material of the first current limiting material layer comprises tantalum or titanium dioxide.
在本發明的一實施例中,上述的電阻式隨機存取記憶體,其中第五導電層與第六導電層的材料包括氮化鈦、氮化鉭、鈦、鉭或氧化銦錫。第五導電層或第六導電層的其中之一者的氧親和力高於另外一者的氧親和力。In an embodiment of the invention, the resistive random access memory, wherein the materials of the fifth conductive layer and the sixth conductive layer comprise titanium nitride, tantalum nitride, titanium, tantalum or indium tin oxide. One of the fifth conductive layer or the sixth conductive layer has an oxygen affinity higher than that of the other one.
在本發明的一實施例中,上述的電阻式隨機存取記憶體,其中可變電阻層的材料包括過渡金屬氧化物。In an embodiment of the invention, the resistive random access memory, wherein the material of the variable resistance layer comprises a transition metal oxide.
在本發明的一實施例中,上述的電阻式隨機存取記憶體,其中可變電阻層的材料包括鋁、鈦、碲、銅、銀或鎳。In an embodiment of the invention, the resistive random access memory, wherein the material of the variable resistance layer comprises aluminum, titanium, tantalum, copper, silver or nickel.
在本發明的一實施例中,上述的電阻式隨機存取記憶體,其中第七導電層與第八導電層的材料包括氮化鈦、氮化鉭、鈦、鉭或氧化銦錫。In an embodiment of the invention, the resistive random access memory, wherein the materials of the seventh conductive layer and the eighth conductive layer comprise titanium nitride, tantalum nitride, titanium, tantalum or indium tin oxide.
在本發明的一實施例中,上述的電阻式隨機存取記憶體,其中第二限流材料層的材料包括矽或二氧化鈦。In an embodiment of the invention, the resistive random access memory, wherein the material of the second current limiting material layer comprises tantalum or titanium dioxide.
基於上述,本發明的電阻式隨機存取記憶體結構藉由於電阻結構上連結選擇器結構與第一限流器結構(即1R1D1S或1D1S1R的結構),替代傳統的電阻式隨機存取記憶體結構(一個電晶體連結一個電阻結構,即1T1R的結構),能縮小電阻式隨機存取記憶體元件的尺寸,提高元件集積度。Based on the above, the resistive random access memory structure of the present invention replaces the conventional resistive random access memory structure by a resistor structure connecting the selector structure and the first current limiter structure (ie, the structure of the 1R1D1S or 1D1S1R). (A transistor is connected to a resistor structure, that is, the structure of 1T1R), which can reduce the size of the resistive random access memory device and improve the component accumulation.
本發明的電阻式隨機存取記憶體具有選擇器結構。在一實施例中,選擇器結構藉由導電層與選擇材料層之間形成肖特基能障(Schottky barrier),可作為控制記憶體單元電路的開關。對此肖特基能障以維持足夠非線性,一個關鍵需求特性是此肖特基能障可藉由高電場窄化。在另一實施例中,選擇材料是在低於其結晶溫度下操作的硫屬化合物,但在高於一臨界電壓(threshold valtage)時經歷轉折。The resistive random access memory of the present invention has a selector structure. In an embodiment, the selector structure forms a Schottky barrier between the conductive layer and the selected material layer, and can be used as a switch for controlling the memory unit circuit. For this Schottky barrier to maintain sufficient nonlinearity, a key requirement is that the Schottky barrier can be narrowed by high electric fields. In another embodiment, the material is selected to be a chalcogenide that operates below its crystallization temperature, but undergoes a transition above a threshold valtage.
本發明的電阻式隨機存取記憶體具有第一限流器結構,其藉由導電層或金屬層,與限流材料層之間形成未藉由電場窄化的肖特基能障,可作為控制記憶體單元電路的電流量的電流限制器(Current limiter),亦即可控制流經電阻結構的電流低於一飽和電流(saturation current)值,可避免電阻結構在SET操作過程改變電阻可能造成不可逆的損傷。The resistive random access memory of the present invention has a first current limiter structure, and a Schottky barrier that is not narrowed by an electric field is formed between the current limiting material layer and the current limiting material layer by using a conductive layer or a metal layer. The current limiter that controls the current amount of the memory unit circuit can also control the current flowing through the resistor structure to be lower than a saturation current value, which can prevent the resistor structure from changing resistance during the SET operation. Irreversible damage.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
請參照圖1A與圖1B,電阻式隨機存取記憶體100具有多條位元線BL與多條字元線WL,多條位元線BL彼此互相平行設置,多條字元線WL彼此互相平行設置,且與位元線BL垂直。每個位元線BL與字元線WL的交點之間,設置有記憶體單元100。換句話說,記憶體單元100例如設置於兩條彼此交叉的導線WL/BL的交點之間,其中一條導線作為字元線,另一條導線則作為位元線。Referring to FIG. 1A and FIG. 1B, the resistive random access memory 100 has a plurality of bit lines BL and a plurality of word lines WL. The plurality of bit lines BL are disposed in parallel with each other, and the plurality of word lines WL are mutually connected to each other. Set in parallel and perpendicular to the bit line BL. A memory cell 100 is provided between the intersection of each bit line BL and the word line WL. In other words, the memory cell 100 is disposed, for example, between intersections of two wires WL/BL crossing each other, one of which serves as a word line and the other of which serves as a bit line.
請參照圖2A與圖2B,記憶體單元110包括選擇器結構S、限流器結構D1與電阻結構R,其中限流器結構D1設置於選擇器結構S與導線WL/BL之間,電阻結構R設置於限流器結構D1與導線WL/BL之間。Referring to FIG. 2A and FIG. 2B, the memory unit 110 includes a selector structure S, a current limiter structure D1 and a resistance structure R, wherein the current limiter structure D1 is disposed between the selector structure S and the wires WL/BL, and the resistance structure R is disposed between the current limiter structure D1 and the wires WL/BL.
選擇器結構S依序包括導電層142、選擇材料層120與導電層140。選擇器結構S例如是雙極性選擇器。選擇器結構S藉由導電層142、導電層140與選擇材料層120之間可形成肖特基能障。對此肖特基能障以維持足夠非線性,一個關鍵需求特性是此肖特基能障可藉由高電場窄化。為了讓上述條件發生的需求是選擇材料層120必須足夠薄。另外,硫屬化合物在低於一臨界電壓Vth時是高度絕緣,但在高於臨界電壓Vth時變成高度導電。導電層142與導電層140的材料例如是導電材料,例如是氮化鈦(TiN)、氮化鉭(TaN)、鈦(Ti)、鉭(Ta)或氧化銦錫(ITO,Indium Tin Oxide)。選擇材料層120的材料例如是半導體材料,例如是矽(Si)或二氧化鈦(TiO2 )或非晶系硫屬化合物,例如碳摻雜GeTe。The selector structure S sequentially includes a conductive layer 142, a selection material layer 120, and a conductive layer 140. The selector structure S is, for example, a bipolar selector. The selector structure S can form a Schottky barrier between the conductive layer 142, the conductive layer 140 and the selective material layer 120. For this Schottky barrier to maintain sufficient nonlinearity, a key requirement is that the Schottky barrier can be narrowed by high electric fields. The requirement for the above conditions to occur is that the material layer 120 must be sufficiently thin. In addition, the chalcogenide compound is highly insulating when it is lower than a threshold voltage Vth, but becomes highly conductive when it is higher than the threshold voltage Vth. The material of the conductive layer 142 and the conductive layer 140 is, for example, a conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), tantalum (Ta) or indium tin oxide (ITO, Indium Tin Oxide). . The material of the material layer 120 is selected, for example, as a semiconductor material such as bismuth (Si) or titanium dioxide (TiO 2 ) or an amorphous chalcogen compound such as carbon doped GeTe.
限流器結構D1依序包括導電層144、金屬層124、限流材料層122與導電層142。限流器結構D1藉由導電層144或金屬層124、限流材料層122與導電層142之間形成足夠厚且未藉由電場窄化的肖特基能障,可作為控制記憶體單元電路的電流量的電流限制器,亦即可控制流經電阻結構的電流低於一飽和電流值,可避免電阻結構在SET操作過程改變電阻可能造成不可逆的損傷。導電層144與導電層142的材料例如是導電材料,例如是氮化鈦、氮化鉭、鈦、鉭或氧化銦錫。金屬層124的材料例如是金屬,例如是鈦。限流材料層122的材料例如是半導體材料,例如是矽或二氧化鈦。The current limiter structure D1 sequentially includes a conductive layer 144, a metal layer 124, a current limiting material layer 122, and a conductive layer 142. The current limiter structure D1 can be used as a control memory unit circuit by forming a Schottky barrier between the conductive layer 144 or the metal layer 124, the current limiting material layer 122 and the conductive layer 142, which is thick enough and not narrowed by an electric field. The current limiter of the current amount can also control the current flowing through the resistor structure below a saturation current value to avoid irreversible damage of the resistor structure during the SET operation. The material of the conductive layer 144 and the conductive layer 142 is, for example, a conductive material such as titanium nitride, tantalum nitride, titanium, tantalum or indium tin oxide. The material of the metal layer 124 is, for example, a metal such as titanium. The material of the current limiting material layer 122 is, for example, a semiconductor material such as tantalum or titanium dioxide.
電阻結構R依序包括導電層146、可變電阻層126與導電層144。導電層144與導電層146的材料例如是導電材料,例如是氮化鈦、氮化鉭、鈦、鉭或氧化銦錫。導電層144的氧親和力高於導電層146的氧親和力。可變電阻層126可為單層結構或多層結構,當可變電阻層126為單層結構時,其材料例如是過渡金屬氧化物,例如是氧化鎳(NiO)、氧化鉿(HfO)、二氧化鉿(HfO2 )、氧化鋯(ZrO)、二氧化鋯(ZrO2 )、五氧化二鉭(Ta2 O5 )、氧化鋅(ZnO)、三氧化鎢(WO3 )、氧化鈷(CoO)以及五氧化二鈮(Nb2 O5 )。當可變電阻層126為多層結構時,可包括金屬層(未繪示)與可變電阻材料層,金屬層可作為氧交換層,金屬層的氧親和力例如是大於導電層144與導電層146的氧親和力。金屬層的材料例如是金屬材料,例如是鈦、鉭、鉿、鋯、鉑或鋁;可變電阻材料層的材料例如是過渡金屬氧化物,例如是氧化鎳(NiO)、氧化鉿(HfO)、二氧化鉿(HfO2 )、氧化鋯(ZrO)、二氧化鋯(ZrO2 )、五氧化二鉭(Ta2 O5 )、氧化鋅(ZnO)、三氧化鎢(WO3 )、氧化鈷(CoO)以及五氧化二鈮(Nb2 O5 )。The resistor structure R sequentially includes a conductive layer 146, a variable resistance layer 126, and a conductive layer 144. The material of the conductive layer 144 and the conductive layer 146 is, for example, a conductive material such as titanium nitride, tantalum nitride, titanium, tantalum or indium tin oxide. The oxygen affinity of the conductive layer 144 is higher than the oxygen affinity of the conductive layer 146. The variable resistance layer 126 may be a single layer structure or a multilayer structure. When the variable resistance layer 126 is a single layer structure, the material thereof is, for example, a transition metal oxide such as nickel oxide (NiO), hafnium oxide (HfO), or HbO 2 , ZrO, ZrO 2 , Ta 2 O 5 , Zinc Oxide (ZnO), T 3 (WO 3 ), Cobalt Oxide (CoO) And bismuth pentoxide (Nb 2 O 5 ). When the variable resistance layer 126 is a multi-layer structure, a metal layer (not shown) and a variable resistance material layer may be included. The metal layer may serve as an oxygen exchange layer. The oxygen affinity of the metal layer is, for example, greater than the conductive layer 144 and the conductive layer 146. Oxygen affinity. The material of the metal layer is, for example, a metal material such as titanium, tantalum, niobium, zirconium, platinum or aluminum; and the material of the variable resistance material layer is, for example, a transition metal oxide such as nickel oxide (NiO) or hafnium oxide (HfO). , cerium oxide (HfO 2 ), zirconium oxide (ZrO), zirconium dioxide (ZrO 2 ), tantalum pentoxide (Ta 2 O 5 ), zinc oxide (ZnO), tungsten trioxide (WO 3 ), cobalt oxide (CoO) and bismuth pentoxide (Nb 2 O 5 ).
在此實施例的記憶體單元110中,導電層142同時作為選擇器結構S的上電極以及限流器結構D1的下電極,而導電層144同時作為限流器結構D1的上電極以及電阻結構R的下電極。導電層142與導電層144可分別為單層材料或為多層材料,當其為多層材料時,各層可分別作為上述各結構的上電極或下電極,其中各層材料可相同亦可不同。In the memory unit 110 of this embodiment, the conductive layer 142 serves as both the upper electrode of the selector structure S and the lower electrode of the current limiter structure D1, and the conductive layer 144 serves as both the upper electrode of the current limiter structure D1 and the resistance structure. The lower electrode of R. The conductive layer 142 and the conductive layer 144 may be a single layer material or a multi-layer material. When it is a multi-layer material, each layer may be used as an upper electrode or a lower electrode of each of the above structures, wherein the layers may be the same or different.
在此實施例的記憶體單元110中,導電層146作為記憶體單元110的上電極,導電層140作為記憶體單元110的下電極。作為上電極的導電層146亦可與位元線或字元線為同一層,作為下電極的導電層140亦可與位元線或字元線為同一層。例如當導電層140與位元線為同一層時導電層146與字元線為同一層,或當導電層140與字元線為同一層時導電層146與位元線為同一層。In the memory unit 110 of this embodiment, the conductive layer 146 serves as the upper electrode of the memory unit 110, and the conductive layer 140 serves as the lower electrode of the memory unit 110. The conductive layer 146 as the upper electrode may also be the same layer as the bit line or the word line, and the conductive layer 140 as the lower electrode may be the same layer as the bit line or the word line. For example, when the conductive layer 140 and the bit line are the same layer, the conductive layer 146 and the word line are the same layer, or when the conductive layer 140 and the word line are the same layer, the conductive layer 146 and the bit line are the same layer.
請參照圖3A與圖3B,記憶體單元110包括選擇器結構S、限流器結構D1與電阻結構R,其中限流器結構D1,設置於選擇器結構S與導線WL/BL之間,電阻結構R設置於選擇器結構S與導線BL/WL之間。Referring to FIG. 3A and FIG. 3B, the memory unit 110 includes a selector structure S, a current limiter structure D1 and a resistor structure R, wherein the current limiter structure D1 is disposed between the selector structure S and the wires WL/BL, and the resistor The structure R is disposed between the selector structure S and the wires BL/WL.
選擇器結構S依序包括導電層154、選擇材料層120與導電層152。選擇器結構S例如是雙極性選擇器。選擇器結構S藉由導電層154、導電層152與選擇材料層120之間可形成肖特基能障,可作為控制記憶體單元電路的開關,或選擇材料層是具有臨界電壓Vth的非晶系硫屬化合物,在偏壓V未達Vth(即0 < |V| < |Vth|)時維持電路打開,而在偏壓V超過Vth(即|V| > |Vth|)時使電路關閉。導電層154與導電層152的材料例如是導電材料,例如是氮化鈦(TiN)、氮化鉭(TaN)、鈦(Ti)、鉭(Ta)或氧化銦錫(ITO,Indium Tin Oxide)。選擇材料層120的材料例如是半導體材料,例如是矽(Si)或二氧化鈦(TiO2 )。The selector structure S sequentially includes a conductive layer 154, a selection material layer 120, and a conductive layer 152. The selector structure S is, for example, a bipolar selector. The selector structure S can form a Schottky barrier between the conductive layer 154, the conductive layer 152 and the selective material layer 120, can be used as a switch for controlling the memory unit circuit, or the selected material layer is amorphous with a threshold voltage Vth. A chalcogen compound that keeps the circuit open when the bias voltage V is less than Vth (ie, 0 < |V| < |Vth|), and turns off the circuit when the bias voltage V exceeds Vth (ie, |V| > |Vth|) . The material of the conductive layer 154 and the conductive layer 152 is, for example, a conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), tantalum (Ta) or indium tin oxide (ITO, Indium Tin Oxide). . The material of the material layer 120 is selected, for example, as a semiconductor material such as bismuth (Si) or titanium dioxide (TiO 2 ).
限流器結構D1依序包括導電層156、金屬層124、限流材料層122與導電層154。限流器結構D1藉由限流材料層122與導電層154之間形成肖特基能障,可作為控制記憶體單元電路的電流量的電流限制器,亦即可控制流經電阻結構的電流低於一飽和電流值,可避免電阻結構在SET操作過程改變電阻可能造成不可逆的損傷。導電層156與導電層154的材料例如是導電材料,例如是氮化鈦、氮化鉭、鈦、鉭或氧化銦錫。金屬層124的材料例如是金屬,例如是鈦。限流材料層122的材料例如是半導體材料,例如是矽或二氧化鈦。The current limiter structure D1 sequentially includes a conductive layer 156, a metal layer 124, a current limiting material layer 122, and a conductive layer 154. The current limiter structure D1 forms a Schottky barrier between the current limiting material layer 122 and the conductive layer 154, and can be used as a current limiter for controlling the current amount of the memory unit circuit, and can also control the current flowing through the resistor structure. Below a saturation current value, it can be avoided that the resistance structure can cause irreversible damage during the SET operation. The material of the conductive layer 156 and the conductive layer 154 is, for example, a conductive material such as titanium nitride, tantalum nitride, titanium, tantalum or indium tin oxide. The material of the metal layer 124 is, for example, a metal such as titanium. The material of the current limiting material layer 122 is, for example, a semiconductor material such as tantalum or titanium dioxide.
電阻結構R依序包括導電層152、可變電阻層126與導電層150。導電層152與導電層150的材料例如是導電材料,例如是氮化鈦、氮化鉭、鈦、鉭或氧化銦錫。可變電阻層126可為單層結構或多層結構,當可變電阻層126為單層結構時,其材料例如是過渡金屬氧化物,例如是氧化鎳(NiO)、氧化鉿(HfO)、二氧化鉿(HfO2 )、氧化鋯(ZrO)、二氧化鋯(ZrO2 )、五氧化二鉭(Ta2 O5 )、氧化鋅(ZnO)、三氧化鎢(WO3 )、氧化鈷(CoO)以及五氧化二鈮(Nb2 O5 )。當可變電阻層126為多層結構時,可包括金屬層(未繪示)與可變電阻材料層,金屬層可作為氧交換層,金屬層的氧親和力例如是大於導電層152與導電層150的氧親和力。金屬層的材料例如是金屬材料,例如是鈦、鉭、鉿、鋯、鉑或鋁;可變電阻材料層的材料例如是過渡金屬氧化物,例如是氧化鎳(NiO)、氧化鉿(HfO)、二氧化鉿(HfO2 )、氧化鋯(ZrO)、二氧化鋯(ZrO2 )、五氧化二鉭(Ta2 O5 )、氧化鋅(ZnO)、三氧化鎢(WO3 )、氧化鈷(CoO)以及五氧化二鈮(Nb2 O5 )。The resistor structure R sequentially includes a conductive layer 152, a variable resistance layer 126, and a conductive layer 150. The material of the conductive layer 152 and the conductive layer 150 is, for example, a conductive material such as titanium nitride, tantalum nitride, titanium, tantalum or indium tin oxide. The variable resistance layer 126 may be a single layer structure or a multilayer structure. When the variable resistance layer 126 is a single layer structure, the material thereof is, for example, a transition metal oxide such as nickel oxide (NiO), hafnium oxide (HfO), or HbO 2 , ZrO, ZrO 2 , Ta 2 O 5 , Zinc Oxide (ZnO), T 3 (WO 3 ), Cobalt Oxide (CoO) And bismuth pentoxide (Nb 2 O 5 ). When the variable resistance layer 126 is a multi-layer structure, a metal layer (not shown) and a variable resistance material layer may be included. The metal layer may serve as an oxygen exchange layer. The oxygen affinity of the metal layer is, for example, greater than the conductive layer 152 and the conductive layer 150. Oxygen affinity. The material of the metal layer is, for example, a metal material such as titanium, tantalum, niobium, zirconium, platinum or aluminum; and the material of the variable resistance material layer is, for example, a transition metal oxide such as nickel oxide (NiO) or hafnium oxide (HfO). , cerium oxide (HfO 2 ), zirconium oxide (ZrO), zirconium dioxide (ZrO 2 ), tantalum pentoxide (Ta 2 O 5 ), zinc oxide (ZnO), tungsten trioxide (WO 3 ), cobalt oxide (CoO) and bismuth pentoxide (Nb 2 O 5 ).
在此實施例的記憶體單元110中,導電層154同時作為選擇器結構S的上電極以及限流器結構D1的下電極,而導電層152同時作為電阻結構R的上電極以及選擇器結構S的下電極。導電層154與導電層152可分別為單層材料或為多層材料,當其為多層材料時,各層可分別作為上述各結構的上電極或下電極,其中各層材料可相同亦可不同。In the memory unit 110 of this embodiment, the conductive layer 154 serves as both the upper electrode of the selector structure S and the lower electrode of the current limiter structure D1, and the conductive layer 152 serves as both the upper electrode of the resistance structure R and the selector structure S. Lower electrode. The conductive layer 154 and the conductive layer 152 may be a single layer material or a multi-layer material. When it is a multi-layer material, each layer may be used as an upper electrode or a lower electrode of each of the above structures, wherein the layers may be the same or different.
在此實施例的記憶體單元110中,導電層156作為記憶體單元110的上電極,導電層150作為記憶體單元110的下電極。作為上電極的導電層156亦可與位元線或字元線為同一層,作為下電極的導電層150亦可與位元線或字元線為同一層。例如當導電層156與位元線為同一層時導電層150與字元線為同一層,或當導電層156與字元線為同一層時導電層150與位元線為同一層。In the memory unit 110 of this embodiment, the conductive layer 156 serves as the upper electrode of the memory unit 110, and the conductive layer 150 serves as the lower electrode of the memory unit 110. The conductive layer 156 as the upper electrode may also be the same layer as the bit line or the word line, and the conductive layer 150 as the lower electrode may be the same layer as the bit line or the word line. For example, when the conductive layer 156 and the bit line are the same layer, the conductive layer 150 and the word line are the same layer, or when the conductive layer 156 and the word line are the same layer, the conductive layer 150 and the bit line are the same layer.
請參照圖4A與圖4B,記憶體單元110包括選擇器結構S、限流器結構D1、限流器結構D2與電阻結構R,其中限流器結構D1,設置於選擇器結構S與導線WL/BL之間,電阻結構R設置於限流器結構D1與導線WL/BL之間,限流器結構D2設置於電阻結構R與導線WL/BL之間。選擇器結構S、限流器結構D1與電阻結構R各結構內的層和各層材料與第一實施例相同,在此不再贅述。4A and FIG. 4B, the memory unit 110 includes a selector structure S, a current limiter structure D1, a current limiter structure D2, and a resistance structure R, wherein the current limiter structure D1 is disposed on the selector structure S and the wire WL. Between /BL, the resistor structure R is disposed between the current limiter structure D1 and the wires WL/BL, and the current limiter structure D2 is disposed between the resistor structure R and the wires WL/BL. The layer of the selector structure S, the current limiter structure D1 and the resistor structure R and the material of each layer are the same as those of the first embodiment, and are not described herein again.
限流器結構D2依序包括導電層148、金屬層130、限流材料層128與導電層146。導電層148與導電層146的材料例如是導電材料,例如是氮化鈦、氮化鉭、鈦、鉭或氧化銦錫。金屬層130的材料例如是金屬,例如是鈦。限流材料層128的材料例如是半導體材料,例如是矽或二氧化鈦。The current limiter structure D2 sequentially includes a conductive layer 148, a metal layer 130, a current limiting material layer 128, and a conductive layer 146. The material of the conductive layer 148 and the conductive layer 146 is, for example, a conductive material such as titanium nitride, tantalum nitride, titanium, tantalum or indium tin oxide. The material of the metal layer 130 is, for example, a metal such as titanium. The material of the current limiting material layer 128 is, for example, a semiconductor material such as tantalum or titanium dioxide.
在此實施例的記憶體單元110中,導電層146同時作為電阻結構R的上電極以及限流器結構D2的下電極,導電層144同時作為限流器結構D1的上電極以及電阻結構R的下電極,而導電層142同時作為選擇器結構S的上電極以及限流器結構D1的下電極。導電層146、導電層144與導電層142可分別為單層材料或為多層材料,當其為多層材料時,各層可分別作為上述各結構的上電極或下電極,其中各層材料可相同亦可不同。In the memory unit 110 of this embodiment, the conductive layer 146 serves as both the upper electrode of the resistor structure R and the lower electrode of the current limiter structure D2, and the conductive layer 144 serves as both the upper electrode of the current limiter structure D1 and the resistor structure R. The lower electrode, while the conductive layer 142 serves as both the upper electrode of the selector structure S and the lower electrode of the current limiter structure D1. The conductive layer 146, the conductive layer 144 and the conductive layer 142 may be a single layer material or a multi-layer material. When it is a multi-layer material, each layer may be used as an upper electrode or a lower electrode of each of the above structures, wherein each layer material may be the same or different.
在此實施例的記憶體單元110中,導電層148作為記憶體單元110的上電極,導電層140作為記憶體單元110的下電極。作為上電極的導電層148亦可與位元線或字元線為同一層,作為下電極的導電層140亦可與位元線或字元線為同一層。例如當導電層148與位元線為同一層時導電層140與字元線為同一層,或當導電層148與字元線為同一層時導電層140與位元線為同一層。In the memory unit 110 of this embodiment, the conductive layer 148 serves as the upper electrode of the memory unit 110, and the conductive layer 140 serves as the lower electrode of the memory unit 110. The conductive layer 148 as the upper electrode may also be the same layer as the bit line or the word line, and the conductive layer 140 as the lower electrode may be the same layer as the bit line or the word line. For example, when the conductive layer 148 and the bit line are the same layer, the conductive layer 140 and the word line are the same layer, or when the conductive layer 148 and the word line are the same layer, the conductive layer 140 and the bit line are the same layer.
請參照圖5A與圖5B,記憶體單元110包括選擇器結構S、限流器結構D1、限流器結構D2與電阻結構R,其中限流器結構D1,設置於選擇器結構S與導線WL/BL之間,電阻結構R設置於選擇器結構S與導線BL/WL之間,限流器結構D2設置於電阻結構R與導線BL/WL之間。選擇器結構S、限流器結構D1與電阻結構R各結構內的層和各層材料與第二實施例相同,在此不再贅述。5A and 5B, the memory unit 110 includes a selector structure S, a current limiter structure D1, a current limiter structure D2, and a resistance structure R, wherein the current limiter structure D1 is disposed on the selector structure S and the wire WL. Between /BL, the resistor structure R is disposed between the selector structure S and the wires BL/WL, and the current limiter structure D2 is disposed between the resistor structure R and the wires BL/WL. The layer of the selector structure S, the current limiter structure D1 and the resistor structure R and the material of each layer are the same as those of the second embodiment, and are not described herein again.
限流器結構D2依序包括導電層150、金屬層130、限流材料層128與導電層158。導電層150與導電層158的材料例如是導電材料,例如是氮化鈦、氮化鉭、鈦、鉭或氧化銦錫。金屬層130的材料例如是金屬,例如是鈦。限流材料層128的材料例如是半導體材料,例如是矽或二氧化鈦。限流器結構D2的目的是限制電流,此電流的方向與限流器結構D1作用的方向相反,因為肖特基能障主要在一優選方向是作用的。The current limiter structure D2 sequentially includes a conductive layer 150, a metal layer 130, a current limiting material layer 128, and a conductive layer 158. The material of the conductive layer 150 and the conductive layer 158 is, for example, a conductive material such as titanium nitride, tantalum nitride, titanium, tantalum or indium tin oxide. The material of the metal layer 130 is, for example, a metal such as titanium. The material of the current limiting material layer 128 is, for example, a semiconductor material such as tantalum or titanium dioxide. The purpose of the current limiter structure D2 is to limit the current, the direction of which is opposite to the direction in which the current limiter structure D1 acts, since the Schottky energy barrier acts primarily in a preferred direction.
在此實施例的記憶體單元110中,導電層154同時作為選擇器結構S的上電極以及限流器結構D1的下電極,導電層152同時作為電阻結構R的上電極以及選擇器結構S的下電極,而導電層150同時作為限流器結構D2的上電極以及電阻結構R的下電極。導電層154、導電層152與導電層150可分別為單層材料或為多層材料,當其為多層材料時,各層可分別作為上述各結構的上電極或下電極,其中各層材料可相同亦可不同。In the memory unit 110 of this embodiment, the conductive layer 154 serves as both the upper electrode of the selector structure S and the lower electrode of the current limiter structure D1, and the conductive layer 152 serves as both the upper electrode of the resistive structure R and the selector structure S. The lower electrode, while the conductive layer 150 serves as both the upper electrode of the current limiter structure D2 and the lower electrode of the resistance structure R. The conductive layer 154, the conductive layer 152 and the conductive layer 150 may be a single layer material or a multi-layer material. When it is a multi-layer material, each layer may be used as an upper electrode or a lower electrode of each of the above structures, wherein each layer material may be the same or different.
在此實施例的記憶體單元110中,導電層156作為記憶體單元110的上電極,導電層158作為記憶體單元110的下電極。作為上電極的導電層156亦可與位元線或字元線為同一層,作為下電極的導電層158亦可與位元線或字元線為同一層。例如當導電層156與位元線為同一層時導電層158與字元線為同一層,或當導電層156與字元線為同一層時導電層158與位元線為同一層。In the memory unit 110 of this embodiment, the conductive layer 156 serves as the upper electrode of the memory unit 110, and the conductive layer 158 serves as the lower electrode of the memory unit 110. The conductive layer 156 as the upper electrode may also be the same layer as the bit line or the word line, and the conductive layer 158 as the lower electrode may be the same layer as the bit line or the word line. For example, when the conductive layer 156 and the bit line are the same layer, the conductive layer 158 and the word line are the same layer, or when the conductive layer 156 and the word line are the same layer, the conductive layer 158 and the bit line are the same layer.
綜上所述,本發明的電阻式隨機存取記憶體具有選擇器結構、第一限流器結構與電阻結構,藉由於電阻結構上連結選擇器結構與限流結構(即1R1D1S或1D1S1R的結構),替代傳統的電阻式隨機存取記憶體結構(一個電晶體連結一個電阻結構,即1T1R的結構),可提高元件集積度。In summary, the resistive random access memory of the present invention has a selector structure, a first current limiter structure and a resistor structure, and the resistor structure is coupled to the selector structure and the current limiting structure (ie, the structure of the 1R1D1S or the 1D1S1R). ), instead of the traditional resistive random access memory structure (a transistor connected to a resistor structure, that is, the structure of 1T1R), the component accumulation can be improved.
本發明的電阻式隨機存取記憶體具有選擇器結構,選擇器結構藉由導電層與選擇材料層之間可形成肖特基能障,可作為控制記憶體單元電路的開關,或選擇材料層是具有臨界電壓Vth的非晶系硫屬化合物,在偏壓V未達Vth(即0 < |V| < |Vth|)時維持電路打開,而在偏壓V超過Vth(即|V| > |Vth|)時使電路關閉。The resistive random access memory of the present invention has a selector structure. The selector structure can form a Schottky barrier between the conductive layer and the selected material layer, can be used as a switch for controlling the memory unit circuit, or select a material layer. It is an amorphous chalcogen compound having a threshold voltage Vth, which maintains the circuit open when the bias voltage V does not reach Vth (ie, 0 < |V| < |Vth|), and the bias voltage V exceeds Vth (ie, |V| >). When |Vth|) turns off the circuit.
本發明的電阻式隨機存取記憶體具有第一限流器結構,其藉由限流材料層和臨近的導電層之間可形成肖特基能障,因此在低於一反向偏壓的情況下,此能障足夠寬以限制電流,亦即可控制流經電阻結構的電流低於一飽和電流值,可避免電阻結構在SET操作過程改變電阻可能造成不可逆的損傷。The resistive random access memory of the present invention has a first current limiter structure, which can form a Schottky barrier between the current limiting material layer and the adjacent conductive layer, and thus is lower than a reverse bias In this case, the energy barrier is wide enough to limit the current, and the current flowing through the resistor structure can be controlled to be lower than a saturation current value, which can prevent irreversible damage of the resistor structure during the SET operation.
本發明的電阻式隨機存取記憶體更具有第二限流器結構,設置於電阻結構臨近第一限流器結構或選擇器結構的另一側,當記憶體單元於另一極性(polarity)操作時,可作為控制記憶體單元電路的電流量的電流限制器,亦即可控制流經電阻結構的電流低於一飽和電流值,可避免電阻結構在SET操作過程改變電阻可能造成不可逆的損傷。The resistive random access memory of the present invention further has a second current limiter structure disposed on the other side of the resistor structure adjacent to the first current limiter structure or the selector structure, when the memory unit is in another polarity In operation, it can be used as a current limiter for controlling the current amount of the memory unit circuit, and can also control the current flowing through the resistor structure to be lower than a saturation current value, thereby avoiding irreversible damage of the resistor structure during the SET operation. .
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧電阻式隨機存取記憶體
110‧‧‧記憶體單元
120‧‧‧選擇材料層
122、128‧‧‧限流材料層
124、130‧‧‧金屬層
126‧‧‧可變電阻層
140、142、144、146、148、150、152、154、156、158‧‧‧導電層
WL、WL1、WL2、WL3、WL4、WL5、WL6‧‧‧字元線
BL、BL1、BL2、BL3‧‧‧位元線
R‧‧‧電阻結構
D1、D2‧‧‧限流器結構
S‧‧‧選擇器結構100‧‧‧Resistive random access memory
110‧‧‧ memory unit
120‧‧‧Select material layer
122, 128‧‧‧Limited material layer
124, 130‧‧‧ metal layer
126‧‧‧Variable Resistance Layer
140, 142, 144, 146, 148, 150, 152, 154, 156, 158‧‧‧ conductive layers
WL, WL1, WL2, WL3, WL4, WL5, WL6‧‧‧ character lines
BL, BL1, BL2, BL3‧‧‧ bit line
R‧‧‧Resistor structure
D1, D2‧‧‧ current limiter structure
S‧‧‧ selector structure
圖1A繪示本發明的電阻式隨機存取記憶體的俯視示意圖。 圖1B繪示本發明的電阻式隨機存取記憶體的側視示意圖。 圖2A繪示本發明的第一實施例的電阻式隨機存取記憶體的記憶體單元的各結構的連結示意圖。 圖2B繪示本發明的第一實施例的電阻式隨機存取記憶體的記憶體單元的各結構的剖面示意圖。 圖3A繪示本發明的第二實施例的電阻式隨機存取記憶體的記憶體單元的各結構的連結示意圖。 圖3B繪示本發明的第二實施例的電阻式隨機存取記憶體的記憶體單元的各結構的剖面示意圖。 圖4A繪示本發明的第三實施例的電阻式隨機存取記憶體的記憶體單元的各結構的連結示意圖。 圖4B繪示本發明的第三實施例的電阻式隨機存取記憶體的記憶體單元的各結構的剖面示意圖。 圖5A繪示本發明的第四實施例的電阻式隨機存取記憶體的記憶體單元的各結構的連結示意圖。 圖5B繪示本發明的第四實施例的電阻式隨機存取記憶體的記憶體單元的各結構的剖面示意圖。1A is a top plan view of a resistive random access memory of the present invention. 1B is a side elevational view of a resistive random access memory of the present invention. 2A is a schematic diagram showing the connection of the respective structures of the memory cells of the resistive random access memory according to the first embodiment of the present invention. 2B is a cross-sectional view showing each structure of a memory cell of the resistive random access memory according to the first embodiment of the present invention. 3A is a schematic diagram showing the connection of the respective structures of the memory cell of the resistive random access memory according to the second embodiment of the present invention. 3B is a cross-sectional view showing the structure of a memory cell of the resistive random access memory according to the second embodiment of the present invention. 4A is a schematic diagram showing the connection of the respective structures of the memory cell of the resistive random access memory according to the third embodiment of the present invention. 4B is a cross-sectional view showing the structure of a memory cell of a resistive random access memory according to a third embodiment of the present invention. FIG. 5A is a schematic diagram showing the connection of the respective components of the memory cell of the resistive random access memory according to the fourth embodiment of the present invention. 5B is a cross-sectional view showing the structure of a memory cell of the resistive random access memory according to the fourth embodiment of the present invention.
R‧‧‧電阻結構 R‧‧‧Resistor structure
D1‧‧‧限流器結構 D1‧‧‧ current limiter structure
S‧‧‧選擇器結構 S‧‧‧ selector structure
Claims (16)
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