TW201723516A - Debug method executed via scan chain for scan test and related circuitry system - Google Patents
Debug method executed via scan chain for scan test and related circuitry system Download PDFInfo
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Abstract
Description
本發明係有關於一除錯方法，尤指一種透過掃描測試的一掃描鏈所執行的一除錯方法及一相關電路系統。The present invention relates to a debugging method, and more particularly to a debugging method performed by a scan chain through a scan test and a related circuit system.
於積體電路測試領域中，由於數位或類比積體電路的訊號線數量眾多，因此在連接墊(Pad)的數量控制上一直為積體電路設計的一重大考量，而除錯(debug)同時亦為積體電路測試不可忽視的一環節，傳統上，若要針對某一特定電路進行除錯，舉例來說，若於一積體電路中有一鎖相迴路(phase lock loop, PLL)所震盪之頻率與設計上有出入，需要對此頻率進行觀察時，先前技術中會使鎖相迴路所震盪產生的頻率訊號進入一除頻器再透過一連接墊輸出後由使用者觀察以進行除錯，如此一來，若是要對多個特定電路進行除錯，將會消耗大量的連接墊，造成生產成本的增加。In the field of integrated circuit testing, due to the large number of signal lines of digital or analog integrated circuits, the control of the number of pads has always been a major consideration in the design of integrated circuits, while debugging is simultaneous. It is also a part of the integrated circuit test that can not be ignored. Traditionally, if you want to debug a specific circuit, for example, if there is a phase lock loop (PLL) in an integrated circuit, it will oscillate. There is a discrepancy between the frequency and the design. When the frequency needs to be observed, the frequency signal generated by the oscillation of the phase-locked loop enters a frequency divider and is output through a connection pad and is then viewed by the user for debugging. In this way, if a plurality of specific circuits are to be debugged, a large number of connection pads will be consumed, resulting in an increase in production cost.
本發明的目的之一在於提供一種透過掃描測試的一掃描鏈所執行的一除錯方法以及一相關電路系統。One of the objects of the present invention is to provide a debug method and a related circuitry that are performed by a scan chain of a scan test.
根據本發明一實施例，揭露一種電路除錯方法，其中該方法包含:利用一除錯電路判斷一特定電路的一操作狀態並產生一判斷結果；透過一掃描鏈(scan chain)路徑上的一暫存器儲存該判斷結果，其中該掃描鏈路徑係用以執行一掃描測試(scan test)；以及透過該掃描鏈路徑上的一輸出連接墊(Pad)來輸出該判斷結果，其中該判斷結果係用來被觀察以對該特定電路進行除錯。According to an embodiment of the invention, a circuit debugging method is disclosed, wherein the method comprises: determining a certain operating state of a specific circuit by using a debugging circuit and generating a determination result; transmitting a path on a scan chain path The temporary storage unit stores the determination result, wherein the scan chain path is used to perform a scan test; and outputting the determination result through an output connection pad (Pad) on the scan chain path, wherein the determination result is Used to be observed to debug a particular circuit.
根據本發明一實施例，揭露一種電路除錯系統，其中該系統包含:一特定電路、一除錯電路、一暫存器以及一輸出連接墊。該除錯電路係用以判斷該特定電路的一操作狀態並產生一判斷結果；該暫存器係用以儲存該判斷結果，其中該暫存器位於用以執行一掃描測試(scan test)的一掃描鏈(Scan chain)路徑上；而該連接墊(pad)係用以輸出該判斷結果，其中該連接墊包含於該掃描測試中，且該判斷結果係用來被觀察以對該特定電路進行除錯。According to an embodiment of the invention, a circuit debugging system is disclosed, wherein the system comprises: a specific circuit, a debugging circuit, a register, and an output connection pad. The debug circuit is configured to determine an operational state of the particular circuit and generate a determination result; the temporary register is configured to store the determination result, wherein the temporary register is located to perform a scan test a scan chain (path); and the connection pad is used to output the determination result, wherein the connection pad is included in the scan test, and the determination result is used to be observed to the specific circuit Troubleshoot.
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有通常知識者應可理解，硬體製造商可能會用不同的名詞來稱呼同一個元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。此外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段，因此，若文中描述一第一裝置耦接於一第二裝置，則代表該第一裝置可直接電氣連接於該第二裝置，或者透過其他裝置或連接手段間接地電氣連接至該第二裝置。Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection means. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the device. The second device is indirectly electrically connected to the second device through other devices or connection means.
第1圖係根據先前技術的掃描測試(scan test)區塊100的示意圖，如第1圖所示，一傳統掃描測試區塊100中包含組合電路111、112與113，多工器121、122與123以及暫存器131與132，其中組合電路111、112與113並不限制於任何種類的數位或類比電路，暫存器131與132同樣不限制其電路種類，可以是D型正反器(D Flip Flop)或T型正反器等，而第1圖中所示的每一箭頭並不僅代表一個訊號，可以是一個或多個訊號，例如組合電路111輸出兩個輸出訊號至多工器121，在掃描測試領域中具有通常知識者應能輕易理解這些電路實現方式，本發明應著重於除錯方法，因此關於掃描測試區塊100中的電路的細節將在此省略以省篇幅。傳統上，控制訊號CS控制多工器121、122與123操作於移入(shift-in)、捕捉(capture)以及移出(shift-out)模式，當多工器121、122與123操作於移入模式時，多工器121、122與123以及暫存器131與132即形成一掃描鏈(scan chain)路徑，需注意的是，掃描測試區塊100並不代表整體掃描測試系統，可能僅為掃描測試系統中的一部分，亦即，組合電路111之前可能耦接於另一掃描測試區塊的輸出端點N1，而多工器123之後可能耦接於另一掃描測試區塊輸入端點N2。1 is a schematic diagram of a scan test block 100 according to the prior art. As shown in FIG. 1, a conventional scan test block 100 includes combination circuits 111, 112, and 113, and multiplexers 121 and 122. And 123 and the registers 131 and 132, wherein the combination circuits 111, 112 and 113 are not limited to any kind of digital or analog circuits, and the registers 131 and 132 also do not limit the types of circuits, and may be D-type flip-flops. (D Flip Flop) or T-type flip-flop, etc., and each arrow shown in FIG. 1 does not only represent one signal, but may be one or more signals, for example, the combination circuit 111 outputs two output signals to the multiplexer. 121. Those having ordinary knowledge in the field of scanning testing should be able to easily understand these circuit implementations. The present invention should focus on the debugging method, and thus details regarding the circuits in the scanning test block 100 will be omitted here to save space. Conventionally, the control signal CS controls the multiplexers 121, 122, and 123 to operate in a shift-in, capture, and shift-out mode when the multiplexers 121, 122, and 123 operate in the shift-in mode. At the same time, the multiplexers 121, 122 and 123 and the registers 131 and 132 form a scan chain path. It should be noted that the scan test block 100 does not represent the overall scan test system, and may only be a scan. A portion of the test system, that is, the combination circuit 111 may be previously coupled to the output terminal N1 of another scan test block, and the multiplexer 123 may be coupled to another scan test block input terminal N2.
第2圖係根據本發明一實施例之電路除錯系統200示意圖，如第2圖所示，電路除錯系統200包含一掃描測試區塊210、一待以除錯的特定電路201以及一除錯電路202，其中掃描測試區塊210除了包含了第1圖所示之掃描測試區塊100的元件之外，另包含了一除錯多工器203；特定電路201為一鎖相迴路(Phase Lock Loop, PLL)電路，然而，在其他實施例中特定電路201可以是一靜態隨機存取記憶體(Static Random Access Memory, SRAM)、一低壓差線性穩壓器(Low Dropout Linear Regulator, LDO)或一快閃記憶體(flash memory)，亦即，特定電路201的電路架構並非本發明的一限制。除錯電路202係用以偵測特定電路201的一操作狀態OS並產生一判斷結果DR，舉例來說，當特定電路201為一鎖相迴路時，操作狀態OS可以是特定電路201所震盪產生的一頻率，而除錯電路202接收該頻率後判斷該頻率是否與設計相符，並產生判斷結果DR，其中判斷結果DR為一邏輯值，若判斷結果DR為邏輯值1，則代表頻率正確，若判斷結果DR為邏輯值0，則代表頻率錯誤；以另一例子而言，操作狀態OS可以是鎖相迴路的抖動(Jitter)，而除錯電路202接收抖動資訊後判斷該抖動的解析度是否大於一預設值，若是則產生判斷結果DR為邏輯值1，否則產生判斷結果DR為邏輯值0；需注意的是，除錯電路202所產生的判斷結果DR並非限制為單一位元的邏輯值，亦可為多個位元的邏輯值，舉例來說，判斷結果DR可以為00、01、10及11，而各種邏輯值代表著特定電路201的不同操作狀態，例如，00為工作週期錯誤，01為頻率錯誤等等，這些設計上的變化皆應隸屬於本發明的範疇。除錯多工器203係用以接收判斷結果DR，並且透過一除錯控制訊號DRS控制除錯多工器203操作於一除錯模式，當操作於該除錯模式時，除錯多工器203將判斷結果DR存入暫存器132中，接著，當多工器121、122與123操作於移出模式時，將判斷結果DR自暫存器132中傳送至後方的輸出連接墊(Pad)(並未顯示於第2圖中)，供使用者於測試機台上可直接觀察判斷結果DR以便進行除錯。需注意的是，當除錯多工器203並非操作於除錯模式時，將與多工器121、122與123同步進行操作，亦即，除錯多工器並不影響正常掃描測試的操作，當多工器121、122與123操作於移入模式時，除錯多工器203同樣將多工器122的輸出訊號傳送至暫存器132中。2 is a schematic diagram of a circuit debugging system 200 according to an embodiment of the present invention. As shown in FIG. 2, the circuit debugging system 200 includes a scan test block 210, a specific circuit 201 to be debugged, and a The error circuit 202, wherein the scan test block 210 includes a debug multiplexer 203 in addition to the component of the scan test block 100 shown in FIG. 1; the specific circuit 201 is a phase-locked loop (Phase) The Lock Loop, PLL) circuit, however, in other embodiments the specific circuit 201 can be a Static Random Access Memory (SRAM), a Low Dropout Linear Regulator (LDO). Or a flash memory, that is, the circuit architecture of the specific circuit 201 is not a limitation of the present invention. The debugging circuit 202 is configured to detect an operating state OS of the specific circuit 201 and generate a determination result DR. For example, when the specific circuit 201 is a phase locked loop, the operating state OS may be generated by the specific circuit 201. a frequency, and the debugging circuit 202 determines whether the frequency is consistent with the design, and generates a judgment result DR, wherein the judgment result DR is a logical value, and if the judgment result DR is a logical value 1, the representative frequency is correct. If the judgment result DR is a logic value of 0, it represents a frequency error; for another example, the operation state OS may be a jitter of a phase-locked loop, and the debug circuit 202 determines the jitter resolution after receiving the jitter information. Whether it is greater than a preset value, if yes, the judgment result DR is a logical value of 1, otherwise the judgment result DR is a logical value 0; it should be noted that the judgment result DR generated by the debug circuit 202 is not limited to a single bit. The logical value may also be a logical value of a plurality of bits. For example, the determination result DR may be 00, 01, 10, and 11, and various logical values represent different operational states of the specific circuit 201, for example, 00 is a duty cycle error, frequency error is 01 and so on, these are changes in the design should belong to the scope of the invention. The debug multiplexer 203 is configured to receive the determination result DR, and control the debug multiplexer 203 to operate in a debug mode through a debug control signal DRS. When operating in the debug mode, the debug multiplexer 203 stores the determination result DR in the temporary storage unit 132. Then, when the multiplexers 121, 122, and 123 operate in the removal mode, the determination result DR is transmitted from the temporary storage unit 132 to the rear output connection pad (Pad). (Not shown in Figure 2), for the user to directly observe the judgment result DR on the test machine for debugging. It should be noted that when the debug multiplexer 203 is not operating in the debug mode, it will operate synchronously with the multiplexers 121, 122, and 123, that is, the debug multiplexer does not affect the operation of the normal scan test. When the multiplexers 121, 122, and 123 operate in the shift-in mode, the debug multiplexer 203 also transmits the output signal of the multiplexer 122 to the register 132.
第3圖係根據本發明另一實施例之電路除錯系統300示意圖，如第3圖所示，電路除錯系統300包含一掃描測試區塊310、特定電路301、除錯電路302，其中掃描測試區塊310除了包含了第1圖所示之掃描測試區塊100的元件之外，另包含了除錯多工器303以及一暫存器304，其中特定電路301、除錯電路302以及除錯多工器303的目的及功能與第2圖實施例所描述相同，其細節在此省略，第3圖實施例與第2圖實施例的不同之處在於，第3圖實施例的掃描鏈的路徑上使用除錯多工器303與暫存器304儲存判斷結果DR，其中除錯多工器303與暫存器304並非原先掃描測試系統的一部分，亦即，除錯多工器303與暫存器304並不影響任何組合電路，僅僅為儲存並傳遞判斷結果DR所用，與第2圖實施例中的共享掃描鏈路徑上的一暫存器不同。在閱讀上述實施例後，本領域具通常知識者應能輕易理解第3圖所示的實施例的詳細操作，因此詳細說明在此省略。3 is a schematic diagram of a circuit debugging system 300 according to another embodiment of the present invention. As shown in FIG. 3, the circuit debugging system 300 includes a scan test block 310, a specific circuit 301, and a debug circuit 302. The test block 310 includes, in addition to the components of the scan test block 100 shown in FIG. 1, a debug multiplexer 303 and a register 304, wherein the specific circuit 301, the debug circuit 302, and the The purpose and function of the multiplexer 303 are the same as those described in the embodiment of Fig. 2. The details are omitted here. The difference between the embodiment of Fig. 3 and the embodiment of Fig. 2 is that the scan chain of the embodiment of Fig. 3 The debug multiplexer 303 and the scratchpad 304 store the determination result DR on the path, wherein the debug multiplexer 303 and the temporary register 304 are not part of the original scan test system, that is, the debug multiplexer 303 and The register 304 does not affect any combination circuit, but is used only for storing and transmitting the determination result DR, which is different from a register on the shared scan chain path in the embodiment of FIG. After reading the above embodiments, those skilled in the art should be able to easily understand the detailed operation of the embodiment shown in FIG. 3, and thus the detailed description is omitted here.
第4圖係根據本發明一實施例之應用電路除錯系統400的測試環境示意圖，如第4圖所示，掃描測試系統410中可包含多個掃描測試區塊(圖中虛線所示)，例如掃描測試區塊210或310，除錯電路402判斷特定電路401的操作狀態DR後，將判斷結果DR傳送至包含於掃描測試區塊中的除錯多工器(未顯示於第4圖中)，在本實施例中，除錯多工器可以將判斷結果DR傳送至如第3圖所示的一專屬暫存器，亦或是如第2圖所示的原掃描路徑上的一暫存器中，之後透過移出模式，將判斷結果DR輸出至耦接於一測試設備430的輸出連接墊420，再由使用者透過測試設備430觀察判斷結果DR以進行除錯。需注意的是，一掃描測試系統並非僅能用於觀察單一特定電路的操作狀態來進行除錯，第5圖係根據本發明一實施例之應用電路除錯系統500的測試環境示意圖，如第5圖所示，一掃描測試系統510可以觀察多個特定電路(於此實施例中為特定電路501與503)的操作狀態，而後經由相對應的除錯電路(於此實施例中為特定電路502與504)將各自的判斷結果DR1與DR2傳送至掃描測試區塊511、512中，並透過上述實施例的操作將判斷結果DR1與DR2輸出至一輸出連接墊520，其中輸出連接墊520耦接至一測試設備530，再由使用者透過測試設備530觀察判斷結果DR1與DR2以對特定電路501與503進行除錯。4 is a schematic diagram of a test environment of an application circuit debug system 400 according to an embodiment of the present invention. As shown in FIG. 4, the scan test system 410 may include a plurality of scan test blocks (shown by dashed lines in the figure). For example, after scanning the test block 210 or 310, the debug circuit 402 determines the operation state DR of the specific circuit 401, and transmits the determination result DR to the debug multiplexer included in the scan test block (not shown in FIG. 4). In this embodiment, the debug multiplexer can transmit the determination result DR to a dedicated register as shown in FIG. 3, or a temporary on the original scan path as shown in FIG. In the memory, the determination result DR is outputted to the output connection pad 420 of the test device 430 through the removal mode, and then the user observes the determination result DR through the test device 430 to perform debugging. It should be noted that a scan test system is not only capable of observing the operation state of a single specific circuit for debugging. FIG. 5 is a schematic diagram of a test environment of the application circuit debug system 500 according to an embodiment of the present invention, such as As shown in FIG. 5, a scan test system 510 can observe the operational states of a plurality of specific circuits (specific circuits 501 and 503 in this embodiment) and then via corresponding debug circuits (specific circuits in this embodiment). 502 and 504) transmitting the respective determination results DR1 and DR2 to the scan test blocks 511, 512, and outputting the determination results DR1 and DR2 to an output connection pad 520 through the operation of the above embodiment, wherein the output connection pad 520 is coupled. Connected to a test device 530, the user then observes the determination results DR1 and DR2 through the test device 530 to debug the specific circuits 501 and 503.
簡單歸納本發明，本發明提出一電路除錯系統與方法，透過掃描路徑中的掃描鏈輸出特定電路的操作狀態以進行除錯，如此一來可省下大量輸出墊以節省製造成本。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。In summary, the present invention provides a circuit debugging system and method for outputting a specific circuit operating state through a scan chain in a scan path for debugging, thereby saving a large number of output pads to save manufacturing costs. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
111、112、113‧‧‧組合電路
121、122、123‧‧‧多工器
131、132、304‧‧‧暫存器
N1、N2‧‧‧端點
100、210、310、511、512‧‧‧掃描測試區塊
CS‧‧‧控制訊號
201、301、401、501、503‧‧‧特定電路
202、302、402、502、504‧‧‧除錯電路
203、303‧‧‧除錯多工器
DR‧‧‧判斷結果
DRS‧‧‧除錯控制訊號
200、300‧‧‧電路除錯系統
400、500‧‧‧測試環境
410、510‧‧‧掃描測試系統
420、520‧‧‧輸出連接墊
430、530‧‧‧測試設備111, 112, 113‧‧‧ combination circuit
121, 122, 123‧‧‧ multiplexers
131, 132, 304‧‧‧ register
N1, N2‧‧‧ endpoints
100, 210, 310, 511, 512‧‧‧ scan test blocks
CS‧‧‧Control signal
201, 301, 401, 501, 503‧‧‧ specific circuits
202, 302, 402, 502, 504‧‧ ‧ debugging circuit
203, 303‧‧‧Debug multiplexer
DR‧‧‧ judgment result
DRS‧‧‧Debug Control Signal
200, 300‧‧‧ circuit debugging system
400, 500‧‧‧ test environment
410, 510‧‧‧ scan test system
420, 520‧‧‧ output connection pad
430, 530‧‧‧ test equipment
第1圖係根據先前技術的掃描測試區塊的示意圖。 第2圖係根據本發明一實施例之電路除錯系統示意圖。 第3圖係根據本發明另一實施例之電路除錯系統示意圖。 第4圖係根據本發明一實施例之應用電路除錯系統的測試環境示意圖。 第5圖係根據本發明另一實施例之應用電路除錯系統的測試環境示意圖。Figure 1 is a schematic diagram of a scan test block according to the prior art. 2 is a schematic diagram of a circuit debug system in accordance with an embodiment of the present invention. Figure 3 is a schematic diagram of a circuit debug system in accordance with another embodiment of the present invention. 4 is a schematic diagram of a test environment of an application circuit debug system according to an embodiment of the present invention. Figure 5 is a schematic diagram of a test environment of an application circuit debug system in accordance with another embodiment of the present invention.
111、112、113‧‧‧組合電路 111, 112, 113‧‧‧ combination circuit
121、122、123‧‧‧多工器 121, 122, 123‧‧‧ multiplexers
131、132‧‧‧暫存器 131, 132‧‧‧ register
N1、N2‧‧‧端點 N1, N2‧‧‧ endpoints
100‧‧‧掃描測試區塊 100‧‧‧Scan test block
CS‧‧‧控制訊號 CS‧‧‧Control signal
201‧‧‧特定電路 201‧‧‧Specific circuit
202‧‧‧除錯電路 202‧‧‧Debug circuit
203‧‧‧除錯多工器 203‧‧‧Debug multiplexer
DR‧‧‧判斷結果 DR‧‧‧ judgment result
DRS‧‧‧除錯控制訊號 DRS‧‧‧Debug Control Signal
200‧‧‧電路除錯系統 200‧‧‧Circuit debugging system
Claims (10)
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| US15/385,841 US10234503B2 (en) | 2015-12-21 | 2016-12-20 | Debugging method executed via scan chain for scan test and related circuitry system |
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| US201562270542P | 2015-12-21 | 2015-12-21 | |
| US62/270,542 | 2015-12-21 |
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| CN109725245B (en) * | 2017-10-30 | 2021-10-08 | 瑞昱半导体股份有限公司 | Integrated circuit testing device |
| CN111103531B (en) * | 2018-10-26 | 2022-11-01 | 瑞昱半导体股份有限公司 | Chip and method for manufacturing the same |
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| US5663991A (en) * | 1996-03-08 | 1997-09-02 | International Business Machines Corporation | Integrated circuit chip having built-in self measurement for PLL jitter and phase error |
| CA2220622C (en) * | 1997-11-03 | 2004-03-30 | Aubin P. J. Roy | Method and circuit for built in self test of phase locked loops |
| US6294935B1 (en) * | 2000-10-17 | 2001-09-25 | Vlsi Technology, Inc. | Built-in-self-test circuitry for testing a phase locked loop circuit |
| US7191373B2 (en) * | 2001-03-01 | 2007-03-13 | Syntest Technologies, Inc. | Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques |
| US7249298B2 (en) * | 2002-04-30 | 2007-07-24 | Samsung Electronics Co., Ltd. | Multiple scan chains with pin sharing |
| US7197680B2 (en) * | 2003-04-17 | 2007-03-27 | Arm Limited | Communication interface for diagnostic circuits of an integrated circuit |
| EP1475891B1 (en) * | 2003-05-07 | 2006-03-15 | STMicroelectronics S.r.l. | Built-in self-test circuit for phase locked loops, test method and computer program product therefore |
| SG146654A1 (en) * | 2003-09-15 | 2008-10-30 | Nvidia Corp | A system and method for testing and configuring semiconductor functional circuits |
| US7793179B2 (en) * | 2006-06-27 | 2010-09-07 | Silicon Image, Inc. | Test clock control structures to generate configurable test clocks for scan-based testing of electronic circuits using programmable test clock controllers |
| CN100495989C (en) * | 2006-07-07 | 2009-06-03 | 中国科学院计算技术研究所 | A test shell circuit and its design method |
| CN101420417B (en) * | 2007-10-26 | 2012-08-29 | 瑞昱半导体股份有限公司 | Digital content scanning circuit and scanning method thereof |
| CN101551439B (en) * | 2009-02-24 | 2012-02-29 | 北京时代民芯科技有限公司 | Built-in self-testing method of FPGA input/output module |
| CN101762783B (en) * | 2010-01-18 | 2011-12-21 | 山东华芯半导体有限公司 | Method for reading out effective error information of on-chip test circuit |
| CN102200426B (en) * | 2011-03-23 | 2012-06-27 | 南京艾驰电子科技有限公司 | Hall encoder-based travel sensor and travel measurement method thereof |
| CN103137212A (en) * | 2011-12-05 | 2013-06-05 | 北大方正集团有限公司 | Synchronous dynamic random access memory (SDRAM) testing method |
| CN103809104B (en) * | 2012-11-09 | 2017-03-01 | 瑞昱半导体股份有限公司 | Scanning clock pulse generator and scanning clock pulse generation methods |
| US20150039956A1 (en) * | 2013-07-30 | 2015-02-05 | Stmicroelectronics Asia Pacific Pte. Ltd. | Test mux flip-flop cell for reduced scan shift and functional switching power consumption |
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| TWI625534B (en) | 2018-06-01 |
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