TW201721882A - Structure of MIM capacitor and the method for fabricating the same - Google Patents
Structure of MIM capacitor and the method for fabricating the same Download PDFInfo
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Abstract
Description
本發明係關於一種電容，特別係一種具有金屬-絕緣層-金屬(Metal-Insulator-Metal：MIM)電容之半導體元件。 The present invention relates to a capacitor, and more particularly to a semiconductor component having a metal-insulator-metal (MIM) capacitor.
近年來，隨著半導體積體電路之製程技術的發達，於半導體基板上所製造之元件的最小線寬已逐漸細微化，並且單位面積的積體電路密度亦隨之變高。然而，由於記憶單元積體電路密度的提高，電荷儲存用的單元電容可佔有空間將變得更小，因此必須開發平均單位面積的靜電電容增加之單元電容。 In recent years, with the development of process technology for semiconductor integrated circuits, the minimum line width of components fabricated on semiconductor substrates has been gradually miniaturized, and the density of integrated circuits per unit area has also become higher. However, since the density of the integrated circuit of the memory cell is increased, the space occupied by the cell for charge storage becomes smaller, and therefore it is necessary to develop a cell capacitance with an increased capacitance per unit area.
半導體元件之密集度變得愈高時，晶胞尺寸和操作電壓就會降低。因而，元件更新時間往往會縮短，而且經常發生軟性錯誤。為了克服這些限制，需要開發一種每個單晶胞具有更高之電容值，以及可降低漏電流之電容。 As the concentration of the semiconductor element becomes higher, the cell size and the operating voltage are lowered. As a result, component update times tend to be shorter, and soft errors often occur. In order to overcome these limitations, it is necessary to develop a capacitance having a higher capacitance value per single cell and a leakage current.
一般而言，在高度密集之下，使用Si3N4當作介電材料之氮化物和氧化物(NO)結構，其所形成的電容並不利於電容性。因欠缺足夠的面積以獲致所需要的電容。另一例子，利用金屬-絕緣-金屬(metal-insulator-metal,MIM)型電容結構則可得到足夠的電容，此為MIM電容優點之一。 In general, under high density, Si 3 N 4 is used as a nitride and oxide (NO) structure of a dielectric material, and the capacitance formed thereof is not favorable for capacitance. Due to the lack of sufficient area to obtain the required capacitance. As another example, a metal-insulator-metal (MIM) type capacitor structure can be used to obtain sufficient capacitance, which is one of the advantages of the MIM capacitor.
其次，在半導體積體電路中，許多的混合信號電路及高頻電路中，常需要使用到高效能及高速度的元件，例如電容或電感。這些元件須具備低串聯電阻、低耗損、高Q值及低電容/電阻時間常數等特性。一般而言，在半導體積體電路中所使用之電容，包含金屬-絕緣-矽(metal-insulator-silicon,MIS)電容或金屬-絕緣-金屬(MIM)電容。在MIS電容之中，由於以矽作為下電極，產生的寄生電阻值較高而只適用於低頻電路。在MIM電容之中，上、下電極都是以金屬作為電極，可降低寄生電阻值而提高元件之共振頻率，是高頻電路中常使用之元件。另外，於製造高頻元件結構時，需能相容於CMOS製程以使製程之整合得以簡化。 Secondly, in semiconductor integrated circuits, many mixed-signal circuits and high-frequency circuits often require high-performance and high-speed components such as capacitors or inductors. These components must have low series resistance, low loss, high Q and low capacitance/resistance time constant. In general, the capacitor used in a semiconductor integrated circuit includes a metal-insulator-silicon (MIS) capacitor or a metal-insulator-metal (MIM) capacitor. Among the MIS capacitors, since 矽 is used as the lower electrode, the parasitic resistance value generated is high and is only applicable to the low frequency circuit. Among the MIM capacitors, the upper and lower electrodes are made of metal as an electrode, which can reduce the parasitic resistance value and increase the resonance frequency of the element, and is a component commonly used in high-frequency circuits. In addition, in the fabrication of high frequency device structures, it is necessary to be compatible with CMOS processes to simplify the integration of the process.
傳統上，MIM電容係形成於第一層金屬內連線(interconnect)之下 方。不幸地，由於會使前段(front-end)與後段(back-end)製程條件發生不匹配而造成製程整合上的困難，近來大多建議將MIM電容設置於多層金屬內連線結構中。當線寬尺寸縮小到一定程度時，元件速度不再只取決於閘極信號的延遲，而將由內連線系統的信號延遲所主宰。為了降低內連線系統的信號延遲時間，在導線方面已廣泛地以金屬銅來取代鋁，而另一方面是利用具有低介電值(Low-K，低K)的絕緣材料(k<3.0)以作為金屬導線間的介電絕緣層(IMD)，來取代傳統所使用的二氧化矽，以降低電容方面的延遲。亦即，在進行後段銅製程時，MIM電容製作在金屬導線間的介電層(inter-metal dielectric,IMD)中。 Traditionally, MIM capacitors have been formed under the first layer of metal interconnects. square. Unfortunately, due to the mismatch between the front-end and back-end process conditions, the integration of the process is difficult. Recently, it has been proposed to set the MIM capacitor in the multilayer metal interconnect structure. When the linewidth size is reduced to a certain extent, the component speed is no longer solely dependent on the delay of the gate signal, but will be dominated by the signal delay of the interconnect system. In order to reduce the signal delay time of the interconnect system, aluminum has been widely used for the replacement of aluminum in terms of wires, and on the other hand, an insulating material having a low dielectric value (Low-K, low K) is utilized (k<3.0). It replaces the conventionally used cerium oxide as a dielectric insulating layer (IMD) between metal wires to reduce the delay in capacitance. That is, in the latter stage copper process, the MIM capacitor is fabricated in an inter-metal dielectric (IMD) between the metal wires.
第一圖顯示習知技術之半導體元件之後段製程線路(back-end of line)結構之截面圖。在後段製程線路結構之中，包括第一金屬層100、絕緣層101與第二金屬層102所組成的金屬-絕緣層-金屬(MIM)電容結構。其中絕緣層101形成於第一金屬層100與第二金屬層102之間，而絕緣層101與第二金屬層102之線寬約略相同。其中絕緣層101為單一層的介電材料所形成。圖案化絕緣層101與第二金屬層102係透過一蝕刻製程所完成，而由於蝕刻製程的關係，絕緣層101之側邊101a接近底部的部分容易形成一切面(undercut)的情況，因此造成絕緣層101之側邊101a的部分容易發生接面尖峰(spiking)現象而形成漏電流，結果影響了元件的性能。金屬導線間介電層104覆蓋且封閉了整個MIM電容結構。然後，導孔(via)103a與103b形成於金屬導線間介電層104之中，其中導孔103a與103b分別電性連接第一金屬層100與第二金屬層102。金屬導線105則形成於金屬導線間介電層104之上並且電性連接導孔103a與103b。 The first figure shows a cross-sectional view of a back-end of line structure of a semiconductor component of the prior art. In the back-end process line structure, a metal-insulator-metal (MIM) capacitor structure composed of the first metal layer 100, the insulating layer 101 and the second metal layer 102 is included. The insulating layer 101 is formed between the first metal layer 100 and the second metal layer 102, and the line width of the insulating layer 101 and the second metal layer 102 is about the same. The insulating layer 101 is formed of a single layer of dielectric material. The patterned insulating layer 101 and the second metal layer 102 are completed by an etching process, and due to the etching process, the portion of the side 101a of the insulating layer 101 near the bottom is likely to form an undercut, thereby causing insulation. A portion of the side 101a of the layer 101 is liable to cause a spiking phenomenon to form a leakage current, and as a result, the performance of the element is affected. The inter-metal inter-layer dielectric layer 104 covers and encloses the entire MIM capacitor structure. Then, vias 103a and 103b are formed in the inter-metal inter-layer dielectric layer 104, wherein the via holes 103a and 103b are electrically connected to the first metal layer 100 and the second metal layer 102, respectively. The metal wires 105 are formed over the inter-metal inter-layer dielectric layer 104 and electrically connected to the via holes 103a and 103b.
鑒於上述在習知MIM電容結構中，漏電流在部分情形中產生，甚至在電晶體已關閉時。當漏電流產生時，例如在邏輯電路中等待輸出訊號之電壓值維持在特定範圍內的情形中，輸出訊號的值變動且因此可能發生誤判。因此，基於傳統的MIM電容結構不佳所造成漏電流的情形，本發明提供一新的MIM電容結構以改善此問題。 In view of the above, in the conventional MIM capacitor structure, leakage current is generated in some cases even when the transistor is turned off. When a leakage current is generated, for example, in a case where the voltage value of the output signal is maintained within a specific range in the logic circuit, the value of the output signal fluctuates and thus a misjudgment may occur. Therefore, the present invention provides a new MIM capacitor structure to improve this problem based on the leakage current caused by the poor structure of the conventional MIM capacitor.
本發明提供一種半導體元件。此半導體元件包含MIM電容，其中該MIM電容包括第一電極層、第二電極層以及倒T型介電層堆疊結構。其中倒T型介電層堆疊結構形成於第一電極層與第二電極層之間。 The present invention provides a semiconductor element. The semiconductor component includes a MIM capacitor, wherein the MIM capacitor includes a first electrode layer, a second electrode layer, and an inverted T-type dielectric layer stack structure. The inverted T-type dielectric layer stack structure is formed between the first electrode layer and the second electrode layer.
本發明之一目的係降低半導體元件之漏電流，且另一目的係使半 導體元件之漏電流降低至使得邏輯電路的故障可受抑制。半導體元件包含邏輯元件。 One of the objects of the present invention is to reduce the leakage current of a semiconductor element, and another purpose is to make the half The leakage current of the conductor element is reduced such that the failure of the logic circuit can be suppressed. The semiconductor component includes a logic component.
根據本發明之一觀點，其中倒T型介電層堆疊結構包括垂直部及水平部連接該垂直部，其中另一介電層圖案(蝕刻終止層)形成於該垂直部與水平部之間，以形成該倒T型介電層堆疊結構。 According to an aspect of the invention, an inverted T-type dielectric layer stack structure includes a vertical portion and a horizontal portion connected to the vertical portion, wherein another dielectric layer pattern (etch stop layer) is formed between the vertical portion and the horizontal portion, To form the inverted T-type dielectric layer stack structure.
根據本發明之另一觀點，其中水平部與蝕刻終止層之線寬大小約略相等，並且大於垂直部之線寬大小。其中垂直部之線寬大小與第一電極層之線寬大小約略相等。 According to another aspect of the present invention, the line width of the horizontal portion and the etch stop layer is approximately equal to each other and larger than the line width of the vertical portion. The line width of the vertical portion is approximately equal to the line width of the first electrode layer.
根據本發明之一觀點，一種形成MIM電容之方法，包含；首先，形成一MIM薄膜層於一底層之上，其中該MIM薄膜層包括一底層金屬層、一介電層堆疊層與一上層金屬層，該介電層堆疊層形成於底層金屬層與上層金屬層之間，該介電層堆疊層至少包含三層介電層，包含第一介電層、第二介電層以及第三介電層；然後，圖案化第三介電層以及上層金屬層，以形成一垂直部與一上電極圖案；之後，圖案化第一介電層、第二介電層以及底層金屬層，以形成一水平堆疊層圖案與一下電極圖案；其中垂直部與水平堆疊層圖案構成一倒T型介電層堆疊結構。 According to one aspect of the present invention, a method of forming a MIM capacitor includes: first, forming a MIM film layer on a bottom layer, wherein the MIM film layer includes an underlying metal layer, a dielectric layer stack layer, and an upper metal layer a dielectric layer stack layer is formed between the underlying metal layer and the upper metal layer, the dielectric layer stack layer comprising at least three dielectric layers, including a first dielectric layer, a second dielectric layer, and a third dielectric layer Electrical layer; then, patterning the third dielectric layer and the upper metal layer to form a vertical portion and an upper electrode pattern; thereafter, patterning the first dielectric layer, the second dielectric layer, and the underlying metal layer to form A horizontally stacked layer pattern and a lower electrode pattern; wherein the vertical portion and the horizontal stacked layer pattern form an inverted T-type dielectric layer stack structure.
根據本發明之又一觀點，半導體元件更包括一金屬導線間介電層以覆蓋MIM電容。 According to still another aspect of the present invention, the semiconductor device further includes a metal inter-wire dielectric layer to cover the MIM capacitor.
根據本發明之一觀點，半導體元件更包括複數個通孔，形成於金屬導線間介電層之中，其中該複數個通孔包括二類：第一類通孔係為從金屬導線間介電層之上表面至第一電極層之上表面，第二類通孔係為從金屬導線間介電層之上表面、貫穿水平部而至第二電極層之上表面。 According to one aspect of the present invention, the semiconductor device further includes a plurality of via holes formed in the dielectric layer between the metal wires, wherein the plurality of via holes comprise two types: the first type of via holes are dielectric between the metal wires. The upper surface of the layer is to the upper surface of the first electrode layer, and the second type of via hole is from the upper surface of the dielectric layer between the metal wires, through the horizontal portion to the upper surface of the second electrode layer.
根據本發明之再一觀點，其中該些通孔之中填入導電材料，以分別於第一類通孔與第二類通孔之中形成第一導孔與第二導孔，其中第一導孔與第二導孔分別電性耦合第一電極層與第二電極層。 According to still another aspect of the present invention, the through holes are filled with a conductive material to form a first via hole and a second via hole among the first type of via holes and the second type of via holes, respectively. The via hole and the second via hole are electrically coupled to the first electrode layer and the second electrode layer, respectively.
根據本發明之又一觀點，其中第二導孔之厚度約略等於第一導孔之厚度加上第一電極層以及倒T型介電層堆疊結構之厚度。 According to still another aspect of the present invention, the thickness of the second via hole is approximately equal to the thickness of the first via hole plus the thickness of the first electrode layer and the inverted T-type dielectric layer stack structure.
根據本發明之另一觀點，複數個通孔包括二類：第一類通孔係為從金屬導線間介電層之上表面至第一電極層之上表面，第二類通孔係為從金屬導線間介電層之上表面貫穿至其下表面。第一導孔與第二導孔分別形成與連接 於第一電極層與金屬導線間介電層之上。第二導孔之厚度約略等於第一導孔之厚度加上第一電極層、倒T型介電層堆疊結構與第二電極層之厚度。 According to another aspect of the present invention, the plurality of vias comprise two types: the first type of via is from the upper surface of the dielectric layer between the metal wires to the upper surface of the first electrode layer, and the second type of via is The upper surface of the dielectric layer between the metal wires penetrates to the lower surface thereof. Forming and connecting the first guiding hole and the second guiding hole respectively Above the dielectric layer between the first electrode layer and the metal wire. The thickness of the second via hole is approximately equal to the thickness of the first via hole plus the thickness of the first electrode layer, the inverted T-type dielectric layer stack structure and the second electrode layer.
根據本發明之另一觀點，半導體元件更包括金屬導線形成於金屬導線間介電層、第一導孔與第二導孔之上，其中金屬導線電性耦合第一導孔與第二導孔。 According to another aspect of the present invention, the semiconductor device further includes a metal wire formed on the dielectric layer between the metal wires, the first via hole and the second via hole, wherein the metal wire electrically couples the first via hole and the second via hole .
此些優點及其他優點從以下較佳實施例之敘述及申請專利範圍將使讀者得以清楚了解本發明。 These and other advantages are apparent from the following description of the preferred embodiments and claims.
100‧‧‧第一金屬層 100‧‧‧First metal layer
101‧‧‧絕緣層 101‧‧‧Insulation
101a‧‧‧側邊 101a‧‧‧ side
102‧‧‧第二金屬層 102‧‧‧Second metal layer
103a、103b、209a、209b‧‧‧導孔 103a, 103b, 209a, 209b‧‧‧ guide holes
104、200、200a‧‧‧金屬導線間介電層 104, 200, 200a‧‧‧ dielectric layer between metal wires
105‧‧‧金屬導線 105‧‧‧Metal wire
201‧‧‧底層金屬層 201‧‧‧ underlying metal layer
201a‧‧‧下電極圖案 201a‧‧‧lower electrode pattern
202‧‧‧第一介電層 202‧‧‧First dielectric layer
202a‧‧‧水平部 202a‧‧‧Horizontal
203‧‧‧第二介電層 203‧‧‧Second dielectric layer
203a‧‧‧介電層圖案 203a‧‧‧dielectric layer pattern
204‧‧‧第三介電層 204‧‧‧ Third dielectric layer
204a‧‧‧垂直部 204a‧‧‧Vertical
205‧‧‧上層金屬層 205‧‧‧Upper metal layer
205a‧‧‧上電極圖案 205a‧‧‧Upper electrode pattern
208‧‧‧水平堆疊層圖案 208‧‧‧ horizontal stacked layer pattern
210‧‧‧金屬導線 210‧‧‧Metal wire
218‧‧‧倒T型介電層堆疊結構 218‧‧‧ inverted T-type dielectric layer stack structure
234‧‧‧介電層堆疊層 234‧‧‧ Dielectric layer stack
如下所述之對本發明的詳細描述與實施例之示意圖，應使本發明更被充分地理解；然而，應可理解此僅限於作為理解本發明應用之參考，而非限制本發明於一特定實施例之中。 The present invention will be more fully understood from the following detailed description of the embodiments of the invention, and In the example.
第一圖顯示根據習知技術之一半導體元件之後段製程線路結構之截面圖；第二圖顯示根據本發明之一實施例之半導體元件之後段線路結構之MIM薄膜層之截面圖；第三圖顯示根據本發明之一實施例之半導體元件之MIM薄膜層之第三介電層以及上層金屬層之圖案化之截面圖；第四圖顯示根據本發明之一實施例之半導體元件之倒T型介電層堆疊結構以及倒T型MIM電容結構之截面圖；第五圖顯示根據本發明之一實施例之半導體元件之金屬導線間介電層覆蓋且封閉倒T型MIM電容結構之截面圖；第六圖顯示根據本發明之一實施例之具有一倒T型MIM電容結構之半導體元件之後段製程線路結構之截面圖；第七圖顯示根據本發明之另一實施例之具有一倒T型MIM電容結構之半導體元件之後段製程線路結構之截面圖。 1 is a cross-sectional view showing a process structure of a semiconductor device in a subsequent stage according to one of the prior art; and a second view showing a cross-sectional view of a MIM film layer in a circuit structure of a semiconductor device in accordance with an embodiment of the present invention; A cross-sectional view showing a pattern of a third dielectric layer and an upper metal layer of a MIM film layer of a semiconductor device according to an embodiment of the present invention; and a fourth view showing an inverted T type of a semiconductor device according to an embodiment of the present invention A cross-sectional view of a dielectric layer stack structure and an inverted T-type MIM capacitor structure; a fifth view showing a cross-sectional view of a dielectric-layer-covered and closed inverted T-type MIM capacitor structure of a semiconductor component in accordance with an embodiment of the present invention; 6 is a cross-sectional view showing a structure of a subsequent process line of a semiconductor device having an inverted T-type MIM capacitor structure according to an embodiment of the present invention; and a seventh diagram showing an inverted T type according to another embodiment of the present invention. A cross-sectional view of a process line structure of a semiconductor component of a MIM capacitor structure.
此處本發明將針對發明具體實施例及其觀點加以詳細描述，此類描述為解釋本發明之結構或步驟流程，其係供以說明之用而非用以限制本發明之申請專利範圍。因此，除說明書中之具體實施例與較佳實施例外，本發明亦可廣泛施行於其他不同的實施例中。在下文的細節描述中，元件符號會標示在隨附的圖示中成為其中的一部份，並且以可實行該實施例之特例方式來表示、 描述。這類實施例會說明足夠的細節俾使該領域之一般技藝人士得以具以實施。閱者須瞭解到本發明中亦可利用其他的實施例，或是在不悖離所述實施例的前提下作出結構性、邏輯性、及電性上的改變。因此，下文之細節描述將不欲被視為是一種限定；反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。再者，本發明通篇說明書與隨附申請專利範圍中會使用某些詞彙來指稱特定的組成元件。該領域的技藝人士將理解到，半導體元件製造商可能會以不同的名稱來指稱一相同的元件，例如絕緣層與介電層等。 The invention is described in detail herein with reference to the particular embodiments of the invention, and the description of the invention. Therefore, the present invention may be widely practiced in other different embodiments in addition to the specific embodiments and preferred embodiments of the specification. In the detailed description that follows, the component symbols are marked as part of the accompanying drawings, and are represented by the specific example in which the embodiment can be practiced, description. Such embodiments will be described in sufficient detail to enable those of ordinary skill in the art to practice. The reader is aware that other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the embodiments. Therefore, the following detailed description is not to be considered as a limitation; rather, the embodiments included therein are defined by the scope of the accompanying claims. Further, certain terms are used throughout the description of the invention and the scope of the appended claims to refer to the particular elements. Those skilled in the art will appreciate that semiconductor component manufacturers may refer to a different component, such as an insulating layer and a dielectric layer, under different names.
本發明提供一半導體元件之電容及其製造方法。其中電容結構為MIM電容結構形成於半導體元件之後段線路結構之中。MIM電容結構為一倒T型的MIM電容結構。倒T字型MIM電容結構包括一倒T型的介電層堆疊結構。倒T型的介電層堆疊結構係由多層介電層依次沉積並圖案化所形成，藉以改善傳統的MIM電容結構不佳所造成漏電流的情形。其中倒T型介電層堆疊結構包括水平部及垂直部，垂直部位於水平部之上。垂直部位於上電極圖案之下，水平部位於下電極圖案之上。一非常薄層介電層圖案形成於垂直部與水平部之間，其中非常薄層介電層圖案係作為垂直部之一蝕刻終止層。 The present invention provides a capacitor of a semiconductor element and a method of fabricating the same. The capacitor structure is formed by forming a MIM capacitor structure in a circuit structure behind the semiconductor component. The MIM capacitor structure is an inverted T-type MIM capacitor structure. The inverted T-shaped MIM capacitor structure includes an inverted T-type dielectric layer stack structure. The inverted T-type dielectric layer stack structure is formed by sequentially depositing and patterning a plurality of dielectric layers, thereby improving the leakage current caused by the poor structure of the conventional MIM capacitor. The inverted T-type dielectric layer stack structure includes a horizontal portion and a vertical portion, and the vertical portion is located above the horizontal portion. The vertical portion is located below the upper electrode pattern and the horizontal portion is above the lower electrode pattern. A very thin dielectric layer pattern is formed between the vertical portion and the horizontal portion, wherein a very thin dielectric layer pattern acts as an etch stop layer for one of the vertical portions.
第二圖顯示根據本發明之一實施例之半導體元件之後段線路結構之MIM薄膜層之截面圖。在一實施例中，半導體元件包括邏輯元件或邏輯電路。一般的半導體元件之整體結構包括一前段線路結構以及一後段線路結構，其中後段線路結構接著前段線路結構完成之後而接續形成於前段線路結構之上，其可以藉由一標準的半導體製程來製作。關於半導體元件之後段線路結構之形成，首先，形成一MIM薄膜層於一底層200之上。其中MIM薄膜層包括一底層金屬層201、一介電層堆疊層234與一上層金屬層205，其中介電層堆疊層234形成於底層金屬層201與上層金屬層205之間，如第二圖所示。介電層堆疊層234形成於底層金屬層201之上，而上層金屬層205形成於介電層堆疊層234之上。舉一實施例而言，介電層堆疊層234至少包含三層介電層，分別為第一介電層202、第二介電層(蝕刻終止層)203以及第三介電層204，第二介電層203形成於第一介電層202與第三介電層204之間。第二介電層203形成於第一介電層202之上，而第三介電層204形成於第二介電層203之上。其中第二介電層203係為上層金屬層205以及第三介電層204之蝕刻終止層(etch stop layer)。 The second figure shows a cross-sectional view of a MIM film layer of a wiring structure in a subsequent stage of a semiconductor device in accordance with an embodiment of the present invention. In an embodiment, the semiconductor component comprises a logic component or a logic circuit. The general structure of a general semiconductor device includes a front-end line structure and a back-end line structure. The back-end line structure is then formed on the front-end line structure after completion of the front-end line structure, which can be fabricated by a standard semiconductor process. Regarding the formation of the wiring structure at the rear of the semiconductor element, first, a MIM film layer is formed over a bottom layer 200. The MIM film layer includes an underlying metal layer 201, a dielectric layer stack layer 234 and an upper metal layer 205, wherein the dielectric layer stack layer 234 is formed between the underlying metal layer 201 and the upper metal layer 205, as shown in the second figure. Shown. A dielectric layer stack layer 234 is formed over the underlying metal layer 201, and an upper metal layer 205 is formed over the dielectric layer stack layer 234. In one embodiment, the dielectric layer stack layer 234 includes at least three dielectric layers, a first dielectric layer 202, a second dielectric layer (etch stop layer) 203, and a third dielectric layer 204, respectively. The second dielectric layer 203 is formed between the first dielectric layer 202 and the third dielectric layer 204. The second dielectric layer 203 is formed over the first dielectric layer 202 and the third dielectric layer 204 is formed over the second dielectric layer 203. The second dielectric layer 203 is an etch stop layer of the upper metal layer 205 and the third dielectric layer 204.
因此，上述MIM薄膜層係藉由依序沉積底層金屬層201、第一介電層202、第二介電層203、第三介電層204以及上層金屬層205於底層200之上而形成。其中第二介電層203係為蝕刻終止層，其厚度較佳為30~150奈米。在某些實施例中，底層金屬層201、第一介電層202、第三介電層204以及上層金屬層205之材料與厚度可以依照實際的應用(不同的半導體元件或其特性)所需而選擇或調整。第二介電層203之厚度遠比第一介電層202、第三介電層204之厚度來得小。 Therefore, the MIM thin film layer is formed by sequentially depositing the underlying metal layer 201, the first dielectric layer 202, the second dielectric layer 203, the third dielectric layer 204, and the upper metal layer 205 on the underlayer 200. The second dielectric layer 203 is an etch stop layer, and the thickness thereof is preferably 30 to 150 nm. In some embodiments, the material and thickness of the underlying metal layer 201, the first dielectric layer 202, the third dielectric layer 204, and the upper metal layer 205 may be as desired for the actual application (different semiconductor components or their characteristics). And choose or adjust. The thickness of the second dielectric layer 203 is much smaller than the thickness of the first dielectric layer 202 and the third dielectric layer 204.
在一個實施例中，底層200為一金屬層間介電層(IMD)。舉一實施例而言，在金屬導線間介電層(IMD)採用低介電常數的材料(k<3.0)，來取代傳統所使用的二氧化矽(k≒3.9)，以降低電容方面的延遲。舉例而言，氟化玻璃(FSG)的介電質材料，其k值介於3.7~.2.8。由於氟化玻璃與二氧化矽的物性與化性相近，因此與原本製程條件之相容性較高。在另一實施例中，金屬導線間介電層(IMD)200包括二氧化矽(SiO2)或硼磷玻璃(BPSG)。 In one embodiment, the bottom layer 200 is an inter-metal dielectric layer (IMD). For one embodiment, the dielectric layer (IMD) between the metal wires uses a low dielectric constant material (k<3.0) to replace the conventionally used cerium oxide (k≒3.9) to reduce the capacitance. delay. For example, a fluorinated glass (FSG) dielectric material has a k value between 3.7 and 2.2.8. Since the physical properties and chemical properties of fluorinated glass and cerium oxide are similar, the compatibility with the original process conditions is high. In another embodiment, the inter-metal dielectric layer (IMD) 200 includes hafnium oxide (SiO 2 ) or borophosphosilicate glass (BPSG).
在一實施例中，上層金屬層205與底層金屬層201之材料係選自鉭、氮化鉭、鈦、氮化鈦、鎢、矽化鎢、氮化鎢、銅或者鋁，或其他性質類似金屬或合金。在一實施例中，第一介電層202與第三介電層204之材料係選自二氧化矽(SiO2)或氮矽化物(Si3N4)。在一實施例中，第一介電層202與第三介電層204可以藉由化學氣相沈積(CVD)、電漿輔助化學氣相沈積(PECVD)或低壓化學氣相沉積(LPCVD)等方法以形成，例如：供應SiH4氣體、N2氣體與NH3氣體，以形成氮矽化物(Si3N4)薄膜層。在一較佳實施例中，基於與第一介電層202與第三介電層204之製程的相容性，第二介電層203之材料可以包含氮氧化矽(SiOxNy)。上述氮氧化膜之形成可以藉由化學氣相沈積(CVD)、電漿輔助化學氣相沈積(PECVD)或低壓化學氣相沉積(LPCVD)等方法以形成，例如：在一溫度範圍之下，供應SiH4氣體、NH3氣體與N2O氣體的混合氣體，以形成氮氧化矽(SiOxNy)薄膜層。在另一例子中，在氮氧化膜的形成步驟中，經由原地處理(in-situ)步驟在一溫度範圍之下，於NH3或NO氣體環境中，採用電漿使二氣化矽層表面產生氮化或氮氧化。 In an embodiment, the material of the upper metal layer 205 and the bottom metal layer 201 is selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten telluride, tungsten nitride, copper or aluminum, or other similar metals. Or alloy. In one embodiment, the materials of the first dielectric layer 202 and the third dielectric layer 204 are selected from the group consisting of cerium oxide (SiO 2 ) or nitrogen lanthanide (Si 3 N 4 ). In an embodiment, the first dielectric layer 202 and the third dielectric layer 204 may be formed by chemical vapor deposition (CVD), plasma assisted chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD). The method is to form, for example, SiH 4 gas, N 2 gas, and NH 3 gas to form a nitrogen telluride (Si 3 N 4 ) thin film layer. In a preferred embodiment, the material of the second dielectric layer 203 may comprise niobium oxynitride (SiO x N y ) based on compatibility with the processes of the first dielectric layer 202 and the third dielectric layer 204. The formation of the above nitrogen oxide film may be formed by a method such as chemical vapor deposition (CVD), plasma assisted chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD), for example, under a temperature range. A mixed gas of SiH 4 gas, NH 3 gas and N 2 O gas is supplied to form a ruthenium oxynitride (SiO x N y ) thin film layer. In another example, in the step of forming the oxynitride film, the in-situ step is performed under a temperature range, in a NH 3 or NO gas environment, and the plasma is used to make the gasified layer. The surface is nitrided or oxidized by nitrogen.
在另一實施例中，第二介電層203之材料為高介電常數(High Dielectric Constant，Hi-K)材料，例如Si3N4、Al2O3、Y2O3、La2O3、CeO2、Dy2O3、Ta2O5、Pr2O3、TiO2、HfO2、ZrO2、BaxSr1-xTiO3(BST)、SrBiTa2O9(SBT)或 PbZrxTi1-xO3。 In another embodiment, the material of the second dielectric layer 203 is a High Dielectric Constant (Hi-K) material, such as Si 3 N 4 , Al 2 O 3 , Y 2 O 3 , La 2 O. 3 , CeO 2 , Dy 2 O 3 , Ta 2 O 5 , Pr 2 O 3 , TiO 2 , HfO 2 , ZrO 2 , Ba x Sr 1-x TiO 3 (BST), SrBiTa 2 O 9 (SBT) or PbZr x Ti 1-x O 3 .
隨之請參考第三圖，在MIM薄膜層形成之後，利用微影與蝕刻製程在所述第三介電層204以及上層金屬層205上進行圖案化；亦即，進行一微影與蝕刻製程以去除蝕刻截止層上之一部分的第三介電層204以及上層金屬層205，而形成一圖案化結構。舉例而言，利用一標準的微影製程以形成一第一光阻層圖案(未圖示)。然後，以該第一光阻層圖案作為蝕刻罩幕進行一蝕刻製程，直到蝕刻進行至蝕刻終止層(第二介電層203)裸露為止，結果形成MIM電容之垂直部204a與MIM電容之上電極圖案205a。由於蝕刻終止層不會被蝕刻，因此可以精準地控制垂直部204a之蝕刻後的厚度。蝕刻完成之後，去除剩餘的光阻層。MIM電容之垂直部204a與MIM電容之上電極圖案205a之線寬大小約略相等。舉例而言，MIM電容之垂直部204a與MIM電容之上電極圖案205a形成第一線圖案結構。換言之，在此步驟中，僅有介電層堆疊層234之第三介電層204進行圖案化，第一介電層202與介電層203維持原來的薄膜層而沒有被圖案化。 Referring to the third figure, after the formation of the MIM film layer, patterning is performed on the third dielectric layer 204 and the upper metal layer 205 by using a lithography and etching process; that is, a lithography and etching process is performed. A patterned portion is formed by removing a portion of the third dielectric layer 204 and the upper metal layer 205 on the etch stop layer. For example, a standard lithography process is utilized to form a first photoresist layer pattern (not shown). Then, an etching process is performed using the first photoresist layer pattern as an etch mask until the etching is performed until the etch stop layer (second dielectric layer 203) is exposed, and the result is that the vertical portion 204a of the MIM capacitor and the MIM capacitor are formed. Electrode pattern 205a. Since the etch stop layer is not etched, the etched thickness of the vertical portion 204a can be precisely controlled. After the etching is completed, the remaining photoresist layer is removed. The vertical portion 204a of the MIM capacitor and the line width of the electrode pattern 205a above the MIM capacitor are approximately equal in magnitude. For example, the vertical portion 204a of the MIM capacitor and the upper electrode pattern 205a of the MIM capacitor form a first line pattern structure. In other words, in this step, only the third dielectric layer 204 of the dielectric layer stack layer 234 is patterned, and the first dielectric layer 202 and the dielectric layer 203 maintain the original thin film layer without being patterned.
然後，請參考第四圖，在MIM電容之垂直部204a與MIM電容之上電極圖案205a形成之後，利用微影與蝕刻製程在所述介電層堆疊層234之第一介電層202與第二介電層203以及底層金屬層201上進行圖案化；亦即，進行一微影與蝕刻製程以去除底層200上之一部分的第一介電層202與第二介電層203以及底層金屬層201，而形成另一圖案化結構。舉例而言，利用一標準的微影製程以形成一第二光阻層圖案(未圖示)。然後，以該第二光阻層圖案作為蝕刻罩幕進行一蝕刻製程，直到蝕刻進行至底層200之上表面裸露為止，結果形成MIM電容之水平堆疊層圖案208以及MIM電容之下電極圖案201a。水平堆疊層圖案208包含水平部202a與介電層圖案203a。蝕刻完成之後，去除剩餘的光阻層。MIM電容之水平部202a、介電層圖案203a與下電極圖案201a之線寬大小約略相等。舉例而言，MIM電容之水平堆疊層圖案208與MIM電容之下電極圖案201a形成第二線圖案結構。第二線圖案結構之線寬大小係大於第一線圖案結構之線寬大小。 Then, referring to the fourth figure, after the vertical portion 204a of the MIM capacitor and the electrode pattern 205a above the MIM capacitor are formed, the first dielectric layer 202 and the first dielectric layer 202 of the dielectric layer stack layer 234 are processed by a lithography and etching process. Patterning is performed on the second dielectric layer 203 and the underlying metal layer 201; that is, a lithography and etching process is performed to remove a portion of the first dielectric layer 202 and the second dielectric layer 203 and the underlying metal layer on the underlying layer 200. 201, forming another patterned structure. For example, a standard lithography process is utilized to form a second photoresist layer pattern (not shown). Then, an etching process is performed using the second photoresist layer pattern as an etching mask until the etching proceeds until the upper surface of the underlayer 200 is exposed, and as a result, the horizontal stacked layer pattern 208 of the MIM capacitor and the electrode pattern 201a under the MIM capacitor are formed. The horizontal stacked layer pattern 208 includes a horizontal portion 202a and a dielectric layer pattern 203a. After the etching is completed, the remaining photoresist layer is removed. The line width of the horizontal portion 202a of the MIM capacitor, the dielectric layer pattern 203a, and the lower electrode pattern 201a is approximately equal. For example, the horizontal stacked layer pattern 208 of the MIM capacitor and the MIM capacitor lower electrode pattern 201a form a second line pattern structure. The line width of the second line pattern structure is greater than the line width of the first line pattern structure.
在此步驟中，形成倒T型介電層堆疊結構218以及倒T型MIM電容結構，其中倒T型介電層堆疊結構218係作為倒T型MIM電容結構之介電層。倒T型介電層堆疊結構218包括水平部202a、介電層圖案203a以及垂直部 204a，其中介電層圖案203a位於水平部202a與垂直部204a之間。換言之，垂直部204a係垂直水平堆疊層圖案208以形成該倒T型介電層堆疊結構218。水平部202a之線寬大小係大於垂直部204a之線寬大小。因此，倒T型MIM電容結構之介電層218之厚度包括水平部202a、介電層圖案203a以及垂直部204a之厚度的總和。因此，倒T型MIM電容之電容值可以藉由倒T型介電層堆疊結構218之總厚度來控制。 In this step, an inverted T-type dielectric layer stack structure 218 and an inverted T-type MIM capacitor structure are formed, wherein the inverted T-type dielectric layer stack structure 218 serves as a dielectric layer of the inverted T-type MIM capacitor structure. The inverted T-type dielectric layer stack structure 218 includes a horizontal portion 202a, a dielectric layer pattern 203a, and a vertical portion. 204a, wherein the dielectric layer pattern 203a is located between the horizontal portion 202a and the vertical portion 204a. In other words, the vertical portion 204a vertically stacks the layer patterns 208 to form the inverted T-type dielectric layer stack 218. The line width of the horizontal portion 202a is larger than the line width of the vertical portion 204a. Therefore, the thickness of the dielectric layer 218 of the inverted T-type MIM capacitor structure includes the sum of the thicknesses of the horizontal portion 202a, the dielectric layer pattern 203a, and the vertical portion 204a. Therefore, the capacitance of the inverted T-type MIM capacitor can be controlled by the total thickness of the inverted T-type dielectric layer stack 218.
倒T型MIM電容結構包括上電極圖案205a、倒T型介電層堆疊結構218與下電極圖案201a。崩潰電壓(breakdown voltage)也可以藉由倒T型介電層堆疊結構218之總厚度來控制。 The inverted T-type MIM capacitor structure includes an upper electrode pattern 205a, an inverted T-type dielectric layer stack structure 218, and a lower electrode pattern 201a. The breakdown voltage can also be controlled by the total thickness of the inverted T-type dielectric layer stack 218.
MIM電容之上電極圖案205a之下的垂直部204a與MIM電容之下電極圖案201a之上的水平部202a之間有介電層圖案203a而隔開彼此，因此，即使垂直部204a於蝕刻之後產生側邊底部切面(undercut)的情況，其側邊底部切面仍然不會接觸到下電極圖案201a，所以可以大大地改善傳統的MIM電容結構之介電層底部直接接觸下電極圖案所造成漏電流的情形。 The vertical portion 204a under the electrode pattern 205a above the MIM capacitor and the horizontal portion 202a above the MIM capacitor under the electrode pattern 201a are separated from each other by the dielectric layer pattern 203a, and therefore, even if the vertical portion 204a is formed after etching In the case of the undercut of the side bottom, the side bottom cut surface still does not contact the lower electrode pattern 201a, so that the leakage current caused by the direct contact of the bottom electrode pattern with the bottom of the dielectric layer of the conventional MIM capacitor structure can be greatly improved. situation.
之後，請參考第五圖，在倒T型MIM電容結構形成之後，在金屬導線間介電層200的基礎上形成一金屬導線間介電層200a，以覆蓋且封閉了整個倒T型MIM電容結構。金屬導線間介電層200a可以透過一化學氣相沉積的方法來形成。 After that, referring to the fifth figure, after the formation of the inverted T-type MIM capacitor structure, a dielectric inter-metal dielectric layer 200a is formed on the dielectric layer 200 between the metal wires to cover and close the entire inverted T-type MIM capacitor. structure. The inter-metal inter-wire dielectric layer 200a can be formed by a chemical vapor deposition method.
接下來，請參考第六圖，在形成金屬導線間介電層200a之後，利用一微影與刻蝕製程在所述金屬導線間介電層200a上進行圖案化；亦即，進行一微影與蝕刻製程以去除下電極圖案201a上之一部分的水平堆疊層圖案208、去除水平堆疊層圖案208上之一部分的金屬導線間介電層200a、以及去除上電極圖案205a上之一部分的金屬導線間介電層200a，而形成複數個通孔於金屬導線間介電層200a之中；該些通孔係貫穿水平堆疊層圖案208，使得該些通孔得以裸露下電極圖案201a之上表面以及上電極圖案205a之上表面。舉例而言，利用一標準的微影製程以形成一第三光阻層圖案(未圖示)。然後，以該第三光阻層圖案作為蝕刻罩幕進行一蝕刻製程，直到蝕刻進行至下電極圖案201a之上表面以及上電極圖案205a之上表面裸露為止，結果形成複數個通孔於金屬導線間介電層200a之中。該些通孔分為二類：第一類通孔係為從金屬導線間介電層200a之上表面至上電極圖案205a之上表面，第二類通孔係為從金屬導線間介 電層200a之上表面、貫穿水平堆疊層圖案208(水平部202a與介電層圖案203a)而至下電極圖案201a之上表面。蝕刻完成之後，去除剩餘的光阻層。 Next, referring to the sixth figure, after forming the inter-metal inter-wire dielectric layer 200a, patterning is performed on the inter-metal inter-layer dielectric layer 200a by a lithography and etching process; that is, performing a lithography And an etching process to remove a horizontally stacked layer pattern 208 of a portion of the lower electrode pattern 201a, a portion of the inter-metal inter-wire dielectric layer 200a on which the horizontally stacked layer pattern 208 is removed, and a metal wire between a portion of the upper electrode pattern 205a removed The dielectric layer 200a forms a plurality of via holes in the inter-metal inter-layer dielectric layer 200a; the through holes pass through the horizontally stacked layer pattern 208 such that the via holes are exposed on the upper surface and the upper electrode pattern 201a The upper surface of the electrode pattern 205a. For example, a standard lithography process is utilized to form a third photoresist layer pattern (not shown). Then, an etching process is performed using the third photoresist layer pattern as an etching mask until the etching proceeds to the upper surface of the lower electrode pattern 201a and the upper surface of the upper electrode pattern 205a is exposed, resulting in forming a plurality of via holes in the metal wires. In the dielectric layer 200a. The through holes are divided into two types: the first type of through holes are from the upper surface of the dielectric layer 200a between the metal wires to the upper surface of the upper electrode pattern 205a, and the second type of through holes are from the metal wires. The upper surface of the electric layer 200a penetrates the horizontally stacked layer pattern 208 (the horizontal portion 202a and the dielectric layer pattern 203a) to the upper surface of the lower electrode pattern 201a. After the etching is completed, the remaining photoresist layer is removed.
然後，於該些通孔之中填入導電材料，例如利用鎢或銅填充該些通孔，以分別於該些第一類通孔與該些第二類通孔之中形成複數個導孔(via)209a與209b於金屬導線間介電層200a之中，其中導孔209a與209b分別電性耦合(連接)上電極圖案205a與下電極圖案201a。在此步驟中，倒T型介電層堆疊結構218之水平堆疊層圖案208被導孔209b所貫穿，如第六圖所示。導孔209b之深度(厚度)約略等於導孔209a之深度(厚度)加上上電極圖案205a以及倒T型介電層堆疊結構218之深度(厚度)。 And filling the through holes with the conductive material, for example, filling the through holes with tungsten or copper to form a plurality of via holes in the first type of through holes and the second type of through holes, respectively. The vias 209a and 209b are among the inter-metal interposer dielectric layers 200a, wherein the via holes 209a and 209b are electrically coupled (connected) to the upper electrode pattern 205a and the lower electrode pattern 201a, respectively. In this step, the horizontal stacked layer pattern 208 of the inverted T-type dielectric layer stack 218 is penetrated by the via 209b as shown in the sixth figure. The depth (thickness) of the via hole 209b is approximately equal to the depth (thickness) of the via hole 209a plus the depth (thickness) of the upper electrode pattern 205a and the inverted T-type dielectric layer stack structure 218.
在另一實施例中，在形成金屬導線間介電層200a之後，利用一微影與刻蝕製程在所述金屬導線間介電層200a上進行圖案化；亦即，進行一微影與蝕刻製程以直接去除金屬導線間介電層200上之一部分的金屬導線間介電層200a，而形成複數個通孔於金屬導線間介電層200a之中；該些通孔係貫穿金屬導線間介電層200a之上表面以及下表面。類似地，該些通孔分為二類：第一類通孔係為從金屬導線間介電層200a之上表面至上電極圖案205a之上表面，第二類通孔係為從金屬導線間介電層200a之上表面貫穿至其下表面。蝕刻完成之後，去除剩餘的光阻層。 In another embodiment, after forming the inter-metal inter-layer dielectric layer 200a, patterning is performed on the inter-metal inter-layer dielectric layer 200a by a lithography and etching process; that is, performing a lithography and etching The process is for directly removing the inter-metal inter-wire dielectric layer 200a on a portion of the dielectric layer 200 between the metal wires to form a plurality of via holes in the inter-metal inter-layer dielectric layer 200a; the through-holes are interposed between the metal wires The upper surface and the lower surface of the electrical layer 200a. Similarly, the through holes are classified into two types: the first type of through holes are from the upper surface of the inter-metal inter-layer dielectric layer 200a to the upper surface of the upper electrode pattern 205a, and the second type of through-hole is formed from the inter-metal line. The upper surface of the electrical layer 200a penetrates to the lower surface thereof. After the etching is completed, the remaining photoresist layer is removed.
相同地，於該些通孔之中填入導電材料，例如利用鎢或銅填充該些通孔，以分別於該些第一類通孔與該些第二類通孔之中形成複數個導孔209a與209b於金屬導線間介電層200a之中，其中導孔209a與209b分別形成與連接於上電極圖案205a與金屬導線間介電層200之上。在此步驟中，倒T型介電層堆疊結構218之水平堆疊層圖案208未被導孔209b所貫穿，如第七圖所示。導孔209b之深度(厚度)約略等於導孔209a之深度(厚度)加上上電極圖案205a、倒T型介電層堆疊結構218與下電極圖案201a之深度(厚度)。 Similarly, a conductive material is filled in the through holes, for example, the through holes are filled with tungsten or copper to form a plurality of leads among the first type of through holes and the second type of through holes, respectively. The holes 209a and 209b are among the inter-metal interposer dielectric layers 200a, wherein the via holes 209a and 209b are respectively formed and connected to the upper electrode pattern 205a and the inter-metal inter-layer dielectric layer 200. In this step, the horizontal stacked layer pattern 208 of the inverted T-type dielectric layer stack 218 is not penetrated by the vias 209b, as shown in the seventh figure. The depth (thickness) of the via hole 209b is approximately equal to the depth (thickness) of the via hole 209a plus the depth (thickness) of the upper electrode pattern 205a, the inverted T-type dielectric layer stack structure 218, and the lower electrode pattern 201a.
最後，利用一微影與刻蝕製程以形成金屬導線210於金屬導線間介電層200a與導孔209a、209b之上；金屬導線210電性耦合(連接)導孔209a與209b，結果完成半導體元件之後段製程線路結構之製作。 Finally, a lithography and etching process is used to form the metal wires 210 over the inter-metal interposer dielectric layer 200a and the via holes 209a, 209b; the metal wires 210 electrically couple (connect) the via holes 209a and 209b, and the semiconductor is completed. Fabrication of the circuit structure at the end of the component.
除描述於此之外，可藉由敘述於本發明中之實施例及實施方式所達成之不同改良方式，皆應涵蓋於本發明之範疇中。一實施例為本發明之一實作或範例。說明書中所述一實施例、一個實施例、某些實施例或其他實施例指 的是一特定被敘述與此實施例有關之特徵、結構、或者特質被包含在至少一些實施例中，但未必於所有實施例。而各態樣之實施例不一定為相同實施例。其中應被理解的是在本發明實施例描述中，各特徵有時會組合於一實施例之圖、文字描述中，其目的為簡化本發明技術特徵，有助於了解本發明各方面之實施方式。除描述於此之外，可藉由敘述於本發明中之實施例及實施方式所達成之不同改良方式，皆應涵蓋於本發明之範疇中。因此，揭露於此之圖式及範例皆用以說明而非用以限制本發明，本發明之保護範疇僅應以列於其後之申請專利範圍為主。 In addition, the various modifications that can be made by the embodiments and the embodiments described in the present invention are intended to be included within the scope of the present invention. An embodiment is an implementation or example of the invention. An embodiment, an embodiment, some embodiments or other embodiments described in the specification The features, structures, or characteristics described in connection with this embodiment are included in at least some embodiments, but not necessarily in all embodiments. The embodiments of the various aspects are not necessarily the same embodiment. It should be understood that in the description of the embodiments of the present invention, the features are sometimes combined in the drawings and text descriptions of an embodiment, the purpose of which is to simplify the technical features of the present invention, and to facilitate understanding of the implementation of various aspects of the present invention. the way. In addition, the various modifications that can be made by the embodiments and the embodiments described in the present invention are intended to be included within the scope of the present invention. Therefore, the drawings and the examples are intended to be illustrative and not to limit the invention, and the scope of the invention is intended to be limited only by the scope of the claims.
200a‧‧‧金屬導線間介電層 200a‧‧‧Metal wire dielectric layer
201a‧‧‧下電極圖案 201a‧‧‧lower electrode pattern
202a‧‧‧水平部 202a‧‧‧Horizontal
203a‧‧‧介電層圖案 203a‧‧‧dielectric layer pattern
204a‧‧‧垂直部 204a‧‧‧Vertical
205a‧‧‧上電極圖案 205a‧‧‧Upper electrode pattern
208‧‧‧水平堆疊層圖案 208‧‧‧ horizontal stacked layer pattern
209a、209b‧‧‧導孔 209a, 209b‧‧‧ guide hole
210‧‧‧金屬導線 210‧‧‧Metal wire
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