TW201721742A - Methods, apparatuses and systems for integrated circuit structures with a replacement inter-layer dielectric (ILD) - Google Patents

Methods, apparatuses and systems for integrated circuit structures with a replacement inter-layer dielectric (ILD) Download PDF

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TW201721742A
TW201721742A TW105125008A TW105125008A TW201721742A TW 201721742 A TW201721742 A TW 201721742A TW 105125008 A TW105125008 A TW 105125008A TW 105125008 A TW105125008 A TW 105125008A TW 201721742 A TW201721742 A TW 201721742A
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layer
ild layer
ild
trenches
openings
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TW105125008A
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TWI720007B (en
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肯瓦爾吉 辛格
啟文 林
詹斯密特 喬拉
理查 史肯克
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英特爾股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Embodiments of the present disclosure describe techniques and configurations associated with an integrated circuit (IC) structure with a replacement inter-layer dielectric (ILD) layer disposed on a first ILD layer. A sacrificial layer may be formed on the first ILD layer. Trenches may be patterned and formed in the sacrificial layer such that the trenches are disposed on the first ILD layer. Vias may be patterned and formed in the first ILD layer below the trenches. After formation of the trenches, the sacrificial layer may be removed, and the replacement ILD layer (e.g., a second ILD layer) may be formed on the first ILD layer between the trenches. Other embodiments may be described and/or claimed.

Description

用於具有取代層間介電質(ILD)的積體電路結構的方法、設備及系統 Method, device and system for integrated circuit structure having substituted interlayer dielectric (ILD)

本發明揭露之實施例係大致有關積體電路之領域，且尤係有關具有取代層間介電質(ILD)之積體電路結構。 The embodiments of the present invention are generally related to the field of integrated circuits, and more particularly to integrated circuit structures having an inter-layer dielectric (ILD).

在積體電路之互連層中，低K值介電質通常被用於將導線間電容(line-to-line capacitance)及層間電容(layer-to-layer capacitance)最小化。然而，低K值介電質有高多孔性(porosity)，因而可能在產生互連層的圖案期間引發問題。 In the interconnect layer of integrated circuits, low K dielectrics are commonly used to minimize line-to-line capacitance and layer-to-layer capacitance. However, low K dielectrics have high porosity and may therefore cause problems during the patterning of the interconnect layers.

10‧‧‧晶圓形式 10‧‧‧ Wafer form

100‧‧‧單粒化形式 100‧‧‧Single granulation

102、103a、103b‧‧‧晶粒 102, 103a, 103b‧‧‧ grain

11‧‧‧晶圓 11‧‧‧ wafer

400、600、800、1000‧‧‧積體電路結構 400, 600, 800, 1000‧‧‧ integrated circuit structure

104‧‧‧電晶體結構 104‧‧‧Optical structure

200‧‧‧積體電路總成 200‧‧‧ integrated circuit assembly

121‧‧‧封裝基板 121‧‧‧Package substrate

122‧‧‧電路板 122‧‧‧ boards

106‧‧‧晶粒層級互連結構 106‧‧‧Grade level interconnect structure

102a‧‧‧半導體基板 102a‧‧‧Semiconductor substrate

102b‧‧‧裝置層 102b‧‧‧Device layer

102c‧‧‧互連層 102c‧‧‧Interconnect layer

1102‧‧‧主機板 1102‧‧‧ motherboard

112‧‧‧焊球 112‧‧‧ solder balls

110‧‧‧墊 110‧‧‧ pads

402、602、802、1002‧‧‧第一層間介電質層 402, 602, 802, 1002‧‧‧ first interlayer dielectric layer

404、604、804、1004‧‧‧下方層 404, 604, 804, 1004‧‧‧ lower layer

406、606、806、1006‧‧‧犧牲材料 406, 606, 806, 1006‧‧‧ sacrificial materials

408、608、808、1008‧‧‧硬遮罩層 408, 608, 808, 1008‧‧‧ hard mask layer

410a、410b、610a-c、616a-d、810a-c、816a-d、1010a-c、1016a-d‧‧‧開口 410a, 410b, 610a-c, 616a-d, 810a-c, 816a-d, 1010a-c, 1016a-d‧‧‧ openings

412、614、814、1014‧‧‧金屬 412, 614, 814, 1014‧‧‧ metal

414a、414b‧‧‧溝槽 414a, 414b‧‧‧ trench

416‧‧‧通孔 416‧‧‧through hole

418、618、824、1024‧‧‧第二層間介電質層 418, 618, 824, 1024‧‧‧Second interlayer dielectric layer

420、620‧‧‧蝕刻終止層 420, 620‧ ‧ etch stop layer

612、812、1012‧‧‧間隔物 612, 812, 1012‧‧‧ spacers

818、1018‧‧‧第二犧牲材料 818, 1018‧‧‧Second sacrificial material

820、1020‧‧‧第一硬遮罩材料 820, 1020‧‧‧ first hard mask material

822、1022‧‧‧第二硬遮罩材料 822, 1022‧‧‧Second hard mask material

826、1026‧‧‧第三硬遮罩材料 826, 1026‧‧‧ Third hard mask material

1100‧‧‧計算裝置 1100‧‧‧ Computing device

1108‧‧‧外殼 1108‧‧‧ Shell

1104‧‧‧處理器 1104‧‧‧ Processor

1106‧‧‧通訊晶片 1106‧‧‧Communication chip

若參閱前文中之詳細說明以及各圖式，將可易於了解各實施例。為了有助於本發明之說明，相像的參考編號標示相像的結構元件。該等圖式以舉例且非限制之方式示出各實施例。 The embodiments can be readily understood by referring to the detailed description and the drawings. To facilitate the description of the present invention, like reference numerals designate structural elements that are similar. The drawings illustrate the embodiments by way of example and not limitation.

第1圖根據某些實施例而以示意方式示出晶圓形式單粒化形式的一例示晶粒之一上視圖。 1 is a top plan view showing an example of a wafer in the form of a wafer in a single granulated form, in accordance with certain embodiments.

第2圖根據某些實施例而以示意方式示出一積體電路(IC)總成的一橫斷面側視圖。 Figure 2 shows, in schematic form, a cross-sectional side view of an integrated circuit (IC) assembly, in accordance with certain embodiments.

第3圖是用於根據各實施例而形成包含一取代層間介電質(ILD)層的一IC結構的一方法之一流程圖。 Figure 3 is a flow diagram of one method for forming an IC structure comprising a substituted interlayer dielectric (ILD) layer in accordance with various embodiments.

第4A-4G圖根據某些實施例而以示意方式示出一IC結構在第4圖的方法的各階段之橫斷面側視圖。 4A-4G are schematic cross-sectional side views showing the stages of an IC structure in the method of FIG. 4, in accordance with certain embodiments.

第5圖是用於根據某些實施例而使用一雙金屬化製程形成包含一取代層間介電質(ILD)層的一IC結構的一方法之一流程圖。 Figure 5 is a flow diagram of one method for forming an IC structure comprising a substituted interlayer dielectric (ILD) layer using a dual metallization process in accordance with certain embodiments.

第6A-6L圖根據某些實施例而以示意方式示出一IC結構在第4圖的方法各階段之橫斷面側視圖。 6A-6L are schematic cross-sectional side views showing an IC structure at various stages of the method of FIG. 4, in accordance with certain embodiments.

第7A-B圖根據某些實施例而示出用於形成包含一取代層間介電質(ILD)層的一IC結構且將多個硬遮罩材料用於短路減輕的一方法之一流程圖。 7A-B illustrate a flow chart of one method for forming an IC structure comprising a substituted interlayer dielectric (ILD) layer and using a plurality of hard mask materials for short circuit mitigation, in accordance with certain embodiments. .

第8A-8R圖根據某些實施例而以示意方式示出一IC結構在第4圖的方法的各階段之橫斷面側視圖。 8A-8R are schematic cross-sectional side views showing the stages of an IC structure in the method of FIG. 4, in accordance with certain embodiments.

第9A-B圖根據某些實施例而示出用於形成包含一取代層間介電質(ILD)層的一IC結構且將多個硬遮罩材料用於短路減輕的另一方法之一流程圖。 9A-B illustrate a flow of another method for forming an IC structure comprising a substituted interlayer dielectric (ILD) layer and using a plurality of hard mask materials for short circuit mitigation, in accordance with certain embodiments Figure.

第10A-10R圖根據某些實施例而以示意方式示出一IC結構在第4圖的方法的各階段之橫斷面側視圖。 10A-10R are schematic cross-sectional side views showing the stages of an IC structure in the method of FIG. 4, in accordance with certain embodiments.

第11圖以示意方式示出一例示系統，該例示系統可 根據某些實施例而包含本發明所述的一電晶體電極總成。 Figure 11 shows an exemplary system in a schematic manner, the exemplary system A transistor electrode assembly of the present invention is included in accordance with certain embodiments.

【發明內容及實施方式】 SUMMARY OF THE INVENTION AND EMBODIMENT

本發明揭露之實施例說明了與具有在一第一ILD層上配置的一取代層間介電質(ILD)層的一積體電路(IC)結構相關聯之技術及組態。可在該第一ILD層上形成一犧牲層。可在該犧牲層中產生溝槽的圖案，且形成該等溝槽，使該等溝槽被配置在該第一ILD層上。可在該第一ILD層中的該等溝槽之下產生通孔的圖案，且形成該等通孔。在形成了該等溝槽之後，可移除該犧牲層，且可在該第一ILD層上的該等溝槽之間形成該取代ILD層(例如，一第二ILD層)。該第二ILD層可具有比該第一ILD層高的多孔性及/或低的介電常數。 Embodiments of the present invention illustrate techniques and configurations associated with an integrated circuit (IC) structure having a replacement interlayer dielectric (ILD) layer disposed on a first ILD layer. A sacrificial layer can be formed on the first ILD layer. Patterns of trenches may be created in the sacrificial layer and the trenches are formed such that the trenches are disposed on the first ILD layer. Patterns of vias may be created under the trenches in the first ILD layer and formed into the vias. After the trenches are formed, the sacrificial layer can be removed and the replacement ILD layer (eg, a second ILD layer) can be formed between the trenches on the first ILD layer. The second ILD layer can have a higher porosity and/or a lower dielectric constant than the first ILD layer.

在下文之實施方式中，將參照構成本發明的一部分之各圖式，其中在所有該等圖式中之類似的代號標示類似的部分，且其中係以例示可實施本發明揭露之標的之各實施例之方式示出該等圖式。我們應可了解：可利用其他實施例，且可在不脫離本發明揭露之範圍下作出結構或邏輯上的改變。因此，不應以限制之方式理解下文中之實施方式，且只由最後之申請專利範圍以及其等效物界定各實施例之範圍。 In the following description, reference is made to the accompanying drawings, in which FIG. The figures are shown in the manner of the embodiments. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. Therefore, the following embodiments are not to be considered as limiting, and the scope of the various embodiments

為了便於說明本發明之揭露，詞語"A及/或B"意指(A)、(B)、或(A及B)。為了便於說明本發明之揭露，詞語"A、B、及/或C"意指(A)、(B)、(C)、(A及B)、(A及 C)、(B及C)、或(A、B、及C)。 For convenience of explanation of the present invention, the words "A and/or B" mean (A), (B), or (A and B). For the purpose of illustrating the disclosure of the present invention, the words "A, B, and/or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

本說明可使用諸如頂部/底部、側、以及在...之上/在...之下等的基於透視之說明。這些說明只是被用於協助討論，且其用意並非將本發明所述的實施例之應用限於任何特定的方位。 This description may use a perspective-based description such as top/bottom, side, and above/under. These descriptions are only used to assist in the discussion, and are not intended to limit the application of the embodiments described herein to any particular orientation.

本說明使用詞語"在一實施例中，"或"在各實施例中，"，而該等詞語可分別意指相同的或不同的實施例中之一或多個實施例。此外，在以與本發明揭露之實施例有關之方式使用術語"包含"、"包括"、及"具有"等的術語時，該等術語都是同義的。 The description uses the words "in an embodiment," or "in various embodiments," and the terms may mean one or more embodiments of the same or different embodiments, respectively. In addition, when the terms "comprising," "including," and "having" are used, the terms are used synonymously in the context of the embodiments disclosed herein.

本發明中可使用術語"被耦合到"及其派生詞。"被耦合"可意指下列意義中之一或多者。"被耦合"可意指兩個或更多個元件在實體上或電氣上直接接觸。然而，"被耦合"亦可意指兩個或更多個元件相互間接接觸，但仍然相互配合或作用，且"被耦合"可意指一或多個其他元件被耦合到或被連接到被稱為相互耦合的該等元件之間。術語"被直接耦合"可意指兩個或更多個元件直接接觸。 The term "coupled to" and its derivatives may be used in the present invention. "Coupled" may mean one or more of the following meanings. "Coupled" may mean that two or more elements are in physical or electrical direct contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or function with each other, and "coupled" may mean that one or more other elements are coupled or connected to being Between these elements, called mutual coupling. The term "directly coupled" may mean that two or more elements are in direct contact.

在各實施例中，詞語"被形成、被沈積、或被以其他方式配置在一第二特徵上之一第一特徵"可意指：在該第二特徵之上形成、沈積、或配置該第一特徵，且該第一特徵的至少一部分可與該第二特徵的至少一部分直接接觸(例如，在實體上及/或電氣上直接接觸)或間接接觸(例如，該第一特徵與該第二特徵之間有一或多個其他特徵)。 In various embodiments, the phrase "formed, deposited, or otherwise configured in a first feature on a second feature" may mean forming, depositing, or configuring the second feature over the second feature. a first feature, and at least a portion of the first feature can be in direct contact (eg, physically and/or electrically in direct contact) or indirect contact with at least a portion of the second feature (eg, the first feature and the first feature) There are one or more other features between the two features).

在本說明書的用法中，術語"電路"可意指特定應用積體電路(Application Specific Integrated Circuit；簡稱ASIC)、電子電路、執行一或多個軟體或韌體程式之處理器(共用、專用、或群組處理器)及/或記憶體(共用、專用、或群組記憶體)、組合式邏輯電路(combinational logic circuit)、及/或提供所需功能之其他適當的組件的一部分，或可包括以上各項。 In the usage of the present specification, the term "circuit" may mean an application specific integrated circuit (ASIC), an electronic circuit, a processor that executes one or more software or firmware programs (shared, dedicated, Or a group processor) and/or a memory (common, dedicated, or group memory), a combined logic circuit, and/or a portion of other suitable components that provide the required functionality, or Includes the above items.

第1圖根據某些實施例而以示意方式示出晶圓形式10及單粒化形式100的一例示晶粒102。在某些實施例中，晶粒102可以是由諸如矽或其他適當的材料等的半導體材料組成的一晶圓11的複數個晶粒(例如，晶粒102、103a、103b)中之一晶粒。可在晶圓11的一表面上形成該複數個晶粒。該等晶粒中之每一晶粒可以是包括本發明所述的一或多個IC結構(例如，IC結構400、600、800、及/或1000、及/或使用方法300、500、700、及/或900形成之IC結構)的一半導體產品之一重複單位。例如，晶粒102可包含具有諸如用於提供一或多個電晶體裝置或源極/汲極區的移動電荷載子的通道路徑之一或多個通道體(例如，鰭結構、奈米線(nanowire)、平面體(planar body)等的通道體)等的電晶體結構104之電路。可在該一或多個電晶體結構104上形成電晶體電極總成(例如，終端接觸)，且可使該等電晶體電極總成被耦合到該一或多個電晶體結構104，以便將電能傳送進或出該等電晶體結構104。例如，可使終端接觸在電氣上被 耦合到一通道體，以便提供一閘極電極，用以傳送一臨界電壓及/或一源極/汲極電流，而提供用於電晶體裝置的操作之移動電荷載子。雖然為了簡化而在第1圖中示出通過該晶粒102的相當大的一部分的各列中之該等電晶體結構104，但是我們應可了解：在其他實施例中，可在該晶粒102上以多種其他適當的安排方式(例如，包括具有比所示的尺寸小許多的尺寸之一些垂直及水平特徵)中之任何安排方式配置該等電晶體結構104。 1 shows an exemplary die 102 of wafer form 10 and single granulated form 100 in a schematic manner in accordance with certain embodiments. In some embodiments, the die 102 may be one of a plurality of grains (eg, grains 102, 103a, 103b) of a wafer 11 composed of a semiconductor material such as germanium or other suitable material. grain. The plurality of crystal grains may be formed on one surface of the wafer 11. Each of the dies may comprise one or more of the IC structures described herein (eg, IC structures 400, 600, 800, and/or 1000, and/or methods of use 300, 500, 700) And/or one of the semiconductor products of the 900 formed IC structure). For example, the die 102 can include one or more channel paths (eg, fin structures, nanowires) having a mobile charge carrier such as a mobile charge carrier for providing one or more transistor devices or source/drain regions. A circuit of a transistor structure 104 such as a nanowire or a channel body of a planar body. A transistor electrode assembly (eg, a terminal contact) can be formed on the one or more transistor structures 104, and the transistor electrode assemblies can be coupled to the one or more transistor structures 104 to Electrical energy is transferred into or out of the transistor structure 104. For example, the terminal can be electrically contacted Coupled to a channel body to provide a gate electrode for transmitting a threshold voltage and/or a source/drain current to provide mobile charge carriers for operation of the transistor device. Although the transistor structures 104 in each of the columns passing through a substantial portion of the die 102 are shown in FIG. 1 for simplicity, it should be understood that in other embodiments, the die may be The optoelectronic structures 104 are configured on any of a variety of other suitable arrangements (e.g., including some vertical and horizontal features having dimensions that are much smaller than the dimensions shown).

在完成以晶粒實施的半導體產品的製程之後，晶圓11可接受一切割製程，其中該等晶粒中之每一晶粒(例如，晶粒102)相互分開，而提供該半導體產品之分離的"晶片"。晶圓11可具有多種尺寸中之任何尺寸。在某些實施例中，晶圓11具有範圍自大約25.4毫米至大約450毫米的直徑。在其他實施例中，晶圓11可包括其他尺寸及/或其他形狀。根據各實施例，可在晶圓形式10或單粒化形式100的一半導體基板上配置該等電晶體結構104。本發明所述的該等電晶體結構104可被包含在用於邏輯或記憶體或以上兩者的組合之一晶粒102中。在某些實施例中，該等電晶體結構104可以是一系統單晶片(System-on-Chip；簡稱SoC)總成的一部分。 After completing the fabrication of the semiconductor product in the die, the wafer 11 can undergo a dicing process in which each of the dies (e.g., die 102) are separated from each other to provide separation of the semiconductor product. "wafer". Wafer 11 can have any of a variety of sizes. In some embodiments, wafer 11 has a diameter ranging from about 25.4 mm to about 450 mm. In other embodiments, wafer 11 may include other sizes and/or other shapes. According to various embodiments, the transistor structures 104 may be disposed on a semiconductor substrate in wafer form 10 or single granulation form 100. The optoelectronic structures 104 of the present invention can be included in one of the dies 102 for logic or memory or a combination of the two. In some embodiments, the transistor structure 104 can be part of a System-on-Chip (SoC) assembly.

第2圖根據某些實施例而以示意方式示出一IC總成200的一橫斷面側視圖。在某些實施例中，IC總成200可包含在電氣上及/或實體上被耦合到一封裝基板121的一或多個晶粒(後文中稱為"晶粒102")。在某些實施例 中，如圖所示，封裝基板121可在電氣上被耦合到一電路板122。在某些實施例中，一IC總成200可根據各實施例而包含晶粒102、封裝基板121、及/或電路板122中之一或多者。根據各實施例，可在任何適當的IC裝置中實施用於IC結構之本發明所述的實施例。 FIG. 2 shows a cross-sectional side view of an IC assembly 200 in a schematic manner, in accordance with certain embodiments. In some embodiments, IC assembly 200 can include one or more dies (hereinafter referred to as "die 102") that are electrically and/or physically coupled to a package substrate 121. In some embodiments As shown, the package substrate 121 can be electrically coupled to a circuit board 122. In some embodiments, an IC assembly 200 can include one or more of the die 102, the package substrate 121, and/or the circuit board 122, in accordance with various embodiments. Embodiments of the invention for an IC structure may be implemented in any suitable IC device in accordance with various embodiments.

晶粒102可代表使用諸如以與形成互補金屬氧化物半導體(CMOS)裝置有關之方式使用的薄膜沈積、微影、及蝕刻等的半導體技術自一半導體材料(例如，矽)製造的一分離的產品。在某些實施例中，晶粒102可以是或包括一處理器、記憶體、SoC、或ASIC，或可以是以上各項的一部分。在某些實施例中，諸如模塑料(molding compound)或底部填充材料(underfill material)(圖中未示出)等的一電氣絕緣材料可封裝晶粒102及/或晶粒層級互連結構106的至少一部分。 The die 102 may represent a separate fabrication from a semiconductor material (eg, germanium) using semiconductor techniques such as thin film deposition, lithography, and etching used in connection with forming a complementary metal oxide semiconductor (CMOS) device. product. In some embodiments, the die 102 can be or include a processor, memory, SoC, or ASIC, or can be part of the above. In some embodiments, an electrically insulating material, such as a molding compound or an underfill material (not shown), may encapsulate the die 102 and/or the grain level interconnect structure 106. At least part of it.

晶粒102可根據多種適當的組態而被連接到封裝基板121，該等組態包括諸如以圖所示之方式在一覆晶(flip-chip)組態下被直接耦合到封裝基板121。在該覆晶組態中，使用諸如凸塊(bump)、銅柱(pillar)、或其他適當的結構等的晶粒層級互連結構106將晶粒102的包含電路之一主動面S1連接到封裝基板121的一表面，其中該等其他適當的結構亦可將晶粒102在電氣上耦合到封裝基板121。晶粒102的該主動面S1可包含諸如電晶體裝置等的主動裝置。如圖所示，一非主動面S2可被配置在該主動面S1的對面。 The die 102 can be connected to the package substrate 121 in accordance with a variety of suitable configurations including direct coupling to the package substrate 121 in a flip-chip configuration, such as shown. In the flip chip configuration, the active level S1 of one of the included circuits of the die 102 is connected to the die level interconnect structure 106, such as a bump, a pillar, or other suitable structure. A surface of the package substrate 121, wherein the other suitable structures can also electrically couple the die 102 to the package substrate 121. The active surface S1 of the die 102 may comprise an active device such as a transistor device. As shown, a non-active surface S2 can be disposed opposite the active surface S1.

晶粒102通常可包含一半導體基板102a、一或多個裝置層(後文中稱為"裝置層102b")、以及一或多個互連層(後文中稱為"互連層102c")。在某些實施例中，可實質上由諸如矽等的體半導體材料(bulk semiconductor material)組成半導體基板102a。裝置層102b可代表在該半導體基板上形成諸如電晶體裝置等的主動裝置之一區域。例如，裝置層102b可包含諸如電晶體裝置的通道體及/或源極/汲極區等的電晶體結構。互連層102c可包含被配置成將電信號傳送進或出裝置層102b中之該等主動裝置的互連結構。例如，互連層102c可包含垂直線(例如，溝槽)、及/或垂直插塞(例如，通孔)、或用於提供電路佈線及/或接觸之其他適當的特徵。在各實施例中，互連層102c中之一或多個層可包含將於下文中進一步說明的一取代ILD。 The die 102 may generally include a semiconductor substrate 102a, one or more device layers (hereinafter referred to as "device layer 102b"), and one or more interconnect layers (hereinafter referred to as "interconnect layer 102c"). In some embodiments, the semiconductor substrate 102a can be substantially composed of a bulk semiconductor material such as germanium. The device layer 102b may represent an area in which an active device such as a transistor device or the like is formed on the semiconductor substrate. For example, device layer 102b can comprise a transistor structure such as a channel body and/or a source/drain region of a transistor device. Interconnect layer 102c may include interconnect structures configured to carry electrical signals into or out of device layers in device layer 102b. For example, interconnect layer 102c can include vertical lines (eg, trenches), and/or vertical plugs (eg, vias), or other suitable features for providing circuit wiring and/or contacts. In various embodiments, one or more of the interconnect layers 102c can comprise a substituted ILD as will be further described below.

在某些實施例中，晶粒層級互連結構106可在電氣上被耦合到互連層102c，且可被配置成在晶粒102與其他電氣裝置之間傳送電信號。該等電信號可包括諸如以與晶粒102的操作有關之方式使用的輸入/輸出(Input/Output；簡稱I/O)信號及/或電源/接地信號。 In some embodiments, the grain level interconnect structure 106 can be electrically coupled to the interconnect layer 102c and can be configured to transfer electrical signals between the die 102 and other electrical devices. The electrical signals may include input/output (I/O) signals and/or power/ground signals, such as used in connection with the operation of die 102.

在某些實施例中，封裝基板121是諸如味之素增層膜(Ajinomoto Build-up Film；簡稱ABF)等的具有芯板(core)及/或增層(build-up layer)之環氧樹脂層壓基板(laminate substrate)。在其他實施例中，封裝基板121可包括其他適當類型的基板，其中包括諸如由玻璃、 陶瓷、或半導體材料形成的基板。 In some embodiments, the package substrate 121 is an epoxy having a core and/or build-up layer, such as Ajinomoto Build-up Film (ABF). A resin laminate substrate. In other embodiments, the package substrate 121 may include other suitable types of substrates including, for example, by glass, A substrate formed of ceramic or semiconductor material.

封裝基板121可包含被配置成將電信號傳送進或出晶粒102之電路佈線特徵。該等電路佈線特徵可包括諸如被配置在封裝基板121的一或多個表面上之墊或走線(trace)(圖中未示出)、及/或諸如用於傳送電信號通過封裝基板121之溝槽、通孔、或其他互連結構等的內部佈線特徵(圖中未示出)。例如，在某些實施例中，封裝基板121可包含諸如被配置成接受晶粒102的各別晶粒層級互連結構106之墊(圖中未示出)等的電路佈線特徵。 The package substrate 121 can include circuit routing features configured to carry electrical signals into or out of the die 102. The circuit routing features can include pads or traces (not shown) disposed on one or more surfaces of the package substrate 121, and/or such as for transmitting electrical signals through the package substrate 121. Internal wiring features (not shown) of trenches, vias, or other interconnect structures. For example, in some embodiments, package substrate 121 can include circuit routing features such as pads (not shown) that are configured to accept respective die level interconnect structures 106 of die 102.

電路板122可以是由諸如環氧樹脂層壓板等的電氣絕緣材料組成之印刷電路板(Printed Circuit Board；簡稱PCB)。例如，電路板122可包括由諸如聚四氟乙烯(polytetrafluoroethylene)、阻燃4(Flame Retardant 4；簡稱FR-4)、FR-1棉紙等的酚醛棉紙(phenolic cotton paper)材料、CEM-1或CEM-3等的環氧樹脂材料、或使用環氧樹脂預浸漬材料(prepreg material)層壓在一起的玻璃布(woven glass)材料等的材料組成之一些電氣絕緣層。可通過該等電氣絕緣層而形成諸如走線、溝槽、或通孔等的互連結構(圖中未示出)，以便經由電路板122而傳送晶粒102之電信號。在其他實施例中，可由其他適當的材料組成電路板122。在某些實施例中，電路板122是一主機板(例如，第11圖之主機板1102)。 The circuit board 122 may be a printed circuit board (PCB) composed of an electrically insulating material such as an epoxy laminate. For example, the circuit board 122 may include a phenolic cotton paper material such as polytetrafluoroethylene, Flame Retardant 4 (FR-4), FR-1 tissue paper, or the like, CEM- 1 or some electrical insulating layer composed of an epoxy resin material such as CEM-3 or a woven glass material laminated with an epoxy prepreg material. An interconnect structure (not shown) such as traces, trenches, or vias may be formed through the electrically insulating layers to transfer electrical signals of the die 102 via the circuit board 122. In other embodiments, circuit board 122 may be comprised of other suitable materials. In some embodiments, circuit board 122 is a motherboard (eg, motherboard 1102 of FIG. 11).

諸如焊球112等的封裝層級互連可被耦合到封裝基板121上的及/或電路板122上的一或多個墊(後文中稱為" 墊110")，以便形成被配置成在封裝基板121與電路板122之間進一步傳送電信號之對應的焊點(solder joint)。可由諸如包括鎳(Ni)、鈀(Pd)、金(Au)、銀(Ag)、銅(Cu)、以及以上各材料的組合等的任何適當之導電材料組成該等墊110。在其他實施例中，可使用在實體上及/或電氣上將封裝基板121耦合到電路板122之其他適當的技術。 Package level interconnects, such as solder balls 112, may be coupled to one or more pads on package substrate 121 and/or on circuit board 122 (hereinafter referred to as "" Pad 110") to form a corresponding solder joint configured to further transfer electrical signals between package substrate 121 and circuit board 122. Such as may include nickel (Ni), palladium (Pd), gold (Au Any suitable conductive material, such as silver (Ag), copper (Cu), and combinations of the above materials, may be used to form the pads 110. In other embodiments, the package substrate may be physically and/or electrically used. 121 other suitable techniques coupled to circuit board 122.

在其他實施例中，IC總成200可包括多種其他適當的組態，其中包括諸如覆晶及/或打線接合(wire-bonding)組態、中介層(interposer)、包括系統級封裝(System-in-Package；簡稱SiP)之多晶片封裝(multi-chip package)組態、及/或封裝堆疊(Package-on-Package；簡稱PoP)組態之適當的組合。在某些實施例中，可使用在晶粒102與IC總成200的其他組件之間傳送電信號之其他適當的技術。 In other embodiments, the IC assembly 200 can include a variety of other suitable configurations including, for example, flip chip and/or wire-bonding configurations, interposers, including system level packages (System- An appropriate combination of in-package (SiP) multi-chip package configuration and/or package-on-package (PoP) configuration. In some embodiments, other suitable techniques for transmitting electrical signals between the die 102 and other components of the IC assembly 200 can be used.

第3圖是用於根據各實施例而形成具有一取代ILD層的一IC結構的一方法300之一流程圖。第4A、4B、4C、4D、4E、4F、及4G圖根據各實施例而以示意方式示出一IC結構400在方法300的各階段之橫斷面側視圖。因此，下文中將參照第4A-4G圖而說明方法300。可將與本發明所述的那些製造原理類似之製造原理用於形成具有與第4A-4G圖所示的組態不同之其他組態之IC結構。在某些實施例中，IC結構400可對應於包含一或多個互連結構(例如，溝槽或通孔)的一互連層。 3 is a flow diagram of a method 300 for forming an IC structure having a substituted ILD layer in accordance with various embodiments. 4A, 4B, 4C, 4D, 4E, 4F, and 4G are schematic cross-sectional side views of an IC structure 400 at various stages of method 300, in accordance with various embodiments. Accordingly, method 300 will be described hereinafter with reference to Figures 4A-4G. Manufacturing principles similar to those described in the present invention can be used to form IC structures having other configurations than those shown in Figures 4A-4G. In some embodiments, IC structure 400 can correspond to an interconnect layer that includes one or more interconnect structures (eg, trenches or vias).

在方塊302中，方法300可包含：在一下方層上形成一第一ILD層。該下方層可以是諸如一裝置層、另一互連層、或一半導體基板等的任何適當的IC層。可以諸如化學氣相沈積(Chemical Vapor Deposition；簡稱CVD)、原子層沈積(Atomic Layer Deposition；簡稱ALD)、或物理氣相沈積(Physical Vapor Deposition；簡稱PVD)等的任何適當的沈積製程形成該第一ILD層。此外，該第一ILD層可包括任何適當的介電材料或介電材料之組合，其中包括一或多種高K值或低K值材料。 At block 302, method 300 can include forming a first ILD layer on a lower layer. The underlying layer can be any suitable IC layer such as a device layer, another interconnect layer, or a semiconductor substrate. The first may be formed by any suitable deposition process such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD). An ILD layer. Additionally, the first ILD layer can comprise any suitable dielectric material or combination of dielectric materials including one or more high K or low K value materials.

例如，該第一ILD層可包括二氧化矽(SiO2)、氮氧化矽(SiOxNy)、氮化矽(SixNy)、氧化鋁(Al2O3)、二氧化鉿(HfO2)、鋁酸鉿(HfAlxOy)、矽酸鉿(HfSixOy)、氧化鋯(ZrO2)、矽酸鋯(ZrSixOy)、氧化鑭(La2O3)、氧化釔(Y2O3)、鋁酸鑭(LaAlxOy)、五氧化二鉭(Ta2O5)、二氧化鈦(TiO2)、鈦酸鋇鍶(BaSrTixOy)、鈦酸鋇(BaTixOy)、鈦酸鍶(SrTixOy)、鉭鈧酸鉛(PbScxTayOz)、或鈮鋅酸鉛(PbZnxNbyOz)、碳摻雜氧化物(Carbon Doped Oxide；簡稱CDO)、諸如全氟環丁烷(perfluorocyclobutane)或聚四氟乙烯(polytetrafluoroethylene)等的有機聚合物、氟矽玻璃(Fluorosilicate Glass；簡稱FSG)、以及諸如聚倍半矽氧烷(silsesquioxane)、矽氧烷(siloxane)、或有機矽玻璃(organosilicate glass)等的有機矽酸鹽(organosilicate)、或以上各項之組合，其中x、y、z代表 各別元素的適當量。在某些實施例中，於使用高k值材料時，可對該第一ILD層執行一退火製程，以便改善其品質。在其他實施例中，亦可將其他材料用於該第一ILD層。 For example, the first ILD layer may include cerium oxide (SiO 2 ), cerium oxynitride (SiO x N y ), cerium nitride (Si x N y ), aluminum oxide (Al 2 O 3 ), cerium oxide ( HfO 2 ), strontium aluminate (HfAl x O y ), bismuth ruthenate (HfSi x O y ), zirconium oxide (ZrO 2 ), zirconium silicate (ZrSi x O y ), lanthanum oxide (La 2 O 3 ), Yttrium oxide (Y 2 O 3 ), barium aluminate (LaAl x O y ), tantalum pentoxide (Ta 2 O 5 ), titanium dioxide (TiO 2 ), barium titanate (BaSrTi x O y ), barium titanate (BaTi x O y ), barium titanate (SrTi x O y ), lead phthalate (PbSc x Ta y O z ), or lead lanthanum zincate (PbZn x Nb y O z ), carbon doped oxide ( Carbon Doped Oxide; abbreviated as CDO), an organic polymer such as perfluorocyclobutane or polytetrafluoroethylene, Fluorosilicate Glass (FSG), and polysilsesquioxanes An organosilicate such as a silsesquioxane, a siloxane, or an organosilicate glass, or a combination of the above, wherein x, y, and z represent appropriate amounts of the respective elements. In some embodiments, when a high-k material is used, an annealing process can be performed on the first ILD layer to improve its quality. In other embodiments, other materials may also be used for the first ILD layer.

在方塊304中，方法300可包含：在該第一ILD層上形成一犧牲層。在某些實施例中，該犧牲層可包括諸如介電材料或硬遮罩(hard mask)材料等的可執行濕式清洗之任何適當的材料。例如，該犧牲層可包括氮化鈦(TiN)或非晶矽(amorphous silicon；簡稱a-Si)。 At block 304, method 300 can include forming a sacrificial layer on the first ILD layer. In some embodiments, the sacrificial layer can comprise any suitable material that can be wet cleaned, such as a dielectric material or a hard mask material. For example, the sacrificial layer may include titanium nitride (TiN) or amorphous silicon (abbreviated as a-Si).

在方塊306中，方法300可包含：在該犧牲層上形成一硬遮罩層。該硬遮罩層可以是一可產生圖案的材料，以便可選擇性地移除該硬遮罩層的一些部分。例如，該硬遮罩層可包含一介電材料(例如，一或多種氧化物、氮化物、碳化物、或混合的氮氧化物、碳摻雜氧化物、氮摻碳化物等的介電材料)及/或一或多種過渡金屬(transition metal)化合物(例如，鈦(Ti)、鋯(Zr)、鉿(Hf)之氧化物或氮化物等的過渡金屬化合物)。 At block 306, method 300 can include forming a hard mask layer on the sacrificial layer. The hard mask layer can be a pattern-generating material to selectively remove portions of the hard mask layer. For example, the hard mask layer may comprise a dielectric material (eg, one or more oxides, nitrides, carbides, or mixed oxynitrides, carbon doped oxides, nitrogen-doped carbides, etc.) And/or one or more transition metal compounds (for example, transition metal compounds such as titanium (Ti), zirconium (Zr), hafnium (Hf) oxides or nitrides).

第4A圖示出在方法300的方塊306之後的IC結構400。IC結構400包含在一下方層404上形成之一第一ILD層402、在第一ILD層402上形成之一犧牲材料406、以及在該犧牲材料上形成之一硬遮罩層408。 FIG. 4A shows the IC structure 400 after block 306 of method 300. The IC structure 400 includes a first ILD layer 402 formed on a lower layer 404, a sacrificial material 406 formed on the first ILD layer 402, and a hard mask layer 408 formed on the sacrificial material.

在方塊308中，方法300可包含：在該硬遮罩層及犧牲層中形成溝槽開口。該等溝槽開口可延伸通過該犧牲層而到該第一ILD層。可移除該硬遮罩層及犧牲材料的一些部分，而形成該等溝槽開口。在某些實施例中，可(諸如 利用一選擇性移除製程)先移除該硬遮罩層的一些部分，且然後可移除被配置在該硬遮罩層的該等被移除的部分之下的該犧牲材料的該等部分。可諸如利用一蝕刻製程移除該犧牲材料的該等部分。該蝕刻製程可使用與該第一ILD層比較對該犧牲材料更有選擇性之一蝕刻劑。亦即，該第一ILD層可被用來作為一蝕刻終止層(etch stop layer)，且可不被該蝕刻製程移除。 At block 308, method 300 can include forming a trench opening in the hard mask layer and the sacrificial layer. The trench openings may extend through the sacrificial layer to the first ILD layer. The hard mask layer and portions of the sacrificial material can be removed to form the trench openings. In some embodiments, Removing portions of the hard mask layer using a selective removal process, and then removing the sacrificial material disposed under the removed portions of the hard mask layer section. The portions of the sacrificial material can be removed, such as by an etch process. The etch process can use an etchant that is more selective to the sacrificial material than the first ILD layer. That is, the first ILD layer can be used as an etch stop layer and can be removed by the etching process.

第4B圖示出具有硬遮罩層408及犧牲材料406中之開口410a及410b的IC結構400。犧牲材料406中之開口410a及410b可對應於將形成在IC結構400中水平地傳送電信號的溝槽之溝槽開口。因此，開口410a及410b可水平地延伸到第4B圖所示的面之外(例如，延伸進入頁面及/或延伸到頁面之外)。 FIG. 4B illustrates an IC structure 400 having openings 410a and 410b in the hard mask layer 408 and the sacrificial material 406. The openings 410a and 410b in the sacrificial material 406 may correspond to trench openings that will form trenches that horizontally transmit electrical signals in the IC structure 400. Thus, the openings 410a and 410b can extend horizontally beyond the face shown in FIG. 4B (eg, extending into the page and/or extending beyond the page).

在方塊310中，方法300可進一步包含：產生在該等溝槽開口的各別部分之下的該第一ILD層中之通孔開口的圖案。可移除該第一ILD層的一些部分，以便形成該等通孔開口。該等通孔開口可延伸到該下方層，以便能夠在該等通孔開口中形成(將在下文中進一步地說明)在導電上將對應的溝槽耦合到該下方層之通孔。 At block 310, method 300 can further include: creating a pattern of via openings in the first ILD layer below respective portions of the trench openings. Portions of the first ILD layer may be removed to form the via openings. The via openings may extend to the underlying layer to enable formation (as will be further explained below) in the via openings to electrically couple corresponding trenches to the vias of the underlying layer.

第4C圖示出在方法300的方塊310之後的IC結構400。已移除了該第一ILD層在開口410a中之部分，而使開口410a延伸到下方層404。如將於下文中進一步說明的，可在開口410a中形成一導電材料，而形成一通孔。可以只在該對應的溝槽的一部分之下配置該通孔，且因而 第一ILD層402中之開口410a(例如，通孔開口)的該部分可以只沿著自第4C圖所示之面出來的水平方向延伸出一小量(例如，顯著地小於犧牲層406中之開口410a(例如，溝槽開口)的該部分之水平延伸量)。 FIG. 4C illustrates IC structure 400 after block 310 of method 300. The portion of the first ILD layer in opening 410a has been removed while opening 410a extends to lower layer 404. As will be explained further below, a conductive material can be formed in the opening 410a to form a through hole. The via may be disposed only under a portion of the corresponding trench, and thus The portion of the opening 410a (e.g., the via opening) in the first ILD layer 402 may extend only a small amount (e.g., significantly smaller than the sacrificial layer 406) in a horizontal direction from the face shown in Fig. 4C. The horizontal extent of the portion of the opening 410a (eg, the trench opening).

在方塊312中，方法300可包含：在該等溝槽開口及該等通孔開口中形成一金屬。可以包括一保形及/或選擇性沈積製程之任何適當的沈積技術在該等溝槽開口及通孔開口中形成該金屬。例如，可以CVD、ALD、PVD、無電鍍、電鍍、或這些沈積技術之適當的組合形成該金屬。 At block 312, method 300 can include forming a metal in the trench openings and the via openings. The metal may be formed in the trench openings and via openings by any suitable deposition technique that may include a conformal and/or selective deposition process. For example, the metal can be formed by CVD, ALD, PVD, electroless plating, electroplating, or a suitable combination of these deposition techniques.

該金屬可包括任何適當的金屬。例如，在某些實施例中，該金屬可包括銅(Cu)、金(Au)、鎢(W)、鈦(Ti)、鉭(Ta)、鉑(Pt)、鎳(Ni)、鈷(Co)、銠(Rh)、釕(Ru)、鈀(Pd)、鉿(Hf)、鋯(Zr)、或鋁(Al)、或以上各項之組合。在某些實施例中，該金屬層可包括諸如氮化鈦(TiN)、氮化鎢(WN)、或氮化鉭(TaN)、或以上各項之組合等的金屬氮化物。在某些實施例中，該金屬層可包括諸如矽化鈦(TiSi)、矽化鎢(WSi)、矽化鉭(TaSi)、矽化鈷(CoSi)、矽化鉑(PtSi)、矽化鎳(NiSi)、或以上各項之組合等的金屬矽化物。在某些實施例中，該金屬層可包括諸如氮化矽鈦(TiSiN)、或氮化矽鉭(TaSiN)、或以上各項之組合等的金屬矽氮化物。在某些實施例中，該金屬層可包括諸如碳化鈦(TiC)、碳化鋯(ZrC)、碳化鉭(TaC)、碳化鉿(HfC)、或碳化鋁(AlC)、或以上各項之組合等的 金屬碳化物。在某些實施例中，該金屬層可包括諸如氮化鉭碳(TaCN)、氮化鈦碳(TiCN)、或以上各項之組合等的金屬碳氮化物。在某些實施例中，該金屬層可包括一導電金屬氧化物(例如，氧化釕)。 The metal can include any suitable metal. For example, in certain embodiments, the metal may include copper (Cu), gold (Au), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), nickel (Ni), cobalt ( Co), rhodium (Rh), ruthenium (Ru), palladium (Pd), hafnium (Hf), zirconium (Zr), or aluminum (Al), or a combination of the above. In some embodiments, the metal layer can include a metal nitride such as titanium nitride (TiN), tungsten nitride (WN), or tantalum nitride (TaN), or a combination of the above. In some embodiments, the metal layer may include, for example, titanium telluride (TiSi), tungsten telluride (WSi), tantalum telluride (TaSi), cobalt telluride (CoSi), platinum telluride (PtSi), nickel telluride (NiSi), or A metal halide of a combination of the above. In some embodiments, the metal layer can include a metal tantalum nitride such as titanium germanium nitride (TiSiN), or tantalum nitride (TaSiN), or a combination thereof. In certain embodiments, the metal layer may include, for example, titanium carbide (TiC), zirconium carbide (ZrC), tantalum carbide (TaC), tantalum carbide (HfC), or aluminum carbide (AlC), or a combination thereof. Wait Metal carbide. In certain embodiments, the metal layer can include a metal carbonitride such as tantalum nitride carbon (TaCN), titanium nitride carbon (TiCN), or a combination of the above. In certain embodiments, the metal layer can include a conductive metal oxide (eg, hafnium oxide).

在某些實施例中，在該等溝槽開口及該等通孔開口中形成了該金屬之後，可研磨該IC結構的頂面。該研磨製程可移除該硬遮罩層的剩餘部分以及被配置在該等溝槽開口之上的任何過量之金屬。該研磨製程可包括諸如使用被設計成移除該IC結構中使用的該等金屬的一研磨液之化學機械研磨。 In some embodiments, the top surface of the IC structure can be ground after the metal is formed in the trench openings and the via openings. The polishing process removes the remainder of the hard mask layer and any excess metal disposed over the trench openings. The polishing process can include, for example, chemical mechanical polishing using a slurry designed to remove the metals used in the IC structure.

第4D圖示出在方塊312之後的IC結構400，且示出被配置在該等開口410a-b中之一金屬412。在第4D圖所示之面中，金屬412形成開口410b中之一溝槽414b、以及開口410a中之一溝槽414a及一通孔416。已研磨了IC結構400的頂面，以便移除硬遮罩層408的剩餘部分以及該等開口410a-b之上的任何過量之金屬412。 The 4D diagram shows the IC structure 400 after block 312 and shows one of the metals 412 disposed in the openings 410a-b. In the face shown in FIG. 4D, metal 412 forms one of trenches 414b in opening 410b, and one of trenches 414a and a via 416 in opening 410a. The top surface of the IC structure 400 has been ground to remove the remainder of the hard mask layer 408 and any excess metal 412 over the openings 410a-b.

在方塊314中，方法300可包含移除該犧牲層。可以諸如濕式清洗等的任何適當的製程移除該犧牲層。 At block 314, method 300 can include removing the sacrificial layer. The sacrificial layer can be removed by any suitable process such as wet cleaning.

第4E圖示出在方塊314之後的IC結構400，且示出已移除了(諸如該等溝槽414a-b之間的)犧牲層406。 4E illustrates the IC structure 400 after block 314 and shows that the sacrificial layer 406 has been removed (such as between the trenches 414a-b).

在方塊316中，方法300可包含：在該第一ILD層上(例如，在該金屬形成的該等溝槽之間)形成一第二ILD層。該第二ILD層可具有比該第一ILD層高的多孔性及/或低的密度。該第二ILD層可額外地或替代地具有比該 第一ILD層低的介電常數(K)。例如，在某些實施例中，該第二ILD層可包含諸如具有一可控制的多孔性(例如，50%多孔性)之矽的碳摻雜氧化物(CDO)等的一多孔之低K值介電材料。在某些實施例中，該第二ILD層可具有與該第一ILD層相同的材料成分，但是可能有較高的多孔性及/或較低的密度。在其他實施例中，該第二ILD層可以是與該第一ILD層不同的材料。 At block 316, method 300 can include forming a second ILD layer on the first ILD layer (eg, between the trenches formed by the metal). The second ILD layer can have a higher porosity and/or a lower density than the first ILD layer. The second ILD layer may additionally or alternatively have a ratio The first ILD layer has a low dielectric constant (K). For example, in certain embodiments, the second ILD layer can comprise a low porosity such as carbon doped oxide (CDO) having a controlled porosity (eg, 50% porosity). K value dielectric material. In some embodiments, the second ILD layer can have the same material composition as the first ILD layer, but may have a higher porosity and/or a lower density. In other embodiments, the second ILD layer can be a different material than the first ILD layer.

可以諸如一旋塗(spin-on)製程或諸如化學氣相沈積(CVD)等的一沈積製程等的任何適當的製程在該第一ILD層上形成該第二ILD層。在某些實施例中，該CVD製程導致的孔洞(voiding)可提供所形成的該第二ILD層之較低的K值。在某些實施例中，可以超載的ILD材料填滿該等溝槽間之開口，而形成該第二ILD層，然後可將過量的ILD材料研磨或凹下到適當的高度(例如，到該等溝槽的高度)。 The second ILD layer may be formed on the first ILD layer by any suitable process such as a spin-on process or a deposition process such as chemical vapor deposition (CVD). In some embodiments, the voiding caused by the CVD process provides a lower K value for the second ILD layer formed. In some embodiments, an overloaded ILD material can fill the openings between the trenches to form the second ILD layer, and then the excess ILD material can be ground or recessed to an appropriate height (eg, to the The height of the groove).

該第一ILD層可提供該等溝槽的結構支持，而該第二ILD層可防止/減少該等溝槽間之電容。 The first ILD layer can provide structural support for the trenches, and the second ILD layer can prevent/reduce the capacitance between the trenches.

第4F圖示出在方塊316之後的IC結構400。在第一ILD層402上(例如，在該等溝槽414a-b之間)配置一第二ILD層418。可在第一ILD層402上(例如，除了通孔被配置在溝槽之下的情況之外)配置該等溝槽414a-b。如第4F圖的面所示，溝槽414b被配置在第一ILD層402上，且溝槽414a被配置在通孔416上。 FIG. 4F shows the IC structure 400 after block 316. A second ILD layer 418 is disposed on the first ILD layer 402 (eg, between the trenches 414a-b). The trenches 414a-b may be disposed on the first ILD layer 402 (e.g., except where vias are disposed under the trenches). As shown in the face of FIG. 4F, the trench 414b is disposed on the first ILD layer 402, and the trench 414a is disposed on the via 416.

在某些實施例中，在方塊318中，方法300可進一步 包含：在該第二ILD層及/或各溝槽上形成一或多個額外的層。例如，可在該第二ILD層及/或各溝槽上形成一蝕刻終止層。可在該蝕刻終止層上形成諸如另一互連層等的額外的層。 In some embodiments, in block 318, method 300 can be further Including: forming one or more additional layers on the second ILD layer and/or each trench. For example, an etch stop layer can be formed on the second ILD layer and/or each trench. Additional layers such as another interconnect layer may be formed on the etch stop layer.

第4G圖示出具有被配置在第二ILD層418及溝槽414a-b上的一蝕刻終止層420之IC結構400。 FIG. 4G illustrates an IC structure 400 having an etch stop layer 420 disposed on the second ILD layer 418 and trenches 414a-b.

在各實施例中，方法300及/或IC結構400可提供勝過先前的方法及/或IC結構之一或多個優點。在某些實施例中，該犧牲材料(例如，犧牲層406的材料)可具有比該第二ILD層(例如，第二ILD層418)的材料更好的圖案保真度。例如，該犧牲材料可比該第二ILD層的材料更稠密，以便能夠有較佳的圖案保真度。額外地或替代地，在產生圖案及金屬化期間，方法300及/或IC結構400可以不將孔填充材料用於填充該第二ILD層的孔，而保持該第二ILD層的結構，這是因為在產生圖案及金屬化之後才形成該第二ILD層。 In various embodiments, method 300 and/or IC structure 400 may provide one or more advantages over previous methods and/or IC structures. In some embodiments, the sacrificial material (eg, the material of the sacrificial layer 406) can have better pattern fidelity than the material of the second ILD layer (eg, the second ILD layer 418). For example, the sacrificial material can be denser than the material of the second ILD layer to enable better pattern fidelity. Additionally or alternatively, during patterning and metallization, method 300 and/or IC structure 400 may not use a hole fill material to fill the holes of the second ILD layer while maintaining the structure of the second ILD layer, which This is because the second ILD layer is formed after patterning and metallization.

額外地或替代地，在該第二ILD層及/或該等溝槽之下配置該第一ILD層可能優於使用取代犧牲層406及第一ILD層402之單一犧牲材料；在形成了該等溝槽及通孔之後，移除該犧牲材料；以及然後在該等溝槽之下以及該等溝槽之間，以一取代ILD回填。例如，與在該等溝槽之下配置該第二ILD材料相比時，該第一ILD層可提供該等溝槽的較佳之結構支持，可無須在該等溝槽之下執行可能損及該等溝槽之蝕刻及回填，且/或可提供用於形成該等 溝槽開口(例如，如參照方塊308所述的形成溝槽開口)的一蝕刻終止層，以便能夠形成該等溝槽的一致且受控制之深度。 Additionally or alternatively, arranging the first ILD layer under the second ILD layer and/or the trenches may be superior to using a single sacrificial material in place of the sacrificial layer 406 and the first ILD layer 402; After the trenches and vias are removed, the sacrificial material is removed; and then, under the trenches and between the trenches, backfilled with a replacement ILD. For example, when the second ILD material is disposed under the trenches, the first ILD layer can provide better structural support for the trenches without performing damage to the trenches. Etching and backfilling of the trenches and/or may be provided for forming such An etch stop layer of trench openings (e.g., forming trench openings as described with reference to block 308) is capable of forming a uniform and controlled depth of the trenches.

在各實施例中，可將一第一ILD層上的一犧牲材料用於產生互連結構的圖案及金屬化且然後以一第二ILD層取代該犧牲材料之技術(例如，如前文中參照第3及4圖所述的)與用於形成互連層的其他技術結合。例如，可將此類技術與分別產生交替的溝槽之圖案且使該等溝槽金屬化之雙金屬化製程及/或在該等溝槽及/或間隔物上使用多種硬遮罩材料的(諸如用於減輕該等溝槽間之短路的)一製程結合。 In various embodiments, a sacrificial material on a first ILD layer can be used to create a pattern of interconnect structures and metallization and then replace the sacrificial material with a second ILD layer (eg, as previously described herein) The features described in Figures 3 and 4 are combined with other techniques for forming interconnect layers. For example, such techniques can be used with bimetallization processes that respectively create patterns of alternating trenches and metallize the trenches and/or use a variety of hard mask materials on the trenches and/or spacers. A process bonding (such as to mitigate shorting between the trenches).

第5圖是用於根據各實施例而使用分別產生交替的溝槽之圖案且使該等溝槽金屬化之雙金屬化製程形成具有一取代ILD層的一IC結構的一方法500之一流程圖。第6A-6L圖根據各實施例而以示意方式示出一IC結構600在方法500的各階段之橫斷面側視圖。因此，下文中將參照第6A-6L圖而說明方法500。為了便於圖示，在第6A-6L圖的每一圖中，並非每一元件都標示了一參考編號。 5 is a flow diagram of a method 500 for forming an IC structure having a substituted ILD layer using a dual metallization process that produces alternating trench patterns and metallizes the trenches, respectively, in accordance with various embodiments. Figure. 6A-6L show, in schematic form, a cross-sectional side view of an IC structure 600 at various stages of method 500, in accordance with various embodiments. Accordingly, method 500 will be described hereinafter with reference to Figures 6A-6L. For ease of illustration, not every component is labeled with a reference number in each of Figures 6A-6L.

可將與本發明所述的那些製造原理類似之製造原理用於形成具有與第6A-6L圖所示的組態不同之其他組態之IC結構。在某些實施例中，IC結構600可對應於包含一或多個互連結構(例如，溝槽或通孔)的一互連層。 Manufacturing principles similar to those described in the present invention can be used to form IC structures having other configurations than those shown in Figures 6A-6L. In some embodiments, IC structure 600 can correspond to an interconnect layer that includes one or more interconnect structures (eg, trenches or vias).

在方塊502中，方法500可包含：提供包含被配置在一下方層上的一第一ILD層、被配置在該第一ILD層上 的一犧牲層、以及被配置在該犧牲層上的一硬遮罩層之一IC結構。可諸如根據前文所述的方法300之方塊302、304、及306而形成該IC結構。 At block 502, method 500 can include providing a first ILD layer disposed on a lower layer, configured on the first ILD layer a sacrificial layer, and an IC structure of a hard mask layer disposed on the sacrificial layer. The IC structure can be formed, such as in accordance with blocks 302, 304, and 306 of method 300 described above.

第6A圖示出包含在一下方層604上形成的一第一ILD層602、在第一ILD層602上形成的一犧牲層606、以及在該犧牲材料之上形成的一硬遮罩層608之IC結構600。 6A illustrates a first ILD layer 602 formed on a lower layer 604, a sacrificial layer 606 formed over the first ILD layer 602, and a hard mask layer 608 formed over the sacrificial material. The IC structure 600.

在方塊504中，方法500可包含：蝕刻該硬遮罩層的一些部分，而在該硬遮罩層中形成一些開口。 At block 504, method 500 can include etching portions of the hard mask layer and forming openings in the hard mask layer.

第6B圖示出藉由蝕刻移除硬遮罩層608的一些部分而形成開口610a-c之IC結構600。 FIG. 6B illustrates an IC structure 600 that forms openings 610a-c by etching portions of the hard mask layer 608.

在方塊506中，方法500可包含：在該硬遮罩層中之該等開口的側面上形成間隔物。該等間隔物可被耦合到該等開口中之該硬遮罩層的側壁。該等間隔物可以是具有所需的蝕刻選擇性之任何適當的耐蝕刻材料，例如，過渡金屬氧化物或氮化物、或諸如氮化矽(SiN)等的介電材料。 At block 506, method 500 can include forming spacers on sides of the openings in the hard mask layer. The spacers can be coupled to the sidewalls of the hard mask layer in the openings. The spacers can be any suitable etch resistant material having the desired etch selectivity, such as a transition metal oxide or nitride, or a dielectric material such as tantalum nitride (SiN).

第6C圖示出具有被配置在開口610a-c的該等側面上的間隔物612之IC結構600。 Figure 6C shows an IC structure 600 having spacers 612 disposed on the sides of the openings 610a-c.

在方塊508中，方法500可包含：在第一組溝槽的犧牲層中形成第一組溝槽開口。例如，可移除特定開口的各間隔物之間的犧牲材料部分，而形成該等溝槽開口。因此，在該等間隔物之間，該等開口可向下延伸到該第一ILD層。 At block 508, method 500 can include forming a first set of trench openings in the sacrificial layer of the first set of trenches. For example, portions of the sacrificial material between the spacers of a particular opening can be removed to form the trench openings. Thus, between the spacers, the openings may extend down to the first ILD layer.

第6D圖示出在每一開口610a-c的該等側面上的該等間隔物612之間的該等開口610a-c向下延伸到第一ILD層602之IC結構600。 FIG. 6D illustrates the openings 610a-c between the spacers 612 on the sides of each opening 610a-c extending down to the IC structure 600 of the first ILD layer 602.

在方塊510中，方法500可包含：在該第一組溝槽開口中之一或多個溝槽開口之下的該第一ILD層中形成通孔開口。該等通孔開口可被稱為第一組通孔開口。 At block 510, method 500 can include forming a via opening in the first ILD layer below one or more of the trench openings in the first set of trench openings. The through hole openings may be referred to as a first set of through hole openings.

第6E圖示出第一ILD層602在開口610c中之部分被移除而形成一通孔開口之IC結構600。 FIG. 6E illustrates an IC structure 600 in which a portion of the first ILD layer 602 is removed in the opening 610c to form a via opening.

在方塊512中，方法500可包含：在該第一組溝槽開口及該第一組通孔開口中形成一金屬(例如，金屬化)。在某些實施例中，在形成了該金屬之後，可研磨該IC結構的頂面。在該研磨之後，該等間隔物及/或該硬遮罩層的各部分可繼續存在。 At block 512, method 500 can include forming a metal (eg, metallization) in the first set of trench openings and the first set of via openings. In some embodiments, the top surface of the IC structure can be ground after the metal is formed. After the grinding, the spacers and/or portions of the hard mask layer may continue to exist.

第6F圖示出具有在開口610a-c中形成的一金屬614之IC結構600。 Figure 6F shows an IC structure 600 having a metal 614 formed in openings 610a-c.

在方塊514中，方法500可包含：在第二組溝槽的犧牲層中形成第二組溝槽開口。例如，可移除該硬遮罩層的剩餘部分，且移除該犧牲層在該硬遮罩層的該等剩餘部分之下的部分，而形成該第二組溝槽開口。因此，該第二組溝槽開口可與該第一組溝槽開口相間。 At block 514, method 500 can include forming a second set of trench openings in the sacrificial layer of the second set of trenches. For example, the remaining portion of the hard mask layer can be removed and the portion of the sacrificial layer below the remaining portions of the hard mask layer removed to form the second set of trench openings. Thus, the second set of trench openings can be spaced apart from the first set of trench openings.

第6G圖示出具有犧牲層606中之開口616a-d之IC結構600。 FIG. 6G illustrates an IC structure 600 having openings 616a-d in the sacrificial layer 606.

在方塊516中，方法500可包含：在該第二組溝槽開口中之一或多個溝槽開口之下的該第一ILD層中形成通孔 開口。該等通孔開口可被稱為第二組通孔開口。 At block 516, method 500 can include forming a via in the first ILD layer below one or more trench openings in the second set of trench openings Opening. The through hole openings may be referred to as a second set of through hole openings.

第6H圖示出第一ILD層602在開口616b中之部分被移除而形成一通孔開口之IC結構600。 FIG. 6H illustrates an IC structure 600 in which a portion of the first ILD layer 602 is removed in the opening 616b to form a via opening.

在方塊518中，方法500可包含：在該第二組溝槽開口及該第二組通孔開口中形成一金屬(例如，金屬化)。在某些實施例中，在形成了該金屬之後，可研磨該IC結構的頂面。該研磨可移除該等間隔物以及方塊512中在該等間隔物之間形成的金屬。 At block 518, method 500 can include forming a metal (eg, metallization) in the second set of trench openings and the second set of via openings. In some embodiments, the top surface of the IC structure can be ground after the metal is formed. The grinding removes the spacers and the metal formed between the spacers in block 512.

第6I圖示出在方塊518之後的IC結構600，圖中示出在開口616a-d中形成之金屬614。已(諸如利用研磨)移除了該等間隔物612。 Figure 6I shows IC structure 600 after block 518, showing metal 614 formed in openings 616a-d. The spacers 612 have been removed (such as with grinding).

在方塊520中，方法500可包含：移除剩餘的犧牲材料(例如，被配置在該等間隔物之下的犧牲材料)。犧牲材料的該移除可留下該等溝槽間之開口。第6J圖示出犧牲層606被移除之IC結構600，且示出各溝槽間之開口。 At block 520, method 500 can include removing remaining sacrificial material (eg, sacrificial material disposed under the spacers). This removal of the sacrificial material can leave an opening between the grooves. Figure 6J shows the IC structure 600 with the sacrificial layer 606 removed, and shows the openings between the trenches.

在方塊522中，方法500可包含：在該等溝槽之間的該第一ILD層上形成一第二ILD層。第6K圖示出包含在該等溝槽之間的一第二ILD層618之IC結構600。 At block 522, method 500 can include forming a second ILD layer on the first ILD layer between the trenches. Figure 6K shows an IC structure 600 of a second ILD layer 618 included between the trenches.

在方塊524中，方法500可包含：在該第二ILD層及/或該等溝槽上形成一蝕刻終止層。第6L圖示出包含在第二ILD層618上的一蝕刻終止層620之IC結構600。 At block 524, method 500 can include forming an etch stop layer on the second ILD layer and/or the trenches. FIG. 6L illustrates an IC structure 600 of an etch stop layer 620 included on the second ILD layer 618.

第7A及7B圖根據各實施例而提供了示出利用一使用該等溝槽及/或間隔物上的多個硬遮罩材料的製程而形 成具有一取代ILD層的一IC結構的一方法700之一流程圖。方法700也使用類似於方法500的該雙金屬化製程之雙金屬化製程。第8A-8R圖根據各實施例而以示意方式示出一IC結構800在方法700的各階段之橫斷面側視圖。因此，下文中將參照第8A-8R圖而說明方法700。為了便於圖示，在第8A-8R圖的每一圖中，並非每一元件都標示了一參考編號。 7A and 7B are diagrams showing the use of a process for using a plurality of hard mask materials on the trenches and/or spacers, in accordance with various embodiments. A flow chart of a method 700 of forming an IC structure having a replacement ILD layer. The method 700 also uses a dual metallization process similar to the dual metallization process of method 500. 8A-8R are schematic cross-sectional side views of an IC structure 800 at various stages of method 700, in accordance with various embodiments. Accordingly, method 700 will be described hereinafter with reference to Figures 8A-8R. For ease of illustration, not every component is labeled with a reference number in each of Figures 8A-8R.

可將與本發明所述的那些製造原理類似之製造原理用於形成具有與第8A-8R圖所示的組態不同之其他組態之IC結構。在某些實施例中，IC結構800可對應於包含一或多個互連結構(例如，溝槽或通孔)的一互連層。 Manufacturing principles similar to those described in the present invention can be used to form IC structures having other configurations than those shown in Figures 8A-8R. In some embodiments, IC structure 800 can correspond to an interconnect layer that includes one or more interconnect structures (eg, trenches or vias).

在各實施例中，方法700的方塊702、704、706、708、710、712、714、及716可類似於方法500的各別方塊502、504、506、508、510、512、514、及516。在方塊702中，方法700可包含：提供包含被配置在一下方層上的一第一ILD層、被配置在該第一ILD層上的一犧牲層、以及被配置在該犧牲層上的一硬遮罩層之一IC結構。可諸如根據前文所述的方法300之方塊302、304、及306而形成該IC結構。該犧牲層可包含一第一犧牲材料。 In various embodiments, blocks 702, 704, 706, 708, 710, 712, 714, and 716 of method 700 can be similar to respective blocks 502, 504, 506, 508, 510, 512, 514 of method 500, and 516. At block 702, method 700 can include providing a first ILD layer disposed on a lower layer, a sacrificial layer disposed on the first ILD layer, and a first one disposed on the sacrificial layer One of the hard mask layers of the IC structure. The IC structure can be formed, such as in accordance with blocks 302, 304, and 306 of method 300 described above. The sacrificial layer can comprise a first sacrificial material.

第8A圖示出包含在一下方層804上形成的一第一ILD層802、在第一ILD層802上形成的一犧牲層806、以及在該犧牲材料之上形成的一硬遮罩層808之IC結構800。 8A illustrates a first ILD layer 802 formed on a lower layer 804, a sacrificial layer 806 formed over the first ILD layer 802, and a hard mask layer 808 formed over the sacrificial material. The IC structure 800.

在方塊704中，方法700可包含：蝕刻該硬遮罩層的一些部分，而在該硬遮罩層中形成一些開口。 At block 704, method 700 can include etching portions of the hard mask layer and forming openings in the hard mask layer.

第8B圖示出藉由蝕刻移除硬遮罩層808的一些部分而形成開口810a-c之IC結構800。 FIG. 8B illustrates an IC structure 800 that forms openings 810a-c by etching portions of the hard mask layer 808.

在方塊706中，方法700可包含：在該硬遮罩層中之該等開口的側面上形成間隔物。該等間隔物可被耦合到該等開口中之該硬遮罩層的側壁。該等間隔物可以是具有所需的蝕刻選擇性之任何適當的耐蝕刻材料，例如，過渡金屬氧化物或氮化物、或諸如氮化矽(SiN)等的介電材料。 At block 706, method 700 can include forming spacers on sides of the openings in the hard mask layer. The spacers can be coupled to the sidewalls of the hard mask layer in the openings. The spacers can be any suitable etch resistant material having the desired etch selectivity, such as a transition metal oxide or nitride, or a dielectric material such as tantalum nitride (SiN).

第8C圖示出具有被配置在開口810a-c的該等側面上的間隔物812之IC結構800。 Figure 8C shows an IC structure 800 having spacers 812 disposed on the sides of the openings 810a-c.

在方塊708中，方法700可包含：在第一組溝槽的犧牲層中形成第一組溝槽開口。例如，可移除特定開口的各間隔物之間的犧牲材料部分，而形成該等溝槽開口。因此，在該等間隔物之間，該等開口可向下延伸到該第一ILD層。 At block 708, method 700 can include forming a first set of trench openings in the sacrificial layer of the first set of trenches. For example, portions of the sacrificial material between the spacers of a particular opening can be removed to form the trench openings. Thus, between the spacers, the openings may extend down to the first ILD layer.

第8D圖示出在每一開口810a-c的該等側面上的該等間隔物812之間的該等開口810a-c向下延伸到第一ILD層802之IC結構800。 8D illustrates the openings 810a-c between the spacers 812 on the sides of each opening 810a-c extending down to the IC structure 800 of the first ILD layer 802.

在方塊710中，方法700可包含：在該第一組溝槽開口中之一或多個溝槽開口之下的該第一ILD層中形成通孔開口。該等通孔開口可被稱為第一組通孔開口。 At block 710, method 700 can include forming a via opening in the first ILD layer below one or more of the trench openings in the first set of trench openings. The through hole openings may be referred to as a first set of through hole openings.

第8E圖示出第一ILD層802在開口810c中之部分被 移除而形成一通孔開口之IC結構800。 Figure 8E shows a portion of the first ILD layer 802 in the opening 810c being The IC structure 800 is removed to form a via opening.

在方塊712中，方法700可包含：在該第一組溝槽開口及該第一組通孔開口中形成一金屬(例如，金屬化)。在某些實施例中，在形成了該金屬之後，可研磨該IC結構的頂面。在該研磨之後，該等間隔物及/或該硬遮罩層的各部分可繼續存在。 At block 712, method 700 can include forming a metal (eg, metallization) in the first set of trench openings and the first set of via openings. In some embodiments, the top surface of the IC structure can be ground after the metal is formed. After the grinding, the spacers and/or portions of the hard mask layer may continue to exist.

第8F圖示出具有在開口810a-c中形成的一金屬814之IC結構800。 Figure 8F shows an IC structure 800 having a metal 814 formed in openings 810a-c.

在方塊714中，方法700可包含：在第二組溝槽的犧牲層中形成第二組溝槽開口。例如，可移除該硬遮罩層的剩餘部分，且移除該犧牲層在該硬遮罩層的該等剩餘部分之下的部分，而形成該第二組溝槽開口。因此，該第二組溝槽開口可與該第一組溝槽開口相間。 At block 714, method 700 can include forming a second set of trench openings in the sacrificial layer of the second set of trenches. For example, the remaining portion of the hard mask layer can be removed and the portion of the sacrificial layer below the remaining portions of the hard mask layer removed to form the second set of trench openings. Thus, the second set of trench openings can be spaced apart from the first set of trench openings.

第8G圖示出具有犧牲層806中之開口816a-d之IC結構800。 FIG. 8G illustrates an IC structure 800 having openings 816a-d in the sacrificial layer 806.

在方塊716中，方法700可包含：在該第二組溝槽開口中之一或多個溝槽開口之下的該第一ILD層中形成通孔開口。該等通孔開口可被稱為第二組通孔開口。 At block 716, method 700 can include forming a via opening in the first ILD layer below one or more of the trench openings in the second set of trench openings. The through hole openings may be referred to as a second set of through hole openings.

第8H圖示出第一ILD層802在開口816b中之部分被移除而形成一通孔開口之IC結構800。 FIG. 8H illustrates an IC structure 800 in which a portion of the first ILD layer 802 is removed in the opening 816b to form a via opening.

在方塊718中，方法700可包含：在該第二組溝槽開口及該第二組通孔開口中形成(例如，沈積或填充)一第二犧牲材料。該第二犧牲材料可以不同於該第一ILD層上形成的該犧牲層之該第一犧牲材料。如將於下文中進一步 說明的，該第二犧牲材料可被用來作為使該第一組溝槽開口中之金屬凹下的一遮罩(例如，硬遮罩)，且可耐受方塊720中被用於使該金屬凹下的製程(例如，不被該製程移除)。例如，該第二犧牲材料可包括諸如CDO等的一旋塗介電質、或非晶碳、或過渡金屬的氮化物或氧化物。 At block 718, method 700 can include forming (eg, depositing or filling) a second sacrificial material in the second set of trench openings and the second set of via openings. The second sacrificial material may be different from the first sacrificial material of the sacrificial layer formed on the first ILD layer. As will be further below Illustratively, the second sacrificial material can be used as a mask (eg, a hard mask) that recesses the metal in the first set of trench openings, and can be tolerated in block 720 for use in The metal recessed process (eg, not removed by the process). For example, the second sacrificial material may comprise a spin-on dielectric such as CDO, or an amorphous carbon, or a transition metal nitride or oxide.

第8I圖示出具有被配置在開口816a-d中之一第二犧牲材料818之IC結構800。 FIG. 8I illustrates an IC structure 800 having a second sacrificial material 818 disposed in one of the openings 816a-d.

在方塊720中，方法700可包含：使被配置在該第一組溝槽開口中之該金屬凹下。例如，可以一蝕刻製程移除該第一組溝槽開口中之該金屬的頂部。可使該金屬凹下到低於該犧牲層的頂面之高度。該第二犧牲材料可保護該第一ILD層不受該蝕刻製程的影響。 At block 720, method 700 can include recessing the metal disposed in the first set of trench openings. For example, the top of the metal in the first set of trench openings can be removed by an etch process. The metal can be recessed to a height below the top surface of the sacrificial layer. The second sacrificial material protects the first ILD layer from the etching process.

第8J圖示出開口810a-c中之金屬814被凹下到低於犧牲層806的頂面的高度之IC結構800。 8J illustrates an IC structure 800 in which the metal 814 in the openings 810a-c is recessed to a lower level than the top surface of the sacrificial layer 806.

在方塊722中，方法700可包含：在該第一組溝槽開口中之該被凹下的金屬上形成一第一硬遮罩材料。然後可研磨該IC結構的頂面，而移除該等間隔物。 At block 722, method 700 can include forming a first hard mask material on the recessed metal in the first set of trench openings. The top surface of the IC structure can then be ground while the spacers are removed.

第8K圖示出一第一硬遮罩材料820被配置在金屬814上且該頂面被研磨而移除該等間隔物812之IC結構800。 FIG. 8K illustrates an IC structure 800 in which a first hard mask material 820 is disposed on metal 814 and the top surface is ground to remove the spacers 812.

在方塊724中，方法700可包含：自該第二組溝槽開口及該第二組通孔開口移除該第二犧牲材料。第8L圖示出自開口816a-d移除第二犧牲材料818之IC結構800。 At block 724, method 700 can include removing the second sacrificial material from the second set of trench openings and the second set of via openings. FIG. 8L illustrates the IC structure 800 with the second sacrificial material 818 removed from the openings 816a-d.

在方塊726中，方法700可包含：在該第二組溝槽開 口及該第二組通孔開口中形成一金屬。第8M圖示出具有被配置在該等開口816a-d中之金屬814之IC結構800。 At block 726, method 700 can include: opening the second set of trenches A metal is formed in the opening and the opening of the second set of through holes. Figure 8M shows an IC structure 800 having a metal 814 disposed in the openings 816a-d.

在方塊728中，方法700可包含：使被配置在該第二組溝槽開口中之該金屬凹下。例如，可以一蝕刻製程移除該第二組溝槽開口中之該金屬的頂部。第8N圖示出使開口816a-d中之金屬814凹下之IC結構800。 At block 728, method 700 can include recessing the metal disposed in the second set of trench openings. For example, the top of the metal in the second set of trench openings can be removed by an etch process. The 8N figure shows the IC structure 800 that recesses the metal 814 in the openings 816a-d.

在方塊730中，方法700可包含：在該第二組溝槽開口中之該金屬上形成一第二硬遮罩材料。可在超填(overfill)之情形下沈積該第二硬遮罩材料，然後研磨該第二硬遮罩材料，使該第二硬遮罩材料的頂面與該第一硬遮罩材料及/或犧牲層的頂面實質上共平面。該第二硬遮罩材料可具有與該第一硬遮罩材料不同的蝕刻選擇性，而能夠在與該第一硬遮罩材料無關之情形下(例如，在不會蝕刻到該第一硬遮罩材料之情形下)蝕刻該第二硬遮罩材料。 At block 730, method 700 can include forming a second hard mask material on the metal in the second set of trench openings. The second hard mask material may be deposited in an overfill condition, and then the second hard mask material is ground to make the top surface of the second hard mask material and the first hard mask material and/or Or the top surface of the sacrificial layer is substantially coplanar. The second hard mask material can have a different etch selectivity than the first hard mask material, and can be independent of the first hard mask material (eg, without etching to the first hard In the case of a masking material, the second hard mask material is etched.

第8O圖示出具有被配置在開口816a-d中之金屬814上的一第二硬遮罩材料822之IC結構800。 FIG. 8O shows an IC structure 800 having a second hard mask material 822 disposed on metal 814 in openings 816a-d.

在方塊732中，方法700可包含：移除(諸如該等溝槽之間的)該犧牲層。移除該犧牲層之後，可露出該等溝槽之間的該第一ILD層。第8P圖示出移除犧牲層806且露出金屬814形成的該等溝槽之間的第一ILD層802之IC結構800。 At block 732, method 700 can include removing (such as between the trenches) the sacrificial layer. After removing the sacrificial layer, the first ILD layer between the trenches may be exposed. FIG. 8P illustrates an IC structure 800 in which the sacrificial layer 806 is removed and the first ILD layer 802 between the trenches formed by the metal 814 is exposed.

在方塊734中，方法700可包含：在該等溝槽之間的該第一ILD層上形成一第二ILD層。可形成及/或凹下 該第二ILD層，使該第二ILD層的頂面與該等溝槽的頂面實質上共平面。或者，該第二ILD層的頂面可高於該等溝槽的頂面。如將於本說明書中進一步說明的，該第二ILD層可以比該第一ILD層更具有多孔性。 At block 734, method 700 can include forming a second ILD layer on the first ILD layer between the trenches. Can be formed and/or recessed The second ILD layer has a top surface of the second ILD layer substantially coplanar with a top surface of the trenches. Alternatively, the top surface of the second ILD layer can be higher than the top surface of the trenches. As will be further explained in this specification, the second ILD layer can be more porous than the first ILD layer.

第8Q圖示出具有被配置在金屬814形成的該等溝槽之間的第一ILD層802上的一第二ILD層824之IC結構800。 The 8Q diagram shows an IC structure 800 having a second ILD layer 824 disposed on a first ILD layer 802 between the trenches formed by the metal 814.

在方塊736中，方法700可包含：在該第二ILD層上形成一第三硬遮罩材料。該第三硬遮罩材料可具有與該第一及/或第二硬遮罩材料不同的蝕刻選擇性，而能夠在與該第一及/或第二硬遮罩材料無關之情形下蝕刻(例如，移除)該第三硬遮罩材料。 At block 736, method 700 can include forming a third hard mask material on the second ILD layer. The third hard mask material can have a different etch selectivity than the first and/or second hard mask material, and can be etched regardless of the first and/or second hard mask material ( For example, removing the third hard mask material.

第8R圖示出具有被配置在第二ILD層824上的一第三硬遮罩材料826之IC結構800。該等硬遮罩材料820、822、及826可有助於形成IC結構800的各後續層與該等溝槽間之導電連接，且避免形成鄰近溝槽間之不需要的導電連接(例如，短路)。例如，可移除硬遮罩材料820，但不移除硬遮罩材料822及826，以便能夠形成與開口810a-c中之該等溝槽間之導電連接，且硬遮罩材料822及826阻擋了對開口816a-d中之該等溝槽的接觸。然後可移除第二硬遮罩材料822，以便能夠形成與開口816a-d中之該等溝槽間之導電連接。 FIG. 8R illustrates an IC structure 800 having a third hard mask material 826 disposed on the second ILD layer 824. The hard mask materials 820, 822, and 826 can help form an electrically conductive connection between each subsequent layer of the IC structure 800 and the trenches, and avoid the formation of unwanted conductive connections between adjacent trenches (eg, Short circuit). For example, the hard mask material 820 can be removed, but the hard mask materials 822 and 826 are not removed to enable the formation of an electrically conductive connection with the trenches in the openings 810a-c, and the hard mask materials 822 and 826 Contact to the grooves in openings 816a-d is blocked. The second hard mask material 822 can then be removed to enable an electrically conductive connection to the trenches in the openings 816a-d.

第9A及9B圖根據各實施例而提供了示出利用一使用該等溝槽及/或間隔物上的多個硬遮罩材料的製程而形 成具有一取代ILD層的一IC結構的另一方法900之一流程圖。方法900也使用類似於方法500及/或方法700的該雙金屬化製程之雙金屬化製程。第10A-10R圖根據各實施例而以示意方式示出一IC結構1000在方法900的各階段之橫斷面側視圖。因此，下文中將參照第10A-10R圖而說明方法900。可將與本發明所述的那些製造原理類似之製造原理用於形成具有與第10A-10R圖所示的組態不同之其他組態之IC結構。在某些實施例中，IC結構1000可對應於包含一或多個互連結構(例如，溝槽或通孔)的一互連層。 9A and 9B are diagrams showing the use of a process for using a plurality of hard mask materials on the trenches and/or spacers, in accordance with various embodiments. A flow chart of another method 900 of forming an IC structure having a replacement ILD layer. The method 900 also uses a dual metallization process similar to the method 500 and/or method 700 of the dual metallization process. 10A-10R are schematic cross-sectional side views of an IC structure 1000 at various stages of method 900, in accordance with various embodiments. Accordingly, method 900 will be described hereinafter with reference to Figures 10A-10R. Manufacturing principles similar to those described in the present invention can be used to form IC structures having other configurations than those shown in Figures 10A-10R. In some embodiments, IC structure 1000 can correspond to an interconnect layer that includes one or more interconnect structures (eg, trenches or vias).

在方法900中，可移除該第一ILD層的一部分(例如，可能被方法900的其他操作損壞的頂部)。在某些實施例中，該犧牲層可包括有助於方法900的一可濕式清洗之硬遮罩材料。 In method 900, a portion of the first ILD layer (eg, the top that may be damaged by other operations of method 900) may be removed. In some embodiments, the sacrificial layer can include a hard mask material that facilitates a wet cleaning of method 900.

在方塊902中，方法900可包含：提供包含被配置在一下方層上的一第一ILD層、被配置在該第一ILD層上的一犧牲層、以及被配置在該犧牲層上的一硬遮罩層之一IC結構。可諸如根據前文所述的方法300之方塊302、304、及306而形成該IC結構。該犧牲層可包含一第一犧牲材料。在某些實施例中，該第一犧牲材料可以是一可濕式清洗的硬遮罩材料。例如，該第一犧牲材料可以是諸如氮化鈦(TiN)等的一過渡金屬之氧化物或氮化物。 At block 902, method 900 can include providing a first ILD layer disposed on a lower layer, a sacrificial layer disposed on the first ILD layer, and a first one disposed on the sacrificial layer One of the hard mask layers of the IC structure. The IC structure can be formed, such as in accordance with blocks 302, 304, and 306 of method 300 described above. The sacrificial layer can comprise a first sacrificial material. In some embodiments, the first sacrificial material can be a wet-cleanable hard mask material. For example, the first sacrificial material may be an oxide or nitride of a transition metal such as titanium nitride (TiN).

第10A圖示出包含在一下方層1004上形成的一第一ILD層1002、在第一ILD層1002上形成的一犧牲層 1006、以及在該犧牲材料之上形成的一硬遮罩層1008之IC結構1000。 FIG. 10A illustrates a first ILD layer 1002 formed on a lower layer 1004, and a sacrificial layer formed on the first ILD layer 1002. 1006, and an IC structure 1000 of a hard mask layer 1008 formed over the sacrificial material.

在方塊904中，方法900可包含：蝕刻該硬遮罩層的一些部分，而在該硬遮罩層中形成一些開口。第10B圖示出藉由蝕刻移除硬遮罩層1008的一些部分而形成開口1010a-c之IC結構1000。 At block 904, method 900 can include etching portions of the hard mask layer and forming openings in the hard mask layer. FIG. 10B illustrates an IC structure 1000 that forms openings 1010a-c by etching portions of the hard mask layer 1008.

在方塊906中，方法900可包含：在該硬遮罩層中之該等開口的側面上形成間隔物。該等間隔物可被耦合到該等開口中之該硬遮罩層的側壁。該等間隔物可以是具有所需的蝕刻選擇性之任何適當的耐蝕刻材料，例如，過渡金屬氧化物或氮化物、或諸如氮化矽(SiN)等的介電材料。 At block 906, method 900 can include forming spacers on sides of the openings in the hard mask layer. The spacers can be coupled to the sidewalls of the hard mask layer in the openings. The spacers can be any suitable etch resistant material having the desired etch selectivity, such as a transition metal oxide or nitride, or a dielectric material such as tantalum nitride (SiN).

第10C圖示出具有被配置在開口1010a-c的該等側面上的間隔物1012之IC結構1000。 FIG. 10C illustrates an IC structure 1000 having spacers 1012 disposed on the sides of the openings 1010a-c.

在方塊908中，方法900可包含：在第一組溝槽的犧牲層中形成第一組溝槽開口。例如，可使該等間隔物間之該等開口凹下通過該犧牲層，且凹下到該第一ILD層，而形成該等溝槽開口。因此，在該等之間的該等開口界定的一水平區中，可移除該犧牲層及該第一ILD層的一部分。 At block 908, method 900 can include forming a first set of trench openings in the sacrificial layer of the first set of trenches. For example, the openings between the spacers may be recessed through the sacrificial layer and recessed into the first ILD layer to form the trench openings. Thus, the sacrificial layer and a portion of the first ILD layer can be removed in a horizontal region defined by the openings between the ones.

第10D圖示出在每一開口1010a-c的該等側面上的該等間隔物1012之間的該等開口1010a-c向下延伸到第一ILD層1002且該等開口1010a-c因而延伸到第一ILD層1002的頂面之下之IC結構1000。 10D shows that the openings 1010a-c between the spacers 1012 on the sides of each opening 1010a-c extend down to the first ILD layer 1002 and the openings 1010a-c thus extend The IC structure 1000 is below the top surface of the first ILD layer 1002.

在方塊910中，方法900可包含：在該第一組溝槽開 口中之一或多個溝槽開口之下的該第一ILD層中形成通孔開口。該等通孔開口可被稱為第一組通孔開口。第10E圖示出第一ILD層1002在開口1010c中之部分被移除而形成一通孔開口之IC結構1000。 At block 910, method 900 can include: opening the first set of trenches A via opening is formed in the first ILD layer below one or more of the trench openings. The through hole openings may be referred to as a first set of through hole openings. FIG. 10E illustrates an IC structure 1000 in which a portion of the first ILD layer 1002 is removed in the opening 1010c to form a via opening.

在方塊912中，方法900可包含：在該第一組溝槽開口及該第一組通孔開口中形成一金屬。在某些實施例中，在形成了該金屬之後，可研磨該IC結構的頂面。在該研磨之後，該等間隔物及/或該硬遮罩層的各部分可繼續存在。第10F圖示出具有在開口1010a-c中形成的一金屬1014之IC結構1000。 At block 912, method 900 can include forming a metal in the first set of trench openings and the first set of via openings. In some embodiments, the top surface of the IC structure can be ground after the metal is formed. After the grinding, the spacers and/or portions of the hard mask layer may continue to exist. FIG. 10F illustrates an IC structure 1000 having a metal 1014 formed in openings 1010a-c.

在方塊914中，方法900可包含：在第二組溝槽的犧牲層中形成第二組溝槽開口。例如，可移除該硬遮罩層的剩餘部分，且蝕刻掉該犧牲層以及該第一ILD層在該硬遮罩層的該等剩餘部分之下的部分(該等剩餘部分也被移除)，而形成該第二組溝槽開口。因此，該第二組溝槽開口可與該第一組溝槽開口相間。 At block 914, method 900 can include forming a second set of trench openings in the sacrificial layer of the second set of trenches. For example, the remaining portion of the hard mask layer can be removed and the sacrificial layer and portions of the first ILD layer below the remaining portions of the hard mask layer are etched away (the remaining portions are also removed) And forming the second set of trench openings. Thus, the second set of trench openings can be spaced apart from the first set of trench openings.

第10G圖示出具有延伸到第一ILD層1002的犧牲層1006中之開口1016a-d(例如，開口1016a-d延伸到第一ILD層1002的頂面之下)之IC結構1000。 FIG. 10G illustrates an IC structure 1000 having openings 1016a-d (eg, openings 1016a-d extending below the top surface of first ILD layer 1002) extending into sacrificial layer 1006 of first ILD layer 1002.

在方塊916中，方法900可包含：在該第二組溝槽開口中之一或多個溝槽開口之下的該第一ILD層中形成通孔開口。該等通孔開口可被稱為第二組通孔開口。第10H圖示出第一ILD層1002在開口1016b中之部分被移除而形成一通孔開口之IC結構1000。 At block 916, method 900 can include forming a via opening in the first ILD layer below one or more of the trench openings in the second set of trench openings. The through hole openings may be referred to as a second set of through hole openings. FIG. 10H illustrates an IC structure 1000 in which a portion of the first ILD layer 1002 is removed in the opening 1016b to form a via opening.

在方塊918中，方法900可包含：在該第二組溝槽開口及該第二組通孔開口中形成一第二犧牲材料。該第二犧牲材料可以不同於該第一ILD層上形成的該犧牲層之該第一犧牲材料。如將於下文中進一步說明的，該第二犧牲材料可被用來作為使該第一組溝槽開口中之金屬凹下的一遮罩(例如，硬遮罩)，且可耐受方塊920中被用於使該金屬凹下的製程(例如，不被該製程移除)。例如，該第二犧牲材料可包括一介電質或一碳基材料(carbon-based material)。 At block 918, method 900 can include forming a second sacrificial material in the second set of trench openings and the second set of via openings. The second sacrificial material may be different from the first sacrificial material of the sacrificial layer formed on the first ILD layer. As will be explained further below, the second sacrificial material can be used as a mask (eg, a hard mask) that recesses the metal in the first set of trench openings and can withstand block 920. The process used to recess the metal (eg, not removed by the process). For example, the second sacrificial material can comprise a dielectric or a carbon-based material.

第10I圖示出具有被配置在開口1016a-d中之一第二犧牲材料1018之IC結構1000。 FIG. 10I illustrates an IC structure 1000 having a second sacrificial material 1018 disposed in one of the openings 1016a-d.

在方塊920中，方法900可包含：使被配置在該第一組溝槽開口中之該金屬凹下。例如，可以一蝕刻製程移除該第一組溝槽開口中之該金屬的頂部。可使該金屬凹下到低於該犧牲層(例如，低於該第一ILD層的頂面)之高度。 At block 920, method 900 can include recessing the metal disposed in the first set of trench openings. For example, the top of the metal in the first set of trench openings can be removed by an etch process. The metal can be recessed below the height of the sacrificial layer (eg, below the top surface of the first ILD layer).

第10J圖示出開口1010a-c中之金屬1014被凹下到低於犧牲層1006且低於第一ILD層1002的頂面的高度之IC結構1000。 FIG. 10J illustrates the IC structure 1000 in which the metal 1014 in the openings 1010a-c is recessed below the sacrificial layer 1006 and below the top surface of the first ILD layer 1002.

在方塊922中，方法900可包含：在該第一組溝槽開口中之該金屬上形成一第一硬遮罩材料。然後可研磨該IC結構的頂面，而移除該等間隔物。 At block 922, method 900 can include forming a first hard mask material on the metal in the first set of trench openings. The top surface of the IC structure can then be ground while the spacers are removed.

第10K圖示出一第一硬遮罩材料1020被配置在金屬1014上且該頂面被研磨而移除該等間隔物1012之IC結 構1000。 FIG. 10K illustrates a first hard mask material 1020 disposed on the metal 1014 and the top surface being ground to remove the IC junction of the spacers 1012. Structure 1000.

在方塊924中，方法900可包含：自該第二組溝槽開口及該第二組通孔開口移除該第二犧牲材料。 At block 924, method 900 can include removing the second sacrificial material from the second set of trench openings and the second set of via openings.

第10L圖示出自開口1016a-d移除第二犧牲材料1018之IC結構1000。 FIG. 10L illustrates the IC structure 1000 with the second sacrificial material 1018 removed from the openings 1016a-d.

在方塊926中，方法900可包含：在該第二組溝槽開口及該第二組通孔開口中形成一金屬。 At block 926, method 900 can include forming a metal in the second set of trench openings and the second set of via openings.

第10M圖示出具有被配置在該等開口1016a-d中之金屬1014之IC結構1000。 FIG. 10M illustrates an IC structure 1000 having a metal 1014 disposed in the openings 1016a-d.

在方塊928中，方法900可包含：使被配置在該第二組溝槽開口中之該金屬凹下。例如，可以一蝕刻製程移除該第二組溝槽開口中之該金屬的頂部。在某些實施例中，該第二組溝槽開口中之該金屬可被凹下到低於該第一ILD層的頂面之高度(例如，被凹下到與該第一組溝槽開口中之該金屬齊平的高度)。 At block 928, method 900 can include recessing the metal disposed in the second set of trench openings. For example, the top of the metal in the second set of trench openings can be removed by an etch process. In some embodiments, the metal in the second set of trench openings can be recessed to a lower level than the top surface of the first ILD layer (eg, recessed to the first set of trench openings) The height of the metal is flat).

第10N圖示出使開口1016a-d中之金屬1014凹下之IC結構1000。 The 10N figure shows the IC structure 1000 that recesses the metal 1014 in the openings 1016a-d.

在方塊930中，方法900可包含：在該第二組溝槽開口中之該金屬上形成一第二硬遮罩材料。可在超填之情形下沈積該第二硬遮罩材料，然後研磨該第二硬遮罩材料，使該第二硬遮罩材料的頂面與該第一硬遮罩材料及/或犧牲層的頂面實質上共平面。該第二硬遮罩材料可具有與該第一硬遮罩材料不同的蝕刻選擇性，而能夠在與該第一硬遮罩材料無關之情形下(例如，在不會蝕刻到該第一硬遮 罩材料之情形下)蝕刻該第二硬遮罩材料。 At block 930, method 900 can include forming a second hard mask material on the metal in the second set of trench openings. Depositing the second hard mask material in an overfill condition, and then grinding the second hard mask material such that the top surface of the second hard mask material and the first hard mask material and/or sacrificial layer The top surface is substantially coplanar. The second hard mask material can have a different etch selectivity than the first hard mask material, and can be independent of the first hard mask material (eg, without etching to the first hard cover In the case of a cover material, the second hard mask material is etched.

第10O圖示出具有被配置在開口1016a-d中之金屬1014上的一第二硬遮罩材料1022之IC結構1000。 FIG. 10O illustrates an IC structure 1000 having a second hard mask material 1022 disposed on metal 1014 in openings 1016a-d.

在方塊932中，方法900可包含：移除(諸如該等溝槽之間的)該犧牲層，且蝕刻掉在該犧牲層之下的該第一ILD層之頂部。例如，可使該犧牲層之下的該第一ILD層之該部分凹下到與該等溝槽的一較低表面實質上齊平。例如，可以一濕式清洗製程移除該犧牲層。例如，可利用電漿蝕刻(plasma etch)移除該第一ILD層的頂部。該第一ILD層的頂部可能被方法900的其他操作損壞，且該第一ILD層的頂部之移除可改善該第一ILD層的結構。 At block 932, method 900 can include removing the sacrificial layer (such as between the trenches) and etching away the top of the first ILD layer below the sacrificial layer. For example, the portion of the first ILD layer below the sacrificial layer can be recessed to be substantially flush with a lower surface of the trenches. For example, the sacrificial layer can be removed by a wet cleaning process. For example, the top of the first ILD layer can be removed using a plasma etch. The top of the first ILD layer may be damaged by other operations of method 900, and removal of the top of the first ILD layer may improve the structure of the first ILD layer.

第10P圖示出犧牲層1006被移除且第一ILD層1002的頂部(例如，金屬1014形成的該等溝槽之間的部分)被移除之IC結構1000。 FIG. 10P illustrates the IC structure 1000 with the sacrificial layer 1006 removed and the top of the first ILD layer 1002 (eg, the portion between the trenches formed by the metal 1014) removed.

在方塊934中，方法900可包含：在該等溝槽之間的該第一ILD層上形成一第二ILD層。可形成及/或凹下該第二ILD層，使該第二ILD層的頂面高於該等溝槽的頂面。或者，該第二ILD層的頂面可與該等溝槽的頂面實質上共平面。如將於本說明書中進一步說明的，該第二ILD層可以比該第一ILD層更具有多孔性。 At block 934, method 900 can include forming a second ILD layer on the first ILD layer between the trenches. The second ILD layer can be formed and/or recessed such that a top surface of the second ILD layer is higher than a top surface of the trenches. Alternatively, the top surface of the second ILD layer can be substantially coplanar with the top surface of the trenches. As will be further explained in this specification, the second ILD layer can be more porous than the first ILD layer.

第10Q圖示出具有被配置在金屬1014形成的該等溝槽之間的第一ILD層1002上的一第二ILD層1024之IC結構1000。 FIG. 10Q illustrates an IC structure 1000 having a second ILD layer 1024 disposed on a first ILD layer 1002 between the trenches formed by the metal 1014.

在方塊936中，方法900可包含：在該第二ILD層上 形成一第三硬遮罩材料。該第三硬遮罩材料可具有與該第一及/或第二硬遮罩材料不同的蝕刻選擇性，而能夠在與該第一及/或第二硬遮罩材料無關之情形下蝕刻(例如，移除)該第三硬遮罩材料。 At block 936, method 900 can include: on the second ILD layer A third hard mask material is formed. The third hard mask material can have a different etch selectivity than the first and/or second hard mask material, and can be etched regardless of the first and/or second hard mask material ( For example, removing the third hard mask material.

第10R圖示出具有被配置在第二ILD層1024上的一第三硬遮罩材料1026之IC結構1000。第10R圖所示之IC結構1000可類似於第8R圖所示之IC結構800。 FIG. 10R illustrates an IC structure 1000 having a third hard mask material 1026 disposed on the second ILD layer 1024. The IC structure 1000 shown in FIG. 10R can be similar to the IC structure 800 shown in FIG. 8R.

係以一種最有助於了解申請專利範圍之標的之方式，而以依次進行的多個分立式操作之形式說明方法300、500、700、及/或900的各操作。然而，不應將說明的順序詮釋為意味著這些操作必然是與順序相依的。可將本發明揭露之實施例實施到使用按照所需而配置的任何適當的硬體及/或軟體之一系統。 The operations of methods 300, 500, 700, and/or 900 are illustrated in the form of a plurality of discrete operations that are sequentially performed in a manner that is most helpful in understanding the scope of the claimed patent. However, the order of the description should not be interpreted as meaning that the operations are necessarily sequential. Embodiments of the present disclosure may be implemented to use any suitable hardware and/or software system configured as desired.

第11圖以示意方式示出一例示系統(例如，一計算裝置1100)，該計算裝置1100可根據某些實施例而包含本發明所述的一IC結構(例如，IC結構400、600、800、及/或1000、及/或使用方法300、500、700、及/或900形成之一IC結構)。計算裝置1100的各組件可被安置在一外殼(例如，外殼1108)中。主機板1102可包含其中包括但不限於一處理器1104以及至少一通訊晶片1106的一些組件。處理器1104可在實體上及電氣上被耦合到主機板1102。在某些實施例中，該至少一通訊晶片1106亦可在實體上及電氣上被耦合到主機板1102。在進一步的實施例中，通訊晶片1106可以是處理器1104的 一部分。 11 is a schematic illustration of an exemplary system (eg, a computing device 1100) that can include an IC structure (eg, IC structure 400, 600, 800) in accordance with certain embodiments. And/or 1000, and/or using methods 300, 500, 700, and/or 900 to form one of the IC structures). The various components of computing device 1100 can be disposed in a housing (eg, housing 1108). The motherboard 1102 can include some components including, but not limited to, a processor 1104 and at least one communication chip 1106. The processor 1104 can be physically and electrically coupled to the motherboard 1102. In some embodiments, the at least one communication chip 1106 can also be physically and electrically coupled to the motherboard 1102. In a further embodiment, the communication chip 1106 can be the processor 1104 portion.

計算裝置1100根據其應用，可包含可在或可不在實體上及電氣上被耦合到主機板1102之其他組件。這些其他組件可包括但不限於揮發性記憶體(例如，動態隨機存取記憶體(DRAM))、非揮發性記憶體(例如，唯讀記憶體(ROM))、快閃記憶體、圖形處理器、數位信號處理器、密碼處理器(crypto processor)、晶片組、天線、顯示器、觸控式螢幕顯示器、觸控式螢幕控制器、電池、音訊編碼解碼器、視訊編碼解碼器、功率放大器、全球衛星定位系統(Global Positioning System；簡稱GPS)裝置、羅盤、蓋革計數器(Geiger counter)、加速度計(accelerometer)、陀螺儀(gyroscope)、喇叭、相機、以及大量儲存裝置(諸如硬碟機、光碟(Compact Disk；簡稱CD)、及數位多功能光碟(Digital Versatile Disk；簡稱DVD)等的大量儲存裝置)等的組件。 Computing device 1100 can include other components that may or may not be physically and electrically coupled to motherboard 1102, depending on its application. These other components may include, but are not limited to, volatile memory (eg, dynamic random access memory (DRAM)), non-volatile memory (eg, read only memory (ROM)), flash memory, graphics processing , digital signal processor, crypto processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, Global Positioning System (GPS) devices, compasses, Geiger counters, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard disk drives, A component such as a compact disk (CD) and a large number of storage devices such as a digital versatile disk (DVD).

通訊晶片1106能夠執行無線通訊，而將資料傳輸進及出計算裝置1100。術語"無線"及其派生詞可被用於描述可利用通過非固體介質之調變電磁輻射而傳送資料之電路、裝置、系統、方法、技術、通訊通道等的術語。該術語並不意味著相關聯的裝置不包含任何導線，但是在某些實施例中，該等相關聯的裝置可能不包含任何導線。通訊晶片1106可實施其中包括但不限於包含Wi-Fi(IEEE 802.11系列)及IEEE 802.16標準(例如，IEEE 802.16-2005 Amendment)之電機及電子工程師協會(Institute of Electrical and Electronic Engineers；簡稱IEEE)標準、長程演進計畫(Long-Term Evolution；簡稱LTE)以及任何修正、更新、及/或修訂(例如，先進LTE計畫、超行動寬頻(Ultra Mobile Broadband；簡稱UMB)計畫(也被稱為3GPP2)等的修正、更新、及/或修訂)的一些無線標準或協定中之任何無線標準或協定。與IEEE 802.16相容之寬頻無線接取(Broadband Wireless Access；簡稱BWA)網路通常被稱為全球互通微波接取(Worldwide Interoperability for Microwave Access；簡稱WiMAX)網路，係為一種通過IEEE 802.16標準的符合性及互通性測試的產品之認證標誌。通訊晶片1106可根據全球行動通訊系統(Global System for Mobile communication；簡稱GSM)、通用封包無線電服務(General Packet Radio Service；簡稱GPRS)、全球行動電信系統(Universal Mobile Telecommunications System；簡稱UMTS)、高速封包存取(High Speed Packet Access；簡稱HSPA)、演進型高速封包存取(Evolved HSPA；簡稱E-HSPA)、或LTE網路而操作。通訊晶片1106可根據全球行動通訊系統增強型數據演進技術(Enhanced Data for GSM Evolution；簡稱EDGE)、GSM EDGE無線電存取網路(GSM EDGE Radio Access Network；簡稱GERAN)、全球地面無線電存取網路(Universal Terrestrial Radio Access Network；簡稱UTRAN)、或演進型UTRAN(Evolved UTRAN；簡稱E-UTRAN)而操作 。通訊晶片1106可根據分碼多工存取(Code Division Multiple Access；簡稱CDMA)、分時多工存取(Time Division Multiple Access；簡稱TDMA)、數位增強無線電信(Digital Enhanced Cordless Telecommunications；簡稱DECT)、演進資料最佳化(Evolution-Data Optimized；簡稱EV-DO)、以上各項的衍生標準或協定、以及被稱為3G、4G、5G、及更新的世代之任何其他無線協定而操作。在其他實施例中，通訊晶片1106可根據其他無線協定而操作。 The communication chip 1106 is capable of performing wireless communication and transmitting data to and from the computing device 1100. The term "wireless" and its derivatives may be used to describe terms, circuits, systems, methods, techniques, communication channels, and the like that may utilize data transmitted by modulated electromagnetic radiation through a non-solid medium. The term does not mean that the associated device does not contain any wires, but in some embodiments, such associated devices may not contain any wires. The communication chip 1106 can implement an Institute of Electrical and Electronics Engineers including, but not limited to, Wi-Fi (IEEE 802.11 series) and IEEE 802.16 standards (eg, IEEE 802.16-2005 Amendment) (Institute of Electrical and Electronic Engineers; IEEE) standards, Long-Term Evolution (LTE) and any amendments, updates, and/or revisions (eg, advanced LTE plans, Ultra Mobile Broadband; UMB) Any wireless standard or agreement in some wireless standards or protocols for amendments, updates, and/or revisions of the program (also known as 3GPP2). The Broadband Wireless Access (BWA) network, which is compatible with IEEE 802.16, is commonly referred to as the Worldwide Interoperability for Microwave Access (WiMAX) network and is an IEEE 802.16 standard. Certification mark for products for compliance and interoperability testing. The communication chip 1106 can be based on the Global System for Mobile communication (GSM), the General Packet Radio Service (GPRS), the Universal Mobile Telecommunications System (UMTS), and the high speed packet. It is operated by High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA for short), or LTE network. The communication chip 1106 can be based on the Global Data Communication System (Enhanced Data for GSM Evolution; EDGE), the GSM EDGE Radio Access Network (GERAN), and the global terrestrial radio access network. (Universal Terrestrial Radio Access Network; UTRAN for short) or Evolved UTRAN (E-UTRAN for short) . The communication chip 1106 can be based on code division multiple access (CDMA), time division multiple access (TDMA), and digital enhanced Cordless Telecommunications (DECT). , Evolution-Data Optimized (EV-DO), derivative standards or agreements for the above, and any other wireless protocols known as 3G, 4G, 5G, and newer generations. In other embodiments, the communication chip 1106 can operate in accordance with other wireless protocols.

計算裝置1100可包含複數個通訊晶片1106。例如，一第一通訊晶片1106可被專用於諸如Wi-Fi及藍牙等的較短距離之無線通訊，且一第二通訊晶片1106可被專用於諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、EV-DO、及其他無線通訊標準等的較長距離之無線通訊。 Computing device 1100 can include a plurality of communication chips 1106. For example, a first communication chip 1106 can be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and a second communication chip 1106 can be dedicated to applications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE. Long-distance wireless communication, such as EV-DO, and other wireless communication standards.

計算裝置1100之處理器1104可包含具有本發明所述的一IC結構(例如，IC結構400、600、800、及/或1000、及/或使用方法300、500、700、及/或900形成的一IC結構)之一晶粒(例如，第1-2圖之晶粒102)。例如，第1-2圖之晶粒102可被安裝在一封裝總成中，而該封裝總成可被安裝在諸如主機板1102等的一電路板上。術語"處理器"可意指用於處理來自暫存器及/或記憶體的電子資料而將該電子資料轉換為可被儲存在暫存器及/或記憶體的其他電子資料之任何裝置或裝置之一部分。 The processor 1104 of the computing device 1100 can comprise an IC structure (eg, IC structures 400, 600, 800, and/or 1000, and/or methods of use 300, 500, 700, and/or 900) as described herein. One of the IC structures) (for example, the die 102 of Figures 1-2). For example, the die 102 of Figures 1-2 can be mounted in a package assembly that can be mounted on a circuit board such as the motherboard 1102. The term "processor" may mean any device that processes electronic data from a register and/or memory and converts the electronic data into other electronic data that can be stored in a register and/or memory or One part of the device.

通訊晶片1106亦可包含具有本發明所述的一IC結構(例如，IC結構400、600、800、及/或1000、及/或使用方法300、500、700、及/或900形成的一IC結構)之一晶粒(例如，第1-2圖之晶粒102)。在進一步的實施例中，被安置在計算裝置1100內之另一組件(例如，記憶體裝置或其他積體電路裝置)可包含具有本發明所述的一IC結構(例如，IC結構400、600、800、及/或1000、及/或使用方法300、500、700、及/或900形成的一IC結構)之一晶粒(例如，第1-2圖之晶粒102)。 The communication chip 1106 can also include an IC having an IC structure (eg, IC structure 400, 600, 800, and/or 1000, and/or using methods 300, 500, 700, and/or 900) as described herein. One of the grains of the structure (for example, the die 102 of Figures 1-2). In further embodiments, another component (eg, a memory device or other integrated circuit device) disposed within computing device 1100 can include an IC structure (eg, IC structure 400, 600) as described herein. One of the dies of 800, and/or 1000, and/or an IC structure formed using methods 300, 500, 700, and/or 900 (eg, die 102 of Figures 1-2).

在各實施例中，計算裝置1100可以是行動計算裝置、膝上型電腦、簡易筆記型電腦、筆記型電腦、超輕薄筆記本電腦、智慧型手機、平板電腦、個人數位助理(Personal Digital Assistant；簡稱PDA)、超級行動個人電腦、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂控制單元、數位相機、可攜式音樂播放器、或數位錄影機。在進一步的實施例中，計算裝置1100可以是用於處理資料之任何其他電子裝置。 In various embodiments, the computing device 1100 can be a mobile computing device, a laptop, a simple notebook, a notebook, an ultra-thin laptop, a smart phone, a tablet, and a personal digital assistant (Personal Digital Assistant; PDA), super mobile PC, mobile phone, desktop, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video machine. In a further embodiment, computing device 1100 can be any other electronic device for processing data.

下文中將提供一些非限制性例子。 Some non-limiting examples are provided below.

例子1是一種製造積體電路(IC)結構之方法，該方法包含：提供一堆疊，該堆疊包含被配置在一下方層上之一第一層間介電質(ILD)層，且包含一介電材料、被配置在該第一ILD層上之一犧牲層、以及被配置在該犧牲層上之一硬遮罩層；在該犧牲層中形成溝槽開口，且在該第 一ILD層中形成通孔開口；在該等溝槽開口及該等通孔開口中形成一金屬，以便形成各別的溝槽及通孔；移除該犧牲層；以及在該等溝槽之間的該第一ILD層上形成一第二ILD層。 Example 1 is a method of fabricating an integrated circuit (IC) structure, the method comprising: providing a stack comprising a first interlayer dielectric (ILD) layer disposed on a lower layer and including a a dielectric material, a sacrificial layer disposed on the first ILD layer, and a hard mask layer disposed on the sacrificial layer; forming a trench opening in the sacrificial layer, and Forming via openings in an ILD layer; forming a metal in the trench openings and the via openings to form respective trenches and vias; removing the sacrificial layer; and A second ILD layer is formed on the first ILD layer.

例子2是例子1之方法，其中該第二ILD層具有比該第一ILD層高的多孔性。 Example 2 is the method of Example 1, wherein the second ILD layer has a higher porosity than the first ILD layer.

例子3是例子1之方法，其中在該等溝槽開口中形成該金屬包含：在該第一ILD層上沈積該金屬。 Example 3 is the method of example 1, wherein forming the metal in the trench openings comprises depositing the metal on the first ILD layer.

例子4是例子1之方法，其中該犧牲層包含一可濕式清洗的介電質或一可濕式清洗的硬遮罩。 Example 4 is the method of Example 1, wherein the sacrificial layer comprises a wet cleanable dielectric or a wet cleanable hard mask.

例子5是例子1至4中之任一例子之方法，其中形成該等溝槽開口及通孔開口且在該等溝槽開口及該等通孔開口中形成該金屬包含：形成第一組溝槽開口及第一組通孔開口；在該第一組溝槽開口及該第一組通孔開口中形成一金屬，以便形成第一組溝槽及第二組溝槽；在該第一組溝槽開口及該第一組通孔開口中形成了該金屬之後，形成第二組溝槽開口及第二組通孔開口，其中該第二組溝槽開口之各溝槽開口係與該犧牲層中之該第一組溝槽開口之各開口相間；以及在該第二組溝槽開口及該第二組通孔開口中形成一金屬，以便形成第二組溝槽及第二組通孔。 Example 5 is the method of any one of examples 1 to 4, wherein forming the trench openings and via openings and forming the metal in the trench openings and the via openings comprises: forming a first set of trenches a slot opening and a first set of through hole openings; forming a metal in the first set of trench openings and the first set of via openings to form a first set of trenches and a second set of trenches; After forming the metal in the trench opening and the first set of via openings, forming a second set of trench openings and a second set of via openings, wherein each trench opening of the second set of trench openings is associated with the sacrifice Forming a metal between the openings of the first set of trench openings in the layer; and forming a metal in the second set of trench openings and the second set of via openings to form a second set of trenches and a second set of vias .

例子6是例子5之方法，進一步包含：在該第一組溝槽上形成一第一硬遮罩材料；以及在該第二組溝槽上形成一第二硬遮罩材料，其中該第二硬遮罩材料具有與該第一硬遮罩材料不同的蝕刻選擇性。 Example 6 is the method of example 5, further comprising: forming a first hard mask material on the first set of trenches; and forming a second hard mask material on the second set of trenches, wherein the second The hard mask material has a different etch selectivity than the first hard mask material.

例子7是例子6之方法，進一步包含：在該第一與第二硬遮罩材料之間的該第二ILD層上形成一第三硬遮罩材料，其中該第三硬遮罩材料具有與該第一及第二硬遮罩材料不同的蝕刻選擇性。 Example 7 is the method of example 6, further comprising: forming a third hard mask material on the second ILD layer between the first and second hard mask materials, wherein the third hard mask material has The first and second hard mask materials have different etch selectivity.

例子8是例子1之方法，其中該等溝槽開口延伸到該第一ILD層的頂面之下。 Example 8 is the method of example 1, wherein the trench openings extend below a top surface of the first ILD layer.

例子9是例子1之方法，其中該第一ILD層具有與該第二ILD層不同的材料成分。 Example 9 is the method of example 1, wherein the first ILD layer has a different material composition than the second ILD layer.

例子10是一種積體電路(IC)，包含：被配置在一下方層上之一第一層間介電質(ILD)層；被配置在該第一ILD層上之複數個溝槽；以及被配置在該複數個溝槽的各溝槽之間的該第一ILD層上之一第二ILD層；其中該第二ILD層具有比該第一ILD層低的介電常數。 Example 10 is an integrated circuit (IC) comprising: a first interlayer dielectric (ILD) layer disposed on a lower layer; a plurality of trenches disposed on the first ILD layer; a second ILD layer disposed on the first ILD layer between the trenches of the plurality of trenches; wherein the second ILD layer has a lower dielectric constant than the first ILD layer.

例子11是例子10之IC，進一步包含：自各別溝槽經由該第一ILD層而延伸到該下方層之複數個通孔。 Example 11 is the IC of Example 10, further comprising: a plurality of vias extending from the respective trenches to the underlying layer via the first ILD layer.

例子12是例子10之IC，其中該第一ILD層之頂面是實質上平的。 Example 12 is the IC of Example 10, wherein the top surface of the first ILD layer is substantially flat.

例子13是例子10之IC，其中該第二ILD層比該第一ILD層更多孔。 Example 13 is the IC of Example 10, wherein the second ILD layer has more holes than the first ILD layer.

例子14是例子10之IC，其中該第二ILD層的底面與該等溝槽的底面實質上共平面。 Example 14 is the IC of Example 10, wherein the bottom surface of the second ILD layer is substantially coplanar with the bottom surface of the trenches.

例子15是例子10之IC，其中該第一ILD層具有與該第二ILD不同的材料成分。 Example 15 is the IC of Example 10, wherein the first ILD layer has a different material composition than the second ILD.

例子16是一種計算裝置，包含：一電路板；一晶 粒，該晶粒之前面被耦合到該電路板。該晶粒包含：被配置在一下方層上之一第一層間介電質(ILD)層，其中該第一ILD層包含一第一介電材料；被配置在該第一ILD層上之複數個溝槽；以及被配置在該複數個溝槽的各溝槽之間的該第一ILD層上之一第二ILD層，其中該第二ILD層包含比該第一介電材料更多孔的一第二介電材料。 Example 16 is a computing device comprising: a circuit board; a crystal The grain, the front face of the die is coupled to the board. The die includes: a first interlayer dielectric (ILD) layer disposed on a lower layer, wherein the first ILD layer includes a first dielectric material; and is disposed on the first ILD layer a plurality of trenches; and a second ILD layer disposed on the first ILD layer between the trenches of the plurality of trenches, wherein the second ILD layer comprises more than the first dielectric material a second dielectric material of the aperture.

例子17是例子16之計算裝置，其中該互連層進一步包含自各別溝槽經由該第一ILD層而延伸到該下方層之複數個通孔。 Example 17 is the computing device of example 16, wherein the interconnect layer further comprises a plurality of vias extending from the respective trenches to the lower layer via the first ILD layer.

例子18是例子16之計算裝置，其中該第二ILD層的底面與該等溝槽的底面實質上共平面。 Example 18 is the computing device of Example 16, wherein the bottom surface of the second ILD layer is substantially coplanar with the bottom surface of the trenches.

例子19是例子16之計算裝置，其中該第一介電材料具有與該第二介電材料不同的材料成分。 Example 19 is the computing device of Example 16, wherein the first dielectric material has a different material composition than the second dielectric material.

例子20是例子16至19中之任一例子之計算裝置，其中：該晶粒是一處理器；以及該計算裝置是包含一天線、一顯示器、一觸控式螢幕顯示器、一觸控式螢幕控制器、一電池、一音訊編碼解碼器、一視訊編碼解碼器、一功率放大器、一全球衛星定位系統(GPS)裝置、一羅盤、一蓋革計數器、一加速度計、一陀螺儀、一喇叭、以及一相機中之一或多者之一行動計算裝置。 Example 20 is the computing device of any one of examples 16 to 19, wherein: the die is a processor; and the computing device comprises an antenna, a display, a touch screen display, and a touch screen Controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker And one of the one or more of the cameras in the mobile computing device.

各實施例可包括其中包括前文中以連接詞形式(例如，"及"可以是"及/或")述及的實施例的替代實施例之前文所述的實施例之任何適當的組合。此外，某些實施例可包括一或多個製品(例如，非暫態電腦可讀取的媒 體)，該一或多個製品具有被儲存在其中的指令，該等指令被執行時，將導致前文所述的實施例中之任何實施例的行動。此外，某些實施例可包括具有用於執行前文所述的實施例的各種操作的任何適當的裝置之設備或系統。 Embodiments may include any suitable combination of the embodiments previously described herein including alternative embodiments of the embodiments described above in the form of conjunctions (e.g., "and" may be "and/or"). Moreover, certain embodiments may include one or more articles (eg, non-transitory computer readable media) The one or more articles have instructions stored therein that, when executed, will result in the actions of any of the embodiments described above. Moreover, some embodiments may include apparatus or systems having any suitable means for performing the various operations of the embodiments described above.

其中包括在"發明摘要"中所述者的前文中對本發明的所示實施例之說明之用意不是詳盡無遺的，也不是將本發明揭露之實施例限制在所揭露之確切形式。雖然為了例示之目的而在本說明書中說明了特定實施例及例子，但是熟悉相關技術者當可了解：可在本發明揭露的範圍內作出各種等效的修改。 The description of the illustrated embodiments of the present invention is not intended to be exhaustive or to limit the invention. While the invention has been described with respect to the specific embodiments and examples of the invention, it will be understood by those skilled in the art that various equivalent modifications can be made within the scope of the invention.

可根據上述之詳細說明而作出本發明揭露的實施例之這些修改。不應將最後的申請專利範圍中使用的術語詮釋為將本發明揭露之各實施例限制在本說明書及申請專利範圍中揭露的特定實施例。而是將完全由將根據申請專利範圍詮釋的公認信條而詮釋之最後的申請專利範圍決定本發明之範圍。 These modifications of the disclosed embodiments of the present invention can be made in accordance with the above detailed description. The terms used in the scope of the claims are not to be construed as limited to the particular embodiments disclosed herein. Rather, the scope of the present invention will be determined by the scope of the final application of the invention, which is to be interpreted in the light of the claims.

Claims (20)

一種用於製造積體電路(IC)結構之方法，包含：提供一堆疊，該堆疊包含被配置在一下方層上之一第一層間介電質(ILD)層，且包含一介電材料、被配置在該第一ILD層上之一犧牲層、以及被配置在該犧牲層上之一硬遮罩層；在該犧牲層中形成溝槽開口，且在該第一ILD層中形成通孔開口；在該等溝槽開口及該等通孔開口中形成一金屬，以形成各別的溝槽及通孔；移除該犧牲層；以及在該等溝槽之間的該第一ILD層上形成一第二ILD層。 A method for fabricating an integrated circuit (IC) structure, comprising: providing a stack comprising a first interlayer dielectric (ILD) layer disposed on a lower layer and comprising a dielectric material a sacrificial layer disposed on the first ILD layer, and a hard mask layer disposed on the sacrificial layer; forming a trench opening in the sacrificial layer, and forming a pass in the first ILD layer a hole opening; forming a metal in the trench opening and the via opening to form respective trenches and vias; removing the sacrificial layer; and the first ILD between the trenches A second ILD layer is formed on the layer. 如申請專利範圍第1項之方法，其中該第二ILD材料具有比該第一ILD材料高的多孔性。 The method of claim 1, wherein the second ILD material has a higher porosity than the first ILD material. 如申請專利範圍第1項之方法，其中在該等溝槽開口中形成該金屬包含：在該第一ILD層上沈積該金屬。 The method of claim 1, wherein forming the metal in the trench openings comprises depositing the metal on the first ILD layer. 如申請專利範圍第1項之方法，其中該犧牲層包含一可濕式清洗的介電質或一可濕式清洗的硬遮罩。 The method of claim 1, wherein the sacrificial layer comprises a wet cleanable dielectric or a wet cleanable hard mask. 如申請專利範圍第1項之方法，其中形成該等溝槽開口及通孔開口且在該等溝槽開口及該等通孔開口中形成該金屬包含：形成第一組溝槽開口及第一組通孔開口；在該第一組溝槽開口及該第一組通孔開口中形成一金 屬，以形成第一組溝槽及第二組溝槽；在該第一組溝槽開口及該第一組通孔開口中形成了該金屬之後，形成第二組溝槽開口及第二組通孔開口，其中該第二組溝槽開口之溝槽開口與該犧牲層中之該第一組溝槽開口之開口相間；以及在該第二組溝槽開口及該第二組通孔開口中形成一金屬，以便形成第二組溝槽及第二組通孔。 The method of claim 1, wherein forming the trench openings and the via openings and forming the metal in the trench openings and the via openings comprises: forming a first set of trench openings and first a through hole opening; forming a gold in the first group of groove openings and the first group of through hole openings Generating to form a first set of trenches and a second set of trenches; forming a second set of trench openings and a second set after forming the metal in the first set of trench openings and the first set of via openings a via opening, wherein the trench opening of the second set of trench openings is spaced apart from the opening of the first set of trench openings in the sacrificial layer; and the second set of trench openings and the second set of via openings A metal is formed in the middle to form a second set of trenches and a second set of vias. 如申請專利範圍第5項之方法，進一步包含：在該第一組溝槽上形成一第一硬遮罩材料；以及在該第二組溝槽上形成一第二硬遮罩材料，其中該第二硬遮罩材料具有與該第一硬遮罩材料不同的蝕刻選擇性。 The method of claim 5, further comprising: forming a first hard mask material on the first set of trenches; and forming a second hard mask material on the second set of trenches, wherein the The second hard mask material has a different etch selectivity than the first hard mask material. 如申請專利範圍第6項之方法，進一步包含：在該第一與第二硬遮罩材料之間的該第二ILD層上形成一第三硬遮罩材料，其中該第三硬遮罩材料具有與該第一及第二硬遮罩材料不同的蝕刻選擇性。 The method of claim 6, further comprising: forming a third hard mask material on the second ILD layer between the first and second hard mask materials, wherein the third hard mask material There is an etch selectivity different from the first and second hard mask materials. 如申請專利範圍第1項之方法，其中該等溝槽開口延伸到該第一ILD層的頂面之下。 The method of claim 1, wherein the trench openings extend below a top surface of the first ILD layer. 如申請專利範圍第1項之方法，其中該第一介電材料具有與該第二介電材料不同的材料成分。 The method of claim 1, wherein the first dielectric material has a different material composition than the second dielectric material. 一種積體電路(IC)，包含：被配置在一下方層上之一第一層間介電質(ILD)層；被配置在該第一ILD層上之複數個溝槽；以及 被配置在該複數個溝槽的溝槽之間的該第一ILD層上之一第二ILD層，其中該第二ILD層具有比該第一ILD層低的介電常數。 An integrated circuit (IC) comprising: a first interlayer dielectric (ILD) layer disposed on a lower layer; a plurality of trenches disposed on the first ILD layer; a second ILD layer disposed on the first ILD layer between the trenches of the plurality of trenches, wherein the second ILD layer has a lower dielectric constant than the first ILD layer. 如申請專利範圍第10項之IC，進一步包含自各別溝槽經由該第一ILD層而延伸到該下方層之複數個通孔。 The IC of claim 10, further comprising a plurality of via holes extending from the respective trenches to the lower layer via the first ILD layer. 如申請專利範圍第10項之IC，其中該第一ILD層之頂面是實質上平的。 The IC of claim 10, wherein the top surface of the first ILD layer is substantially flat. 如申請專利範圍第10項之IC，其中該第二ILD層比該第一ILD層更多孔。 The IC of claim 10, wherein the second ILD layer has more holes than the first ILD layer. 如申請專利範圍第10項之IC，其中該第二ILD層的底面與該等溝槽的底面實質上共平面。 The IC of claim 10, wherein the bottom surface of the second ILD layer is substantially coplanar with the bottom surface of the trenches. 如申請專利範圍第10項之IC，其中該第一ILD層具有與該第二ILD層不同的材料成分。 The IC of claim 10, wherein the first ILD layer has a different material composition than the second ILD layer. 一種計算裝置，包含：一電路板；以及一晶粒，該晶粒之前面被耦合到該電路板，該晶粒具有一互連層，該互連層包含：被配置在一下方層上之一第一層間介電質(ILD)層，該第一ILD層包含一第一介電材料；被配置在該第一ILD層上之複數個溝槽；以及被配置在該複數個溝槽的溝槽之間的該第一ILD層上之一第二ILD層，其中該第二ILD層包含比該第一介電材料更多孔的一第二介電材料。 A computing device comprising: a circuit board; and a die having a front face coupled to the circuit board, the die having an interconnect layer, the interconnect layer comprising: being disposed on a lower layer a first interlayer dielectric (ILD) layer, the first ILD layer comprising a first dielectric material; a plurality of trenches disposed on the first ILD layer; and being disposed in the plurality of trenches a second ILD layer on the first ILD layer between the trenches, wherein the second ILD layer comprises a second dielectric material having more holes than the first dielectric material. 如申請專利範圍第16項之計算裝置，其中該互連 層進一步包含自各別溝槽經由該第一ILD層而延伸到該下方層之複數個通孔。 A computing device as claimed in claim 16, wherein the interconnection The layer further includes a plurality of vias extending from the respective trenches to the underlying layer via the first ILD layer. 如申請專利範圍第16項之計算裝置，其中該第二ILD層的底面與該等溝槽的底面實質上共平面。 The computing device of claim 16, wherein the bottom surface of the second ILD layer is substantially coplanar with the bottom surface of the trenches. 如申請專利範圍第16項之計算裝置，其中該第一介電材料具有與該第二介電材料不同的材料成分。 The computing device of claim 16, wherein the first dielectric material has a different material composition than the second dielectric material. 如申請專利範圍第16項之計算裝置，其中：該晶粒是一處理器；以及該計算裝置是包含一天線、一顯示器、一觸控式螢幕顯示器、一觸控式螢幕控制器、一電池、一音訊編碼解碼器、一視訊編碼解碼器、一功率放大器、一全球衛星定位系統(GPS)裝置、一羅盤、一蓋革計數器、一加速度計、一陀螺儀、一喇叭、以及一相機中之一或多者之一行動計算裝置。 The computing device of claim 16, wherein: the die is a processor; and the computing device comprises an antenna, a display, a touch screen display, a touch screen controller, a battery , an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, and a camera One or more of the mobile computing devices.
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