TW201721448A - Data transmission method for SGPIO - Google Patents
Data transmission method for SGPIO Download PDFInfo
- Publication number
- TW201721448A TW201721448A TW104141937A TW104141937A TW201721448A TW 201721448 A TW201721448 A TW 201721448A TW 104141937 A TW104141937 A TW 104141937A TW 104141937 A TW104141937 A TW 104141937A TW 201721448 A TW201721448 A TW 201721448A
- Authority
- TW
- Taiwan
- Prior art keywords
- data
- expander
- page
- line
- universal serial
- Prior art date
Links
Landscapes
- Information Transfer Systems (AREA)
Abstract
Description
本發明係關於一種通用串行輸入輸出的資料傳輸方法,特別是一種以通用串行輸入輸出匯流排連接的擴展器和目標裝置之間的資料傳輸方法。The present invention relates to a data transmission method for universal serial input and output, and more particularly to a data transmission method between an expander and a target device connected by a universal serial input/output bus.
隨著科技的發展,電子裝置之間的資料傳輸速度與資料量的需求也隨之成長。為了因應大量的資料快速地在電子裝置之間傳輸,目前技術上多會採用通用串行輸入輸出(Serial General Purpose Input Output,SGPIO)匯流排或內部整合電路(Inter-Integrated Circuit,I2 C)、通用非同步收發傳輸器(Universal Asynchronous Receiver Transmitter,UART)等進行擴展器(Expander)或啟動裝置(Initiator)與目標裝置(Target)之間的資料傳輸。With the development of technology, the demand for data transmission speed and data volume between electronic devices has also grown. In order to quickly transfer a large amount of data between electronic devices, the current technology generally uses a general serial input/output (SGPIO) bus or an integrated circuit (I 2 C). The Universal Asynchronous Receiver Transmitter (UART) performs data transmission between an expander or an Initiator and a Target.
然而,當以通用串行輸入輸出匯流排進行擴展器與目標設備之間的資料傳輸時,現有的通用串行輸入輸出匯流排架構中,係預先分配與定義一定數量的時槽(timeslot)給目標設備,目標設備再根據定義好的時槽,將對應的資料內容從定義的時槽傳送到擴展器。如此一來,預先分配和定義好的時槽數量就限制了目標設備傳輸到擴展器的資料數量。例如事先定義60個時槽讓目標設備傳送資料到擴展器,目標設備就只能傳送60個不同的資料內容到擴展器,而無法再增加更多的資料量。However, when the data transmission between the expander and the target device is performed by the universal serial input/output bus, the existing universal serial input/output bus architecture pre-allocates and defines a certain number of time slots (timeslot). The target device, the target device transmits the corresponding data content from the defined time slot to the expander according to the defined time slot. As a result, the number of pre-allocated and defined time slots limits the amount of data that the target device transmits to the expander. For example, if 60 time slots are defined in advance for the target device to transmit data to the expander, the target device can only transmit 60 different data contents to the expander, and no more data can be added.
本發明在於提供一種通用串行輸入輸出的資料傳輸方法,藉以解決先前技術中目標設備傳輸資料量受到限制的問題。The present invention provides a data transmission method for universal serial input and output, thereby solving the problem that the amount of data transmitted by the target device in the prior art is limited.
本發明所揭露的通用串行輸入輸出的資料傳輸方法,適用於以通用串行輸入輸出匯流排連接的擴展器和目標裝置。通用串行輸入輸出匯流排至少具有資料輸出線及資料讀取線。擴展器經由資料輸出線輸出分頁指示信號至目標裝置,分頁指示信號指示分頁位址。目標裝置依據分頁指示信號,查找分頁位址指示的分頁資料。目標裝置經由資料讀取線將分頁位址和分頁資料輸出至擴展器。擴展器讀取經由資料讀取線傳送的內容。當擴展器判斷資料讀取線傳送的內容具有分頁位址時,擴展器接收分頁資料。The universal serial input and output data transmission method disclosed in the present invention is applicable to an expander and a target device connected by a universal serial input/output bus. The universal serial input/output bus has at least a data output line and a data read line. The expander outputs a paging indication signal to the target device via the data output line, and the paging indication signal indicates the paging address. The target device searches for the paging data indicated by the paging address according to the paging indication signal. The target device outputs the paged address and the paging data to the expander via the data read line. The expander reads the content transmitted via the data reading line. The expander receives the paging material when the expander determines that the content transmitted by the data read line has a paged address.
根據上述本發明所揭露的通用串行輸入輸出的資料傳輸方法,藉由擴展器主動輸出分頁指示信號給目標裝置,目標裝置再依據分頁指示信號指示的分頁位址,將分頁位址下的分頁資料傳輸給擴暫器,據以增加目標裝置藉由通用串行輸入輸出匯流排傳輸給擴展器的資料量。當部分擴展器或目標裝置不支援如I2 C或UART的傳輸介面時,擴展器和目標裝置之間仍可利用通用串行輸入輸出匯流排來實現的通訊。According to the data transmission method of the universal serial input and output disclosed by the present invention, the expander actively outputs the paging indication signal to the target device, and the target device further divides the paging under the paging address according to the paging address indicated by the paging indication signal. The data is transmitted to the spreader to increase the amount of data that the target device transmits to the expander through the universal serial input/output bus. When a part of the expander or target device does not support the transmission interface such as I 2 C or UART, the communication can be realized by the universal serial input/output bus between the expander and the target device.
以上之關於本揭露內容之說明及以下之實施方式之說明係用以示範與解釋本發明之精神與原理,並且提供本發明之專利申請範圍更進一步之解釋。The above description of the disclosure and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention, and to provide further explanation of the scope of the invention.
以下在實施方式中詳細敘述本發明之詳細特徵以及優點,其內容足以使任何熟習相關技藝者了解本發明之技術內容並據以實施,且根據本說明書所揭露之內容、申請專利範圍及圖式,任何熟習相關技藝者可輕易地理解本發明相關之目的及優點。以下之實施例係進一步詳細說明本發明之觀點,但非以任何觀點限制本發明之範疇。The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.
請參照圖1,圖1係根據本發明一實施例所繪示之通用串行輸入輸出匯流排電性連接擴展器和目標裝置的示意圖,圖2係根據本發明一實施例所繪示之通用串行輸入輸出匯流排時槽分配的示意圖,圖3係根據本發明一實施例所繪示之通用串行輸入輸出的資料傳輸方法的步驟流程圖。如圖所示,本發明通用串行輸入輸出的資料傳輸方法,適用於以通用串行輸入輸出(Serial General Purpose Input Output,SGPIO)匯流排10連接的擴展器(expander)20和目標裝置(target)30。擴展器20例如序列式小型電腦系統介面擴展器、微處理器(microcontroller)、嵌入式處理器(embedded controller)、基板管理控制器(baseboard management controller ,BMC)或其他合適的裝置。目標裝置30例如背板模組(backplane module)、磁碟陣列裝置包括硬碟、備用電池、控制單元及風扇、簡單磁片捆綁(Just Bundle Of Disks,JBOD)大型硬碟陣列組、獨立硬碟冗餘陣列(RAID, Redundant Array of Independent Disks,RAID)大型硬碟陣列組、可程式邏輯裝置(Programmable Logic Device,PLD)、複雜式可程式邏輯裝置(Complex PLD,CPLD)、現場可程式化閘陣列(Field-programmable gate array,FPGA)或其他合適的裝置。1 is a schematic diagram of a universal serial input/output bus bar electrical connection expander and a target device according to an embodiment of the invention. FIG. 2 is a schematic diagram of an embodiment of the present invention. FIG. 3 is a flow chart showing the steps of a data transmission method for universal serial input and output according to an embodiment of the invention. As shown in the figure, the data transmission method of the universal serial input and output of the present invention is applicable to an expander 20 and a target device (target) connected by a general-purpose serial input/output (SGPIO) bus bar 10. ) 30. The expander 20 is, for example, a serial small computer system interface extender, a microprocessor, an embedded controller, a baseboard management controller (BMC), or other suitable device. The target device 30, such as a backplane module and a disk array device, includes a hard disk, a backup battery, a control unit and a fan, a Just Bundle Of Disks (JBOD) large hard disk array group, and a stand-alone hard disk. Redundant Array of Independent Disks (RAID) large hard disk array group, Programmable Logic Device (PLD), Complex Programmable Logic Device (Complex PLD, CPLD), Field Programmable Gate Field-programmable gate array (FPGA) or other suitable device.
通用串行輸入輸出匯流排10具有資料輸出線SDataOut、資料讀取線SDataIn、時脈信號線SClock及負載信號線SLoad。擴展器20和目標裝置30分別具有對應的時脈腳位、負載腳位、資料輸入腳位及資料輸出腳位,擴展器20和目標裝置30對應的腳位分別藉由通用串行輸入輸出匯流排10的資料輸出線SDataOut、資料讀取線SDataIn、時脈信號線SClock及負載信號線SLoad電性連接。擴展器20定義為通用串行輸入輸出匯流排10的起始者(SGPIO initiator),而目標裝置30定義為通用串行輸入輸出匯流排10的目標者(SGPIO Target)。於所屬技術領域具有通常知識者應可理解通用串行輸入輸出匯流排10、擴展器20和目標裝置30之間的連接方式,於此不再加以贅述。The universal serial input/output bus 10 has a data output line SDataOut, a data read line SDataIn, a clock signal line SClock, and a load signal line SLoad. The expander 20 and the target device 30 respectively have corresponding clock pin, load pin, data input pin and data output pin. The pin corresponding to the expander 20 and the target device 30 are respectively connected by a universal serial input and output. The data output line SDataOut, the data read line SDataIn, the clock signal line SClock, and the load signal line SLoad of the row 10 are electrically connected. The expander 20 is defined as the SGPIO initiator of the universal serial input/output bus 10, and the target device 30 is defined as the target of the universal serial input/output bus 10 (SGPIO Target). A person skilled in the art should understand the connection between the universal serial input/output bus bar 10, the expander 20 and the target device 30, and details are not described herein.
通用串行輸入輸出匯流排10的時脈信號線SClock用以提供擴展器20傳送時脈信號至目標裝置30,而負載信號線SLoad提供擴展器20傳送負載信號至目標裝置30,資料輸出線SDataOut提供擴展器20發送信號至目標裝置30,資料讀取線SDataIn提供目標裝置30發送信號至擴展器20。時脈信號係用以定義通用串行輸入輸出匯流排10的傳輸時脈。負載信號是定義資料輸出線SDataOut或資料讀取線SDataIn傳輸數據的框架,例如一個傳輸框架是負載信號在時脈波形的上升邊緣後觸發8個時鐘週期至時脈波形的下降邊緣。The clock signal line SClock of the universal serial input/output bus 10 is used to provide the expander 20 to transmit the clock signal to the target device 30, and the load signal line SLoad provides the expander 20 to transmit the load signal to the target device 30, and the data output line SDataOut The expander 20 is provided to transmit a signal to the target device 30, and the data read line SDataIn provides the target device 30 to transmit a signal to the expander 20. The clock signal is used to define the transmission clock of the universal serial input/output bus. The load signal is a frame for defining the data output line SDataOut or the data read line SDataIn to transmit data. For example, a transmission frame is a load signal that is triggered for 8 clock cycles to the falling edge of the clock waveform after the rising edge of the clock waveform.
當擴展器20和目標裝置30透過通用串行輸入輸出匯流排10進行資料傳輸時,於步驟S401中,擴展器20經由資料輸出線SDataOut輸出分頁指示信號至目標裝置30,藉由分頁指示信號指示一個分頁位址。於步驟S403中,目標裝置30依據分頁指示信號,查找分頁位址指示的分頁資料。於步驟S405中,目標裝置30經由資料讀取線SDataIn將分頁位址和分頁資料輸出至擴展器20。於步驟S407中,擴展器20讀取經由資料讀取線SDataIn傳送的內容。於步驟S409中,當擴展器20判斷資料讀取線SDataIn傳送的內容具有分頁位址時,擴展器20接收分頁資料。When the expander 20 and the target device 30 transmit data through the universal serial input/output bus 10, in step S401, the expander 20 outputs a page indication signal to the target device 30 via the data output line SDataOut, which is indicated by the page indication signal. A paged address. In step S403, the target device 30 searches for the paging material indicated by the paging address according to the paging instruction signal. In step S405, the target device 30 outputs the paged address and the paging material to the expander 20 via the material read line SDataIn. In step S407, the expander 20 reads the content transmitted via the material reading line SDataIn. In step S409, when the expander 20 determines that the content transmitted by the material reading line SDataIn has a paging address, the expander 20 receives the paging material.
更詳細來說,通用串行輸入輸出匯流排10會先分配資料輸出線SDataOut和資料讀取線SDataIn的多個時槽。例如分配資料輸出線SDataOut中的8個時槽來傳輸分頁指示信號,而分配資料讀取線SDataIn中的8個時槽來傳輸分頁位址,另8個時槽來傳輸分頁位址下的分頁資料。在實際的例子中,以擴展器20為微處理器,目標裝置為CPLD來說,當微處理器和CPLD之間要進行資料傳輸時,微處理器會先透過資料輸出線SDataOut的8個時槽傳輸分頁指示信號給CPLD,以指示CPLD提供微處理器所需要的資料內容。當CPLD接收到分頁指示信號時,CPLD依據分頁指示信號指示的分頁位址,切換到分頁位址下的分頁,並將分頁位址和分頁位址下的分頁資料一併藉由資料讀取線SDataIn傳送給微處理器。In more detail, the universal serial input/output bus 10 first allocates a plurality of time slots of the data output line SDataOut and the data read line SDataIn. For example, eight time slots in the data output line SDataOut are allocated to transmit the paging instruction signal, and eight time slots in the data reading line SDataIn are allocated to transmit the paging address, and another eight time slots are used to transmit the paging in the paging address. data. In a practical example, the expander 20 is a microprocessor and the target device is a CPLD. When data is to be transferred between the microprocessor and the CPLD, the microprocessor first transmits the data output line SDataOut 8 times. The slot transmits a paging indicator to the CPLD to instruct the CPLD to provide the data content required by the microprocessor. When the CPLD receives the paging instruction signal, the CPLD switches to the paging under the paging address according to the paging address indicated by the paging indication signal, and uses the paging data under the paging address and the paging address together by the data reading line. SDataIn is passed to the microprocessor.
於本實施例中,分頁指示信號為8位元的信號,因此分配8個時槽來傳送。而資料讀取線SDataIn配合分頁指示信號的8個位元,亦分配了8個時槽給CPLD來傳送分頁位址,而另外的8個時槽提供給CPLD來傳送分頁資料。In the present embodiment, the paging instruction signal is an 8-bit signal, so 8 time slots are allocated for transmission. The data read line SDataIn is matched with the 8 bits of the paging indication signal, and 8 time slots are allocated to the CPLD to transmit the paging address, and the other 8 time slots are provided to the CPLD to transmit the paging data.
據此,微處理器透過主動地向CPLD要求資料,並透過分頁指示信號來指定所需要的資料內容,取代以往CPLD直接傳送資料給微處理器的方式,CPLD和微處理器之間可以傳輸的資料內容更為多元。舉例來說,以往CPLD透過資料讀取線SDataIn的16個時槽傳輸資料給微處理器時,只能傳送16筆資料給微處理器。而微處理器主動地向CPLD要求資料,並透過資料輸出線SDataOut的8個時槽來傳送分頁指示信號和資料讀取線SDataIn的8個時槽來傳送分頁資料的方式,CPLD可提供8×28 筆或更多的資料給微處理器。Accordingly, the microprocessor actively requests data from the CPLD and specifies the required data content through the paging instruction signal, instead of transmitting the data directly to the microprocessor by the CPLD, the CPLD and the microprocessor can transmit. The content of the information is more diverse. For example, when the CPLD transmits data to the microprocessor through the 16 time slots of the data read line SDataIn, only 16 pieces of data can be transmitted to the microprocessor. The microprocessor actively requests data from the CPLD, and transmits the paging instruction signal and the eight time slots of the data reading line SDataIn through the eight time slots of the data output line SDataOut to transmit the paging data. The CPLD can provide 8×. 2 8 or more pieces of information to the microprocessor.
也就是說,CPLD將8×28 個資料,每8筆資料分類至28 個分頁位址中,當CPLD收到微處理器主動要求28 個分頁位址中的其中一個分頁位址下的分頁資料時,CPLD將微處理器要求的該分頁位址和該分頁位址下的8筆資料一併從資料讀取線SDataIn的16個時槽傳輸資料給微處理器。於其他實施例中,CPLD的每個分頁位址下亦可以有更多或更少筆的資料,例如CPLD的一個分頁位址下具有16筆分頁資料時,當微處理器要求CPLD提供該分頁位址下的分頁資料時,CPLD批次地將16筆分頁資料輸出至微處理器,換言之,CPLD可以透過兩次的傳送,將分頁位址下的16筆分頁資料傳送給微處理器。That is, the CPLD 2 8 × 8 data, classified data to each of 8 pens 28 pagination addresses when the microprocessor receives CPLD active in claim 28 wherein a page address in the address pagination When paging data, the CPLD transmits the paging address requested by the microprocessor and the eight data under the paging address to the microprocessor from the 16 time slots of the data reading line SDataIn. In other embodiments, the CPLD may have more or less data under each page address, for example, when the CPLD has 16 paging materials under one paging address, when the microprocessor requests the CPLD to provide the paging. When paging data under the address, the CPLD batches 16 paging data to the microprocessor. In other words, the CPLD can transmit 16 paging data under the paging address to the microprocessor through two transmissions.
於本實施例中,CPLD可以依據微處理器輸出的分頁指示信號將分頁位址下的所有分頁資料一次地或分批地輸出給微處理器,於其他實施例中,微處理器亦可以透過其他合適的方式,指定CPLD輸出分頁下部分的分頁資料,例如分配其他時槽傳送要求信號來指定,本實施例不予限制。再者,本實施例亦不限制每個分頁位址下具有相同數量筆的資料,於所屬技術領域具有通常知識者可以依據實際的需求而配置分頁位址下的分頁資料數量。此外,前述實施例中,資料輸出線SDataOut傳輸分頁指示信號的時槽數量和資料讀取線SDataIn中用以傳輸分頁位址和分頁資料的時槽數量僅為方便說明之用,並非加以限制本發明其他可行的實施方式。In this embodiment, the CPLD can output all the paging data under the paging address to the microprocessor one time or batch according to the paging indication signal output by the microprocessor. In other embodiments, the microprocessor can also pass through the microprocessor. In other suitable manners, the paging data of the lower portion of the CPLD output page is specified, for example, the other time slot transmission request signal is assigned to be specified, which is not limited in this embodiment. Moreover, the embodiment does not limit the data having the same number of pens under each paging address. Those having ordinary knowledge in the technical field can configure the amount of paging data under the paging address according to actual needs. In addition, in the foregoing embodiment, the number of time slots for transmitting the paging indication signal by the data output line SDataOut and the number of time slots for transmitting the paging address and the paging data in the data reading line SDataIn are for convenience of explanation, and are not limited thereto. Other possible embodiments of the invention are found.
為了更清楚說明本發明通用串行輸入輸出的資料傳輸方法,茲舉另一實施例說明,請一併參照圖1和圖4,圖4係根據本發明另一實施例所繪示之通用串行輸入輸出的資料傳輸方法的步驟流程圖。如圖4所示,於步驟S401中,擴展器20依據時脈信號及負載信號,經由資料輸出線SDataOut輸出分頁指示信號至目標裝置30,換言之,擴展器20依據時脈信號的週期以及負載信號的信號框架,傳送分頁指示信號,當分頁指示信號為8位元時,擴展器20在負載信號上升邊緣輸出第一個位元,並在時脈信號的八個週期各別傳輸一個位元。In order to more clearly illustrate the data transmission method of the universal serial input and output of the present invention, another embodiment will be described. Please refer to FIG. 1 and FIG. 4 together. FIG. 4 is a general string according to another embodiment of the present invention. Flow chart of the steps of the data transmission method of line input and output. As shown in FIG. 4, in step S401, the expander 20 outputs a page indication signal to the target device 30 via the data output line SDataOut according to the clock signal and the load signal. In other words, the expander 20 depends on the period of the clock signal and the load signal. The signal frame transmits a paging indicator signal. When the paging indicator signal is 8 bits, the expander 20 outputs the first bit at the rising edge of the load signal and transmits one bit in each of the eight cycles of the clock signal.
於步驟S403中,目標裝置30判斷分頁指示信號指示的分頁位址,並於步驟S405中,依據分頁指示信號,查找分頁位址指示的分頁資料。接著,於步驟S407中,目標裝置30將分頁位址和分頁資料經由資料讀取線SDataIn分配的時槽輸出至擴展器20。於步驟S409中,擴展器20讀取經由資料讀取線SDataIn傳送的內容的分頁位址,並於步驟S411中,判斷資料讀取線SDataIn傳送內容的分頁位址是否符合輸出給目標裝置30的分頁指示信號所指示的分頁位址。當資料讀取線SDataIn傳送內容的分頁位址符合輸出給目標裝置30的分頁位址時,於步驟S413中,擴展器20接收資料讀取線SDataIn傳送的分頁資料。也就是說,當目標裝置30將分頁位址和分頁資料傳送給擴展器20後,擴展器20會更進一步判斷資料讀取線SDataIn中用以傳輸分頁位址的時槽,其所傳輸的分頁位址是否為要求的分頁位址,若分頁位址符合時,擴展器20才接收資料讀取線SDataIn傳輸的分頁資料。In step S403, the target device 30 determines the paging address indicated by the paging instruction signal, and in step S405, searches for the paging material indicated by the paging address according to the paging instruction signal. Next, in step S407, the target device 30 outputs the page address and the paging data to the expander 20 via the time slot allocated by the data read line SDataIn. In step S409, the expander 20 reads the paged address of the content transmitted via the material reading line SDataIn, and in step S411, determines whether the paged address of the content of the data reading line SDataIn matches the output to the target device 30. The paging indicates the paging address indicated by the signal. When the page address of the content of the data read line SDataIn matches the page address output to the target device 30, in step S413, the expander 20 receives the page data transmitted by the material read line SDataIn. That is, after the target device 30 transmits the paging address and the paging data to the expander 20, the expander 20 further determines the time slot in the data reading line SDataIn for transmitting the paging address, and the transmitted paging. Whether the address is the required paging address, if the paging address matches, the expander 20 receives the paging data transmitted by the data reading line SDataIn.
此外,當資料讀取線SDataIn傳送內容的分頁位址不符合輸出給目標裝置30的分頁位址時,於步驟S415中,擴展器20忽略資料讀取線SDataIn傳送的內容。Further, when the paging address of the content of the data reading line SDataIn does not conform to the paging address output to the target device 30, the expander 20 ignores the content transmitted by the material reading line SDataIn in step S415.
綜合以上所述,本發明實施例提供一種通用串行輸入輸出的資料傳輸方法,適用於以通用串行輸入輸出匯流排連接的擴展機和目標裝置中。於本發明實施例中,藉由擴展器主動地輸出分頁指示信號給目標裝置,使目標裝置依據分頁指示信號指示的分頁位址,來查找分頁位址下的分頁資料,並將分頁資料傳輸給擴展器,據以增加目標裝置可以經由通用串行輸入輸出匯流排傳輸給擴展器的資料量。於一個實施例中,擴展器可以一次性地或批次性當將分頁位址下的分頁資料輸出至擴展器中,並當擴展器或目標裝置不支援如I2 C或UART的傳輸介面時,擴展器和目標裝置之間不僅可透過通用串行輸入輸出匯流排來實現的資料通訊,通用串行輸入輸出匯流排還可以傳輸多種不同的資料內容。In summary, the embodiments of the present invention provide a data transmission method for universal serial input and output, which is suitable for use in an extension machine and a target device connected by a universal serial input/output bus. In the embodiment of the present invention, the pager indication signal is actively outputted to the target device by the expander, so that the target device searches for the paged data under the paged address according to the paged address indicated by the page indication signal, and transmits the paged data to The expander is configured to increase the amount of data that the target device can transmit to the expander via the universal serial input/output bus. In one embodiment, the expander can output the paging data under the paging address to the expander once or batch, and when the expander or the target device does not support the transmission interface such as I 2 C or UART The data communication between the expander and the target device can be realized not only through the universal serial input/output bus, but also the universal serial input/output bus can transmit a variety of different data contents.
雖然本發明以前述之實施例揭露如上,然其並非用以限定本發明。在不脫離本發明之精神和範圍內,所為之更動與潤飾,均屬本發明之專利保護範圍。關於本發明所界定之保護範圍請參考所附之申請專利範圍。Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.
10‧‧‧通用串行輸入輸出匯流排
20‧‧‧擴展器
30‧‧‧目標裝置
SClock‧‧‧時脈信號線
SLoad‧‧‧負載信號線
SDataOut‧‧‧資料輸出線
SDataIn‧‧‧資料讀取線10‧‧‧Common Serial I/O Bus
20‧‧‧Expander
30‧‧‧ Target device
SClock‧‧‧ clock signal line
SLoad‧‧‧ load signal line
SDataOut‧‧‧ data output line
SDataIn‧‧‧ data reading line
圖1係根據本發明一實施例所繪示之通用串行輸入輸出匯流排電性連接擴展器和目標裝置的示意圖。 圖2係根據本發明一實施例所繪示之通用串行輸入輸出匯流排時槽分配的示意圖。 圖3係根據本發明一實施例所繪示之通用串行輸入輸出的資料傳輸方法的步驟流程圖。 圖4係根據本發明另一實施例所繪示之通用串行輸入輸出的資料傳輸方法的步驟流程圖。FIG. 1 is a schematic diagram of a universal serial input/output bus bar electrical connection expander and a target device according to an embodiment of the invention. 2 is a schematic diagram of a slot assignment of a universal serial input/output bus bar according to an embodiment of the invention. FIG. 3 is a flow chart showing the steps of a data transmission method for universal serial input and output according to an embodiment of the invention. 4 is a flow chart showing the steps of a data transmission method for universal serial input and output according to another embodiment of the present invention.
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW104141937A TWI542998B (en) | 2015-12-14 | 2015-12-14 | Data transmission method for sgpio |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW104141937A TWI542998B (en) | 2015-12-14 | 2015-12-14 | Data transmission method for sgpio |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI542998B TWI542998B (en) | 2016-07-21 |
TW201721448A true TW201721448A (en) | 2017-06-16 |
Family
ID=56997196
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW104141937A TWI542998B (en) | 2015-12-14 | 2015-12-14 | Data transmission method for sgpio |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI542998B (en) |
-
2015
- 2015-12-14 TW TW104141937A patent/TWI542998B/en active
Also Published As
Publication number | Publication date |
---|---|
TWI542998B (en) | 2016-07-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2017084229A1 (en) | Data transmission method for serial general purpose input output | |
EP3614253B1 (en) | Data processing method and storage system | |
US10649815B2 (en) | Apparatus and method of managing shared resources in achieving IO virtualization in a storage device | |
US7603501B2 (en) | Communication circuit of serial peripheral interface devices | |
US7457897B1 (en) | PCI express-compatible controller and interface for flash memory | |
CN109766302B (en) | Method and device for managing equipment | |
US10127170B2 (en) | High density serial over LAN management system | |
US11513734B2 (en) | Hardware-based power management integrated circuit register file write protection | |
CN112673341A (en) | NVMe direct virtualization with configurable storage | |
CN103077102A (en) | Computer starting detection system | |
CN103176913B (en) | Hard disk method for mapping dynamically and the server applying it | |
CN1811480A (en) | Method and apparatus for real-time monitoring level signal | |
US9639489B2 (en) | I/O device sharing system and I/O device sharing method | |
CN109582592B (en) | Resource management method and device | |
CN103412838B (en) | A kind of expanding system, communication means, address configuration method, equipment and device | |
US9379980B1 (en) | Methods and systems for AXI ID compression | |
CN101620652B (en) | Main board, computer and method for protecting memory data | |
US11314668B2 (en) | Method, apparatus and system for device transparent grouping of devices on a bus | |
US20140164659A1 (en) | Regulating access to slave devices | |
US20180364946A1 (en) | Data storage device | |
TWI542998B (en) | Data transmission method for sgpio | |
US20140229688A1 (en) | Storage control device, storage system, and storage control method | |
CN112597080A (en) | Read request control device and method and memory controller | |
CN102902647B (en) | Be arranged on I2C from the asic chip of machine printed circuit board (PCB) and printed circuit board (PCB) | |
TWI467385B (en) | Mapping between two buses using serial addressing bits |