TW201719842A - 半導體元件結構及其形成方法 - Google Patents

半導體元件結構及其形成方法 Download PDF

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TW201719842A
TW201719842A TW105124289A TW105124289A TW201719842A TW 201719842 A TW201719842 A TW 201719842A TW 105124289 A TW105124289 A TW 105124289A TW 105124289 A TW105124289 A TW 105124289A TW 201719842 A TW201719842 A TW 201719842A
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Taiwan
Prior art keywords
layer
semiconductor device
device structure
nickel
gold
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TW105124289A
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English (en)
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TWI639217B (zh
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楊明憲
王俊智
楊敦年
洪豐基
黃信耀
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台灣積體電路製造股份有限公司
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

提供一半導體元件結構。半導體元件結構包括一第一半導體基板，第一半導體基板具有一第一表面、一第二表面、以及一凹槽。第二表面相對於第一表面。凹槽貫穿第一半導體基板。半導體元件結構包括一第一線路層，第一線路層係位於第二表面上。半導體元件結構包括第一接墊，第一接墊位於凹槽中並延伸至第一線路層以電性連接至第一線路層。半導體元件結構包括一鎳層，鎳層位於第一接墊上。半導體元件結構包括一金層，金層位於鎳層上。

Description

半導體元件結構及其形成方法
本發明有關於半導體元件結構，且特別是有關於具有鎳層的半導體元件結構。
半導體積體電路(IC)工業已歷經快速發展的階段。積體電路材料及設計在技術上的進步已生產出許多代的積體電路。每一代的積體電路比前代的積體電路具有更小且更複雜的電路。然而，這些進步也增加了積體電路在加工和製造上的複雜度。
在積體電路發展的進程中，功能性密度(亦即每一個晶片區域中內連接元件的數目)已經普遍增加，而幾何尺寸(亦即製程中所能創造出最小的元件或線路)則是下降。這種微縮化的過程通常可藉由增加生產效率及降低相關支出提供許多利益。
然而，因為特徵尺寸持續縮小，製程也持續變得更加難以實施。因此，形成具有越來越小的尺寸之可靠的半導體元件將是一個挑戰。
本發明一實施例提供一種半導體元件結構，包括：一第一半導體基板，具有一第一表面、一第二表面、以及 一凹槽，其中第二表面相對於第一表面，以及凹槽貫穿第一半導體基板；一第一線路層，位於第二表面上；一第一接墊，位於凹槽中且延伸至第一線路層以電性連接第一線路層；一鎳層，位於第一接墊上；以及一金層，位於鎳層上。
本發明一實施例提供一種半導體元件結構，包括：一第一半導體基板，具有一表面以及一凹槽，其中凹槽貫穿第一半導體基板；一第一線路層，位於表面上；一鎳層，位於凹槽中並延伸至第一線路層，以電性連接至第一線路層；以及一金層，位於鎳層上。
本發明另一實施例提供一種形成一半導體元件結構的方法，包括：提供一第一半導體基板，其中第一半導體基板具有一表面；形成一第一線路層於表面上；形成一凹槽於第一半導體基板中，其中凹槽貫穿第一半導體基板以暴露出第一線路層；形成一第一接墊於凹槽內，其中第一接墊延伸至第一線路層以電性連接第一線路層；形成一鎳層於第一接墊上；以及形成一金層於鎳層上。
10、160、950‧‧‧絕緣層
10a‧‧‧通孔
100、500、900、1300、1700、1800、1900、2000‧‧‧半導體元件結構
110、250‧‧‧半導體基板
112、114‧‧‧表面
114a、116‧‧‧凹槽
116a‧‧‧側壁
116b‧‧‧底面
120、150、260、910、930‧‧‧介電層
122、132a、134a、136a、152、162、192、P1、P2、P3‧‧‧開口
132、134、136、272、274、276、278‧‧‧線路層
142、144、282、284、286、960‧‧‧導電通孔結構
152a‧‧‧側壁
154‧‧‧頂面
156‧‧‧凹槽
180‧‧‧接墊
182‧‧‧帶狀部分
190‧‧‧介電填層
210‧‧‧不透光層
212‧‧‧遮光部
214‧‧‧格柵部
230‧‧‧鎳層
240‧‧‧金層
290‧‧‧鈀層
310‧‧‧導線
320‧‧‧接墊
330‧‧‧基板
340‧‧‧黏著層
410‧‧‧導電凸塊
920、940‧‧‧保護層
1710‧‧‧厚線路層
H、H1、H2、H3‧‧‧貫孔
R1、R2、R3‧‧‧導電環形結構
S‧‧‧線路基板
T1、T1’、T2、T2’、T3、T4‧‧‧厚度
W1‧‧‧內壁
第1A~1L、1L-1~1L-3圖繪示多個實施例之一半導體元件結構形成製程的各階段的剖面圖。
第2圖繪示多個實施例之一半導體元件結構的剖面圖。
第3圖繪示多個實施例之一半導體元件結構的剖面圖。
第4圖繪示多個實施例之一半導體元件結構的剖面圖。
第5A-5B圖係繪示多個實施例之一半導體元件結構的製程 的各步驟的剖面圖。
第6圖繪示多個實施例之一半導體元件結構的剖面圖。
第7圖繪示多個實施例之一半導體元件結構的剖面圖。
第8圖繪示多個實施例之一半導體元件結構的剖面圖。
第9圖繪示多個實施例之一半導體元件結構的剖面圖。
第10圖繪示多個實施例之一半導體元件結構的剖面圖。
第11圖繪示多個實施例之一半導體元件結構的剖面圖。
第12圖繪示多個實施例之一半導體元件結構的剖面圖。
第13圖繪示多個實施例之一半導體元件結構的剖面圖。
第14圖繪示多個實施例之一半導體元件結構的剖面圖。
第15圖繪示多個實施例之一半導體元件結構的剖面圖。
第16圖繪示多個實施例之一半導體元件結構的剖面圖。
第17圖繪示多個實施例之一半導體元件結構的剖面圖。
第18A圖繪示多個實施例之一半導體元件結構的剖面圖。
第18B圖繪示多個實施例之半導體元件結構的一鎳層、一導電環形結構、以及一部分的線路層的上視圖。
第19圖繪示多個實施例之一半導體元件結構的剖面圖。
第20圖繪示多個實施例之一半導體元件結構的剖面圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅 為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。在圖式中，實施例之形狀或是厚度可能擴大，以簡化或是突顯其特徵。再者，圖中未繪示或描述之元件，可為所屬技術領域中具有通常知識者所知的任意形式。
第1A~1L圖繪示多個實施例之一半導體元件結構形成製程的各階段的剖面圖。
如第1A圖所示，提供一半導體基板110。半導體基板110具有表面112、114。表面112、114彼此相對。半導體基板110為一半導體晶圓(例如一矽晶圓)或是一半導體晶圓的一部份。
在一些實施例中，半導體基板110是由一元素(elementary)半導體材料包括單晶、多晶、或非晶形(amorphous)結構的矽或鍺。在一些其他的實施例中，半導體基板110是由一化合物半導體構成，化合物半導體例如是碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、合金半導體(像是SiGe、或GaAsP)、或前述之組合。半導體基板110也可包括多層半導體、絕緣物上半導體(semiconductor on insulator；SOI)(像是絕緣體上覆矽或絕緣體上覆鍺)、或前述之組合。
在一些實施例中，如第1A圖所示，表面114具有一凹槽114a。在一些實施例中，如第1A圖所示，一絕緣層10形成在凹槽114a內。在一些實施例中，絕緣層10填充在凹槽114a內。
在一些實施例中，絕緣層10包括任何合適的絕緣材料，例如氫化碳氧化矽(hydrogenated silicon oxycarbide；SiCO：H)、氮氧化矽、氧化矽、硼矽酸鹽玻璃(BSG)、磷矽酸鹽玻璃(PSG)、硼磷矽玻璃(BPSG)、氟矽玻璃(FSG)、低介電常數材料、多孔介電材料、或前述之組合。
如第1A圖所示，在一些實施例中，沉積一介電層120於表面114與絕緣層10上。在一些實施例中，介電層120為一多層結構(multi-layer structure)。在一些實施例中，介電層120包括多個彼此堆疊的介電層(未繪示)。
在一些實施例中，介電層120包括任何適合的介電材料，例如氫化碳氧化矽(SiCO：H)、氮氧化矽、氧化矽、硼矽酸鹽玻璃(BSG)、磷矽酸鹽玻璃(PSG)、硼磷矽玻璃(BPSG)、氟矽玻璃(FSG)、低介電常數材料(low-k material)、多孔介電材料、或前述之組合。在一些實施例中，介電層120可以任何一種適合的沉積製程形成，例如化學氣相沉積製程、高密度電漿化學氣相沉積(HDPCVD)製程、旋轉塗布製程(spin-on process)、濺鍍製程(sputtering process)、或前述之組合。
如第1A圖所示，在一些實施例中，線路層132、134形成於介電層120中。在一些實施例中，一線路層136係埋於介電層120中。在一些實施例中，介電層120暴露出線路層136。線路層132、134、136包括任何適合的導電材料，例如銅、銅合金、銀、金、鋁、或前述之組合。
如第1A圖所示，在一些實施例中，多個導電通孔 結構142、144形成在介電層120中。在一些實施例中，導電通孔結構142電性連接線路層132至線路層134。在一些實施例中，導電通孔結構144電性連接線路層134至線路層136。
在一些實施例中，如第1B圖所示，翻轉(倒置)半導體基板110。如第1B圖所示，提供一半導體基板250。在一些實施例中，半導體基板250為一半導體晶圓(例如矽晶圓)或半導體晶圓的一部分。在一些實施例中，半導體基板250是由一元素(elementary)半導體材料所構成，元素半導體材料包括單晶、多晶、或非晶形(amorphous)結構的矽或鍺。
在一些其他的實施例中，半導體基板250是由一化合物半導體構成，化合物半導體例如是碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、合金半導體(例如SiGe、或GaAsP)、或前述之組合。半導體基板250也可包括多層半導體、絕緣物上半導體(semiconductor on insulator；SOI)(像是絕緣體上覆矽或絕緣體上覆鍺)、或前述之組合。
如第1B圖所示，在一些實施例中，沉積一介電層260於半導體基板250上。在一些實施例中，介電層260為一多層結構(multi-layer structure)。在一些實施例中，介電層260包括多個彼此堆疊的介電層(未繪示)。
在一些實施例中，介電層260包括任何適合的介電材料，例如氫化碳氧化矽(SiCO：H)、氮氧化矽、氧化矽、硼矽酸鹽玻璃(BSG)、磷矽酸鹽玻璃(PSG)、硼磷矽玻璃(BPSG)、氟矽玻璃(FSG)、低介電常數材料(low-k material)、多孔介電材料、或前述之組合。在一些實施例中，介電層260 可以任何一種適合的沉積製程形成，例如化學氣相沉積製程、高密度電漿化學氣相沉積(HDPCVD)製程、旋轉塗布製程(spin-on process)、濺鍍製程(sputtering process)、或前述之組合。
如第1B圖所示，在一些實施例中，線路層272、274、276形成於介電層260中。在一些實施例中，一線路層278係埋於介電層260中。在一些實施例中，介電層260暴露出線路層278。線路層272、274、276、278包括任何適合的導電材料，例如銅、銅合金、銀、金、鋁、或前述之組合。
在一些實施例中，如第1B圖所示，多個導電通孔結構282、284、286形成在介電層260中。在一些實施例中，導電通孔結構282電性連接線路層272至線路層274。在一些實施例中，導電通孔結構284電性連接線路層274至線路層276。
在一些實施例中，導電通孔結構286電性連接線路層276至線路層278。在一些實施例中，半導體基板250、介電層260、線路層272、274、276、278、以及導電通孔結構282、284、286共同形成一線路基板S。
在一些實施例中，如第1B圖所示，接合介電層260、120。在一些實施例中，線路層278、136彼此接合。在一些實施例中，線路層278、136彼此電性連接。
如第1B圖所示，一介電層150形成在表面112上。在一些實施例中，介電層150是一透明層。在一些實施例中，介電層150包括一高介電常數材料。在一些實施例中，介電層150包括氧化物及/或氮化物。在一些實施例中，介電層150包 括氧化矽、氮化矽、及/或氮氧化矽。在一些實施例中，介電層150是由任何合適的方法形成，例如化學氣相沉積製程、高密度電漿化學氣相沉積(HDPCVD)製程、旋轉塗布製程(spin-on process)、濺鍍製程(sputtering process)、或前述之組合。
如第1C圖所示，在一些實施例中，移除部分的介電層150和半導體基板110。在一些實施例中，在移除製程後，形成一開口152和一凹槽116。在一些實施例中，開口152貫穿介電層150。
在一些實施例中，凹槽116形成在半導體基板110中並凹陷自表面112。在一些實施例中，凹槽116貫穿半導體基板110。在一些實施例中，凹槽116暴露出一部分的絕緣層10。在一些實施例中，移除製程包括微影製程和蝕刻製程。
在一些實施例中，如第1C圖所示，一絕緣層160形成在介電層150上，以覆蓋開口152的側壁152a和凹槽116的側壁116a和底面116b。在一些實施例中，絕緣層160直接接觸絕緣層10。在一些實施例中，絕緣層160包括氧化物，如氧化矽。
在一些實施例中，如第1D圖所示，移除部分的絕緣層160、絕緣層10、以及介電層120。在一些實施例中，在移除製程後，形成多個開口162和通孔10a。在一些實施例中，開口162貫穿絕緣層160。在一些實施例中，通孔10a貫穿絕緣層10並***介電層120中以暴露線路層132。移除製程包括微影製程和蝕刻製程。
在一些實施例中，如第1E圖所示，一接墊180係形 成在凹槽116的底面116b上，並延伸入通孔10a中，以電連接線路層132。在一些實施例中，接墊180包括導電材料。在一些實施例中，接墊180包括鋁或銅。在一些實施例中，接墊180的形成方法包括物理氣相沉積製程、微影製程、和蝕刻製程。
在一些實施例中，如第1F圖所示，移除位於介電層150的頂面154上的絕緣層160。在一些實施例中，薄化位於凹槽116和開口152中且被接墊180暴露出的絕緣層160。在一些實施例中，移除和薄化絕緣層160的製程包括非等向性蝕刻製程(anisotropic etching process)。在一些實施例中，非等向性蝕刻製程包括乾蝕刻製程。
在一些實施例中，如第1G圖所示，一介電填層190係形成在凹槽116、開口152、和通孔10a中。在一些實施例中，介電填層190被填入凹槽116、開口152、和通孔10a中。在一些實施例中，介電填層190的形成方法包括一沉積製程和一化學研磨製程(chemical polishing process)。介電填層190包括氧化物(例如，氧化矽)或其他合適的介電材料。
在一些實施例中，如第1H圖所示，一不透光層(opaque layer)210形成在介電層150的頂面154。在一些實施例中，不透光層210具有多個遮光部212和多個格柵部214。在一些實施例中，遮光部212係用以阻擋光線，以避免光線照射到位於半導體基板110之上或之內的感光元件(例如光電二極體，photodiodes)。在一些實施例中，格柵部214係用以引導光線朝向位於半導體基板110之上或之內的感光元件(例如光電二極體)。
在一些實施例中，如第1I圖所示，移除介電層150之位於格柵部214之間或是位於格柵部214和遮光部212之間的部分。在一些實施例中，移除製程在介電層150中形成多個凹槽156，凹槽156位於格柵部214之間或是位於格柵部214和遮光部212之間。
在一些實施例中，保護層(未繪示)形成在不透光層210、介電層150、絕緣層160、和介電填層190上。在一些實施例中，保護層包括絕緣材料。
在一些實施例中，如第1J圖所示，移除部分的介電填層190。在一些實施例中，移除製程在介電填層190中形成一開口192。在一些實施例中，開口192暴露出位於底面116b(或絕緣層10)上的接墊180。
在一些實施例中，如第1K圖所示，形成一鎳層230於接墊180上。在一些實施例中，鎳層230的主要成分為鎳。在一些實施例中，鎳層230包含至少60重量百分比(wt%)的鎳。在一些實施例中，鎳層230包含至少80重量百分比(wt%)的鎳。
在一些實施例中，鎳層230係位於開口192內。在一些實施例中，整個鎳層230皆位於開口192內。在一些實施例中，鎳層230不延伸出開口192。在一些實施例中，鎳層230為一大抵平坦層(Substantially planar layer)。
在一些實施例中，鎳層230是用無電鍍製程形成。在一些實施例中，無電鍍製程能選擇性地沉積鎳層230在金屬層(即，接墊180)上。因此，在一些實施例中，鎳層230可在不使用微影製程和蝕刻製程的情況下形成。
在一些實施例中，如第1L圖所示，在鎳層230上形成一金層240。在一些實施例中，金層240的主要成分為金。在一些實施例中，金層240含有至少60重量百分比(wt%)的金。在一些實施例中，金層240含有至少80重量百分比(wt%)的金。
在一些實施例中，金層240是使用浸鍍製程(immersion plating process)形成。在一些實施例中，金層240和鎳層230不延伸到表面112上。在一些實施例中，整個金層240和整個鎳層230係位於開口192內。在一些實施例中，鎳層230的厚度T1大於金層240的厚度T2。
在一些實施例中，接墊180的材料不同於鎳層230的材料和金層240的材料。由於鎳的楊氏模數(Young’s modulus)大於接墊180的材料(例如，銅或鋁)的楊氏模數，因此，在相同的垂直應力(normal stress)之下，鎳的垂直應變(normal strain)小於接墊180的材料(例如，銅或鋁)的垂直應變。
因此，鎳層230的形成防止了接墊180在導線拉力測試(wire pull test)或推球測試(ball shear test)的過程中剝落(peeling off)。由於金的硬度小於鎳的硬度，金層240可緩衝後續進行的打線接合製程(wire bonding process)或球接合製程(ball bonding process)所產生的接合應力。在一些實施例中，在此步驟，半導體元件結構100係大體上形成。
在上視圖中，接墊180可具有不同的形狀，並且鎳層230和金層240僅形成在開口192所暴露出的接墊180上。不同形狀的接墊180係繪示於第IL-1、IL-2、IL-3圖。
在一些實施例中，第IL-1圖是第IL圖的接墊180、鎳層230、和金層240的上視圖。在一些實施例中，第1L圖繪示第1L-1圖之接墊180、鎳層230、和金層240沿剖面線I-I的剖面圖。如第1L和IL-1圖所示，接墊180係呈島狀(island-like shape)，並且鎳層230和金層240係形成在接墊180上。
在一些實施例中，第IL-2圖是第1L圖的接墊180、鎳層230、和金層240的上視圖。在一些實施例中，第1L圖繪示第1L-2圖之接墊180、鎳層230、和金層240沿剖面線I-I的剖面圖。在一些實施例中，如第1L和IL-2圖所示，接墊180具有彼此分離的帶狀部分182。在一些實施例中，鎳層230及金層240形成在帶狀部分182上。
在一些實施例中，第IL-3圖是第1L圖的接墊180、鎳層230、和金層240的上視圖。在一些實施例中，第1L圖繪示第1L-3圖之接墊180、鎳層230、和金層240沿剖面線I-I的剖面圖。在一些實施例中，如第1L和IL-3圖所示，接墊180係呈環形。在一些實施例中，鎳層230及金層240形成在接墊180上。
第2圖繪示多個實施例之一半導體元件結構的剖面圖。在一些實施例中，如第2圖所示，半導體元件結構100更包括一鈀層290。在一些實施例中，鈀層290形成在鎳層230及金層240之間。在一些實施例中，鈀層290是以無電鍍製程形成。
在一些實施例中，鈀具有類似於金的物理性質，並且比金便宜。因此，在一些實施例中，鈀層290的形成減少了用於形成金層230的金的使用量。因此，在一些實施例中，鈀層290的形成降低了半導體元件結構100的製造成本。
第3圖繪示多個實施例之一半導體元件結構的剖面圖。在一些實施例中，如第3圖所示，半導體元件結構100更包括一導線310，導線310連接金層240至一接墊320。導線310包括金、鋁、或其他適合的導電材料。在一些實施例中，接墊320位於一基板330上。在一些實施例中，接墊320包括導電材料，例如銅或鋁。
基板330包括半導體材料、塑膠材料、金屬材料、玻璃材料、陶瓷材料、或其它適合的材料。在一些實施例中，一黏著層340係形成在半導體基板250和基板330之間。在一些實施例中，黏著層340包括高分子材料(polymer material)。在一些其他實施例中，半導體基板250不位於基板330上。
第4圖繪示多個實施例之一半導體元件結構的剖面圖。在一些實施例中，如第4圖所示，半導體元件結構100更包括一導電凸塊410，導電凸塊410位於金層240上。在一些實施例中，導電凸塊410電性連接金層240。在一些實施例中，導電凸塊410包括導電材料。在一些實施例中，導電凸塊410包括焊料材料，例如錫(Sn)和銅(Cu)。
在一些實施例中，半導體元件結構100不具有接墊180，相關的詳細說明將示範性地介紹如下。
第5A-5B圖係繪示多個實施例之一半導體元件結構的製程的各步驟的剖面圖。在一些實施例中，在第1B圖的步驟之後，如第5A圖所示，移除部分的介電層150和半導體基底110。在一些實施例中，在移除製程之後，形成一開口152和一凹槽116。
在一些實施例中，開口152貫穿介電層150。在一些實施例中，凹槽116形成在半導體基板110中並凹陷自表面112。在一些實施例中，凹槽116貫穿半導體基板110。在一些實施例中，凹槽116暴露出一部分的絕緣層10。在一些實施例中，移除製程包括微影製程和蝕刻製程。
在一些實施例中，如第5A圖所示，在開口152和凹槽116中形成一絕緣層160。在一些實施例中，絕緣層160直接接觸絕緣層10。在一些實施例中，絕緣層160包括氧化物，如氧化矽。
在一些實施例中，如第5A圖所示，進行第1H-1I圖的步驟以形成一不透光層210和多個凹槽156。在一些實施例中，不透光層210係形成在介電層150的頂面154上。
在一些實施例中，不透光層210具有多個遮光部212和多個格柵部214。在一些實施例中，如第5A圖所示，凹槽156形成在介電層150中並位於格柵部214之間或位於格柵部214和遮光部212之間。
在一些實施例中，如第5B圖所示，移除部分的絕緣層160、10與介電層120。在一些實施例中，在移除製程之後，形成一貫孔H和一開口122。在一些實施例中，貫孔H貫穿絕緣層160、10。
在一些實施例中，開口122位於介電層120中且位於凹槽116之下。在一些實施例中，開口122連接貫孔H。在一些實施例中，開口122和貫孔H共同暴露出一部分的線路層132。移除製程包括微影製程和蝕刻製程。
在一些實施例中，如第5B圖所示，在貫孔H和開口122中形成一鎳層230。在一些實施例中，開口122填充有鎳層230。在一些實施例中，部分的貫孔H填充有鎳層230。在一些其它實施例中，鎳層230填滿整個貫孔H。
在一些實施例中，鎳層230電性連接線路層132。在一些實施例中，鎳層230直接接觸線路層132。在一些實施例中，鎳層230直接接觸絕緣層160、10和介電層120。
在一些實施例中，鎳層230是以無電鍍製程形成。在一些實施例中，鎳層230的主要成分為鎳。在一些實施例中，鎳層230包含至少60重量百分比(wt%)的鎳。在一些實施例中，鎳層230包含至少80重量百分比(wt%)的鎳。
在一些實施例中，如第5B圖所示，在鎳層230上形成一金層240。在一些實施例中，金層240的主要成分為金。在一些實施例中，金層240含有至少60重量百分比(wt%)的金。
在一些實施例中，金層240含有至少80重量百分比(wt%)的金。在一些實施例中，金層240是使用浸鍍製程(immersion plating process)形成。在一些實施例中，金層240和鎳層230不延伸到表面112上。在一些實施例中，在此步驟，大致上形成半導體元件結構500。
第6圖繪示多個實施例之一半導體元件結構的剖面圖。在一些實施例中，如第6圖所示，半導體元件結構500更包括一鈀層290。在一些實施例中，鈀層290係形成在鎳層230及金層240之間。在一些實施例中，鈀層290直接接觸絕緣層160。在一些實施例中，鈀層290是以無電鍍製程形成。
第7圖繪示多個實施例之一半導體元件結構的剖面圖。在一些實施例中，如第7圖所示，半導體元件結構500更包括一導線310，導線310連接金層240與一接墊320。在一些實施例中，導線310直接接觸金層240和接墊320。在一些實施例中，接墊320位於一基板330上。接墊320包括導電材料，例如銅或鋁。
基板330包括半導體材料、塑膠材料、金屬材料、玻璃材料、陶瓷材料、或其它適合的材料。在一些實施例中，在半導體基板250和基板330之間形成一黏著層340。在一些實施例中，黏著層340包括高分子材料。在一些其他實施例中，半導體基板250不位於基板330上。
第8圖繪示多個實施例之一半導體元件結構的剖面圖。在一些實施例中，如第8圖所示，半導體元件結構500更包括一導電凸塊410，導電凸塊410位於金層240上。在一些實施例中，導電凸塊410電性連接金層240。
在一些實施例中，導電凸塊410與金層240直接接觸。在一些實施例中，導電凸塊410包括導電材料。在一些實施例中，導電凸塊410包括焊料材料，例如錫(Sn)和銅(Cu)。
第9圖繪示多個實施例之一半導體元件結構的剖面圖。在一些實施例中，如第9圖所示，一半導體元件結構900類似於第1L圖的半導體元件結構100，兩者主要差異之處在於半導體元件結構900更包括一介電層910、一保護層920、一介電層930、一保護層940、一絕緣層950、以及一導電通孔結構960。
在一些實施例中，介電層910係形成在介電層120和線路層136上。在一些實施例中，介電層910、120具有相同的材料。在一些實施例中，保護層920形成在介電層910上。在一些實施例中，保護層920包括氧化物(例如，氧化矽)或氮化物。
在一些實施例中，線路基板S更包括介電層930和保護層940。在一些實施例中，介電層930形成在線路層278和介電層260上。
在一些實施例中，介電層930、260具有相同的材料。在一些實施例中，保護層940形成於介電層930上。在一些實施例中，保護層940包括氧化物(例如，氧化矽)或氮化物。在一些實施例中，保護層920和940彼此接合。
在一些實施例中，如第9圖所示，一貫孔H1貫穿介電層150、半導體基板110、與絕緣層10。在一些實施例中，貫孔H1暴露出一部分的介電層120。在一些實施例中，如第9圖所示，絕緣層950形成於貫孔H1的內壁W1上。在一些實施例中，絕緣層950包括氧化物，如氧化矽。
在一些實施例中，如第9圖所示，一貫孔H2貫穿介電層120。在一些實施例中，如第9圖所示，線路層136具有開口136a，開口136a位於貫孔H1和線路層278之間。
在一些實施例中，如第9圖所示，一貫孔H3貫穿介電層910、保護層920、介電層930、和保護層940。在一些實施例中，貫孔H1、H2、H3和開口136a一起暴露出一部分的線路層278。在一些實施例中，貫孔H1、H2、H3和開口136a彼此連 通(或彼此連接)。
在一些實施例中，導電通孔結構960係形成在貫孔H1、H2、H3和開口136a中。在一些實施例中，貫孔H1、H2、H3和開口136a填充有導電通孔結構960。在一些實施例中，導電通孔結構960依序貫穿介電層150、半導體基板110、絕緣層10、介電層120、介電層910、保護層920、保護層940、和介電層930。
在一些實施例中，導電通孔結構960電性連接線路層136至線路層278。在一些實施例中，導電通孔結構960包括導電材料。導電材料包括鎢、鋁、銅、或其它合適的導電材料。
第10圖繪示多個實施例之一半導體元件結構的剖面圖。在一些實施例中，如第10圖所示，半導體元件結構900更包括一鈀層290。在一些實施例中，鈀層290係形成在鎳層230及金層240之間。在一些實施例中，鈀層290是以無電鍍製程形成。
第11圖繪示多個實施例之一半導體元件結構的剖面圖。在一些實施例中，如第11圖所示，半導體元件結構900更包括一導線310，導線310連接金層240與一接墊320。在一些實施例中，接墊320位於基板330上。在一些實施例中，接墊320包括導電材料，例如銅或鋁。
基板330包括半導體材料、塑膠材料、金屬材料、玻璃材料、陶瓷材料、或其它適合的材料。在一些實施例中，一黏著層340形成在半導體基板250和基板330之間。在一些實施例中，黏著層340包括高分子材料。在一些其他實施例中， 半導體基板250不位於基板330上。
第12圖繪示多個實施例之一半導體元件結構的剖面圖。在一些實施例中，如第12圖所示，半導體元件結構900更包括一導電凸塊410，導電凸塊410位於金層240上。在一些實施例中，導電凸塊410電性連接金層240。
在一些實施例中，導電凸塊410直接接觸金層240。在一些實施例中，導電凸塊410包括導電材料。在一些實施例中，導電凸塊410包括焊料材料，例如錫(Sn)和銅(Cu)。
第13圖繪示多個實施例之一半導體元件結構的剖面圖。在一些實施例中，如第13圖所示，一半導體元件結構1300相似於第5B圖的半導體元件結構500，兩者主要差異之處在於半導體元件結構1300更包括一介電層910、一保護層920、一介電層930、一保護層940、一絕緣層950、以及一導電通孔結構960。
在一些實施例中，介電層910係形成在介電層120和線路層136上。在一些實施例中，介電層910、120具有相同的材料。在一些實施例中，保護層920係形成於介電層910上。在一些實施例中，保護層920包括氧化物(例如，氧化矽)或氮化物。
在一些實施例中，如第13圖所示，線路基板S更包括介電層930和保護層940。在一些實施例中，介電層930形成在線路層278和介電層260上。
在一些實施例中，介電層930、260具有相同的材料。在一些實施例中，保護層940形成在介電層930上。在一些 實施例中，保護層940包括氧化物(例如，氧化矽)或氮化物。在一些實施例中，保護層920、940彼此接合。
在一些實施例中，如第13圖所示，一貫孔H1貫穿介電層150、半導體基板110、與絕緣層10。在一些實施例中，貫孔H1暴露出一部分的介電層120。在一些實施例中，如第13圖所示，絕緣層950係形成在貫孔H1的內壁W1上。在一些實施例中，絕緣層950包括氧化物，如氧化矽。
在一些實施例中，如第13圖所示，一貫孔H2貫穿介電層120。在一些實施例中，如第13圖所示，線路層136具有一開口136a，開口136a位於貫孔H1和線路層278之間。
在一些實施例中，如第13圖所示，一貫孔H3貫穿介電層910、保護層920、介電層930、和保護層940。在一些實施例中，貫孔H1、H2、和H3和開口136a共同曝露出一部分的線路層278。在一些實施例中，貫孔H1、H2、和H3和開口136a彼此連通(或彼此連接)。
在一些實施例中，導電通孔結構960形成在貫孔H1、H2、H3和開口136a中。在一些實施例中，導電通孔結構960填滿貫孔H1、H2、H3和開口136a。
在一些實施例中，導電通孔結構960依序貫穿介電層150、半導體基板110、絕緣層10、介電層120、介電層910、保護層920、保護層940、和介電層930。
在一些實施例中，導電通孔結構960電性連接線路層136至線路層278。在一些實施例中，導電通孔結構960包括導電材料。導電材料包括鎢、鋁、銅、或其它合適的導電材料。
第14圖繪示多個實施例之一半導體元件結構的剖面圖。在一些實施例中，如第14圖所示，半導體元件結構1300更包括一鈀層290。在一些實施例中，鈀層290形成在鎳層230及金層240之間。在一些實施例中，鈀層290是以無電鍍製程形成。
第15圖繪示多個實施例之一半導體元件結構的剖面圖。如第15圖所示，半導體元件結構1300更包括一導線310，導線310連接金層240至一接墊320。導線310包括金、鋁、或其他適合的導電材料。在一些實施例中，接墊320位於一基板330上。在一些實施例中，接墊320包括導電材料，例如銅或鋁。
基板330包括半導體材料、塑膠材料、金屬材料、玻璃材料、陶瓷材料、或其它適合的材料。在一些實施例中，一黏著層340係形成在半導體基板250和基板330之間。在一些實施例中，黏著層340包括高分子材料。在一些其他實施例中，半導體基板250不位於基板330上。
第16圖繪示多個實施例之一半導體元件結構的剖面圖。如第16圖所示，半導體元件結構1300更包括一導電凸塊410，導電凸塊410位於金層240上。在一些實施例中，導電凸塊410電性連接金層240。在一些實施例中，導電凸塊410包括導電材料。在一些實施例中，導電凸塊410包括焊料材料，例如錫(Sn)和銅(Cu)。
第17圖繪示多個實施例之一半導體元件結構1700的剖面圖。在一些實施例中，如第17圖所示，半導體元件結構1700類似於第16圖的半導體元件結構1300，兩者主要差異之處 在於半導體元件結構1700更具有一厚線路層1710。厚線路層1710係位於鎳層230之下。
在一些實施例中，鎳層230直接接觸厚線路層1710。在一些實施例中，鎳層230電性連接厚線路層1710。在一些實施例中，厚線路層1710鄰近線路層132、134和導電通孔結構142。
在一些實施例中，厚線路層1710具有一厚度T1’。在一些實施例中，線路層132具有一厚度T2’。在一些實施例中，導電通孔結構142具有一厚度T3。在一些實施例中，線路層134具有一厚度T4。在一些實施例中，厚度T1’大於厚度T2’、T3、或T4。在一些實施例中，厚度T1’大於或等於厚度T2’、T3、和T4的總和。
由於過蝕刻(over etching)，貫孔H可延伸入厚線路層1710中。由於厚線路層1710具有較大的厚度T1’，故可避免貫孔H貫穿厚線路層1710。因此，形成厚線路層1710可提升半導體元件結構1700的良率。
第18A圖繪示多個實施例之一半導體元件結構1800的剖面圖。第18B圖繪示多個實施例之半導體元件結構1800的一鎳層230、一導電環形結構R1、以及一部分的線路層132的上視圖。
在一些實施例中，如第18A、18B圖所示，半導體元件結構1800類似於第16圖的半導體元件結構1300，兩者主要差異之處在於半導體元件結構1800更具有導電環形結構R1、R2、R3。
在一些實施例中，導電環形結構R1形成在介電層120中且位於線路層132上。在一些實施例中，導電環形結構R1連接線路層132。在一些實施例中，導電環形結構R2形成在介電層120中且位於線路層132、134之間。
在一些實施例中，導電環形結構R2連接線路層132、134。在一些實施例中，導電環形結構R3形成在介電層120中且位於線路層134、136之間。在一些實施例中，導電環形結構R3連接線路層134、136。在一些實施例中，導電環形結構R1、R2、R3和線路層132、134係由相同的材料製成。
在一些實施例中，導電環形結構R1、R2、R3和線路層132、134分別具有開口P1、P2、P3、132a、134a。在一些實施例中，開口P1、P2、P3、132a、134a彼此連通。在一些實施例中，鎳層230更延伸入開口P1、P2、P3、132a、134a中。在一些實施例中，導電環形結構R1、R2、R3和線路層132、134圍繞鎳層230。
導電環形結構R1、R2、R3和線路層132、134可共同防止(用於形成鎳層230的)電鍍液擴散到介電層120中。因此，可提高半導體元件結構1800的良率。
第19圖繪示多個實施例之一半導體元件結構的剖面圖。如第19圖所示，半導體元件結構1900類似於第17圖的半導體元件結構1700，兩者不同之處在於半導體元件結構1900更包括一導線310，且半導體元件結構1900不具有導電凸塊410。導線310連接金層240至一接墊320。導線310包括金、鋁、或其他適合的導電材料。
在一些實施例中，接墊320位於一基板330上。在一些實施例中，接墊320包括導電材料，例如銅或鋁。基板330包括半導體材料、塑膠材料、金屬材料、玻璃材料、陶瓷材料、或其它適合的材料。
在一些實施例中，一黏著層340係形成在半導體基板250和基板330之間。在一些實施例中，黏著層340包括高分子材料。在一些其他實施例中，半導體基板250不位於基板330上。
第20圖繪示多個實施例之一半導體元件結構的剖面圖。如第20圖所示，半導體元件結構2000類似於第18A圖的半導體元件結構1800，兩者主要差異之處在於半導體元件結構2000更包括一導線310，且半導體元件結構2000不具有導電凸塊410。導線310連接金層240至一接墊320。導線310包括金、鋁、或其他適合的導電材料。
在一些實施例中，接墊320位於一基板330上。在一些實施例中，接墊320包括導電材料，例如銅或鋁。基板330包括半導體材料、塑膠材料、金屬材料、玻璃材料、陶瓷材料、或其它適合的材料。
在一些實施例中，一黏著層340係形成在半導體基板250和基板330之間。在一些實施例中，黏著層340包括高分子材料。在一些其他實施例中，半導體基板250不位於基板330上。
根據一些實施例，提供半導體元件結構及其形成方法。用於形成半導體元件結構的方法係形成一鎳層於接墊 上，以防止接墊剝落。前述方法在鎳層上形成一金層，以緩衝打線接合製程或銲球接合製程所產生的接合應力。因此，形成鎳層和金層可提升半導體元件結構的可靠度。
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧絕緣層
100‧‧‧半導體元件結構
110、250‧‧‧半導體基板
112、114‧‧‧表面
120、150、260‧‧‧介電層
192‧‧‧開口
132、134、136、272、274、276、278‧‧‧線路層
142、144、282、284、286‧‧‧導電通孔結構
154‧‧‧頂面
180‧‧‧接墊
190‧‧‧介電填層
210‧‧‧不透光層
230‧‧‧鎳層
240‧‧‧金層
S‧‧‧線路基板
T1、T2‧‧‧厚度

Claims (10)

  1. 一種半導體元件結構，包括：一第一半導體基板，具有一第一表面、一第二表面、以及一凹槽，其中該第二表面相對於該第一表面，以及該凹槽貫穿該第一半導體基板；一第一線路層，位於該第二表面上；一第一接墊，位於該凹槽中且延伸至該第一線路層以電性連接該第一線路層；一鎳層，位於該第一接墊上；以及一金層，位於該鎳層上。
  2. 如申請專利範圍第1項所述之半導體元件結構，更包括：一導線，連接該金層至一第二接墊。
  3. 如申請專利範圍第1項所述之半導體元件結構，更包括：一鈀層，位於該鎳層與該金層之間。
  4. 如申請專利範圍第1項所述之半導體元件結構，更包括：一介電填層，填入該凹層以及該通孔中，其中該介電填層具有一開口，該開口暴露出位於該底面上的該第一接墊，且該鎳層與該金層係位於該開口中。
  5. 一種半導體元件結構，包括：一第一半導體基板，具有一表面以及一凹槽，其中該凹槽貫穿該第一半導體基板；一第一線路層，位於該表面上；一鎳層，位於該凹槽中並延伸至該第一線路層，以電性連接至該第一線路層；以及 一金層，位於該鎳層上。
  6. 如申請專利範圍第5項所述之半導體元件結構，其中該鎳層直接接觸該第一線路層。
  7. 如申請專利範圍第5項所述之半導體元件結構，更包括：一第二線路層，位於該表面上，其中該第一線路層的厚度大於該第二線路層的厚度。
  8. 如申請專利範圍第5項所述之半導體元件結構，更包括：一導電環形結構，位於該第一線路層以及該半導體基板之間，其中該導電環形結構圍繞該鎳層且連接該第一線路層。
  9. 一種形成一半導體元件結構的方法，包括：提供一第一半導體基板，其中該第一半導體基板具有一表面；形成一第一線路層於該表面上；形成一凹槽於該第一半導體基板中，其中該凹槽貫穿該第一半導體基板以暴露出該第一線路層；形成一第一接墊於該凹槽內，其中該第一接墊延伸至該第一線路層以電性連接該第一線路層；形成一鎳層於該第一接墊上；以及形成一金層於該鎳層上。
  10. 如申請專利範圍第9項所述之形成一半導體元件結構的方法，更包括：形成一導線連接該金層至一第二接墊。
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DE102016100017A1 (de) 2017-02-16
TWI639217B (zh) 2018-10-21
US11282802B2 (en) 2022-03-22
KR20170020198A (ko) 2017-02-22
US10475758B2 (en) 2019-11-12
US9881884B2 (en) 2018-01-30
CN106469701A (zh) 2017-03-01
US20170047301A1 (en) 2017-02-16
US20200013736A1 (en) 2020-01-09
US20180151522A1 (en) 2018-05-31

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