TW201715843A - Apparatus with bootstrap capacitor charging circuit - Google Patents
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Abstract
Description
本發明係關於一種具有靴帶電容充電電路的電子裝置。 The present invention relates to an electronic device having a bootstrap capacitor charging circuit.
第一圖繪示一傳統靴帶電容充電電路10的示意圖。該靴帶電容充電電路10包含一穩壓電路12和一二極體DX,藉以對一靴帶電容C1進行充電。如第一圖所示,該二極體DX具有一陽極端和一陰極端,其中,該陽極端耦接於該穩壓電路12,而該陰極端耦接於該靴帶電容C1。 The first figure shows a schematic diagram of a conventional shoe with a capacitor charging circuit 10. The shoe with capacitor charging circuit 10 includes a voltage stabilizing circuit 12 and a diode DX for charging a boot band capacitor C1. As shown in the first figure, the diode DX has an anode terminal and a cathode terminal, wherein the anode terminal is coupled to the voltage stabilizing circuit 12, and the cathode terminal is coupled to the shoe capacitor C1.
在運作時,當時脈信號CLK在邏輯0位準時,時脈信號CLK會透過驅動電路14關閉輸出級19中的上橋開關M1和透過驅動電路16開啟輸出級19中的下橋開關M2,所以電壓切換端SW的電壓位準為接地電位。此時,該穩壓電路12開始透過二極體DX對該靴帶電容C1進行充電。當該靴帶電容C1上端子A1的電壓位準等於該穩壓電路12提供的電壓GVDD減去二極體DX的順向壓降Vf時,該穩壓電路12方停止對該靴帶電容C1充電。 In operation, when the clock signal CLK is at the logic 0 level, the clock signal CLK turns off the upper bridge switch M1 in the output stage 19 through the drive circuit 14 and turns on the lower bridge switch M2 in the output stage 19 through the drive circuit 16, so The voltage level of the voltage switching terminal SW is the ground potential. At this time, the regulator circuit 12 starts to charge the shoe capacitor C1 through the diode DX. When the voltage level of the terminal A1 on the bootband capacitor C1 is equal to the voltage GVDD provided by the regulator circuit 12 minus the forward voltage drop Vf of the diode DX, the regulator circuit 12 stops the strap capacitor C1. Charging.
當時脈信號CLK在邏輯1位準時,時脈信號CLK 會透過驅動電路14開啟輸出級19中的上橋開關M1和透過驅動電路16關閉輸出級19中的下橋開關M2,所以電壓切換端SW的電壓VSW為供應電源電壓PVDD。此時,該靴帶電容CB上端子A1的電壓位準VA1係由式(1)決定。 When the pulse signal CLK is at the logic 1 level, the clock signal CLK The upper bridge switch M1 in the output stage 19 is turned on by the drive circuit 14, and the lower bridge switch M2 in the output stage 19 is turned off by the drive circuit 16, so that the voltage VSW of the voltage switch terminal SW is the supply power supply voltage PVDD. At this time, the voltage level VA1 of the terminal A1 on the shoe capacitor CB is determined by the formula (1).
VA1=PVDD+GVDD-Vf (1) VA1=PVDD+GVDD-Vf (1)
由式(1)可知,該靴帶電容C1上端子A1的電壓位準VA1大於供應電源電壓PVDD,因此驅動電路14可利用較高的電壓位準VA1將上橋驅動單元M1開啟,藉以驅動負載18。 It can be seen from the formula (1) that the voltage level VA1 of the terminal A1 on the bootband capacitor C1 is greater than the supply power supply voltage PVDD, so the drive circuit 14 can turn on the upper bridge drive unit M1 with a higher voltage level VA1, thereby driving the load. 18.
然而,當輸出級19為D類放大器(class D amplifier)的一部分,且該負載18為一揚聲器(speaker)時,具有單端(single-ended)輸出級的D類放大器組態會在傳送低頻輸出功率時產生一供電電路能量倒灌(bus pumping)的現象。該供電電路能量倒灌現象會使能量從該負載18回灌至供應電源,造成供應電源電壓PVDD的振幅波動。為了解決此一問題,在供應電源PVDD和地端間會有包含大電容的一分壓電路20連接於該負載18的另一側以吸收能量,如第二圖所示。然而,該分壓電路20可能造成D類放大器在開機時需要較長的淡入(fade-in)時間。 However, when output stage 19 is part of a class D amplifier and the load 18 is a speaker, a Class D amplifier configuration with a single-ended output stage will transmit low frequencies. When the power is output, a phenomenon of bus pumping of the power supply circuit is generated. The power supply circuit energy backflow phenomenon causes energy to be recharged from the load 18 to the supply power source, causing the amplitude of the supply power supply voltage PVDD to fluctuate. In order to solve this problem, a voltage dividing circuit 20 including a large capacitance between the power supply PVDD and the ground terminal is connected to the other side of the load 18 to absorb energy, as shown in the second figure. However, the voltage divider circuit 20 may cause the class D amplifier to require a long fade-in time when powering up.
根據本發明一實施例之一種電子裝置,包含一第一N型電晶體、一第二N型電晶體、一靴帶電容、一第一充電電路以及一第二充電電路。該第一N型電晶體耦接至一電源輸 入端和一切換節點之間,該電源輸入端用以接收一第二電源。該第二N型電晶體耦接至該切換節點和一接地端之間。該靴帶電容具有耦接至該切換節點的一下端子和一上端子,該上端子用以產生導通該第一N型電晶體的一電位。該第一充電電路耦接至該靴帶電容的該上端子,該第一充電電路藉由一第一電源以對該靴帶電容進行充電。該第二充電電路耦接至該靴帶電容的該上端子,該第二充電電路藉由該第二電源以對該靴帶電容進行充電。該第二電源的電位高於該第一電源的電位。 An electronic device according to an embodiment of the invention includes a first N-type transistor, a second N-type transistor, a bootband capacitor, a first charging circuit, and a second charging circuit. The first N-type transistor is coupled to a power supply The power input is used to receive a second power source between the input terminal and a switching node. The second N-type transistor is coupled between the switching node and a ground. The shoe strap capacitor has a lower terminal coupled to the switching node and an upper terminal for generating a potential to conduct the first N-type transistor. The first charging circuit is coupled to the upper terminal of the bootband capacitor, and the first charging circuit charges the bootband capacitor by a first power source. The second charging circuit is coupled to the upper terminal of the bootband capacitor, and the second charging circuit charges the bootband capacitor by the second power source. The potential of the second power source is higher than the potential of the first power source.
根據本發明另一實施例之一種電子裝置,包含一第一D類放大器、一第二D類放大器、一第一電感、一第二電感以及一揚聲器。該第一D類放大器包含一第一N型電晶體,其耦接至一電源輸入端和一切換節點之間,該電源輸入端用以接收一第二電源。該第一D類放大器包含一第二N型電晶體,其耦接至該切換節點和一接地端之間。該第一D類放大器包含一靴帶電容,其具有耦接至該切換節點的一下端子和一上端子,該上端子用以產生導通該第一N型電晶體的一電位。該第一D類放大器包含一第一充電電路,其耦接至該靴帶電容的該上端子,該第一充電電路藉由一第一電源以對該靴帶電容進行充電。該第一D類放大器包含一第二充電電路,其耦接至該靴帶電容的該上端子,該第二充電電路藉由該第二電源以一定電流對該靴帶電容進行充電。該第二D類放大器包含一 第一N型電晶體,其耦接至一電源輸入端和一切換節點之間,該電源輸入端用以接收該第二電源。該第二D類放大器包含一第二N型電晶體,其耦接至該切換節點和一接地端之間。該第二D類放大器包含一靴帶電容,其具有耦接至該切換節點的一下端子和一上端子,該上端子用以產生導通該第一N型電晶體的一電位。該第二D類放大器包含一第一充電電路,其耦接至該靴帶電容的該上端子,該第一充電電路藉由一第一電源以對該靴帶電容進行充電。該第二D類放大器包含一第二充電電路,其耦接至該靴帶電容的該上端子,該第二充電電路藉由該第二電源以一定電流對該靴帶電容進行充電。該第一電感耦接至該第一D類放大器的該切換節點。該第二電感耦接至該第二D類放大器的該切換節點。該揚聲器耦接於該第一電感和該第二電感之間。 An electronic device according to another embodiment of the present invention includes a first class D amplifier, a second class D amplifier, a first inductor, a second inductor, and a speaker. The first class D amplifier includes a first N-type transistor coupled between a power input terminal and a switching node for receiving a second power source. The first class D amplifier includes a second N-type transistor coupled between the switching node and a ground. The first class D amplifier includes a bootband capacitor having a lower terminal coupled to the switching node and an upper terminal for generating a potential to conduct the first N-type transistor. The first class D amplifier includes a first charging circuit coupled to the upper terminal of the shoe capacitor, the first charging circuit charging the shoe capacitor by a first power source. The first class D amplifier includes a second charging circuit coupled to the upper terminal of the boot band capacitor, and the second charging circuit charges the shoe cap capacitor with a certain current by the second power source. The second class D amplifier comprises a The first N-type transistor is coupled between a power input end and a switching node, and the power input end is configured to receive the second power source. The second class D amplifier includes a second N-type transistor coupled between the switching node and a ground. The second class D amplifier includes a bootband capacitor having a lower terminal coupled to the switching node and an upper terminal for generating a potential to conduct the first N-type transistor. The second class D amplifier includes a first charging circuit coupled to the upper terminal of the shoe capacitor, the first charging circuit charging the shoe capacitor by a first power source. The second class D amplifier includes a second charging circuit coupled to the upper terminal of the boot band capacitor, and the second charging circuit charges the shoe cap capacitor with a certain current by the second power source. The first inductor is coupled to the switching node of the first class D amplifier. The second inductor is coupled to the switching node of the second class D amplifier. The speaker is coupled between the first inductor and the second inductor.
10‧‧‧靴帶電容充電電路 10‧‧‧ Boots with capacitor charging circuit
12‧‧‧穩壓電路 12‧‧‧ Voltage regulator circuit
14,16‧‧‧驅動電路 14,16‧‧‧ drive circuit
18‧‧‧負載 18‧‧‧load
19‧‧‧輸出級 19‧‧‧Output level
20‧‧‧分壓電路 20‧‧‧voltage circuit
30‧‧‧電子裝置 30‧‧‧Electronic devices
32‧‧‧D類放大器 32‧‧‧Class D amplifier
322,322”‧‧‧輸出級 322,322”‧‧‧Output
324,324”‧‧‧靴帶電容充電電路 324,324"‧‧‧ boots with capacitor charging circuit
3242,3242”‧‧‧低壓充電電路 3242, 3242" ‧‧‧Low-voltage charging circuit
3244,3244’,3244”‧‧‧高壓充電電路 3244, 3244', 3244" ‧ ‧ high voltage charging circuit
326,328,326”,328”‧‧‧驅動電路 326,328,326",328"‧‧‧ drive circuit
34‧‧‧揚聲器 34‧‧‧Speakers
36‧‧‧分壓電路 36‧‧‧voltage circuit
42‧‧‧穩壓電路 42‧‧‧Variable circuit
60‧‧‧電子裝置 60‧‧‧Electronic devices
62,64‧‧‧D類放大器 62,64‧‧‧D class amplifier
66‧‧‧揚聲器 66‧‧‧Speakers
C1,CBT,CBT”‧‧‧靴帶電容 C1, CBT, CBT"‧‧‧ boots with capacitor
C3,C4‧‧‧電容 C3, C4‧‧‧ capacitor
CL,CL1,CL2‧‧‧電容 CL, CL1, CL2‧‧‧ capacitor
D1,D2,DX‧‧‧二極體 D1, D2, DX‧‧‧ diode
L1,L2‧‧‧電感 L1, L2‧‧‧ inductance
M1,M2,MU,MD‧‧‧電晶體 M1, M2, MU, MD‧‧‧ transistor
N1‧‧‧電晶體 N1‧‧‧O crystal
P1,P2,P3,P4,P5‧‧‧電晶體 P1, P2, P3, P4, P5‧‧‧ transistors
ZD1,ZD2‧‧‧箝制元件 ZD1, ZD2‧‧‧ clamp components
第一圖繪示一傳統靴帶電容充電電路的示意圖。 The first figure shows a schematic diagram of a conventional shoe with a capacitor charging circuit.
第二圖繪示一傳統單端輸出的D類放大器的示意圖。 The second figure shows a schematic diagram of a conventional single-ended output class D amplifier.
第三圖顯示結合本發明一實施例之具有靴帶電容充電電路的電子裝置之方塊示意圖。 The third figure shows a block diagram of an electronic device having a bootstrap capacitor charging circuit in accordance with an embodiment of the present invention.
第四圖顯示結合本發明一實施例之該低壓充電電路和該高壓充電電路之電路圖。 The fourth figure shows a circuit diagram of the low voltage charging circuit and the high voltage charging circuit in combination with an embodiment of the present invention.
第五圖顯示結合本發明另一實施例之該低壓充電電路和 該高壓充電電路之電路圖。 The fifth figure shows the low voltage charging circuit and another embodiment of the present invention. A circuit diagram of the high voltage charging circuit.
第六圖顯示結合本發明另一實施例之具有靴帶電容充電電路的電子裝置之方塊示意圖。 Figure 6 is a block diagram showing an electronic device having a bootstrap capacitor charging circuit in accordance with another embodiment of the present invention.
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有通常知識者應可理解,製造商可能會用不同的名詞來稱呼同樣的元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式,而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」或「包含」係為一開放式的用語,故應解釋成「包含但不限定於」。另外,「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此,若文中描述一第一裝置耦接於一第二裝置,則代表該第一裝置可直接電氣連接於該第二裝置,或透過其他裝置或連接手段間接地電氣連接至該第二裝置。 Certain terms are used throughout the description and following claims to refer to particular elements. It should be understood by those of ordinary skill in the art that manufacturers may refer to the same elements by different nouns. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" or "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.
第三圖顯示結合本發明一實施例之具有靴帶電容充電電路的電子裝置30之方塊示意圖。在本實施例中,該電子裝置30包含一D類放大器32。該D類放大器32包含一輸出級322,其中該輸出級322由一上橋開關MU和一下橋開關MD所組成。該上橋開關MU和該下橋開關MD以串聯方式耦接於一電源輸入端(接收一供應電源電壓PVDD)和一接地端之間。在本實施例中,該上橋開關MU和該下橋開關MD為一N型電晶 體元件。 The third figure shows a block diagram of an electronic device 30 having a bootstrap capacitor charging circuit in accordance with an embodiment of the present invention. In the present embodiment, the electronic device 30 includes a class D amplifier 32. The class D amplifier 32 includes an output stage 322, wherein the output stage 322 is comprised of an upper bridge switch MU and a lower bridge switch MD. The upper bridge switch MU and the lower bridge switch MD are coupled in series between a power input terminal (receiving a supply power voltage PVDD) and a ground terminal. In this embodiment, the upper bridge switch MU and the lower bridge switch MD are an N-type electric crystal. Body component.
參考第三圖,該電子裝置30另包含一靴帶電容充電電路324用以對一靴帶電容CBT進行充電。該靴帶電容充電電路324包含一低壓充電電路3242和一高壓充電電路3244。該靴帶電容CBT耦接於該靴帶電容充電電路324以及該上橋開關MU和該下橋開關MD的一交越點SW之間。該靴帶電容CBT係藉由該靴帶電容充電電路34充電以產生導通該上橋開關MU的導通(turn on)電壓。 Referring to the third figure, the electronic device 30 further includes a bootband capacitor charging circuit 324 for charging a bootband capacitor CBT. The shoe with capacitor charging circuit 324 includes a low voltage charging circuit 3242 and a high voltage charging circuit 3244. The shoe strap capacitor CBT is coupled between the shoe strap capacitor charging circuit 324 and a crossover point SW of the upper bridge switch MU and the lower bridge switch MD. The bootband capacitor CBT is charged by the bootband capacitor charging circuit 34 to produce a turn-on voltage that turns on the upper bridge switch MU.
第四圖顯示結合本發明一實施例之該低壓充電電路3242和該高壓充電電路3244之電路圖。參考第四圖,該低壓充電電路342包含一穩壓電路42和一二極體D1。該穩壓電路42用以產生一穩定的供應電壓GVDD。在本發明一實施例中,該供應電壓GVDD為5V,然而,本發明不應以此為限。該二極體D1具有接收該供應電壓GVDD的一陽極(Anode)和耦接至該靴帶電容CBT的上端子BST的一陰極(Cathode)。 The fourth figure shows a circuit diagram of the low voltage charging circuit 3242 and the high voltage charging circuit 3244 in connection with an embodiment of the present invention. Referring to the fourth figure, the low voltage charging circuit 342 includes a voltage stabilizing circuit 42 and a diode D1. The voltage stabilizing circuit 42 is configured to generate a stable supply voltage GVDD. In an embodiment of the invention, the supply voltage GVDD is 5V. However, the invention should not be limited thereto. The diode D1 has an anode (Anode) that receives the supply voltage GVDD and a cathode that is coupled to the upper terminal BST of the shoe capacitor CBT.
該高壓充電電路3244包含一偏壓電流源IB1、P型電晶體P1和P2,一二極體D2以及一箝制元件ZD1。在本實施例中,該箝制元件ZD1為一齊納二極體(Zener diode),然而,本發明不應以此為限,任何具有箝制電壓功能的半導體元件,例如一雪崩二極體或一瞬態電壓抑制器(Transient Voltage Suppresser,TVS)均可實施為該箝制元件。該P型電晶體P1具有接收該供應電源電壓PVDD的一源極端,接收該偏壓 電流源IB1的一汲極端和耦接至該汲極端的一閘極端。該P型電晶體P2具有接收該供應電源電壓PVDD的一源極端和耦接至該P型電晶體P1的該閘極端的一閘極端。該箝制元件ZD1具有耦接至該P型電晶體P2的一汲極端的一第一端和耦接至該交越點SW的一第二端。在本實施例中,該箝制元件ZD為一齊納二極體ZD1,其具有耦接至該P型電晶體P2的一汲極端的一陰極和耦接至該交越點SW的一陽極。該二極體D2具有耦接至該P型電晶體P2的該汲極端的一陽極和耦接至該靴帶電容CBT的該上端子BST的一陰極。在本發明一實施例中,該供應電源電壓PVDD為24V,該偏壓電流源IB1的電流值為10μA,然而,本發明不應以此為限。 The high voltage charging circuit 3244 includes a bias current source IB1, P-type transistors P1 and P2, a diode D2, and a clamping element ZD1. In this embodiment, the clamping component ZD1 is a Zener diode. However, the invention should not be limited thereto. Any semiconductor component having a clamping voltage function, such as an avalanche diode or a transient state. A voltage regulator (Transient Voltage Suppresser, TVS) can be implemented as the clamp component. The P-type transistor P1 has a source terminal receiving the supply power voltage PVDD, and receives the bias voltage A drain terminal of current source IB1 is coupled to a gate terminal of the drain terminal. The P-type transistor P2 has a source terminal receiving the supply power voltage PVDD and a gate terminal coupled to the gate terminal of the P-type transistor P1. The clamping component ZD1 has a first end coupled to a terminal end of the P-type transistor P2 and a second end coupled to the crossing point SW. In the present embodiment, the clamping element ZD is a Zener diode ZD1 having a cathode coupled to a terminal of the P-type transistor P2 and an anode coupled to the crossing point SW. The diode D2 has an anode coupled to the drain terminal of the P-type transistor P2 and a cathode coupled to the upper terminal BST of the boot capacitor CBT. In an embodiment of the invention, the supply voltage PVDD is 24V, and the current value of the bias current source IB1 is 10μA. However, the invention should not be limited thereto.
以下參考第三圖和第四圖的電路圖說明該靴帶電容CBT的充電方式。當該D類放大器32在供電後的一啟動時間內,驅動電路326和328尚未提供驅動信號給該上橋開關MU和該下橋開關MD。此時,該上橋開關MU和該下橋開關MD為關閉狀態。由於揚聲器18是由具有單端輸出級的D類放大器32所推動,為了解決前述供電電路能量倒灌的現象,該揚聲器18的右側會耦接至包含大電容C1和C2的一分壓電路36以吸收能量。因為該分壓電路36會等分該供應電源電壓PVDD和該接地端之間的電位差值,因此,該揚聲器的左側端X1的電壓為1/2*PVDD,且該交越點SW的電壓亦為1/2*PVDD。 The charging mode of the shoe belt capacitor CBT will be described below with reference to the circuit diagrams of the third and fourth figures. When the class D amplifier 32 is within a startup time after power is supplied, the drive circuits 326 and 328 have not supplied a drive signal to the upper bridge switch MU and the lower bridge switch MD. At this time, the upper bridge switch MU and the lower bridge switch MD are in a closed state. Since the speaker 18 is driven by the class D amplifier 32 having a single-ended output stage, in order to solve the phenomenon of energy backflow of the power supply circuit, the right side of the speaker 18 is coupled to a voltage dividing circuit 36 including large capacitors C1 and C2. To absorb energy. Because the voltage dividing circuit 36 bisects the potential difference between the supply voltage PVDD and the ground, the voltage of the left end X1 of the speaker is 1/2*PVDD, and the voltage of the crossing point SW Also 1/2*PVDD.
在此狀況下,由於該低壓充電電路3242中的該穩 壓電路42所提供的供應電壓GVDD小於該交越點SW的電壓,因此,該低壓充電電路3242不會對該靴帶電容CBT進行充電。另一方面,由於用於該高壓充電電路3244中的該供應電源電壓PVDD大於該交越點SW的電壓,因此,第四圖中的該P型電晶體P2會以比例於該偏壓電流源IB1的電流值對該靴帶電容CBT進行充電。此時,該低壓充電電路3242中的該二極體D1會避免電流回灌至該穩壓電路42。 In this case, due to the stability in the low voltage charging circuit 3242 The supply voltage GVDD provided by the voltage circuit 42 is smaller than the voltage of the crossover point SW, and therefore, the low voltage charging circuit 3242 does not charge the shoe capacitor CBT. On the other hand, since the supply voltage PVDD used in the high voltage charging circuit 3244 is greater than the voltage of the crossover point SW, the P-type transistor P2 in the fourth figure is proportional to the bias current source. The current value of IB1 charges the shoe capacitor CBT. At this time, the diode D1 in the low voltage charging circuit 3242 can prevent current from being recharged to the voltage stabilizing circuit 42.
現以第三圖和第四圖說明該二極體D2和該齊納二極體ZD1的一選擇方式。考量到正常運作時(亦即該驅動電路326和328有提供驅動信號後),該驅動電路326的電壓位準差值(節點BST和節點SW間的電位差值)較佳為實質上等於該驅動電路328的電壓位準差值(該供應電壓GVDD和該接地端之間的電位差值),因此該節點BST可選擇為充電至1/2*PVDD+GVDD。參考第四圖,在一較佳實施例中,該齊納二極體ZD1的逆向崩潰電壓值可選擇為GVDD+Vf,其中Vf等於二極體D2的順向偏壓值。如此一來,當該高壓充電電路3244對該靴帶電容CBT進行充電時,該齊納二極體ZD1工作於逆向偏壓區,而該二極體D2工作於順向偏壓區,因此該節點BST的電壓可箝制至1/2*PVDD+GVDD。 A selection of the diode D2 and the Zener diode ZD1 will now be described in the third and fourth figures. Considering normal operation (i.e., after the drive circuits 326 and 328 provide a drive signal), the voltage level difference (the potential difference between the node BST and the node SW) of the drive circuit 326 is preferably substantially equal to the drive. The voltage level difference of circuit 328 (the potential difference between the supply voltage GVDD and the ground), so the node BST can be selected to charge to 1/2*PVDD+GVDD. Referring to the fourth figure, in a preferred embodiment, the reverse collapse voltage value of the Zener diode ZD1 can be selected as GVDD + Vf, where Vf is equal to the forward bias value of the diode D2. In this way, when the high voltage charging circuit 3244 charges the shoe capacitor CBT, the Zener diode ZD1 operates in a reverse bias region, and the diode D2 operates in a forward bias region, so The voltage at node BST can be clamped to 1/2*PVDD+GVDD.
第五圖顯示結合本發明另一實施例之該高壓充電電路3244’之電路圖。參考第五圖,該低壓充電電路3244’包含一偏壓電流源IB2、P型電晶體P3、P4和P5,一N型電晶體 N1、一二極體D3以及一齊納二極體(Zener diode)ZD2。該P型電晶體P3具有接收該供應電源電壓PVDD的一源極端,接收該偏壓電流源IB2的一汲極端和耦接至該汲極端的一閘極端。該P型電晶體P4具有接收該供應電源電壓PVDD的一源極端和耦接至該P型電晶體P3的該閘極端的一閘極端。該P型電晶體P5具有接收該供應電源電壓PVDD的一源極端和耦接至該P型電晶體P3的該閘極端的一閘極端。該N型電晶體N1具有耦接該P型電晶體P5的一汲極端的一汲極端和耦接至該P型電晶體P4的一汲極端的一閘極端。 The fifth figure shows a circuit diagram of the high voltage charging circuit 3244' in connection with another embodiment of the present invention. Referring to the fifth figure, the low voltage charging circuit 3244' includes a bias current source IB2, P-type transistors P3, P4 and P5, an N-type transistor. N1, a diode D3, and a Zener diode ZD2. The P-type transistor P3 has a source terminal receiving the supply power voltage PVDD, receiving a drain terminal of the bias current source IB2 and a gate terminal coupled to the drain terminal. The P-type transistor P4 has a source terminal receiving the supply power supply voltage PVDD and a gate terminal coupled to the gate terminal of the P-type transistor P3. The P-type transistor P5 has a source terminal receiving the supply power supply voltage PVDD and a gate terminal coupled to the gate terminal of the P-type transistor P3. The N-type transistor N1 has a terminal end coupled to a terminal of the P-type transistor P5 and a gate terminal coupled to a terminal of the P-type transistor P4.
該齊納二極體ZD2具有耦接至該P型電晶體P4的該汲極端的一陰極和耦接至該交越點SW的一陽極。該二極體D3具有耦接至該N型電晶體N1的一源極端的一陽極和耦接至該靴帶電容CBT的該上端子BST的一陰極。在本發明一實施例中,該供應電源電壓PVDD為24V,該偏壓電流源IB2的電流值為10μA,然而,本發明不應以此為限。 The Zener diode ZD2 has a cathode coupled to the drain terminal of the P-type transistor P4 and an anode coupled to the crossover point SW. The diode D3 has an anode coupled to a source terminal of the N-type transistor N1 and a cathode coupled to the upper terminal BST of the shoe capacitor CBT. In an embodiment of the invention, the supply voltage PVDD is 24V, and the current value of the bias current source IB2 is 10μA. However, the invention should not be limited thereto.
在運作上,由於該揚聲器18的右側會耦接至包含大電容C1和C2的該分壓電路36以吸收前述供電電路能量倒灌的能量,如第三圖所示。因此,第五圖中的節點SW的電壓初始值為1/2*PVDD。在該D類放大器32供電後的一啟動時間內,該驅動電路326和328尚未提供驅動信號給該上橋開關MU和該下橋開關MD。該高壓充電電路3244’中的該P型電晶體P5會以比例於該偏壓電流源IB2的電流值對該靴帶電容CBT進行 充電。在一實施例中,該節點BST可選擇為充電至1/2*PVDD+GVDD。因此,該齊納二極體ZD1的逆向崩潰電壓值可選擇為VGS,N1+GVDD+Vf,其中VGS,M1為該N型電晶體N1的閘-源極電壓位準差值,而Vf等於二極體D3的順向偏壓值。如此一來,當該高壓充電電路3244’對該靴帶電容CBT進行充電時,該齊納二極體ZD2工作於逆向偏壓區,而該二極體D3工作於順向偏壓區,因此該節點BST的電壓可箝制至1/2*PVDD+GVDD。 In operation, since the right side of the speaker 18 is coupled to the voltage dividing circuit 36 including the large capacitors C1 and C2 to absorb the energy of the power supply circuit energy backflow, as shown in the third figure. Therefore, the initial value of the voltage of the node SW in the fifth figure is 1/2*PVDD. The drive circuits 326 and 328 have not provided a drive signal to the upper bridge switch MU and the lower bridge switch MD during a start-up time after the class D amplifier 32 is powered. The P-type transistor P5 in the high voltage charging circuit 3244' charges the shoe capacitor CBT in proportion to the current value of the bias current source IB2. In an embodiment, the node BST may be selected to charge to 1/2*PVDD+GVDD. Therefore, the reverse collapse voltage value of the Zener diode ZD1 can be selected as V GS, N1 + GVDD + Vf, where V GS, M1 is the gate-source voltage level difference of the N-type transistor N1, and Vf is equal to the forward bias value of the diode D3. In this way, when the high voltage charging circuit 3244' charges the shoe capacitor CBT, the Zener diode ZD2 operates in the reverse bias region, and the diode D3 operates in the forward bias region. The voltage at this node BST can be clamped to 1/2*PVDD+GVDD.
在第三圖中,該揚聲器34是由具有單端輸出級的D類放大器32所推動。在本發明另一實施例中,揚聲器可由具有H-橋式(H-bridge)的電子裝置60所推動,如第六圖所示。參考第六圖,揚聲器66是由輸出級322中的上橋開關MU和下橋開關MD以及輸出級322”中的上橋開關MU和下橋開關MD所推動。輸出級322中的上橋開關MU和下橋開關MD以及輸出級322”中的上橋開關MU和下橋開關MD形成一H-橋式組態。揚聲器66左側的D類放大器62和揚聲器66右側的D類放大器64具有近似的運作方式,具有H-橋式組態的D類放大器在正常運作時的工作模式已為熟悉本項技術之人士所熟知,在此不再贅述。 In the third figure, the speaker 34 is driven by a class D amplifier 32 having a single ended output stage. In another embodiment of the invention, the speaker can be pushed by an electronic device 60 having an H-bridge, as shown in the sixth diagram. Referring to the sixth diagram, the speaker 66 is driven by the upper bridge switch MU and the lower bridge switch MD in the output stage 322 and the upper bridge switch MU and the lower bridge switch MD in the output stage 322". The upper bridge switch in the output stage 322 The upper bridge switch MU and the lower bridge switch MD of the MU and the lower bridge switch MD and the output stage 322" form an H-bridge configuration. The Class D amplifier 62 on the left side of the speaker 66 and the Class D amplifier 64 on the right side of the speaker 66 have an approximate mode of operation. The Class D amplifier with H-bridge configuration operates in a normal mode of operation for those skilled in the art. Well known, will not repeat them here.
參考第六圖,在該等D類放大器62和64供電後的一啟動時間內,該等輸出級322和322”尚未被對應的驅動電路所驅動。此時,該等靴帶電容CBT和CBT’會藉由該等高壓充 電電路3244和3244”而被充電。充電方式可參考第四圖和第五圖所繪示的電路圖和先前之說明。藉由該等高壓充電電路3244和3244”,該等靴帶電容CBT和CBT”可充電至足夠高的電壓位準以驅動對應的上橋開關。在該等靴帶電容CBT和CBT”完成充電後,D類放大器62中的輸出級322和D類放大器64中的輸出級322”會接收對應的驅動電路的信號,以進入正常模式運作。其後,該靴帶電容充電電路324中的該低壓充電電路3242和該靴帶電容充電電路324”中的該低壓充電電路3242”也會分別對該靴帶電容CBT和該靴帶電容CBT”進行充電。 Referring to the sixth diagram, the output stages 322 and 322" are not yet driven by the corresponding drive circuit during a start-up time after the power supplies of the class D amplifiers 62 and 64. At this time, the bootstrap capacitors CBT and CBT 'will be charged by such high voltage The electrical circuits 3244 and 3244" are charged. The charging method can refer to the circuit diagrams shown in the fourth and fifth figures and the previous description. With the high voltage charging circuits 3244 and 3244", the bootstrap capacitors CBT and The CBT" can be charged to a sufficiently high voltage level to drive the corresponding upper bridge switch. After the bootstrap capacitors CBT and CBT" are fully charged, the output in the output stage 322 and the class D amplifier 64 in the class D amplifier 62 The stage 322" receives the signal of the corresponding drive circuit to enter the normal mode operation. Thereafter, the low voltage charging circuit 3242 in the shoe band capacitance charging circuit 324 and the low voltage charging circuit in the shoe band charging circuit 324" The 3242" will also charge the bootband capacitor CBT and the bootband capacitor CBT" respectively.
本發明之技術內容及技術特點已揭示如上,然而熟悉本項技術之人士仍可能基於本發明之教示及揭示而作種種不背離本發明精神之替換及修飾。因此,本發明之保護範圍應不限於實施例所揭示者,而應包含各種不背離本發明之替換及修飾,並為隨後之申請專利範圍所涵蓋。 The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention is not to be construed as being limited by the scope of the invention, and
30‧‧‧電子裝置 30‧‧‧Electronic devices
32‧‧‧D類放大器 32‧‧‧Class D amplifier
322‧‧‧輸出級 322‧‧‧Output
324‧‧‧靴帶電容充電電路 324‧‧‧ Boots with capacitor charging circuit
3242‧‧‧低壓充電電路 3242‧‧‧Low voltage charging circuit
3244‧‧‧高壓充電電路 3244‧‧‧High voltage charging circuit
326,328‧‧‧驅動電路 326,328‧‧‧ drive circuit
34‧‧‧揚聲器 34‧‧‧Speakers
36‧‧‧分壓電路 36‧‧‧voltage circuit
CBT‧‧‧靴帶電容 CBT‧‧‧ boots with capacitor
C3,C4,CL‧‧‧電容 C3, C4, CL‧‧‧ capacitor
L1‧‧‧電感 L1‧‧‧Inductance
MU,MD‧‧‧電晶體 MU, MD‧‧‧O crystal
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