TW201637126A - Semiconductor device and method of fabricating the same - Google Patents
Semiconductor device and method of fabricating the same Download PDFInfo
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本發明是有關於一種半導體元件及其製造方法。The present invention relates to a semiconductor device and a method of fabricating the same.
隨著半導體元件的積體化，為了達到高密度以及高效能的目標，在製造半導體元件時，傾向形成向上堆疊的結構，以更有效利用晶圓面積。因此，具有高深寬比（high aspect ratio）的半導體結構經常出現在小尺寸元件中。With the integration of semiconductor elements, in order to achieve high density and high performance, when manufacturing semiconductor elements, it tends to form an upward stacked structure to more effectively utilize the wafer area. Therefore, semiconductor structures having a high aspect ratio are often found in small-sized components.
製造上述具有高深寬比的半導體結構，通常會進行多次的蝕刻，以形成不同圖案的材料層。然而，由於尺寸微小化，造成對準不易、蝕刻製程不易掌控或蝕刻後圖形產生形變，甚至導致結構倒塌，而可能影響半導體元件製程的良率。因此，如何減少蝕刻製程的次數，及降低蝕刻後圖形產生形變或結構倒塌的現象，為當前所需研究的課題。Fabrication of the above-described semiconductor structures having a high aspect ratio is typically performed multiple times to form a layer of material of a different pattern. However, due to the small size, the alignment is not easy, the etching process is not easy to control or the pattern is deformed after etching, and even the structure collapses, which may affect the yield of the semiconductor device process. Therefore, how to reduce the number of etching processes and reduce the phenomenon of deformation or structural collapse after etching is a subject of current research.
本發明提供一種半導體元件的製造方法，可減少蝕刻製程的次數，並降低蝕刻後圖形產生形變或結構倒塌的現象。The present invention provides a method of fabricating a semiconductor device, which can reduce the number of etching processes and reduce the phenomenon of deformation or structural collapse of the pattern after etching.
本發明提供一種半導體元件的製造方法，其包括以下步驟。於基底上形成堆疊層。圖案化堆疊層，以形成沿著第一方向延伸的多個堆疊結構，相鄰的兩個堆疊結構之間具有沿著第一方向延伸的溝渠，每一溝渠具有相互交替的多個寬部和多個窄部，其中寬部沿著第二方向的最大寬度大於窄部沿著第二方向的最大寬度。形成電荷儲存層，以覆蓋寬部的底表面與側壁及填滿窄部。形成導體層，以填滿寬部。The present invention provides a method of fabricating a semiconductor device comprising the following steps. A stacked layer is formed on the substrate. Patterning the stacked layers to form a plurality of stacked structures extending along the first direction, the adjacent two stacked structures having trenches extending along the first direction, each of the trenches having a plurality of wide portions alternating with each other a plurality of narrow portions, wherein a maximum width of the wide portion along the second direction is greater than a maximum width of the narrow portion along the second direction. A charge storage layer is formed to cover the bottom surface and sidewalls of the wide portion and fill the narrow portion. A conductor layer is formed to fill the wide portion.
在本發明的一實施例中，上述寬部沿著第二方向的最大寬度為窄部沿著第二方向的最大寬度的2-5倍。In an embodiment of the invention, the maximum width of the wide portion along the second direction is 2-5 times the maximum width of the narrow portion along the second direction.
在本發明的一實施例中，上述寬部的形狀包括圓形、橢圓形、正方形、矩形、菱形或其組合。In an embodiment of the invention, the shape of the wide portion includes a circle, an ellipse, a square, a rectangle, a diamond, or a combination thereof.
在本發明的一實施例中，上述電荷儲存層為複合層，複合層包括氧化物層、氮化物層或其組合。In an embodiment of the invention, the charge storage layer is a composite layer, and the composite layer includes an oxide layer, a nitride layer, or a combination thereof.
在本發明的一實施例中，上述堆疊層包括導體層、介電層或其組合。In an embodiment of the invention, the stacked layer comprises a conductor layer, a dielectric layer or a combination thereof.
在本發明的一實施例中，上述溝渠上的每一寬部在第二方向與相鄰的溝渠上的每一寬部的排列方式包括並排排列、交替排列或其組合。In an embodiment of the invention, each wide portion of the trench is arranged in a second direction with each wide portion of the adjacent trench, including side by side, alternating, or a combination thereof.
本發明又提供一種半導體元件，半導體元件包括基底、堆疊結構、電荷儲存層以及導體層。上述堆疊結構，位於基底上相鄰的兩個堆疊結構之間具有沿著第一方向延伸的溝渠，每一溝渠具有相互交替的多個寬部和多個窄部，其中寬部沿著第二方向的最大寬度大於窄部沿著第二方向的最大寬度。電荷儲存層，覆蓋寬部的底表面與側壁及填滿窄部。導體層，填滿寬部。The present invention further provides a semiconductor device including a substrate, a stacked structure, a charge storage layer, and a conductor layer. The stacking structure has a trench extending along the first direction between two adjacent stacked structures on the substrate, each trench having a plurality of wide portions and a plurality of narrow portions alternately with each other, wherein the wide portion is along the second The maximum width of the direction is greater than the maximum width of the narrow portion along the second direction. A charge storage layer covering the bottom surface and side walls of the wide portion and filling the narrow portion. The conductor layer fills the wide part.
在本發明的一實施例中，上述寬部沿著第二方向的最大寬度為窄部沿著第二方向的最大寬度的2-5倍。In an embodiment of the invention, the maximum width of the wide portion along the second direction is 2-5 times the maximum width of the narrow portion along the second direction.
在本發明的一實施例中，上述寬部的形狀包括圓形、橢圓形、正方形、矩形、菱形或其組合。In an embodiment of the invention, the shape of the wide portion includes a circle, an ellipse, a square, a rectangle, a diamond, or a combination thereof.
在本發明的一實施例中，上述電荷儲存層為複合層，複合層包括氧化物層、氮化物層或其組合。In an embodiment of the invention, the charge storage layer is a composite layer, and the composite layer includes an oxide layer, a nitride layer, or a combination thereof.
在本發明的一實施例中，上述堆疊結構包括導體層、介電層或其組合。In an embodiment of the invention, the stacked structure comprises a conductor layer, a dielectric layer or a combination thereof.
在本發明的一實施例中，上述溝渠上的每一寬部在第二方向與相鄰的溝渠上的每一窄部的排列方式包括並排排列、交替排列或其組合。In an embodiment of the invention, each of the wide portions of the trenches in the second direction and each narrow portion of the adjacent trenches are arranged in a side by side arrangement, an alternating arrangement or a combination thereof.
基於上述，本發明藉由形成具有不同寬度的寬部與窄部的溝渠，以利後續於溝渠中形成電荷儲存層時，於寬部形成電荷儲存層的同時，於窄部所形成的電荷儲存層能直接做為絕緣層，之後便不需再額外進行形成絕緣層的製程。藉此可減少製程的程序，進而降低蝕刻後圖形產生形變或結構倒塌的現象。Based on the above, the present invention forms a trench having a wide portion and a narrow portion having different widths, so as to form a charge storage layer formed in a wide portion while forming a charge storage layer in the trench, and a charge storage formed in the narrow portion. The layer can be directly used as an insulating layer, and then no additional process for forming the insulating layer is required. Thereby, the process of the process can be reduced, thereby reducing the deformation or structural collapse of the pattern after etching.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
圖1A至圖1E為依照本發明的一實施例所繪示的半導體元件的製造方法的上視示意圖。圖2A至圖2E為沿圖1A至圖1E之A-A’線所繪示的半導體元件的製造方法的剖面示意圖。圖3、圖4以及圖5為依照本發明的數種實施例所繪示的半導體元件的上視圖。1A-1E are schematic top views of a method of fabricating a semiconductor device in accordance with an embodiment of the invention. 2A to 2E are schematic cross-sectional views showing a method of manufacturing a semiconductor device taken along line A-A' of Figs. 1A to 1E. 3, 4, and 5 are top views of semiconductor devices in accordance with several embodiments of the present invention.
請同時參照圖1A和圖2A，首先提供基底10。基底10可包括半導體材料、絕緣體材料、導體材料或上述材料的任意組合。基底10的材質例如是選自於由Si、Ge、SiGe、GaP、GaAs、SiC、SiGeC、InAs與InP所組成的群組中的至少一種物質所構成的材質或任何適合用於本發明製程的物理結構。基底10包括單層結構或多層結構。此外，也可使用絕緣層上矽（silicon on insulator，SOI）基底。基底10例如是矽或矽化鍺。Referring to FIG. 1A and FIG. 2A simultaneously, the substrate 10 is first provided. Substrate 10 can comprise a semiconductor material, an insulator material, a conductor material, or any combination of the foregoing. The material of the substrate 10 is, for example, a material selected from at least one selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP, or any suitable material for use in the process of the present invention. Physical structure. The substrate 10 includes a single layer structure or a multilayer structure. In addition, a silicon on insulator (SOI) substrate can also be used. The substrate 10 is, for example, tantalum or niobium.
請同時參照圖1B和圖2B，於基底10上形成堆疊層11。堆疊層11例如是包括多層導體層14以及多層介電層16所構成。堆疊層11例如是以多層導體層14與多層介電層16以相互交替的方式往基底10上方堆疊構成。在一實施例中，堆疊層11例如是8層、16層、32層或更多層堆疊構成，但本發明不以此為限。導體層14的材料包括未摻雜的半導體或是經摻雜的半導體，例如是多晶矽或是摻雜的多晶矽。導體層14的厚度例如是介於200埃至600埃之間。導體層14的形成方法包括化學氣相沈積法。在一實施例中，導體層14例如是做為半導體元件100的位元線或字元線。介電層16的材料包括氧化物、氮化物、氮氧化物或是介電常數小於4的低介電常數材料。介電層16的厚度例如是介於200埃至600埃之間。介電層16的形成方法例如是熱氧化法或化學氣相沈積法。Referring to FIG. 1B and FIG. 2B simultaneously, a stacked layer 11 is formed on the substrate 10. The stacked layer 11 is composed of, for example, a multilayer conductor layer 14 and a multilayer dielectric layer 16. The stacked layer 11 is formed, for example, by stacking a plurality of conductor layers 14 and a plurality of dielectric layers 16 in an alternating manner above the substrate 10. In an embodiment, the stacked layer 11 is composed of, for example, 8 layers, 16 layers, 32 layers or more, but the invention is not limited thereto. The material of the conductor layer 14 includes an undoped semiconductor or a doped semiconductor such as polysilicon or doped polysilicon. The thickness of the conductor layer 14 is, for example, between 200 angstroms and 600 angstroms. The method of forming the conductor layer 14 includes a chemical vapor deposition method. In an embodiment, the conductor layer 14 is, for example, a bit line or a word line as the semiconductor element 100. The material of the dielectric layer 16 includes an oxide, a nitride, an oxynitride or a low dielectric constant material having a dielectric constant of less than 4. The thickness of the dielectric layer 16 is, for example, between 200 angstroms and 600 angstroms. The method of forming the dielectric layer 16 is, for example, a thermal oxidation method or a chemical vapor deposition method.
請繼續參照圖1B和圖2B，堆疊層11可以選擇性地更包括形成硬罩幕層18。硬罩幕層18例如是位於堆疊層11的最上層，但本發明不以此為限。硬罩幕層18可為單層或多層。硬罩幕層18的材料例如是氧化矽、氮化矽或其他合適的材料。形成硬罩幕層18的方法包括化學氣相沈積法或有機金屬化學氣相沈積法（MOCVD）。With continued reference to FIGS. 1B and 2B, the stacked layer 11 can optionally further comprise a hard mask layer 18. The hard mask layer 18 is, for example, located at the uppermost layer of the stacked layer 11, but the invention is not limited thereto. The hard mask layer 18 can be a single layer or multiple layers. The material of the hard mask layer 18 is, for example, tantalum oxide, tantalum nitride or other suitable material. The method of forming the hard mask layer 18 includes chemical vapor deposition or metal organic chemical vapor deposition (MOCVD).
請同時參照圖1C和圖2C，圖案化堆疊層11，以形成沿著第一方向D1延伸的多個堆疊結構12。圖案化堆疊層11的方法例如是微影與蝕刻法。蝕刻法例如是乾式蝕刻法。乾式蝕刻法可以是濺鍍蝕刻、反應性離子蝕刻等。相鄰兩個堆疊結構12之間具有沿著第一方向D1延伸的溝渠T。每一條溝渠T具有彼此相互交替的多個寬部30和多個窄部40。從半導體元件100的上視角度所看到的平面（第一方向D1和第二方向D2所構成的平面），寬部30的形狀可以是矩形（圖1E）、圓形（圖3）、橢圓形（圖4，長軸在第一方向D1；圖5，長軸在第二方向D2）、正方形、菱形或其組合；窄部40的形狀可以是矩形（圖1E、圖3-4）、正方形、瓶狀或其組合。但本發明不以此為限。從第二方向D2和第三方向D3所構成的平面來看，寬部30和窄部40的剖面形狀可為任意形狀，例如是V型、U型、菱形或其組合。Referring to FIGS. 1C and 2C simultaneously, the stacked layer 11 is patterned to form a plurality of stacked structures 12 extending along the first direction D1. The method of patterning the stacked layers 11 is, for example, lithography and etching. The etching method is, for example, a dry etching method. The dry etching method may be sputtering etching, reactive ion etching, or the like. A trench T extending along the first direction D1 is provided between the adjacent two stacked structures 12. Each of the trenches T has a plurality of wide portions 30 and a plurality of narrow portions 40 that alternate with each other. The plane of the wide portion 30 may be a rectangle (FIG. 1E), a circle (FIG. 3), an ellipse as seen from a top view angle of the semiconductor element 100 (a plane formed by the first direction D1 and the second direction D2). Shape (Fig. 4, the major axis is in the first direction D1; Fig. 5, the major axis is in the second direction D2), the square, the diamond or a combination thereof; the shape of the narrow portion 40 may be a rectangle (Fig. 1E, Fig. 3-4), Square, bottle or combination thereof. However, the invention is not limited thereto. The cross-sectional shape of the wide portion 30 and the narrow portion 40 may be any shape as viewed in a plane formed by the second direction D2 and the third direction D3, for example, a V shape, a U shape, a diamond shape, or a combination thereof.
寬部30沿著第二方向D2的最大寬度w1大於窄部40沿著第二方向D2的最大寬度w2。在一實施例中，寬部30沿著第二方向D2的最大寬度w1為窄部40沿著第二方向D2的最大寬度w2的2-5倍。在另一實施例中，窄部40沿著第二方向D2的最大寬度w2小於或等於之後形成的電荷儲存層22沿著第三方向D3的厚度t1的2倍（請參照下述圖2D）。第一方向D1與第二方向D2不同。第三方向D3與第一方向D1不同且與第二方向D2不同。舉例來說，第一方向D1與第二方向D2實質上垂直；第一方向D1與第三方向D3實質上垂直；第二方向D2與第三方向D3實質上垂直。The maximum width w1 of the wide portion 30 along the second direction D2 is greater than the maximum width w2 of the narrow portion 40 along the second direction D2. In an embodiment, the maximum width w1 of the wide portion 30 along the second direction D2 is 2-5 times the maximum width w2 of the narrow portion 40 along the second direction D2. In another embodiment, the maximum width w2 of the narrow portion 40 along the second direction D2 is less than or equal to twice the thickness t1 of the charge storage layer 22 formed in the third direction D3 (refer to FIG. 2D below). . The first direction D1 is different from the second direction D2. The third direction D3 is different from the first direction D1 and is different from the second direction D2. For example, the first direction D1 is substantially perpendicular to the second direction D2; the first direction D1 is substantially perpendicular to the third direction D3; and the second direction D2 is substantially perpendicular to the third direction D3.
在一實施例中，寬部30沿著第二方向D2的最大寬度w1例如是介於300埃至1500埃之間，窄部40沿著第二方向D2的最大寬度w2例如是介於150埃至450埃之間。In an embodiment, the maximum width w1 of the wide portion 30 along the second direction D2 is, for example, between 300 angstroms and 1500 angstroms, and the maximum width w2 of the narrow portion 40 along the second direction D2 is, for example, 150 angstroms. Up to 450 angstroms.
請參照圖1E、圖3以及圖4，溝渠T的每一寬部30在第二方向D2與相鄰的另一溝渠T的每一寬部30的排列方式為交錯排列。然而，本發明不以此為限。在另一實施例中，溝渠T的每一寬部30在第二方向D2與相鄰的另一溝渠T的每一寬部30的排列方式也可以是並排排列。Referring to FIG. 1E, FIG. 3 and FIG. 4, each wide portion 30 of the trench T is arranged in a staggered manner in the second direction D2 and each wide portion 30 of the adjacent other trench T. However, the invention is not limited thereto. In another embodiment, the arrangement of each wide portion 30 of the trench T in the second direction D2 and each of the wide portions 30 of the adjacent other trench T may also be arranged side by side.
請同時參照圖1D和圖2D，在溝渠T中形成電荷儲存層22。具體地說，位在溝渠T寬部30的電荷儲存層22僅覆蓋寬部30的底表面與側壁，而未填滿溝渠T的寬部30；而位在溝渠T窄部40的電荷儲存層22則將溝渠T填滿。也就是說，在溝渠T中形成電荷儲存層後，於溝渠T寬部30會留下凹槽23，後續可填入導體層做為字元線或位元線；而溝渠T窄部40則因為已經被電荷儲存層22填滿，而無法再填入導體層。電荷儲存層22例如是介電層。電荷儲存層22可以為複合層，舉例來說，電荷儲存層22例如是包括氧化物層、氮化物層或其組合所構成的複合層。更具體地說，電荷儲存層22的材料包括氮化矽、氧化矽或其組合。在一實施例中，電荷儲存層22例如是由氧化層/氮化層/氧化層（Oxide/Nitride/Oxide，ONO）所構成的複合層。電荷儲存層22沿著第三方向D3的厚度t1需大於每一窄部40沿著第二方向D2的最大寬度w2的1/2倍以上，以確保形成電荷儲存層22時能填滿窄部40。電荷儲存層22沿著第三方向D3的厚度t1例如是介於100埃至250埃之間，但本發明不以此為限。電荷儲存層22的形成方法例如是熱氧化法或化學氣相沈積法。Referring to FIG. 1D and FIG. 2D simultaneously, a charge storage layer 22 is formed in the trench T. Specifically, the charge storage layer 22 located in the wide portion 30 of the trench T covers only the bottom surface and the sidewall of the wide portion 30, but does not fill the wide portion 30 of the trench T; and the charge storage layer located in the narrow portion 40 of the trench T 22 fills the trench T. That is to say, after the charge storage layer is formed in the trench T, a recess 23 is left in the wide portion 30 of the trench T, and the conductor layer can be subsequently filled as a word line or a bit line; and the narrow portion 40 of the trench T is Since it has been filled by the charge storage layer 22, it is no longer possible to fill the conductor layer. The charge storage layer 22 is, for example, a dielectric layer. The charge storage layer 22 may be a composite layer, for example, the charge storage layer 22 is, for example, a composite layer including an oxide layer, a nitride layer, or a combination thereof. More specifically, the material of the charge storage layer 22 includes tantalum nitride, tantalum oxide, or a combination thereof. In one embodiment, the charge storage layer 22 is, for example, a composite layer composed of an oxide layer/nitride layer/oxide layer (Oxide/Nitride/Oxide, ONO). The thickness t1 of the charge storage layer 22 along the third direction D3 needs to be greater than 1/2 times the maximum width w2 of each narrow portion 40 along the second direction D2 to ensure that the charge storage layer 22 can be filled to fill the narrow portion. 40. The thickness t1 of the charge storage layer 22 along the third direction D3 is, for example, between 100 angstroms and 250 angstroms, but the invention is not limited thereto. The method of forming the charge storage layer 22 is, for example, a thermal oxidation method or a chemical vapor deposition method.
請同時參照圖1D、圖1E、圖2D和圖2E，形成導體層24，以填滿寬部30。具體地說，導體層24填滿凹槽23。導體層24的材料例如是多晶矽、摻雜的多晶矽、金屬、金屬合金或其組合。金屬例如是鎢。金屬合金例如是鋁矽合金。形成導體層24的方法包括化學氣相沈積法。在一實施例中，在形成導體層24之前可以先在寬部30的側壁與底部形成阻障層。阻障層的材料例如是包括鈦、氮化鈦、鉭、氮化鉭、或其組合。阻障層的厚度例如是介於10埃至200埃之間。阻障層的形成方法例如是化學氣相沈積法。本發明不限於此。在另一實施例中，在完全形成導體層24前，對寬部30之底部的電荷儲存層22進行處理，以形成導體層24通道，但，本發明不以此為限。導體層24例如是做為記憶元件的字元線或位元線。在一實施例中，導體層24是做為記憶元件的字元線（例如通道結構）；位於堆疊結構12中的導體層14做為記憶元件的位元線（例如閘極結構）。在另一實施例中，導體層24是做為記憶元件的位元線；位於堆疊結構12中的導體層14做為記憶元件的字元線。本發明不限於此。Referring to FIG. 1D, FIG. 1E, FIG. 2D, and FIG. 2E simultaneously, the conductor layer 24 is formed to fill the wide portion 30. Specifically, the conductor layer 24 fills the recess 23. The material of the conductor layer 24 is, for example, polycrystalline germanium, doped polysilicon, metal, metal alloy or a combination thereof. The metal is, for example, tungsten. The metal alloy is, for example, an aluminum-bismuth alloy. The method of forming the conductor layer 24 includes a chemical vapor deposition method. In an embodiment, a barrier layer may be formed on the sidewalls and the bottom of the wide portion 30 prior to forming the conductor layer 24. The material of the barrier layer includes, for example, titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. The thickness of the barrier layer is, for example, between 10 angstroms and 200 angstroms. The formation method of the barrier layer is, for example, a chemical vapor deposition method. The invention is not limited thereto. In another embodiment, the charge storage layer 22 at the bottom of the wide portion 30 is processed to form a conductor layer 24 channel before the conductor layer 24 is completely formed, but the invention is not limited thereto. The conductor layer 24 is, for example, a word line or a bit line as a memory element. In one embodiment, conductor layer 24 is a word line (eg, a channel structure) that is a memory element; conductor layer 14 is located in a stacked structure 12 as a bit line (eg, a gate structure) of the memory element. In another embodiment, conductor layer 24 is a bit line that acts as a memory element; conductor layer 14 that is located in stacked structure 12 acts as a word line for the memory element. The invention is not limited thereto.
在本發明實施例中，將溝渠T窄部40最大寬度w2設定為小於或等於之後形成的電荷儲存層22厚度t1的2倍，使得電荷儲存層22可以填滿窄部40；而導體層24可以填入寬部30因為未填滿電荷儲存層22所留下的凹槽23。因此，位於窄部40的電荷儲存層22可以直接做為絕緣層，以電性隔絕沿著第一方向D1上相鄰兩個導體層24。而後續無需再進行另外的絕緣層製程。也就是說，藉由形成電荷儲存層22單一的製程，可同時於寬部30形成的電荷儲存層22，而於窄部40形成絕緣層。In the embodiment of the present invention, the maximum width w2 of the narrow portion 40 of the trench T is set to be less than or equal to twice the thickness t1 of the charge storage layer 22 formed later, so that the charge storage layer 22 can fill the narrow portion 40; and the conductor layer 24 The wide portion 30 can be filled because the recess 23 left by the charge storage layer 22 is not filled. Therefore, the charge storage layer 22 located in the narrow portion 40 can be directly used as an insulating layer to electrically isolate the adjacent two conductor layers 24 along the first direction D1. There is no need to perform another insulation process later. That is, by forming a single process of the charge storage layer 22, the charge storage layer 22 formed at the wide portion 30 can be simultaneously formed, and the insulating layer can be formed at the narrow portion 40.
另一方面，藉由每一條溝渠T具有彼此相互交替的多個寬部30和多個窄部40，以及每一溝渠T的每一寬部30在第二方向D2與相鄰的另一溝渠T的每一寬部30的排列方式為交替排列、並排排列或其組合，可達到較習知技術中不分寬部與窄部的堆疊結構不易倒塌的效果。具體地說，習知技術中不分寬部與窄部的堆疊結構中，兩相鄰溝渠之間堆疊結構的距離皆同為本實施例之寬部之間的距離。本發明實施例則可藉由上述寬部與窄部排列的方式，增加相鄰兩溝渠之間堆疊結構的距離，進而降低半導體結構發生倒塌的現象。On the other hand, each of the trenches T has a plurality of wide portions 30 and a plurality of narrow portions 40 that alternate with each other, and each wide portion 30 of each of the trenches T is in the second direction D2 and another adjacent one of the trenches The arrangement of each of the wide portions 30 of the T is alternately arranged, arranged side by side, or a combination thereof, and the effect that the stacked structure of the wide portion and the narrow portion is not easily collapsed in the prior art can be achieved. Specifically, in the conventional stacked structure in which the wide portion and the narrow portion are not divided, the distance between the stacked structures of the two adjacent trenches is the same as the distance between the wide portions of the embodiment. In the embodiment of the present invention, the distance between the adjacent two trenches can be increased by the arrangement of the wide portion and the narrow portion, thereby reducing the collapse of the semiconductor structure.
請參照圖1E和圖2E，本發明實施例的半導體元件100包括基底10、堆疊結構12、電荷儲存層22以及導體層24。堆疊結構12位於基底10上且其彼此之間具有溝渠T。溝渠T沿著第一方向D1延伸，且具有彼此相互交替的多個寬部30和多個窄部40。電荷儲存層22，填充於溝渠T之中。在溝渠T的寬部30之中的電荷儲存層22，未填滿寬部30，僅覆蓋底表面與側壁，而留有凹槽23；在溝渠T的窄部40之中的電荷儲存層22，則將窄部40填滿。導體層24，填滿凹槽23。導體層24的材料及製造方法如上所述，於此不再贅述。Referring to FIGS. 1E and 2E , the semiconductor device 100 of the embodiment of the present invention includes a substrate 10 , a stacked structure 12 , a charge storage layer 22 , and a conductor layer 24 . The stack structure 12 is located on the substrate 10 and has a trench T between each other. The trench T extends along the first direction D1 and has a plurality of wide portions 30 and a plurality of narrow portions 40 that alternate with each other. The charge storage layer 22 is filled in the trench T. The charge storage layer 22 in the wide portion 30 of the trench T is not filled with the wide portion 30, covering only the bottom surface and the sidewall, leaving a recess 23; the charge storage layer 22 in the narrow portion 40 of the trench T Then, the narrow portion 40 is filled. The conductor layer 24 fills the recess 23. The material and manufacturing method of the conductor layer 24 are as described above, and will not be described herein.
本發明的半導體元件100的絕緣層的材料與電荷儲存層22的材料相同。具體地說，本發明的半導體元件100位於窄部40的電荷儲存層22可做為後續的絕緣層，位於寬部30的電荷儲存層22可做為後續的電荷儲存層。在一實施例中，當窄部40沿著第二方向D2的最大寬度w2小於電荷儲存層22沿著第三方向D3的厚度t1的2倍時，則位於窄部40與位於寬部30的電荷儲存層22的層數可不相同。The material of the insulating layer of the semiconductor element 100 of the present invention is the same as the material of the charge storage layer 22. Specifically, the charge storage layer 22 of the semiconductor device 100 of the present invention located in the narrow portion 40 can serve as a subsequent insulating layer, and the charge storage layer 22 at the wide portion 30 can serve as a subsequent charge storage layer. In an embodiment, when the maximum width w2 of the narrow portion 40 along the second direction D2 is less than 2 times the thickness t1 of the charge storage layer 22 along the third direction D3, then the narrow portion 40 is located at the wide portion 30. The number of layers of the charge storage layer 22 may be different.
請同時參照圖1E、3和4，在上述的實施例中（圖1E），寬部30的形狀為方形。在其他實施例中，與上述實施例不同的是寬部30的形狀為圓形（圖3）或橢圓形（圖4與圖5），其他結構、材料、厚度以及製造方法如上所述，於此不再贅述。Referring also to FIGS. 1E, 3 and 4, in the above embodiment (FIG. 1E), the wide portion 30 has a square shape. In other embodiments, the difference from the above embodiment is that the shape of the wide portion 30 is circular (Fig. 3) or elliptical (Fig. 4 and Fig. 5), and other structures, materials, thicknesses, and manufacturing methods are as described above. This will not be repeated here.
本發明實施例之的半導體元件的製造方法可應用於動態隨機存取記憶體（DRAM）、反及閘快閃記憶體（NAND flash）、NOR型快閃記憶體（NOR-flash）等，但本發明不以此為限。The method for fabricating a semiconductor device according to the embodiment of the present invention can be applied to a dynamic random access memory (DRAM), a NAND flash, a NOR flash, or the like. The invention is not limited thereto.
綜上所述，本發明實施例中用以分隔堆疊結構的溝渠具有不同寬度的寬部與窄部，因此後續形成電荷儲存層可將溝渠的的窄部填滿電荷儲存層，直接做為絕緣層。因此，後續不需再進行其他形成隔絕結構的製程，藉此可減少蝕刻製程的次數，進而降低蝕刻後圖形產生形變或結構倒塌的現象，提升半導體元件的電性表現及製程良率。In summary, the trenches for separating the stacked structures in the embodiments of the present invention have wide and narrow portions of different widths, so that the subsequent formation of the charge storage layer fills the narrow portion of the trenches with the charge storage layer and directly serves as insulation. Floor. Therefore, there is no need to carry out other processes for forming the isolation structure, thereby reducing the number of etching processes, thereby reducing the phenomenon of deformation or structural collapse after etching, and improving the electrical performance and process yield of the semiconductor device.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
10‧‧‧基底
11‧‧‧堆疊層
12‧‧‧堆疊結構
14‧‧‧導體層
16‧‧‧介電層
18‧‧‧硬罩幕層
22‧‧‧電荷儲存層
23‧‧‧凹槽
24‧‧‧導體層
30‧‧‧寬部
40‧‧‧窄部
100、200、300‧‧‧半導體元件
D1、D2、D3‧‧‧方向
T‧‧‧溝渠
w1、w2、w3、w4‧‧‧寬度
t1‧‧‧厚度
A-A’‧‧‧線10‧‧‧Base
11‧‧‧Stacking
12‧‧‧Stack structure
14‧‧‧Conductor layer
16‧‧‧Dielectric layer
18‧‧‧hard mask layer
22‧‧‧Charge storage layer
23‧‧‧ Groove
24‧‧‧ conductor layer
30‧‧‧ Wide Department
40‧‧‧narrow
100, 200, 300‧‧‧ semiconductor components
D1, D2, D3‧‧‧ direction
T‧‧‧ Ditch
W1, w2, w3, w4‧‧‧ width
T1‧‧‧ thickness
A-A'‧‧‧ line
圖1A至圖1E為依照本發明的一實施例所繪示的半導體元件的製造方法的上視圖。 圖2A至圖2E為沿圖1A至圖1E之A-A’線所繪示的半導體元件的製造方法的剖面示意圖。 圖3、圖4以及圖5為依照本發明的數種實施例所繪示的半導體元件的上視圖。1A-1E are top views of a method of fabricating a semiconductor device in accordance with an embodiment of the invention. 2A to 2E are schematic cross-sectional views showing a method of manufacturing a semiconductor device taken along line A-A' of Figs. 1A to 1E. 3, 4, and 5 are top views of semiconductor devices in accordance with several embodiments of the present invention.
10‧‧‧基底 10‧‧‧Base
12‧‧‧堆疊結構 12‧‧‧Stack structure
14‧‧‧導體層 14‧‧‧Conductor layer
16‧‧‧介電層 16‧‧‧Dielectric layer
18‧‧‧硬罩幕層 18‧‧‧hard mask layer
22‧‧‧電荷儲存層 22‧‧‧Charge storage layer
23‧‧‧凹槽 23‧‧‧ Groove
24‧‧‧導電層 24‧‧‧ Conductive layer
100‧‧‧半導體元件 100‧‧‧Semiconductor components
D2、D3‧‧‧方向 D2, D3‧‧‧ direction
t1‧‧‧厚度 T1‧‧‧ thickness
Claims (12)
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