TW201636767A - Over current protection (OCP) chip and OCP circuit of power supply - Google Patents
Over current protection (OCP) chip and OCP circuit of power supply Download PDFInfo
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Abstract
Description
本發明係相關於一種電源供應器之過電流保護晶片及過電流保護電路,尤指一種可設定多組過電流保護值的電源供應器之過電流保護晶片及過電流保護電路。 The invention relates to an overcurrent protection chip and an overcurrent protection circuit of a power supply, in particular to an overcurrent protection chip and an overcurrent protection circuit of a power supply capable of setting a plurality of sets of overcurrent protection values.
電源供應器係用來供應電源給電子裝置,為了避免電子裝置之負載過大而超過電源供應器之安全負載範圍,電源供應器通常會設置一過電流保護(over current protection;OCP)電路,用來偵測負載電流,並於負載電流高於負載上限時輸出一過電流保護訊號,以通知電源供應器進行相對應之保護措施,例如關機。 The power supply is used to supply power to the electronic device. In order to avoid the overload of the electronic device and exceed the safe load range of the power supply, the power supply usually sets an over current protection (OCP) circuit for The load current is detected, and an overcurrent protection signal is output when the load current is higher than the load upper limit to notify the power supply to perform corresponding protection measures, such as shutdown.
請參考第1圖,第1圖為習知電源供應器之過電流保護電路10耦接於校正工具及負載機120時之示意圖。過電流保護電路10設置於電源供應器中,用於提供電源供應器的過電流保護。過電流保護晶片100則是用以提供過電流保護值140,以設定過電流保護電路10於啟動過電流保護機制時的電流值。當電源供應器所輸出的電流超過所設定的過電流保護值140時,過電流保護電路10即會啟動其過電流保護機制。為因應不同的電源供應器的過電流保護之需要,過電流保護晶片100被設計成可對其過電流保護值140進行校正。當進行過電流保護值140的校正時,過電流保護晶片100會與校正工具110及負載機120耦接,以使校正工具110及負載機120對過電流保 護晶片100進行校正,並於完成校正時使過電流保護晶片100產生校正資料130。校正資料130會被儲存在過電流保護晶片100當中,而當過電流保護晶片100出廠並被設置於電源供應器後,過電流保護晶片100即可依據所儲存的校正資料130即時地產生過電流保護值140,以設定過電流保護電路10於啟動過電流保護機制時的電流值。 Please refer to FIG. 1 . FIG. 1 is a schematic diagram of the conventional overcurrent protection circuit 10 of the power supply coupled to the calibration tool and the loader 120 . The overcurrent protection circuit 10 is disposed in the power supply for providing overcurrent protection of the power supply. The overcurrent protection die 100 is used to provide an overcurrent protection value 140 to set the current value of the overcurrent protection circuit 10 when the overcurrent protection mechanism is activated. When the current output by the power supply exceeds the set overcurrent protection value 140, the overcurrent protection circuit 10 activates its overcurrent protection mechanism. The overcurrent protection die 100 is designed to correct its overcurrent protection value 140 in response to the need for overcurrent protection of different power supplies. When the overcurrent protection value 140 is corrected, the overcurrent protection wafer 100 is coupled to the calibration tool 110 and the loader 120 so that the calibration tool 110 and the loader 120 are overcurrent protected. The wafer 100 is calibrated and causes the overcurrent protection wafer 100 to generate calibration data 130 upon completion of the calibration. The calibration data 130 is stored in the overcurrent protection wafer 100, and when the overcurrent protection wafer 100 is shipped from the power supply, the overcurrent protection wafer 100 can instantaneously generate an overcurrent according to the stored calibration data 130. The protection value 140 is used to set the current value of the overcurrent protection circuit 10 when the overcurrent protection mechanism is activated.
然而,因當過電流保護晶片100出廠後,被儲存在過電流保護晶片100中的校正資料130即無法再更改,而導致當電源供應器廠於生產其電源供應器後須變更其規格、設計時,電源供應器內的過電流保護晶片100並無法再重新被校正以回收使用。再者,當電源供應器需要有多組的過電流保護設定時,因過電流保護晶片100只能提供一組過電流保護值140,而有不敷使用的情況。此外,若電源供應器有多組過電流保護值140需要校正時,負載機120必須配合多個過電流保護晶片100的校正順序,而無法隨意地變更其校正順序,而缺乏彈性。 However, since the correction data 130 stored in the overcurrent protection wafer 100 cannot be changed after the overcurrent protection wafer 100 is shipped, the power supply factory must change its specifications and design after producing its power supply. At this time, the overcurrent protection wafer 100 in the power supply can no longer be recalibrated for recycling. Moreover, when the power supply requires multiple sets of overcurrent protection settings, the overcurrent protection chip 100 can only provide a set of overcurrent protection values 140, which is insufficient. In addition, if the power supply has multiple sets of overcurrent protection values 140 to be corrected, the loader 120 must cooperate with the correction sequence of the plurality of overcurrent protection wafers 100, and cannot change the correction order arbitrarily, and lacks flexibility.
本發明提供一種電源供應器之過電流保護晶片。過電流保護晶片包含第一輸入端、第二輸入端、第三輸入端、第一記憶模組、第二記憶模組以及切換選擇電路。第一輸入端用以接收校正資料。第二輸入端用以接收第一電流負載電位。第三輸入端用以接收第二電流負載電位。第一記憶模組及第二記憶模組各包含至少一記憶單元,而每一記憶單元用以記錄一過電流保護值。切換選擇電路耦接於第一輸入端、第二輸入端及第三輸入端,用以比較校正資料及第一電流負載電位,並比較校正資料及第二電流負載電位。其中當校正資料與第一電流負載電位相符時,校正資料被儲存到第一記憶模組的一個記憶單元中。當校正資料與第二電流負載電位相符時,校正資料被儲存到第二記憶模組的一個記憶單元中。 The invention provides an overcurrent protection wafer for a power supply. The overcurrent protection chip includes a first input terminal, a second input terminal, a third input terminal, a first memory module, a second memory module, and a switching selection circuit. The first input is for receiving correction data. The second input is configured to receive the first current load potential. The third input is configured to receive a second current load potential. The first memory module and the second memory module each include at least one memory unit, and each memory unit records an overcurrent protection value. The switching selection circuit is coupled to the first input terminal, the second input terminal and the third input terminal for comparing the calibration data and the first current load potential, and comparing the calibration data with the second current load potential. When the calibration data matches the first current load potential, the calibration data is stored in a memory unit of the first memory module. When the correction data matches the second current load potential, the correction data is stored in a memory unit of the second memory module.
本發明另提供一種電源供應器之過電流保護電路。過電流保護電路包含多個過電流保護晶片,其中每一個過電流保護晶片包含第一輸入端、第二輸入端、第三輸入端、第一記憶模組、第二記憶模組、切換選擇電路、槽位比對單元、第一選擇開關以及第二選擇開關。第一輸入端用以接收校正資料。第二輸入端用以接收第一電流負載電位。第三輸入端用以接收第二電流負載電位。第一記憶模組及第二記憶模組各包含至少一記憶單元,而每一記憶單元用以記錄一過電流保護值。切換選擇電路耦接於第一輸入端、第二輸入端及第三輸入端,用以比較校正資料及第一電流負載電位,並比較校正資料及第二電流負載電位。其中當校正資料與第一電流負載電位相符時,校正資料被儲存到第一記憶模組的一個記憶單元中。當校正資料與第二電流負載電位相符時,校正資料被儲存到第二記憶模組的一個記憶單元中。槽位比對單元用以比對槽位比對命令及槽位位置,以輸出致能訊號並決定致能訊號的電位。第一選擇開關用以依據致能訊號控制第一輸入端至切換選擇電路及第一記憶模組之間的電性連接。第二選擇開關用以依據致能訊號控制第一輸入端至切換選擇電路及第二記憶模組之間的電性連接。其中上述多個過電流保護晶片的槽位比對單元彼此耦接,而各自地接收槽位比對命令及槽位位置。 The invention further provides an overcurrent protection circuit for a power supply. The overcurrent protection circuit includes a plurality of overcurrent protection chips, wherein each of the overcurrent protection chips includes a first input terminal, a second input terminal, a third input terminal, a first memory module, a second memory module, and a switching selection circuit The slot alignment unit, the first selection switch, and the second selection switch. The first input is for receiving correction data. The second input is configured to receive the first current load potential. The third input is configured to receive a second current load potential. The first memory module and the second memory module each include at least one memory unit, and each memory unit records an overcurrent protection value. The switching selection circuit is coupled to the first input terminal, the second input terminal and the third input terminal for comparing the calibration data and the first current load potential, and comparing the calibration data with the second current load potential. When the calibration data matches the first current load potential, the calibration data is stored in a memory unit of the first memory module. When the correction data matches the second current load potential, the correction data is stored in a memory unit of the second memory module. The slot alignment unit compares the slot alignment command with the slot position to output an enable signal and determine the potential of the enable signal. The first selection switch is configured to control the electrical connection between the first input end and the switching selection circuit and the first memory module according to the enable signal. The second selection switch is configured to control the electrical connection between the first input end to the switching selection circuit and the second memory module according to the enabling signal. The slot alignment units of the plurality of overcurrent protection wafers are coupled to each other, and respectively receive the slot alignment command and the slot position.
10、20、30‧‧‧過電流保護電路 10, 20, 30‧‧‧Overcurrent protection circuit
110‧‧‧校正工具 110‧‧‧ calibration tool
120‧‧‧負載機 120‧‧‧Loader
130、130A、130B、130C、130D、DS‧‧‧校正資料 130, 130A, 130B, 130C, 130D, D S ‧ ‧ correction data
140、240A、240B、240C、240D‧‧‧過電流保護值 140, 240A, 240B, 240C, 240D‧‧‧ overcurrent protection values
100、200、200_1、200_2‧‧‧過電流保護晶片 100, 200, 200_1, 200_2‧‧‧ overcurrent protection chip
210‧‧‧切換選擇電路 210‧‧‧Switch selection circuit
212A、212B‧‧‧負載比較單元 212A, 212B‧‧‧ load comparison unit
214‧‧‧校正組選擇器 214‧‧‧Correction group selector
216‧‧‧比較器 216‧‧‧ comparator
217‧‧‧電位調整單元 217‧‧‧potentiometer adjustment unit
218‧‧‧解碼器 218‧‧‧Decoder
220‧‧‧槽位比對單元 220‧‧‧Slot comparison unit
224A‧‧‧第一記憶模組 224A‧‧‧First Memory Module
224B‧‧‧第二記憶模組 224B‧‧‧Second memory module
230A、230B‧‧‧重工選擇器 230A, 230B‧‧‧Rework Selector
A1至AX、B1至BX‧‧‧記憶單元 A1 to AX, B1 to BX‧‧‧ memory unit
EN1、EN2‧‧‧致能訊號 E N1 , E N2 ‧‧‧ enable signal
IA1‧‧‧負載電流 I A1 ‧‧‧Load current
IA2‧‧‧電流 I A2 ‧‧‧ Current
Iv1至Ivn‧‧‧電流源 Iv1 to Ivn‧‧‧ current source
P1至P3‧‧‧輸入端 P1 to P3‧‧‧ input
VA1‧‧‧第一電流負載電位 V A1 ‧‧‧First current load potential
VA2‧‧‧第一校正電流感應電位 V A2 ‧‧‧First corrected current sense potential
VB1‧‧‧第二電流負載電位 V B1 ‧‧‧second current load potential
VB2‧‧‧第二校正電流感應電位 V B2 ‧‧‧Second corrected current sense potential
VC1‧‧‧第三電流負載電位 V C1 ‧‧‧third current load potential
VC2‧‧‧第三校正電流感應電位 V C2 ‧‧‧ third corrected current sense potential
VD1‧‧‧第四電流負載電位 V D1 ‧‧‧fourth current load potential
VD2‧‧‧第四校正電流感應電位 V D2 ‧‧‧ fourth corrected current sense potential
VS1‧‧‧第一輸出位準 V S1 ‧‧‧first output level
VS2‧‧‧第二輸出位準 V S2 ‧‧‧second output level
Vcs‧‧‧電壓輸入端 Vcs‧‧‧ voltage input
V1至Vn‧‧‧開關控制訊號 V1 to Vn‧‧‧ switch control signal
RA1、RA2、RB2、RC2、RD2‧‧‧電阻 R A1 , R A2 , R B2 , R C2 , R D2 ‧‧‧ resistance
S1、S2‧‧‧槽位位置 S1, S2‧‧‧ slot position
SCOM‧‧‧槽位比對命令 S COM ‧‧‧ slot alignment command
SW1、SW2‧‧‧選擇開關 SW 1 , SW 2 ‧‧‧ selection switch
SW、SWA、SWB‧‧‧開關 SW, SW A , SW B ‧‧‧ switch
S410至S460、S510至S550、S610至S670‧‧‧步驟 Steps S410 to S460, S510 to S550, S610 to S670‧‧
T1至T3‧‧‧輸入端 T1 to T3‧‧‧ input
第1圖為習知電源供應器之過電流保護電路耦接於校正工具及負載機時之示意圖。 FIG. 1 is a schematic diagram of the conventional overcurrent protection circuit of the power supply coupled to the calibration tool and the loader.
第2圖為本發明一實施例之電源供應器的過電流保護電路耦接於校正工具及負載機時之示意圖。 FIG. 2 is a schematic diagram of the overcurrent protection circuit of the power supply of the embodiment of the present invention coupled to the calibration tool and the loader.
第3圖為本發明一實施例之過電流保護晶片的切換選擇電路之示意圖。 FIG. 3 is a schematic diagram of a switching selection circuit of an overcurrent protection wafer according to an embodiment of the present invention.
第4圖為本發明另一實施例之電源供應器的過電流保護電路耦接於校正工具 及負載機時之示意圖。 4 is a schematic diagram of an overcurrent protection circuit of a power supply coupled to a calibration tool according to another embodiment of the present invention; And the schematic diagram of the load machine.
第5圖為對第2圖的過電流保護晶片進行校正時的流程圖。 Fig. 5 is a flow chart for correcting the overcurrent protection wafer of Fig. 2.
第6圖為對第4圖的多個過電流保護晶片進行校正時的流程圖。 Fig. 6 is a flow chart showing the correction of the plurality of overcurrent protection wafers of Fig. 4.
第7圖為對安裝有第2圖的過電流保護晶片的電源供應器由校正設定到出廠的流程圖。 Fig. 7 is a flow chart showing the setting of the power supply to the overcurrent protection chip of Fig. 2 from the calibration setting to the factory.
請參考第2圖。第2圖為本發明一實施例之電源供應器的過電流保護電路20耦接於校正工具110及負載機120時之示意圖。過電流保護電路20設置於電源供應器中,用於提供電源供應器多組的過電流保護值。在本實施例中,過電流保護電路20具有一個過電流保護晶片200,而過電流保護晶片200可提供電源供應器兩組的過電流保護值240A及240B。然而,本發明並不以此為限,每一個過電流保護晶片200亦可設計成提供三組或更多組的過電流保護值。 Please refer to Figure 2. FIG. 2 is a schematic diagram of the overcurrent protection circuit 20 of the power supply of the embodiment of the present invention coupled to the calibration tool 110 and the loader 120. The overcurrent protection circuit 20 is disposed in the power supply for providing a plurality of sets of overcurrent protection values of the power supply. In the present embodiment, the overcurrent protection circuit 20 has an overcurrent protection die 200, and the overcurrent protection die 200 provides overcurrent protection values 240A and 240B for the two sets of power supplies. However, the present invention is not limited thereto, and each of the overcurrent protection wafers 200 may also be designed to provide three or more sets of overcurrent protection values.
藉由所提供的兩組過電流保護值240A及240B,過電流保護晶片200即可設定過電流保護電路20於啟動過電流保護機制時的兩組電流值。當電源供應器的兩組電源輸出其輸出電流有任一組超過所設定的過電流保護值240A或240B時,過電流保護電路20即會啟動其過電流保護機制。同樣地,為因應不同的電源供應器的過電流保護之規格需要,過電流保護晶片200被設計成可對其過電流保護值240A及240B分別進行校正。當進行過電流保護值240A及240B的校正時,過電流保護晶片200會與校正工具110及負載機120耦接,以使校正工具110及負載機120對過電流保護晶片200進行校正,並於完成校正時使過電流保護晶片200產生校正資料130A及130B。校正資料130A及130B會分別被儲存在過電流保護晶片200的第一記憶模組224A及第二記憶模組224B中,而當過電流保護晶片200出廠並被設置於電源供應 器後,過電流保護晶片200即可依據第一記憶模組224A及第二記憶模組224B所儲存的校正資料130A及130B即時地產生過電流保護值240A及240B,以設定過電流保護電路20於啟動過電流保護機制時的兩組電流值。 By providing two sets of overcurrent protection values 240A and 240B, the overcurrent protection chip 200 can set two sets of current values of the overcurrent protection circuit 20 when the overcurrent protection mechanism is activated. When the two sets of power supply outputs of the power supply have any set of output currents exceeding the set overcurrent protection value 240A or 240B, the overcurrent protection circuit 20 activates its overcurrent protection mechanism. Similarly, the overcurrent protection die 200 is designed to be calibrated for its overcurrent protection values 240A and 240B, respectively, in response to the specifications of the overcurrent protection of different power supplies. When the overcurrent protection values 240A and 240B are corrected, the overcurrent protection wafer 200 is coupled to the calibration tool 110 and the loader 120 to cause the calibration tool 110 and the loader 120 to correct the overcurrent protection wafer 200, and The overcurrent protection wafer 200 is caused to generate correction data 130A and 130B when the correction is completed. The calibration data 130A and 130B are stored in the first memory module 224A and the second memory module 224B of the overcurrent protection chip 200, respectively, and the overcurrent protection chip 200 is shipped from the power supply. After the overcurrent protection chip 200, the overcurrent protection values 240A and 240B can be instantaneously generated according to the calibration data 130A and 130B stored in the first memory module 224A and the second memory module 224B to set the overcurrent protection circuit 20 Two sets of current values when the overcurrent protection mechanism is activated.
在本實施例中,過電流保護晶片200包含三個輸入端P1至P3、第一記憶模組224A、第二記憶模組224B以及切換選擇電路210。三個輸入端P1至P3分別用以從校正工具110接收校正資料DS,並從負載機120接收第一電流負載電位VA1及第二電流負載電位VB1。切換選擇電路210耦接過電流保護晶片200的三個輸入端P1至P3,用以比較校正資料DS及第一電流負載電位VA1,並比較校正資料DS及第二電流負載電位VB1。在本實施例中,第一記憶模組224A及第二記憶模組224B各包含多個記憶單元A1至AX及B1至BX,而每一記憶單元用以記錄一過電流保護值。其中,第一記憶模組224A及第二記憶模組224B所包含的記憶單元的數目可視需要調整,例如第一記憶模組224A及第二記憶模組224B可分別僅具有一個記憶單元。 In the present embodiment, the overcurrent protection wafer 200 includes three input terminals P1 to P3, a first memory module 224A, a second memory module 224B, and a switching selection circuit 210. The three input terminals P1 to P3 are respectively used to receive the correction data D S from the calibration tool 110 and receive the first current load potential V A1 and the second current load potential V B1 from the loader 120. The switching selection circuit 210 is coupled to the three input terminals P1 to P3 of the overcurrent protection chip 200 for comparing the correction data D S and the first current load potential V A1 , and comparing the correction data D S and the second current load potential V B1 . . In this embodiment, the first memory module 224A and the second memory module 224B each include a plurality of memory cells A1 to AX and B1 to BX, and each memory cell records an overcurrent protection value. The number of memory units included in the first memory module 224A and the second memory module 224B can be adjusted as needed. For example, the first memory module 224A and the second memory module 224B can each have only one memory unit.
此外,過電流保護晶片200的過電流保護校正是透過切換選擇電路210對校正資料DS、第一電流負載電位VA1及第二電流負載電位VB1進行比較的方式來達成。詳言之,在對過電流保護晶片200進行過電流保護校正的過程中,在尚未完成電流保護晶片200的校正之前,校正工具110會持續地輸出不同的校正資料DS,而當校正資料DS與第一電流負載電位VA1相符時,即完成過電流保護值240A的校正;且當校正資料DS與第二電流負載電位VB1相符時,即完成過電流保護值240B的校正。至於如何判斷校正資料DS是否與負載機120所提供的電流負載電位(如VA1及/或VB1)相符,則可參考申請人於民國101年10月26日所提出的第101139698號專利申請案,或是稍後參考對於第3圖的說明。此外,當校正資料DS與第一電流負載電位VA1相符時(如:此時的校正資料DS為校正資料130A),校正資料DS會被儲 存到第一記憶模組224A的記憶單元A1至AX中的一個記憶單元;而當校正資料DS與第二電流負載電位VB1相符時(如:此時的校正資料DS為校正資料130B),校正資料DS會被儲存到第二記憶模組224B的記憶單元B1至BX中的一個記憶單元。之後,過電流保護晶片200即可依據分別儲存於第一記憶模組224A及第二記憶模組224B的校正資料,輸出兩組過電流保護值240A及240B。由於過電流保護晶片200可提供兩組的電流保護值240A及240B,故相較於習知技術中的過電流保護晶片100只能提供一組過電流保護值140,過電流保護晶片200更適合用於可提供多組電力輸出(如多組不同的電壓)的電源供應器。此外,由於可各別地設定負載機120所提供的第一電流負載電位VA1及第二電流負載電位VB1,且當校正資料DS與第一電流負載電位VA1或第二電流負載電位VB1相符時,即完成過電流保護值240A或240B的校正,故過電流保護晶片200所要校正的電流保護值240A及240B的先後順序可依據實際情況而有所不同,而不受特定校正順序的限制。詳言之,可以先完成電流保護值240A的校正再完成電流保護值240B的校正,亦或是先完成電流保護值240B的校正再完成電流保護值240A的校正。另外,倘若第一電流負載電位VA1被設定成與第二電流負載電位VB1一樣的話,則可同時完成電流保護值240A及240B的設定。 Further, the overcurrent protection correction of the overcurrent protection wafer 200 is achieved by the switching selection circuit 210 comparing the correction data D S , the first current load potential V A1 , and the second current load potential V B1 . In detail, in the process of the overcurrent protection wafer 200 overcurrent protection corrected, prior to the correction current protective wafer 200 is not completed, the correction tool 110 continues to output a different correction data D S, and when the correction data D When S coincides with the first current load potential V A1 , the correction of the over current protection value 240A is completed; and when the correction data D S coincides with the second current load potential V B1 , the correction of the over current protection value 240B is completed. As to how to judge whether the correction data D S is consistent with the current load potential (such as V A1 and / or V B1 ) provided by the loader 120, refer to the patent No. 101139698 proposed by the applicant on October 26, 101, the Republic of China. The application, or reference to the description of Figure 3 later. In addition, when the correction data D S matches the first current load potential V A1 (eg, the correction data D S at this time is the correction data 130A), the correction data D S is stored in the memory unit of the first memory module 224A. A memory unit of A1 to AX; and when the correction data D S coincides with the second current load potential V B1 (eg, the correction data D S at this time is the correction data 130B), the correction data D S is stored to the first One of the memory cells B1 to BX of the two memory modules 224B. Thereafter, the overcurrent protection chip 200 can output two sets of overcurrent protection values 240A and 240B according to the correction data stored in the first memory module 224A and the second memory module 224B, respectively. Since the overcurrent protection wafer 200 can provide two sets of current protection values 240A and 240B, the overcurrent protection wafer 100 can only provide a set of overcurrent protection values 140, and the overcurrent protection wafer 200 is more suitable. Used for power supplies that provide multiple sets of power outputs, such as multiple sets of different voltages. In addition, since the first current load potential V A1 and the second current load potential V B1 provided by the loader 120 can be separately set, and the correction data D S and the first current load potential V A1 or the second current load potential When V B1 matches, the correction of the overcurrent protection value 240A or 240B is completed, so the order of the current protection values 240A and 240B to be corrected by the overcurrent protection chip 200 may be different depending on the actual situation, and is not subject to a specific correction sequence. limits. In detail, the correction of the current protection value 240A may be completed before the current protection value 240B is corrected, or the current protection value 240B may be corrected before the current protection value 240A is corrected. Further, if the first current load potential V A1 is set to be the same as the second current load potential V B1 , the current protection values 240A and 240B can be simultaneously set.
在本發明一實施例中,切換選擇電路210包含兩個負載比較單元212A及212B、校正組選擇器214以及兩個開關SWA及SWB。負載比較單元212A及212B分別透過電阻RA2及RB2耦接於電壓輸入端Vcs。負載比較單元212A可依據校正資料DS調整負載比較單元212A的第一校正電流感應電位VA2。類似地,負載比較單元212B可依據校正資料DS調整負載比較單元212B的第二校正電流感應電位VB2。至於負載比較單元212A及212B如何依據校正資料DS分別調整第一校正電流感應電位VA2及第二校正電流感應電位VB2,下面將會有進一步的說明。此外,開關SWA用以控制校正工具110與 第一記憶模組224A之間的電性連接,而開關SWB用以控制校正工具110與第二記憶模組224B之間的電性連接。校正組選擇器214耦接於兩負載比較單元212A及212B的輸出端。其中當第一校正電流感應電位VA2等於第一電流負載電位VA1時,校正組選擇器214開啟SWA,以使校正資料DS被儲存到第一記憶模組224A的一個記憶單元中。類似地,當第二校正電流感應電位VB2等於第二電流負載電位VB1時,校正組選擇器214開啟SWB,以使校正資料DS被儲存到第二記憶模組224B的一個記憶單元中。 In an embodiment of the invention, the switching selection circuit 210 includes two load comparison units 212A and 212B, a correction group selector 214, and two switches SW A and SW B . The load comparison units 212A and 212B are coupled to the voltage input terminal Vcs through the resistors R A2 and R B2 , respectively. The load comparison unit 212A can adjust the first correction current sensing potential V A2 of the load comparison unit 212A according to the correction data D S . Similarly, the load comparison unit 212B can adjust the second correction current sensing potential V B2 of the load comparison unit 212B according to the correction data D S . As for the load comparison units 212A and 212B, the first correction current sensing potential V A2 and the second correction current sensing potential V B2 are respectively adjusted according to the correction data D S , which will be further described below. In addition, the switch SW A is used to control the electrical connection between the calibration tool 110 and the first memory module 224A, and the switch SW B is used to control the electrical connection between the calibration tool 110 and the second memory module 224B. The correction group selector 214 is coupled to the outputs of the two load comparison units 212A and 212B. When the first correction current sensing potential V A2 is equal to the first current load potential V A1 , the correction group selector 214 turns on the SW A so that the correction data D S is stored in a memory unit of the first memory module 224A. Similarly, when the second correction current sensing potential V B2 is equal to the second current load potential V B1 , the correction group selector 214 turns on the SW B to cause the correction data D S to be stored in one memory unit of the second memory module 224B. in.
以下將就如何判斷校正資料DS是否與負載機120所提供的電流負載電位(如VA1及/或VB1)相符作進一步的說明。請參考第3圖,第3圖為本發明一實施例之過電流保護晶片的切換選擇電路212A之示意圖。負載比較單元212A耦接於電阻RA1及RA2,並包含三個輸入端T1至T3、比較器216、電位調整單元217以及解碼器218。其中,三個輸入端T1至T3分別耦接於過電流保護晶片200的輸入端P2、電壓輸入端Vcs及輸入端P1,以分別接收第一電流負載電位VA1、系統電壓以及校正資料DS。電阻RA1(電流偵測電阻)之第一端耦接至電壓輸入端Vcs,而電阻RA1之第二端耦接至負載機120。電阻RA2之第一端耦接至電壓輸入端Vcs。輸入端T1所接收的第一電流負載電位VA1亦為電阻RA1之第二端的電壓訊號。由於負載電流IA1會流經電阻RA1,因此電阻RA1之第一端及第二端之間之電壓降會正比於負載電流IA1之大小,所以電阻RA1之第二端之電壓訊號(即第一電流負載電位VA1)可作為負載電流偵測訊號。輸入端T2則用以接收第一校正電流感應電位VA2,亦即電阻RA2之第二端之電壓訊號。第一校正電流感應電位VA2的大小係由電位調整單元217所決定。比較器216之第一輸入端係耦接至輸入端T1,比較器216之第二輸入端係耦接至輸入端T2,比較器216係用以比較第一電流負載電位VA1及第一校正電流感應電位VA2以於其輸出端輸出第一輸出位準VS1。在本實施例中,當第一電流負載電位VA1低於第一校正電流感應電位VA2時,第一輸 出位準VS1係從低電壓位準升到高電壓位準,亦即於輸出端輸出一過電流保護訊號,以通知電源供應器進行相對應之保護措施,例如關機或其他操作等。 Further explanation will be given below as to how to determine whether the correction data D S matches the current load potential (such as V A1 and/or V B1 ) provided by the loader 120. Please refer to FIG. 3. FIG. 3 is a schematic diagram of a switching selection circuit 212A of an overcurrent protection wafer according to an embodiment of the present invention. The load comparison unit 212A is coupled to the resistors R A1 and R A2 and includes three input terminals T1 to T3 , a comparator 216 , a potential adjustment unit 217 , and a decoder 218 . The three input terminals T1 to T3 are respectively coupled to the input terminal P2, the voltage input terminal Vcs and the input terminal P1 of the overcurrent protection chip 200 to respectively receive the first current load potential V A1 , the system voltage, and the correction data D S . . The first end of the resistor R A1 (current detecting resistor) is coupled to the voltage input terminal Vcs, and the second end of the resistor R A1 is coupled to the loader 120. The first end of the resistor R A2 is coupled to the voltage input terminal Vcs. The first current load potential V A1 received by the input terminal T1 is also the voltage signal of the second end of the resistor R A1 . Since the load current I A1 will flow through the resistor R A1 , the voltage drop between the first end and the second end of the resistor R A1 will be proportional to the magnitude of the load current I A1 , so the voltage signal at the second end of the resistor R A1 (ie, the first current load potential V A1 ) can be used as a load current detection signal. The input terminal T2 is configured to receive the first correction current sensing potential V A2 , that is, the voltage signal of the second end of the resistor R A2 . The magnitude of the first correction current sensing potential V A2 is determined by the potential adjustment unit 217. The first input end of the comparator 216 is coupled to the input terminal T1, the second input end of the comparator 216 is coupled to the input terminal T2, and the comparator 216 is configured to compare the first current load potential V A1 with the first correction The current sense potential V A2 outputs a first output level V S1 at its output. In this embodiment, when the first current load potential V A1 is lower than the first correction current sensing potential V A2 , the first output level V S1 rises from a low voltage level to a high voltage level, that is, at the output. The terminal outputs an overcurrent protection signal to notify the power supply to perform corresponding protection measures, such as shutdown or other operations.
電位調整單元217耦接於輸入端T2,在本實施例中,電位調整單元217包含複數個電流源Iv1至Ivn以及複數個開關SW。複數個開關SW分別耦接至複數個電流源Iv1至Ivn及接地端之間,用以根據開關控制訊號V1至Vn進行開啟與關閉,以控制流經電阻RA2之電流IA2之大小,進而調整第一校正電流感應電位VA2。解碼器218用以根據接收到之校正資料DS輸出複數個開關控制訊號V1至Vn至複數個開關SW,以控制複數個開關SW之開啟與關閉。舉例來說,在本發明電源供應器之過電流保護設定狀態中,校正工具110會提供一預定負載,使通過電阻RA1之負載電流IA1為負載上限。校正工具110會經由輸入端T3傳送校正資料DS至解碼器218。校正資料DS包含複數個設定值,每個設定值可被解碼器218解碼為複數個開關控制訊號V1至Vn,以控制複數個開關SW之開啟與關閉,並進而控制流經電阻RA2之電流IA2之大小(亦即控制第一校正電流感應電位VA2)。電位調整單元217根據複數個設定值逐漸調整第一校正電流感應電位VA2,直到比較器216所輸出的第一輸出位準VS1轉態時(例如從低電壓位準升到高電壓位準,或從高電壓位準降到低電壓位準),此時代表第一校正電流感應電位VA2等於或相當接近負載上限時之電壓位準,第一輸出位準VS1可迴授至校正工具110以使校正工具110可得知第一輸出位準VS1的轉態時機,並將相對應之校正資料DS寫入並儲存於第一記憶模組224A中,而成為校正資料130A。至於負載比較單元212B之第二輸出位準VS2的轉態方式,因與負載比較單元212A之第一輸出位準VS1的轉態方式類似,故不再贅述。 The potential adjustment unit 217 is coupled to the input terminal T2. In the embodiment, the potential adjustment unit 217 includes a plurality of current sources Iv1 to Ivn and a plurality of switches SW. The plurality of switches SW are respectively coupled between the plurality of current sources Iv1 to Ivn and the ground terminal for turning on and off according to the switch control signals V1 to Vn to control the magnitude of the current I A2 flowing through the resistor R A2 , and further The first correction current sensing potential V A2 is adjusted. The decoder 218 is configured to output a plurality of switch control signals V1 to Vn to a plurality of switches SW according to the received correction data D S to control the opening and closing of the plurality of switches SW. For example, in the overcurrent protection setting state of the power supply of the present invention, the calibration tool 110 provides a predetermined load such that the load current I A1 through the resistor R A1 is the upper load limit. The calibration tool 110 transmits the correction data D S to the decoder 218 via the input terminal T3. The calibration data D S includes a plurality of set values, each of which can be decoded by the decoder 218 into a plurality of switch control signals V1 to Vn to control the opening and closing of the plurality of switches SW, and further control the flow through the resistor RA 2 The magnitude of the current I A2 (ie, controlling the first corrected current sense potential V A2 ). The potential adjustment unit 217 gradually adjusts the first correction current sensing potential V A2 according to the plurality of set values until the first output level V S1 outputted by the comparator 216 transitions (for example, from a low voltage level to a high voltage level) , or from the high voltage level to the low voltage level), at this time represents the first correction current sensing potential V A2 is equal to or relatively close to the voltage level of the load upper limit, the first output level V S1 can be fed back to the correction The tool 110 causes the calibration tool 110 to know the transition timing of the first output level V S1 , and writes and stores the corresponding correction data D S in the first memory module 224A to become the calibration data 130A. As for the transition mode of the second output level V S2 of the load comparison unit 212B, the transition state of the first output level V S1 of the load comparison unit 212A is similar, and therefore will not be described again.
在本發明一實施例中,過電流保護晶片200可另包含兩個重工選擇器230A及230B。重工選擇器230A用以從第一記憶模組224A的多個記憶 單元A1至AX中選出第一記憶模組224A所儲存的最近一筆校正資料,而重工選擇器230B則用以從第二記憶模組224B的多個記憶單元B1至BX中選出第二記憶模組224B所儲存的最近一筆校正資料。換言之,重工選擇器230A及230B只會分別從第一記憶模組224A及第二記憶模組224B選出最新記錄的校正資料,而其他舊的校正資料並不會被選出。當重工選擇器230A及230B分別選出最新記錄的校正資料後,過電流保護電路20即可依據所選出的校正資料產生上述的兩組過電流保護值240A及240B。此外,值得注意地,重工選擇器230A及230B是分別因應第一記憶模組224A及第二記憶模組224B有多個記憶單元A1至AX及B1至BX而設置的。換言之,在本發明其他實施例中,倘若第一記憶模組224A及第二記憶模組224B各僅有一個記憶單元的話,則不必設置重工選擇器230A及230B。 In an embodiment of the invention, the overcurrent protection wafer 200 may further include two rework selectors 230A and 230B. The rework selector 230A is used for multiple memories from the first memory module 224A The latest correction data stored in the first memory module 224A is selected from the units A1 to AX, and the rework selector 230B is used to select the second memory module from the plurality of memory units B1 to BX of the second memory module 224B. The most recent calibration data stored in 224B. In other words, the rework selectors 230A and 230B will only select the latest recorded correction data from the first memory module 224A and the second memory module 224B, respectively, and other old correction data will not be selected. When the rework selectors 230A and 230B respectively select the latest recorded correction data, the overcurrent protection circuit 20 can generate the above two sets of overcurrent protection values 240A and 240B according to the selected correction data. In addition, it is noted that the rework selectors 230A and 230B are provided in response to the first memory module 224A and the second memory module 224B having a plurality of memory units A1 to AX and B1 to BX, respectively. In other words, in the other embodiments of the present invention, if the first memory module 224A and the second memory module 224B each have only one memory unit, it is not necessary to set the rework selectors 230A and 230B.
此外,雖然在本實施例中的電流保護晶片200係設計成提供兩組的過電流保護值240A及240B。然而,本發明並不以此為限,每一個過電流保護晶片200亦可設計成提供三組或更多組的過電流保護值。其中,每增加一組過電流保護值,只需再配置一個負載比較單元及記憶模組,並使負載機120再提供另一電流負載電位至此額外配置的負載比較單元,再完成對應的佈線(如:開關控制、訊號傳輸...等)即可。詳言之,倘若在本發明一實施例中,電流保護晶片被設計成可提供三組電流保護值的話,則電流保護晶片除了上述的三個輸入端P1至P3之外,可再另新增一個輸入端以接收負載機120所提供的第三電流負載電位。此外,切換選擇電路210可再包含另一個負載比較單元,用以比較校正資料Ds及上述的第三電流負載電位,而當校正資料Ds與上述的第三電流負載電位相符時,校正資料Ds即被儲存到上述所額外配置的記憶模組的一個記憶單元中。單一過電流保護晶片提供四組或四組以上的過電流保護值的電路設置也可以以此類推。 Furthermore, although the current protection die 200 in this embodiment is designed to provide two sets of overcurrent protection values 240A and 240B. However, the present invention is not limited thereto, and each of the overcurrent protection wafers 200 may also be designed to provide three or more sets of overcurrent protection values. Wherein, for each additional set of overcurrent protection values, only one load comparison unit and the memory module are configured, and the loader 120 is further provided with another current load potential to the additionally configured load comparison unit, and then the corresponding wiring is completed ( Such as: switch control, signal transmission, etc.). In detail, if, in an embodiment of the invention, the current protection wafer is designed to provide three sets of current protection values, the current protection wafer may be additionally added in addition to the three input terminals P1 to P3 described above. An input receives the third current load potential provided by the loader 120. In addition, the switching selection circuit 210 may further include another load comparison unit for comparing the correction data Ds and the third current load potential, and when the correction data Ds matches the third current load potential, the correction data Ds is It is stored in a memory unit of the above-mentioned additionally configured memory module. Circuit setups that provide four or more sets of overcurrent protection values for a single overcurrent protection die can be deduced by analogy.
在本發明一實施例中,過電流保護晶片200可另包含槽位比對單元220以及兩個選擇開關SW1及SW2。槽位比對單元220主要是用來與其他的過電流保護晶片200並接,以擴增電源供應器可校正的電力輸出之組數,以下將以第4圖來作說明。請參考第4圖,第4圖為本發明另一實施例之電源供應器的過電流保護電路30耦接於校正工具110及負載機120時之示意圖。過電流保護電路30包含兩個過電流保護晶片200_1及200_2。過電流保護晶片200_1及200_2與第2圖中的過電流保護晶片200的電路結構是一樣的。其中,過電流保護晶片200_1用以依據校正資料DS、第一電流負載電位VA1及第二電流負載電位VB1產生兩組過電流保護值240A及240B,而過電流保護晶片200_2則是用以依據校正資料DS、第三電流負載電位VC1及第四電流負載電位VD1產生兩組過電流保護值240C及240D。基本上,過電流保護晶片200_1的作動方式與第2圖中的過電流保護晶片200的作動方式一樣。至於過電流保護晶片200_2其作動方式亦類似,只是過電流保護晶片200_2所輸入的是第三電流負載電位VC1及第四電流負載電位VD1,並產生校正資料130C及130D及對應地輸出另外兩組的過電流保護值240C及240D。此外,過電流保護晶片200_2的負載比較單元212A及212B則分別透過電阻RC2及RD2耦接於電壓輸入端Vcs。過電流保護晶片200_2的負載比較單元212A可依據校正資料DS調整第三校正電流感應電位VC2,而過電流保護晶片200_2的負載比較單元212B可依據校正資料DS調整第四校正電流感應電位VD2。由於過電流保護晶片200_1及200_2的作動方式與過電流保護晶片200類似,故對於過電流保護晶片200_1及200_2的作動方式,在以下說明中將只對槽位比對單元220及兩個選擇開關SW1及SW2的部分作說明,而其他元件的作動方式將不再贅述。 In an embodiment of the invention, the overcurrent protection wafer 200 may further include a slot alignment unit 220 and two selection switches SW 1 and SW 2 . The slot alignment unit 220 is mainly used to be connected to other overcurrent protection wafers 200 to amplify the number of sets of power outputs that can be corrected by the power supply, which will be described below with reference to FIG. Please refer to FIG. 4 , which is a schematic diagram of the overcurrent protection circuit 30 of the power supply coupled to the calibration tool 110 and the loader 120 according to another embodiment of the present invention. The overcurrent protection circuit 30 includes two overcurrent protection wafers 200_1 and 200_2. The overcurrent protection wafers 200_1 and 200_2 are identical in circuit configuration to the overcurrent protection wafer 200 in FIG. The overcurrent protection wafer 200_1 is configured to generate two sets of overcurrent protection values 240A and 240B according to the calibration data D S , the first current load potential V A1 and the second current load potential V B1 , and the overcurrent protection wafer 200_2 is used. Two sets of overcurrent protection values 240C and 240D are generated based on the correction data D S , the third current load potential V C1 , and the fourth current load potential V D1 . Basically, the overcurrent protection wafer 200_1 operates in the same manner as the overcurrent protection wafer 200 in FIG. The operation mode of the overcurrent protection wafer 200_2 is similar, except that the overcurrent protection wafer 200_2 inputs the third current load potential V C1 and the fourth current load potential V D1 , and generates correction data 130C and 130D and correspondingly outputs another The overcurrent protection values of the two groups are 240C and 240D. In addition, the load comparison units 212A and 212B of the overcurrent protection wafer 200_2 are coupled to the voltage input terminal Vcs through the resistors R C2 and R D2 , respectively. The load comparison unit 212A of the overcurrent protection wafer 200_2 can adjust the third correction current sensing potential V C2 according to the correction data D S , and the load comparison unit 212B of the overcurrent protection wafer 200_2 can adjust the fourth correction current sensing potential according to the correction data D S . V D2 . Since the operation modes of the overcurrent protection wafers 200_1 and 200_2 are similar to those of the overcurrent protection wafer 200, for the operation modes of the overcurrent protection wafers 200_1 and 200_2, only the slot alignment unit 220 and the two selection switches will be described in the following description. The parts of SW 1 and SW 2 are explained, and the operation of other elements will not be described again.
過電流保護晶片200_1及200_2會接收槽位比對命令SCOM及槽位位置S1和S2,並比較槽位比對命令SCOM及槽位位置S1和S2,以分別輸出 致能訊號EN1及EN2,及決定致能訊號EN1及EN2的電位。在本發明一實施例中,可藉由對過電流保護晶片200_1及200_2的槽位比對單元220的多個腳位之狀態(例如:是否接地或耦接至特定電壓)進行設置,以分別地設定槽位位置S1和S2。此外,當收槽位比對命令SCOM與槽位位置S1一致時,致能訊號EN1會為第一電位,以開啟過電流保護晶片200_1的選擇開關SW1及SW2。當收槽位比對命令SCOM與槽位位置S1不一致時,致能訊號EN1則為第二電位,以關閉過電流保護晶片200_1的選擇開關SW1及SW2。類似地,當收槽位比對命令SCOM與槽位位置S2一致時,致能訊號EN2會為第一電位,以開啟過電流保護晶片200_2的選擇開關SW1及SW2。當收槽位比對命令SCOM與槽位位置S2不一致時,致能訊號EN2則為第二電位,以關閉過電流保護晶片200_2的選擇開關SW1及SW2。因此,過電流保護晶片200_1的選擇開關SW1會依據致能訊號EN1控制校正工具110至切換選擇電路210及第一記憶模組224A之間的電性連接,而過電流保護晶片200_1的選擇開關SW2會依據致能訊號EN1控制校正工具110至切換選擇電路210及第二記憶模組224B之間的電性連接。類似地,過電流保護晶片200_2的選擇開關SW1會依據致能訊號EN2控制校正工具110至過電流保護晶片200_2的切換選擇電路210及第一記憶模組224A之間的電性連接,而過電流保護晶片200_1的選擇開關SW2會依據致能訊號EN2控制校正工具110至過電流保護晶片200_2的切換選擇電路210及第二記憶模組224B之間的電性連接。因此,藉由上述串接多個過電流保護晶片的方式,即可擴增電源供應器可校正的電力輸出之組數。此外,第4圖中雖以串接兩顆過電流保護晶片200_1及200_2的方式作說明,但本發明並不以此為限。換句話說,透過上述比較槽位比對命令SCOM及多個電流保護晶片之槽位位置的方式,本發明可另應用於串接三顆或更多顆過電流保護晶片的電源供應器中。 The overcurrent protection chips 200_1 and 200_2 receive the slot alignment command S COM and the slot positions S1 and S2, and compare the slot alignment command S COM and the slot positions S1 and S2 to respectively output the enable signal E N1 and E N2 , and determine the potential of the enable signals E N1 and E N2 . In an embodiment of the present invention, the states of the plurality of pins of the cell alignment unit 220 of the overcurrent protection wafers 200_1 and 200_2 (eg, whether grounded or coupled to a specific voltage) are set to respectively Set the slot positions S1 and S2. In addition, when the sinking bit comparison command S COM coincides with the slot position S1, the enable signal E N1 will be at the first potential to turn on the selection switches SW 1 and SW 2 of the overcurrent protection wafer 200_1. When the sinking bit comparison command S COM does not coincide with the slot position S1, the enable signal E N1 is at the second potential to turn off the selection switches SW 1 and SW 2 of the overcurrent protection wafer 200_1. Similarly, when the sink bit alignment command S COM coincides with the slot position S2, the enable signal E N2 will be at the first potential to turn on the selection switches SW 1 and SW 2 of the overcurrent protection wafer 200_2. When the sinking bit comparison command S COM does not coincide with the slot position S2, the enable signal E N2 is at the second potential to turn off the selection switches SW 1 and SW 2 of the overcurrent protection wafer 200_2. Thus, the overcurrent protection wafer out switch SW 1 selection will be based on the enabling signal 200_1 E N1 correction tool 110 to control selection switch 224A is electrically connected between the first circuit 210 and a memory module, selecting the overcurrent protection wafer 200_1 The switch SW 2 controls the electrical connection between the calibration tool 110 to the switching selection circuit 210 and the second memory module 224B according to the enable signal E N1 . Similarly, the overcurrent protection wafer out switch SW 1 selection will be based 200_2 enabling signal E N2 correction tool 110 to control an overcurrent protection wafer 224A is electrically connected between the selection circuit 210 switches 200_2 and the first memory module, and The selection switch SW 2 of the overcurrent protection wafer 200_1 controls the electrical connection between the calibration tool 110 to the switching selection circuit 210 and the second memory module 224B of the overcurrent protection wafer 200_2 according to the enable signal E N2 . Therefore, by serially connecting a plurality of overcurrent protection wafers, the number of sets of power output correctable by the power supply can be amplified. In addition, in FIG. 4, although the two overcurrent protection wafers 200_1 and 200_2 are connected in series, the present invention is not limited thereto. In other words, the present invention can be additionally applied to a power supply in which three or more overcurrent protection chips are serially connected through the comparison of the slot alignment command S COM and the positions of the slots of the plurality of current protection chips. .
請參考第5圖,第5圖為對第2圖的過電流保護晶片200進行校 正時的流程圖。在步驟S410中,透過校正工具110設定校正目標組別,以決定負載機120後續輸出至校正目標的電流負載電位。在步驟S420中,透過負載機120給予校正目標電流負載電位。在步驟S430中,藉由切換選擇電路210判斷應校正的組別,以決定後續校正資料DS應該儲存至記憶模組224A及224B中的哪一個記憶模組。在步驟S440中,藉由負載比較單元212A或212B對應校正的組別進行校正。在步驟S450中,透過校正工具110,判斷是否還有其他組別需要校正。若還有其他組別需要校正,則回到步驟S410;反之,則完成過電流保護晶片200的校正(步驟S460)。 Please refer to FIG. 5, which is a flow chart when the overcurrent protection wafer 200 of FIG. 2 is corrected. In step S410, the correction target group is set by the correction tool 110 to determine the current load potential that the loader 120 subsequently outputs to the correction target. In step S420, the correction target current load potential is given through the loader 120. In step S430, the group to be corrected is determined by the switching selection circuit 210 to determine which of the memory modules 224A and 224B the subsequent correction data D S should be stored. In step S440, the correction is performed by the load comparison unit 212A or 212B corresponding to the corrected group. In step S450, it is determined by the correction tool 110 whether there are other groups that need correction. If there are other groups that need to be corrected, then return to step S410; otherwise, the correction of the overcurrent protection wafer 200 is completed (step S460).
請參考第6圖,第6圖為對第4圖的多個過電流保護晶片200_1及200_2進行校正時的流程圖。在步驟S510中,透過每個過電流保護晶片的槽位比對單元220連接多個過電流保護晶片。在步驟S520中,校正工具110送出槽位比對命令SCOM至各過電流保護晶片的槽位比對單元220。在步驟S530中,各槽位比對單元220比對槽位比對命令SCOM與槽位位置S1及S2。在步驟S540中,各槽位比對單元220判斷槽位比對命令SCOM與槽位位置S1或S2是否匹配。若匹配,則執行步驟S550,以進行如第5圖的校正程序。反之,若不匹配,則回到步驟S520。 Please refer to FIG. 6. FIG. 6 is a flow chart when the plurality of overcurrent protection wafers 200_1 and 200_2 of FIG. 4 are corrected. In step S510, a plurality of overcurrent protection wafers are connected through the slot alignment unit 220 of each overcurrent protection wafer. In step S520, the calibration tool 110 sends the slot alignment command S COM to the slot alignment unit 220 of each of the overcurrent protection wafers. In step S530, each slot alignment unit 220 compares the slot alignment command S COM with the slot positions S1 and S2. In step S540, each slot alignment unit 220 determines whether the slot alignment command S COM matches the slot position S1 or S2. If there is a match, step S550 is performed to perform the correction procedure as shown in FIG. On the other hand, if it does not match, the process returns to step S520.
請參考第7圖,第7圖為對安裝有第2圖的過電流保護晶片200的電源供應器由校正設定到出廠的流程圖。在步驟S610中,藉由校正工具110進行校正規格的設定。在步驟S620中,藉由校正工具110及負載機120開始進行如第5圖的校正程序。在步驟S630中,將校正後所決定的校正資料130A及130B分別被儲存在第一記憶模組224A及第二記憶模組224B的一個記憶單元中。在步驟S640中,藉由重工選擇器230A及230B分別自第一記憶模組224A及第二記憶模組224B選出最新記錄的校正資料。在步驟S650中,依據所選出的最新記錄的校正資料,對電源供應器進行測試。在步驟S660 中,判斷測試結果是否符合規格。若符合規格,則進行步驟S670的出貨程序。反之,若不符合規格,則回到步驟S610,以重新進行校正。 Please refer to FIG. 7. FIG. 7 is a flow chart showing the setting of the power supply of the overcurrent protection wafer 200 to which the second figure is mounted from the calibration to the factory. In step S610, the correction specification is set by the correction tool 110. In step S620, the calibration procedure as shown in Fig. 5 is started by the correction tool 110 and the loader 120. In step S630, the corrected correction data 130A and 130B are stored in a memory unit of the first memory module 224A and the second memory module 224B, respectively. In step S640, the newly recorded correction data is selected from the first memory module 224A and the second memory module 224B by the rework selectors 230A and 230B, respectively. In step S650, the power supply is tested according to the selected latest recorded correction data. At step S660 In the determination of whether the test results meet the specifications. If the specification is met, the shipping procedure of step S670 is performed. On the other hand, if the specification is not met, the process returns to step S610 to perform the correction again.
綜上所述,透過本發明的過電流保護晶片及過電流保護電路,可很方便地對電源供應器進行多組的過電流保護設定。再者,每組可校正的電力輸出可搭配一個包含多個記憶單元的記憶模組,以方便電源供應器製造廠於生產其電源供應器後如須變更其規格、設計時,可輕易地回收電源供應器且透過更新記憶模組所儲存的校正資料,完成新規格的過電流校正的設定。此外,可透過槽位比對單元來串接多個槽位比對單元,而使電源供應器的可校正電力輸出之組數得以輕易地擴增,而不須再另外設計新的過電流保護晶片,故使用上具有極高的彈性。 In summary, through the overcurrent protection chip and the overcurrent protection circuit of the present invention, multiple sets of overcurrent protection settings can be conveniently performed on the power supply. Furthermore, each set of calibratable power output can be combined with a memory module containing a plurality of memory units to facilitate the power supply manufacturer to easily recycle after changing its specifications and design after producing its power supply. The power supply device completes the setting of the over-current correction of the new specification by updating the calibration data stored in the memory module. In addition, a plurality of slot alignment units can be serially connected through the slot alignment unit, so that the number of sets of correctable power output of the power supply can be easily expanded without additionally designing a new overcurrent protection. The wafer is extremely flexible in use.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
20‧‧‧過電流保護電路 20‧‧‧Overcurrent protection circuit
110‧‧‧校正工具 110‧‧‧ calibration tool
120‧‧‧負載機 120‧‧‧Loader
130A、130B、DS‧‧‧校正資料 130A, 130B, D S ‧ ‧ calibration data
200‧‧‧過電流保護晶片 200‧‧‧Overcurrent protection chip
210‧‧‧切換選擇電路 210‧‧‧Switch selection circuit
212A、212B‧‧‧負載比較單元 212A, 212B‧‧‧ load comparison unit
214‧‧‧校正組選擇器 214‧‧‧Correction group selector
220‧‧‧槽位比對單元 220‧‧‧Slot comparison unit
224A‧‧‧第一記憶模組 224A‧‧‧First Memory Module
224B‧‧‧第二記憶模組 224B‧‧‧Second memory module
230A、230B‧‧‧重工選擇器 230A, 230B‧‧‧Rework Selector
240A、240B‧‧‧過電流保護值 240A, 240B‧‧‧Overcurrent protection value
A1至AX、B1至BX‧‧‧記憶單元 A1 to AX, B1 to BX‧‧‧ memory unit
EN1‧‧‧致能訊號 E N1 ‧‧‧Enable signal
IA1‧‧‧負載電流 I A1 ‧‧‧Load current
P1至P3‧‧‧輸入端 P1 to P3‧‧‧ input
VA1‧‧‧第一電流負載電位 V A1 ‧‧‧First current load potential
VB1‧‧‧第二電流負載電位 V B1 ‧‧‧second current load potential
VA2‧‧‧第一校正電流感應電位 V A2 ‧‧‧First corrected current sense potential
VB2‧‧‧第二校正電流感應電位 V B2 ‧‧‧Second corrected current sense potential
VS1‧‧‧第一輸出位準 V S1 ‧‧‧first output level
VS2‧‧‧第二輸出位準 V S2 ‧‧‧second output level
Vcs‧‧‧電壓輸入端 Vcs‧‧‧ voltage input
RA1、RA2‧‧‧電阻 R A1 , R A2 ‧‧‧resistance
S1‧‧‧槽位位置 S1‧‧‧ slot position
SCOM‧‧‧槽位比對命令 S COM ‧‧‧ slot alignment command
SW1、SW2‧‧‧選擇開關 SW 1 , SW 2 ‧‧‧ selection switch
SWA、SWB‧‧‧開關 SW A , SW B ‧‧‧ switch
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TWI801220B (en) * | 2022-04-26 | 2023-05-01 | 宏碁股份有限公司 | Power supply device |
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TW201239600A (en) * | 2011-03-25 | 2012-10-01 | Delta Electronics Inc | Power supply |
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