TW201621691A - Application processor for performing real time in-loop filtering, method thereof and system including the same - Google Patents

Abstract

An application processor includes a first core configured to process a first picture including a first processing unit and a second processing unit and a second core configured to process a second picture including a third processing unit and a fourth processing unit, wherein the first core and the second core are configured to perform processing of the second processing unit and the third processing unit, respectively, in parallel.

Description

用於進行即時迴路內濾波的應用處理機、用於該應用處理機之方法以及包括該應用處理機的系統 An application processor for performing in-loop loop filtering, a method for the application processor, and a system including the application processor 相關申請案 Related application

本申請案根據35U.S.C.§119主張2014年10月22日向印度專利局申請之印度臨時專利申請案第5269/CHE/2014號的優先權，該案之揭示內容以全文引用的方式併入本文中。 The present application claims priority to Indian Provisional Patent Application No. 5269/CHE/2014, filed on Oct. 22, 2014, to the PCT Application Serial No. in.

發明領域 Field of invention

例示性實施例係關於一種半導體裝置，且更明確而言係關於一種包括用於進行即時迴路內濾波之多個核心的應用處理機、用於該應用處理機之方法以及包括該應用處理機的系統。 The illustrative embodiments are directed to a semiconductor device, and more particularly to an application processor including a plurality of cores for performing in-circuit loop filtering, a method for the application processor, and a processor including the application processor system.

發明背景 Background of the invention

圖像中之切片及影像塊可減小熵編碼或熵解碼中之依賴性。然而，當圖像中之多個切片或影像塊由多個處理機並行地處理時，多個切片或影像塊的解塊操作可被 停止，直至鄰近於多個切片或影像塊之邊界的巨型區塊的處理操作結束。另外，多個處理機需要交換關於鄰近於多個切片或影像塊之邊界的巨型區塊之解塊操作的資訊。 Slices and image blocks in the image can reduce the dependence in entropy coding or entropy decoding. However, when multiple slices or image blocks in an image are processed in parallel by multiple processors, the deblocking operation of multiple slices or image blocks can be Stopping until the processing operation of the giant block adjacent to the boundary of multiple slices or image blocks ends. In addition, multiple processors need to exchange information about the deblocking operations of megablocks adjacent to the boundaries of multiple slices or image blocks.

亦即，當圖像中的多個經劃分區由多個處理機並行地處理時，解塊操作可歸因於由多個處理機處理的圖像中之多個經劃分區的依賴性及分佈而被停止或延遲。 That is, when a plurality of divided regions in an image are processed in parallel by a plurality of processors, the deblocking operation may be attributed to the dependency of a plurality of partitioned regions in the image processed by the plurality of processors and The distribution is stopped or delayed.

發明概要 Summary of invention

根據例示性實施例的態樣，提供一種包括經組配以處理包括第一處理單元及第二處理單元之第一圖像的第一核心及經組配以處理包括第三處理單元及第四處理單元之第二圖像的第二核心的應用處理機，其中第一核心及第二核心經組配以並行地分別進行第二處理單元及第三處理單元之處理。 According to an aspect of the exemplary embodiments, there is provided a first core comprising being configured to process a first image including a first processing unit and a second processing unit and configured to include a third processing unit and a fourth An application processor of the second core of the second image of the processing unit, wherein the first core and the second core are assembled to perform processing of the second processing unit and the third processing unit, respectively, in parallel.

第一核心可基於第一圖像之處理複雜度將第一圖像劃分成第一處理單元及第二處理單元，第二核心可基於第二圖像之處理複雜度將第二圖像劃分成第三處理單元及第四處理單元，且當第二處理單元中之切片的數目不同於第三處理單元中之切片的數目時，第一核心在第一時間段中完成第二處理單元的處理且第二核心在第一時間段中完成第三處理單元之處理。 The first core may divide the first image into a first processing unit and a second processing unit based on processing complexity of the first image, and the second core may divide the second image into processing based on processing complexity of the second image a third processing unit and a fourth processing unit, and when the number of slices in the second processing unit is different from the number of slices in the third processing unit, the first core completes processing of the second processing unit in the first time period And the second core completes the processing of the third processing unit in the first time period.

第一核心可基於第一圖像之處理複雜度將第一圖像劃分成第一處理單元及第二處理單元，第二核心可基於第二圖像之處理複雜度將第二圖像劃分成第三處理單元 及第四處理單元，且當第二處理單元中之影像塊的數目不同於第三處理單元中之影像塊的數目時，第一核心在第一時間段中完成第二處理單元之處理且第二核心在第一時間段中完成第三處理單元之處理。 The first core may divide the first image into a first processing unit and a second processing unit based on processing complexity of the first image, and the second core may divide the second image into processing based on processing complexity of the second image Third processing unit And a fourth processing unit, and when the number of image blocks in the second processing unit is different from the number of image blocks in the third processing unit, the first core completes processing of the second processing unit in the first time period and The second core completes the processing of the third processing unit in the first time period.

第一核心可包括符合H.264視訊寫碼標準的迴路內濾波器，且在第一核心處理第二處理單元並使用迴路內濾波器進行第二處理單元中之經處理區塊的迴路內濾波的同時第二核心處理第三處理單元。 The first core may include an in-loop filter conforming to the H.264 video writing standard, and processing the second processing unit in the first core and using the in-loop filter to perform in-loop filtering of the processed block in the second processing unit At the same time, the second core processes the third processing unit.

第一核心可包括符合高效率視訊寫碼(HEVC)標準之迴路內濾波器，且在第一核心處理第二處理單元並使用迴路內濾波器進行第二處理單元中之經處理區塊的迴路內濾波的同時第二核心處理第三處理單元。 The first core may include an in-loop filter that conforms to the High Efficiency Video Write Code (HEVC) standard, and the second processing unit is processed in the first core and the loop of the processed block in the second processing unit is performed using the in-loop filter The second core processes the third processing unit while filtering internally.

第一處理單元、第二處理單元、第三處理單元及第四處理單元中之每一者可包括至少一個切片。 Each of the first processing unit, the second processing unit, the third processing unit, and the fourth processing unit may include at least one slice.

第一處理單元、第二處理單元、第三處理單元及第四處理單元中的每一者可包括至少一個影像塊。 Each of the first processing unit, the second processing unit, the third processing unit, and the fourth processing unit may include at least one image block.

第一核心可體現於第一硬體編解碼器中且第二核心可體現於第二硬體編解碼器中。 The first core may be embodied in the first hardware codec and the second core may be embodied in the second hardware codec.

第一核心及第二核心可體現於單一硬體編解碼器中。 The first core and the second core can be embodied in a single hardware codec.

第一核心可為中央處理單元(CPU)之第一核心且第二核心可為CPU之第二核心。 The first core may be the first core of the central processing unit (CPU) and the second core may be the second core of the CPU.

第三處理單元之處理可在來自第一處理單元之處理的處理時間的延遲之後進行。 The processing of the third processing unit may be performed after a delay in processing time from the processing of the first processing unit.

根據另一例示性實施例的態樣，提供系統單晶片(SoC)，其包括：接收器介面，經組配以接收具有第一處理單元及第二處理單元之第一圖像及具有第三處理單元及第四處理單元之第二圖像；第一核心，經組配以處理第一圖像；以及第二核心，經組配以處理第二圖像，其中第一核心及第二核心經組配以並行地分別進行第二處理單元及第三處理單元的處理。 In accordance with an aspect of another exemplary embodiment, a system single chip (SoC) is provided, comprising: a receiver interface configured to receive a first image having a first processing unit and a second processing unit and having a third a second image of the processing unit and the fourth processing unit; a first core configured to process the first image; and a second core configured to process the second image, wherein the first core and the second core The processing of the second processing unit and the third processing unit is performed in parallel in parallel.

當第二處理單元中之切片的數目不同於第三處理單元中之切片的數目時，第一核心可在第一時間段中完成第二處理單元的處理且第二核心可在第一時間段中完成第三處理單元的處理。 When the number of slices in the second processing unit is different from the number of slices in the third processing unit, the first core may complete processing of the second processing unit in the first time period and the second core may be in the first time period The processing of the third processing unit is completed.

當第二處理單元中之影像塊的數目不同於第三處理單元中之影像塊的數目時，第一核心可在第一時間段中完成第二處理單元的處理且第二核心可在第一時間段中完成第三處理單元的處理。 When the number of image blocks in the second processing unit is different from the number of image blocks in the third processing unit, the first core may complete the processing of the second processing unit in the first time period and the second core may be in the first The processing of the third processing unit is completed in the time period.

第一核心可包括符合H.264視訊寫碼標準的迴路內濾波器，且第二核心可在第一核心處理第二處理單元並使用迴路內濾波器進行第二處理單元中之經處理區塊的迴路內濾波的同時處理第三處理單元。 The first core may include an in-loop filter conforming to the H.264 video writing standard, and the second core may process the second processing unit in the first core and use the in-loop filter to perform the processed block in the second processing unit The intra-loop filtering simultaneously processes the third processing unit.

第一核心可包括符合高效率視訊寫碼(HEVC)標準之迴路內濾波器，且第二核心可在第一核心處理第二處理單元並使用迴路內濾波器進行第二處理單元中之經處理區塊的迴路內濾波的同時處理第三處理單元。 The first core may include an in-loop filter conforming to the High Efficiency Video Write Code (HEVC) standard, and the second core may process the second processing unit at the first core and perform processing in the second processing unit using the in-loop filter The third processing unit is processed while the intra-loop filtering of the block.

根據另一例示性實施例的態樣，提供資料處理系 統，其包括：接收器介面，經組配以接收具有第一處理單元及第二處理單元之第一圖像及具有第三處理單元及第四處理單元之第二圖像；第一核心，經組配以處理第一圖像；以及第二核心，經組配以處理第二圖像，其中第一核心及第二核心經組配以並行地分別進行第二處理單元及第三處理單元的處理。 According to another aspect of the exemplary embodiment, a data processing system is provided The system includes: a receiver interface configured to receive a first image having a first processing unit and a second processing unit and a second image having a third processing unit and a fourth processing unit; the first core, Composing to process the first image; and the second core is configured to process the second image, wherein the first core and the second core are assembled to perform the second processing unit and the third processing unit, respectively, in parallel Processing.

當第二處理單元中之切片的數目不同於第三處理單元中之切片的數目時，第一核心可在第一時間段中完成第二處理單元的處理且第二核心可在第一時間段中完成第三處理單元的處理。 When the number of slices in the second processing unit is different from the number of slices in the third processing unit, the first core may complete processing of the second processing unit in the first time period and the second core may be in the first time period The processing of the third processing unit is completed.

當第二處理單元中之影像塊的數目不同於第三處理單元中之影像塊的數目時，第一核心可在第一時間段中完成第二處理單元的處理且第二核心可在第一時間段中完成第三處理單元的處理。 When the number of image blocks in the second processing unit is different from the number of image blocks in the third processing unit, the first core may complete the processing of the second processing unit in the first time period and the second core may be in the first The processing of the third processing unit is completed in the time period.

第一核心可包括符合H.264視訊寫碼標準的迴路內濾波器，且第二核心可在第一核心處理第二處理單元並使用迴路內濾波器進行第二處理單元中之經處理區塊的迴路內濾波的同時處理第三處理單元。 The first core may include an in-loop filter conforming to the H.264 video writing standard, and the second core may process the second processing unit in the first core and use the in-loop filter to perform the processed block in the second processing unit The intra-loop filtering simultaneously processes the third processing unit.

第一核心可包括符合高效率視訊寫碼(HEVC)標準之迴路內濾波器，且第二核心可在第一核心處理第二處理單元並使用迴路內濾波器進行第二處理單元中之經處理區塊的迴路內濾波的同時處理第三處理單元。 The first core may include an in-loop filter conforming to the High Efficiency Video Write Code (HEVC) standard, and the second core may process the second processing unit at the first core and perform processing in the second processing unit using the in-loop filter The third processing unit is processed while the intra-loop filtering of the block.

接收器介面可為無線介面。 The receiver interface can be a wireless interface.

第三處理單元之處理可在來自第一處理單元之 處理的處理時間的延遲之後進行。 The processing of the third processing unit can be from the first processing unit The processing time of the processing is delayed after the processing.

根據另一例示性實施例的態樣，提供一種用於處理視訊資料的方法，其包括：將視訊資料之第一圖像指派至第一核心並將視訊資料之第二圖像指派至第二核心；藉由第一核心處理第一圖像之第一處理單元；藉由第一核心處理第一圖像之第二處理單元；與藉由第一核心處理第二處理單元並行地，藉由第二核心處理第二圖像之第三處理單元；以及基於第一處理單元之處理結果進行經處理第一處理單元及經處理第二處理單元的迴路內濾波。 In accordance with an aspect of another exemplary embodiment, a method for processing video material is provided, comprising: assigning a first image of video material to a first core and assigning a second image of video data to a second a core; a first processing unit that processes the first image by the first core; a second processing unit that processes the first image by the first core; and in parallel with the second processing unit by the first core a second processing unit that processes the second image by the second core; and performs in-loop filtering of the processed first processing unit and the processed second processing unit based on the processing result of the first processing unit.

第一處理單元、第二處理單元及第三處理單元中的每一者可包括至少一個切片或影像塊。 Each of the first processing unit, the second processing unit, and the third processing unit may include at least one slice or image block.

視訊資料可包括奇數圖像及偶數圖像，且視訊資料之所有奇數圖像可經指派至第一核心，且視訊資料之所有偶數圖像可經指派至第二核心直至視訊資料之處理完成。 The video data may include odd and even images, and all odd images of the video data may be assigned to the first core, and all even images of the video data may be assigned to the second core until processing of the video data is completed.

該方法可進一步包括將視訊資料之第三圖像指派至第三核心；以及與第二圖像之第三處理單元的處理並行地，藉由第三核心處理第三圖像之第四處理單元。 The method can further include assigning a third image of the video material to the third core; and processing the fourth processing unit of the third image by the third core in parallel with the processing of the third processing unit of the second image .

根據另一例示性實施例之態樣，提供一種應用處理機，其包括：第一核心；以及第二核心，其中第一核心處理第一圖像之第一區塊集合而第二核心不處理，且第一核心處理第一圖像之第二區塊集合而第二核心處理第二圖像之第一區塊集合。 According to another exemplary embodiment, an application processor is provided, comprising: a first core; and a second core, wherein the first core processes the first block set of the first image and the second core does not process And the first core processes the second set of blocks of the first image and the second core processes the first set of blocks of the second image.

第一核心可處理第一圖像之第二區塊集合且第 二核心可並行處理第二圖像之第一區塊集合。 The first core can process the second block set of the first image and The second core can process the first set of blocks of the second image in parallel.

第一核心可在第二核心開始處理第二圖像之第一區塊集合的同時開始處理第一圖像之第二區塊集合。 The first core may begin processing the second set of blocks of the first image while the second core begins processing the first set of blocks of the second image.

10、610、612、614、616、620、622、624、626、630、632、634、636、638、640、642、644、646、650、652、654、656、660、662、664、666‧‧‧圖像 10, 610, 612, 614, 616, 620, 622, 624, 626, 630, 632, 634, 636, 638, 640, 642, 644, 646, 650, 652, 654, 656, 660, 662, 664, 666‧‧‧ images

100A、100B、100C‧‧‧資料處理系統 100A, 100B, 100C‧‧‧ data processing system

200A、200B、200C‧‧‧控制器 200A, 200B, 200C‧‧‧ controller

201‧‧‧匯流排 201‧‧‧ busbar

210A、210B‧‧‧中央處理單元(CPU) 210A, 210B‧‧‧ central processing unit (CPU)

220‧‧‧圖形處理單元(GPU) 220‧‧‧Graphical Processing Unit (GPU)

230、230-1、230-2、230-N、231-1、231-2、231-N‧‧‧硬體編解碼器 230, 230-1, 230-2, 230-N, 231-1, 231-2, 231-N‧‧‧ hardware codec

240‧‧‧記憶體介面(I/F) 240‧‧‧Memory Interface (I/F)

241‧‧‧第一記憶體介面 241‧‧‧First Memory Interface

243‧‧‧第二記憶體介面 243‧‧‧Second memory interface

245‧‧‧第三記憶體介面 245‧‧‧ third memory interface

250‧‧‧攝影機介面(I/F) 250‧‧‧ Camera Interface (I/F)

260‧‧‧顯示介面(I/F) 260‧‧‧Display Interface (I/F)

270‧‧‧接收器介面(I/F) 270‧‧‧ Receiver Interface (I/F)

301、303、305‧‧‧記憶體 301, 303, 305‧‧‧ memory

400‧‧‧顯示器 400‧‧‧ display

500‧‧‧攝影機 500‧‧‧ camera

610-1、612-1、614-1、616-1‧‧‧第一切片/第一處理單元 610-1, 612-1, 614-1, 616-1‧‧‧ first slice/first processing unit

610-2、612-2、614-2、616-2‧‧‧第二切片/第二處理單元 610-2, 612-2, 614-2, 616-2‧‧‧ second slice/second processing unit

700‧‧‧編碼器 700‧‧‧Encoder

701‧‧‧選擇電路 701‧‧‧Selection circuit

710‧‧‧預測器 710‧‧‧ predictor

712‧‧‧運動估計器 712‧‧‧Sports estimator

714、840‧‧‧運動補償器 714, 840‧‧ ‧ motion compensator

720‧‧‧減法器 720‧‧‧Subtractor

730‧‧‧變換器 730‧‧ converter

740‧‧‧量化器 740‧‧‧Quantifier

750、810‧‧‧熵編碼器 750, 810‧‧ Entropy Encoder

760、820‧‧‧反量化器 760, 820‧‧‧ inverse quantizer

770、830‧‧‧反變換器 770, 830‧‧ ‧ inverse converter

780、850‧‧‧加法器 780, 850‧‧ ‧ adder

790、860‧‧‧迴路內濾波器 790, 860‧‧‧ In-loop filter

800‧‧‧解碼器 800‧‧‧Decoder

S100、S110、S120、S130‧‧‧操作 S100, S110, S120, S130‧‧‧ operations

EB、EBS‧‧‧經編碼位元串流 EB, EBS‧‧‧ encoded bit stream

INV‧‧‧影像資料或視訊資料 INV‧‧‧Image data or video material

SEL‧‧‧選擇信號 SEL‧‧‧Selection signal

RV‧‧‧經重建構影像資料或經重建構視訊資料 RV‧‧‧ reconstructed image data or reconstructed video material

以上及其他態樣將藉由參看附圖詳細地描述例示性實施例而變得更清楚，在該等附圖中： The above and other aspects will become more apparent from the detailed description of the exemplary embodiments illustrated in the accompanying drawings in which:

圖1為根據例示性實施例之資料處理系統的方塊圖；圖2為說明包括多個切片的圖像之概念圖；圖3為說明分別包括兩個切片的圖像序列之概念圖；圖4為說明由兩個核心處理展示於圖3中的圖像序列之程序的概念圖；圖5為說明分別包括兩個切片群組的圖像序列之概念圖；圖6為說明由兩個核心處理展示於圖5中的圖像序列之程序的概念圖；圖7為說明分別包括三個切片的圖像序列之概念圖；圖8為說明由三個核心處理展示於圖7中的圖像序列之程序的概念圖；圖9為說明根據例示性實施例的運動向量搜尋的概念圖；圖10為說明根據例示性實施例的圖像序列之概 念圖，圖像中的每一者包括兩個影像塊。 1 is a block diagram of a data processing system according to an exemplary embodiment; FIG. 2 is a conceptual diagram illustrating an image including a plurality of slices; and FIG. 3 is a conceptual diagram illustrating an image sequence including two slices, respectively; A conceptual diagram illustrating a procedure for processing an image sequence shown in FIG. 3 by two cores; FIG. 5 is a conceptual diagram illustrating an image sequence including two slice groups, respectively; FIG. 6 is a diagram illustrating processing by two cores A conceptual diagram of a program of the sequence of images shown in FIG. 5; FIG. 7 is a conceptual diagram illustrating an image sequence including three slices, respectively; and FIG. 8 is a diagram illustrating an image sequence shown in FIG. 7 by three core processes. Conceptual diagram of a program; FIG. 9 is a conceptual diagram illustrating motion vector search in accordance with an exemplary embodiment; FIG. 10 is a diagram illustrating an image sequence in accordance with an exemplary embodiment. In the picture, each of the images includes two image blocks.

圖11為說明由兩個核心處理展示於圖10中的圖像序列之程序的概念圖。圖12為說明圖像序列的概念圖，圖像中的每一者分別包括兩個影像塊；圖13為說明圖像序列的概念圖，圖像中的每一者分別包括四個影像塊；圖14為說明由兩個核心處理展示於圖13中的圖像序列之程序的概念圖；圖15為說明展示於圖1中的資料處理系統之硬體編解碼器的方塊圖；圖16為展示於圖15中之硬體編解碼器的編碼器之方塊圖；圖17為展示於圖15中之硬體編解碼器的解碼器之方塊圖；圖18為說明根據例示性實施例之資料處理系統的方塊圖；圖19為說明根據例示性實施例之資料處理系統的方塊圖；且圖20為說明根據例示性實施例的由展示於圖1、圖18及圖19中的資料處理系統處理視訊資料的方法之流程圖。 Figure 11 is a conceptual diagram illustrating a procedure for processing the sequence of images shown in Figure 10 by two cores. 12 is a conceptual diagram illustrating an image sequence, each of the images including two image blocks; FIG. 13 is a conceptual diagram illustrating an image sequence, each of the images including four image blocks; Figure 14 is a conceptual diagram illustrating a procedure for processing a sequence of images shown in Figure 13 by two cores; Figure 15 is a block diagram illustrating a hardware codec of the data processing system shown in Figure 1; A block diagram of an encoder of the hardware codec shown in FIG. 15; FIG. 17 is a block diagram of a decoder of the hardware codec shown in FIG. 15; FIG. 18 is a diagram illustrating information according to an exemplary embodiment. A block diagram of a processing system; FIG. 19 is a block diagram illustrating a data processing system in accordance with an exemplary embodiment; and FIG. 20 is a diagram illustrating a data processing system shown in FIGS. 1, 18, and 19, in accordance with an exemplary embodiment. Flowchart of a method of processing video material.

較佳實施例之詳細說明 Detailed description of the preferred embodiment

現將在下文中參看隨附圖式來更充分地描述各種例示性實施例，在該等隨附圖式中展示例示性實施例。然而，本發明概念可以許多不同形式實施，且不應解釋為限於本文中所闡述的例示性實施例。實情為，提供此等例示性實施例使得本發明將透徹且完整，且將向熟習此項技術者充分傳達本發明概念之範疇。相同參考編號在整個說明書中可指示相同組件。在附圖中，出於清晰的目的，可能誇示層及區的厚度。 Various illustrative embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which FIG. However, the inventive concept may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be The same reference numbers may indicate the same components throughout the specification. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

亦應理解，當層被稱作「在另一層或基板上」時，其可直接在另一層或基板上，或亦可存在介入層。相比之下，當元件被稱作「直接在」另一元件「上」時，不存在介入元件。 It will also be understood that when a layer is referred to as "on another layer or substrate" it may be directly on the other layer or substrate, or an intervening layer may also be present. In contrast, when an element is referred to as being "directly on" another element, there is no intervening element.

諸如「底下」、「以下」、「下部」、「以上」、「上部」及類似者的空間相對術語本文中出於易於描述而使用以描述如諸圖中所說明的一個元件或特徵對於另一元件或特徵的關係。應理解，空間相對術語意欲涵蓋裝置在使用或操作中除圖中描繪之定向外的不同定向。舉例而言，若諸圖中之裝置翻轉，則描述為「在」其他元件或特徵「下方」或「底下」之元件將定向「在」其他元件或特徵「上方」。因此，例示性術語「在...下方」可涵蓋在...上方及在...下方之定向。裝置可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用的空間相對描述詞相應地進行解釋。 Spatially relative terms such as "bottom", "below", "lower", "above", "upper" and the like are used herein for the convenience of description to describe one element or feature as illustrated in the figures. The relationship of a component or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, elements in the "following" or "under" or "under" other elements or features will be "above" other elements or features. Thus, the exemplary term "below" can encompass an orientation above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the space used herein is interpreted accordingly with respect to the descriptor.

除非本文另外指示或明顯與內容相矛盾，否則在描述例示性實施例之上下文中(尤其在以下申請專利範圍 之上下文中)所使用的術語「一」及「該」以及類似參照物應解釋為涵蓋單數與複數兩者。除非另外指出，否則術語「包含」、「具有」、「包括」及「含有」應理解為開放術語(亦即，意謂「包括(但不限於)」)。 In the context of describing illustrative embodiments, particularly in the following claims, unless otherwise indicated herein or otherwise clearly contradicted. The terms "a", "an" and "the" are used in the context of the singular and plural. Unless otherwise stated, the terms "including", "having", "including" and "including" are understood to mean an open term (ie, meaning "including (but not limited to)").

除非另外界定，否則本文中所用的所有技術及科學術語具有與本發明概念所屬領域的一般熟習此項技術者通常所理解含義相同的含義。應注意，除非另外指定，否則本文中所提供的任何以及所有實例或例示性術語的使用僅僅意欲更好地闡明本發明概念而非限制本發明概念之範疇。另外，除非另外規定，否則不可過度解譯常用詞典中所定義之所有術語。 All technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains, unless otherwise defined. It is to be noted that the use of any and all examples or exemplifications of the present invention are intended to be illustrative only and not to limit the scope of the inventive concept. In addition, all terms defined in a common dictionary may not be overly interpreted unless otherwise specified.

將參看透視圖、橫截面圖及/或平面圖來描述例示性實施例。因此，例示性視圖的輪廓可根據製造技術及/或容許度進行修正。亦即，例示性實施例並非意欲限制本發明概念的範疇，而是覆蓋可歸因於製造過程的改變引起的所有改變及修改。因此，展示於圖式中的區以示意性形式說明，且區的形狀借助於說明且並非作為限制來簡單地呈現。 The illustrative embodiments will be described with reference to a perspective, cross-sectional view, and/or plan view. Thus, the outline of the illustrative views can be modified in accordance with manufacturing techniques and/or tolerances. That is, the exemplary embodiments are not intended to limit the scope of the inventive concept, but cover all changes and modifications that may result from changes in the manufacturing process. Accordingly, the regions illustrated in the drawings are illustrated in a schematic form, and the shapes of the regions are simply presented by way of illustration and not limitation.

將參看隨附圖式更全面地描述各種例示性實施例。 Various illustrative embodiments will be described more fully with reference to the drawings.

各種例示性實施例中之圖像或處理單元(亦即，待處理單元)可包括一或多個經劃分區，例如切片或影像塊。根據例示性實施例，圖像可由核心來處理。換言之，圖像中的所有經劃分區(例如，所有切片或所有影像塊)可由單一 核心處理。此處，處理可意謂編碼、解碼、包括迴路內濾波的編碼或包括迴路內濾波的解碼。 The image or processing unit (i.e., the unit to be processed) in various exemplary embodiments may include one or more partitioned regions, such as slices or image blocks. According to an exemplary embodiment, the image may be processed by the core. In other words, all divided regions in the image (for example, all slices or all image blocks) can be single Core processing. Here, processing may mean encoding, decoding, encoding including intra-loop filtering, or decoding including intra-loop filtering.

在各種例示性實施例中，圖像可經劃分成切片。切片界定一序列整數數目個巨型區塊(MB)或寫碼樹單元(CTU)分別用於AVC或HEVC。在用於HEVC之例示性實施例中，圖像亦可被劃分成影像塊。影像塊界定整數數目個CTU之矩形區，且可包括或含有於一個以上切片中的CTU。 In various exemplary embodiments, the image may be divided into slices. A slice defines a sequence of integer numbers of megablocks (MB) or code tree units (CTUs) for AVC or HEVC, respectively. In an exemplary embodiment for HEVC, an image may also be divided into image blocks. An image block defines a rectangular number of integer numbers of CTUs and may include or contain CTUs in more than one slice.

在一些例示性實施例中，資料處理系統100A、100B或100C可以全高清晰度(FHD)TV或超高清晰度(UHD)TV來實施。另外，資料處理系統100A、100B或100C可與諸如H.264、高效率視訊寫碼(HEVC)等視訊寫碼標準相容。 In some demonstrative embodiments, data processing system 100A, 100B, or 100C may be implemented in full high definition (FHD) TV or ultra high definition (UHD) TV. Additionally, data processing system 100A, 100B or 100C can be compatible with video writing standards such as H.264, High Efficiency Video Writing (HEVC).

在一些例示性實施例中，資料處理系統100A、100B或100C可實施於以下各者上：個人電腦(PC)、智慧型手機、平板PC、行動網際網路裝置(MID)、膝上型電腦、行動數位媒體播放器(M-DMP)或攜帶型媒體播放機(PMP)。 In some exemplary embodiments, data processing system 100A, 100B, or 100C may be implemented on: a personal computer (PC), a smart phone, a tablet PC, a mobile internet device (MID), a laptop. , mobile digital media player (M-DMP) or portable media player (PMP).

圖1為根據例示性實施例之資料處理系統的方塊圖。參看圖1，資料處理系統100A可包括控制器200A；多個記憶體301、303及305；及顯示器400。在一些例示性實施例中，資料處理系統100A可進一步包括攝影機500。 1 is a block diagram of a data processing system in accordance with an illustrative embodiment. Referring to FIG. 1, a data processing system 100A can include a controller 200A; a plurality of memories 301, 303, and 305; and a display 400. In some demonstrative embodiments, data processing system 100A may further include a camera 500.

控制器200A可實施為積體電路(IC)、系統單晶片(SoC)、主機板、應用處理機(AP)或行動AP。 The controller 200A can be implemented as an integrated circuit (IC), a system single chip (SoC), a motherboard, an application processor (AP), or a mobile AP.

控制器200A可接收並編碼輸入之未經壓縮YUV/RGB資料或解碼經編碼位元串流，控制諸如多個記憶體301、303及305的讀取/寫入操作的操作，且傳輸顯示資料或視訊資料至顯示器400。另外，控制器200A可處理自攝影機500輸出的影像資料或視訊資料，且可將經處理影像資料或經處理視訊資料儲存於多個記憶體301、303及305中之至少一者中，及/或將經處理影像資料或經處理視訊資料傳輸至顯示器400。 The controller 200A can receive and encode the input uncompressed YUV/RGB data or decode the encoded bit stream, control operations such as read/write operations of the plurality of memories 301, 303, and 305, and transmit the display data. Or video data to display 400. In addition, the controller 200A can process the image data or the video data output from the camera 500, and store the processed image data or the processed video data in at least one of the plurality of memories 301, 303, and 305, and/ The processed image data or the processed video data may be transmitted to the display 400.

控制器200A可包括中央處理單元(CPU)210A、圖形處理單元(GPU)220、多個硬體編解碼器230-1至230-N(N為等於或大於2的自然數)、記憶體介面(I/F)240、顯示介面(I/F)260及接收器介面(I/F)270。當資料處理系統100A進一步包括攝影機500時，控制器200A可進一步包括攝影機介面(I/F)250。 The controller 200A may include a central processing unit (CPU) 210A, a graphics processing unit (GPU) 220, a plurality of hardware codecs 230-1 to 230-N (N is a natural number equal to or greater than 2), a memory interface (I/F) 240, display interface (I/F) 260, and receiver interface (I/F) 270. When the data processing system 100A further includes the camera 500, the controller 200A may further include a camera interface (I/F) 250.

CPU 210A、GPU 220、多個硬體編解碼器230-1至230-N、記憶體介面240、顯示介面260及接收器介面270可經由匯流排201傳輸資料至彼此/自彼此接收資料。攝影機介面250可連接至其他組件(例如，210A及/或220)，且傳輸資料至其他組件/自其他組件接收資料。 The CPU 210A, the GPU 220, the plurality of hardware codecs 230-1 to 230-N, the memory interface 240, the display interface 260, and the receiver interface 270 can transmit data to/from each other via the bus 201. The camera interface 250 can be connected to other components (eg, 210A and/or 220) and transfer data to/from other components.

CPU 210A可包括一或多個核心。CPU 210A可控制控制器200A之總體操作。舉例而言，CPU 210A可執行用於控制以下各者之操作的程式碼或應用程式：GPU 220、多個硬體編解碼器230-1至230-N、記憶體介面240、攝影機介面250、顯示介面260及/或接收器介面270。 CPU 210A may include one or more cores. The CPU 210A can control the overall operation of the controller 200A. For example, the CPU 210A may execute a code or an application for controlling the operation of each of the following: the GPU 220, the plurality of hardware codecs 230-1 to 230-N, the memory interface 240, the camera interface 250, Display interface 260 and/or receiver interface 270.

GPU 220可處理2D或3D圖形資料。由GPU 220處理的圖形資料可儲存於多個記憶體301、303及305中之至少一者中，或可由顯示器400顯示。 GPU 220 can process 2D or 3D graphics data. The graphics data processed by GPU 220 may be stored in at least one of plurality of memories 301, 303, and 305, or may be displayed by display 400.

多個硬體編解碼器230-1至230-N鑒於結構及操作可實質上相同。在一些例示性實施例中，多個硬體編解碼器230-1至230-N中之每一者可被稱作核心。多個硬體編解碼器230-1至230-N中之每一者可分別包括記憶體MEM1至MEMN中之一者。記憶體MEM1至MEMN中之每一者可儲存一或多個經編碼及/或經解碼圖像中之一者，及/或進行一或多個經編碼及/或經解碼圖像的迴路內濾波。 The plurality of hardware codecs 230-1 to 230-N may be substantially identical in view of structure and operation. In some demonstrative embodiments, each of the plurality of hardware codecs 230-1 through 230-N may be referred to as a core. Each of the plurality of hardware codecs 230-1 to 230-N may include one of the memories MEM1 to MEMN, respectively. Each of the memories MEM1 through MEMN may store one of one or more encoded and/or decoded images and/or perform one or more encoded and/or decoded images in a loop Filtering.

記憶體介面240可包括第一記憶體介面241、第二記憶體介面243及第三記憶體介面245。舉例而言，當多個記憶體301、303、305中之第一記憶體301為動態隨機存取記憶體(DRAM)時，第一記憶體介面241可為DRAM介面。當第二記憶體303為NAND快閃記憶體時，第二記憶體介面243可為NAND快閃介面。當第三記憶體305為嵌入式多媒體卡(eMMC)時，第三記憶體介面可為eMMC介面。為了圖1中之描述方便起見，說明三個記憶體介面241、243及245以及三個記憶體301、303及305；然而，此為僅一個實例，且記憶體之數目不受特別限制。因此，本發明概念之技術概念並不受記憶體介面及連接至記憶體介面之記憶體的數目限制。 The memory interface 240 can include a first memory interface 241, a second memory interface 243, and a third memory interface 245. For example, when the first memory 301 of the plurality of memories 301, 303, 305 is a dynamic random access memory (DRAM), the first memory interface 241 can be a DRAM interface. When the second memory 303 is a NAND flash memory, the second memory interface 243 can be a NAND flash interface. When the third memory 305 is an embedded multimedia card (eMMC), the third memory interface may be an eMMC interface. For convenience of description in FIG. 1, three memory interfaces 241, 243, and 245 and three memories 301, 303, and 305 are illustrated; however, this is only one example, and the number of memories is not particularly limited. Therefore, the technical concept of the inventive concept is not limited by the number of memory interfaces and the memory connected to the memory interface.

顯示介面260可在CPU 210A、GPU 220或多個硬體編解碼器230-1至230-N中之每一者的控制下傳輸顯示資 料(例如，視訊資料)至顯示器400。在一些例示性實施例中，顯示介面260可體現為行動業界處理器介面MIPI®、嵌入式顯示埠(eDP)介面或高清晰度多媒體介面(HDMI)等的顯示器串列介面(DSI)。然而，此等介面僅為例示性的，且顯示介面260並不限於此。 The display interface 260 can transmit display funds under the control of each of the CPU 210A, the GPU 220, or the plurality of hardware codecs 230-1 to 230-N. Material (eg, video material) to display 400. In some exemplary embodiments, the display interface 260 may be embodied as a display serial interface (DSI) of the mobile industry processor interface MIPI®, embedded display (eDP) interface, or high definition multimedia interface (HDMI). However, such interfaces are merely exemplary, and the display interface 260 is not limited thereto.

接收器介面270可經由有線通訊網路或無線通訊網路來接收未經壓縮圖像資料(RGB/YUV)或/及經編碼位元串流。在一些例示性實施例中，接收器介面270可體現為通用串列匯流排介面(USB)、乙太網介面、藍芽介面、Wi-Fi介面或長期演進(LTETM)介面等。然而，此等介面僅為例示性的，且接收器介面270不限於此。 The receiver interface 270 can receive uncompressed image data (RGB/YUV) or/and encoded bitstreams via a wired communication network or a wireless communication network. In some exemplary embodiments, the receiver interface 270 may be embodied as a universal serial bus interface (USB), an Ethernet interface, a Bluetooth interface, a Wi-Fi interface, or a Long Term Evolution (LTETM) interface. However, such interfaces are merely exemplary and the receiver interface 270 is not limited thereto.

攝影機介面250可接收自攝影機500輸出的影像資料。在一些例示性實施例中，攝影機介面250可為MIPI®之攝影機串列介面(CSI)。然而，此介面僅為例示性的，且攝影機介面250不限於此。攝影機500可為包括CMOS影像感測器的攝影機模組。 The camera interface 250 can receive image data output from the camera 500. In some exemplary embodiments, camera interface 250 may be MIPI® Camera Serial Interface (CSI). However, this interface is merely exemplary, and the camera interface 250 is not limited thereto. Camera 500 can be a camera module that includes a CMOS image sensor.

圖2為說明包括多個切片之圖像的概念圖。 FIG. 2 is a conceptual diagram illustrating an image including a plurality of slices.

參看圖2，圖像10可包括多個切片SLICE1至SLICE3，且多個切片SLICE1至SLICE3中之每一者可包括多個區塊。舉例而言，如圖2的實例中所展示，SLICE1可包括區塊0至21，SLICE2可包括區塊22至39，且SLICE3可包括區塊40至63。包括於多個切片SLICE1至SLICE3中之每一者中的區塊之數目可彼此不同。替代地，包括於多個切片SLICE1至SLICE3中之每一者的區塊的數目對於每一切片 可相同。圖像10可為待編碼圖框、原始圖像、待編碼圖像的原始位元串流、待解碼圖框、經編碼圖像或經編碼位元串流EB。圖2展示具有64個區塊(亦即，區塊0至63)之圖像。然而，此僅為實例，且區塊之數目可比64更多或更少。 Referring to FIG. 2, the image 10 may include a plurality of slices SLICE1 to SLICE3, and each of the plurality of slices SLICE1 to SLICE3 may include a plurality of tiles. For example, as shown in the example of FIG. 2, SLICE 1 may include blocks 0 through 21, SLICE 2 may include blocks 22 through 39, and SLICE 3 may include blocks 40 through 63. The number of blocks included in each of the plurality of slices SLICE1 to SLICE3 may be different from each other. Alternatively, the number of blocks included in each of the plurality of slices SLICE1 to SLICE3 is for each slice Can be the same. Image 10 may be the frame to be encoded, the original image, the original bit stream of the image to be encoded, the frame to be decoded, the encoded image, or the encoded bit stream EB. Figure 2 shows an image with 64 blocks (i.e., blocks 0 to 63). However, this is only an example, and the number of blocks may be more or less than 64.

在H.264視訊寫碼標準中，區塊可為巨型區塊。在高效率視訊寫碼(HEVC)標準中，區塊可為寫碼樹單元(CTU)。在一些例示性實施例中，圖像10可為待編碼圖框、原始圖像、待編碼圖像之原始位元串流、待解碼圖框、經編碼圖像或經編碼位元串流EB等。 In the H.264 video writing standard, a block can be a giant block. In the High Efficiency Video Recording (HEVC) standard, a block may be a Code Tree Unit (CTU). In some exemplary embodiments, image 10 may be a frame to be encoded, an original image, an original bit stream of the image to be encoded, a frame to be decoded, an encoded image, or an encoded bit stream EB Wait.

編碼器可編碼圖像中之區塊，且解碼器可依序自區塊0至區塊63解碼圖像中的區塊。 The encoder can encode the tiles in the image, and the decoder can decode the tiles in the image from block 0 to block 63 in sequence.

在處理第一切片SLICE1中之第一區塊0之後，編碼器或解碼器並不進行經處理第一區塊0邊緣的迴路內濾波，此是因為不存在在經處理第一區塊0之前的區塊。另一方面，在處理第一切片SLICE1中的第二區塊1之後，編碼器或解碼器可基於經處理第一區塊0之第一視訊資料及經處理第二區塊1之第二視訊資料而進行第一區塊0邊緣及第二區塊1的迴路內濾波。亦即，編碼器或解碼器可對區塊邊界進行迴路內濾波。此處，區塊邊界表示兩個區塊之間的邊界。 After processing the first block 0 in the first slice SLICE1, the encoder or decoder does not perform in-loop filtering of the processed first block 0 edge because the first block 0 is not processed. The previous block. On the other hand, after processing the second block 1 in the first slice SLICE1, the encoder or decoder may be based on the first video data of the processed first block 0 and the second of the processed second block 1 In-loop filtering of the first block 0 edge and the second block 1 is performed for the video material. That is, the encoder or decoder can perform in-loop filtering on the block boundaries. Here, the block boundary represents the boundary between the two blocks.

在處理了第二切片SLICE2中之第23經處理區塊22之後，編碼器或解碼器可基於區塊14、21及23的視訊資料而進行第二SLICE2中之第23經處理區塊22邊緣以及第一切片SLICE1中之前區塊14及21的迴路內濾波。亦即，編碼 器或解碼器可對切片邊界進行迴路內濾波。 After processing the 23rd processed block 22 in the second slice SLICE2, the encoder or decoder may perform the 23rd processed block 22 edge in the second SLICE 2 based on the video data of the blocks 14, 21 and 23. And the in-loop filtering of the previous blocks 14 and 21 in the first slice SLICE1. That is, coding The decoder or decoder can perform in-loop filtering on the slice boundaries.

在處理了第三切片SLICE3中之第41經編碼區塊40之後，編碼器或解碼器可基於第33區塊32之視訊資料而進行第三SLICE3中之第41經處理區塊40邊緣以及第一切片SLICE2中之前區塊32的迴路內濾波。亦即，編碼器或解碼器可對切片邊界進行迴路內濾波。換言之，當前經處理區塊之迴路內濾波可使用較高經處理區塊及鄰近於當前區塊的剩餘經處理區塊來進行。 After processing the 41st encoded block 40 in the third slice SLICE3, the encoder or decoder may perform the 41st processed block 40 edge and the third in the third SLICE3 based on the video data of the 33rd block 32. In-loop filtering of the previous block 32 in a slice SLICE2. That is, the encoder or decoder can perform in-loop filtering on the slice boundaries. In other words, intra-loop filtering of the current processed block can be performed using the higher processed block and the remaining processed blocks adjacent to the current block.

根據例示性實施例，包括符合H.264之視訊寫碼標準的迴路內濾波的解碼器可針對每一區塊進行迴路內濾波。根據例示性實施例，包括符合HEVC之視訊寫碼標準的迴路內濾波的解碼器可針對每一區塊進行迴路內濾波。舉例而言，解碼器可進行區塊邊界上鄰近於當前經解碼區塊之多個區塊的迴路內濾波，或根據樣本適應性偏移(SAO)之視訊寫碼標準而進行當前經解碼區塊中所有像素的迴路內濾波。 According to an exemplary embodiment, a decoder including in-loop filtering conforming to the H.264 video writing code standard may perform in-loop filtering for each block. According to an exemplary embodiment, a decoder including in-loop filtering conforming to the HEVC-based video writing code standard may perform in-loop filtering for each block. For example, the decoder may perform in-loop filtering on a block boundary adjacent to a plurality of blocks of the currently decoded block, or perform a current decoded area according to a sample adaptive offset (SAO) video writing standard. In-loop filtering of all pixels in the block.

根據H.264之視訊寫碼標準的迴路內濾波可基於運動向量、預測模式資訊及/或量化參數等來進行。根據HEVC之視訊寫碼標準的迴路內濾波可基於運動向量、預測模式資訊、量化參數及/或SAO濾波器的多個參數等而進行。預測模式可包括框內預測模式資訊或框間預測模式資訊。 In-loop filtering according to the video coding standard of H.264 can be performed based on motion vectors, prediction mode information, and/or quantization parameters, and the like. In-loop filtering according to the video coding standard of HEVC can be performed based on motion vectors, prediction mode information, quantization parameters, and/or parameters of the SAO filter, and the like. The prediction mode may include in-frame prediction mode information or inter-frame prediction mode information.

圖3為說明分別包括兩個切片之圖像序列的概念圖。圖4為說明藉由兩個核心處理展示於圖3中之圖像序列的程序的概念圖。 FIG. 3 is a conceptual diagram illustrating an image sequence including two slices, respectively. 4 is a conceptual diagram illustrating a procedure for processing the sequence of images shown in FIG. 3 by two cores.

參看圖1、圖3及圖4，控制器200A可包括兩個硬體編解碼器230-1及230-2。第一核心CORE0可為第一硬體編解碼器230-1，且第二核心CORE1可為第二硬體編解碼器230-2。參看圖2描述的編碼器或解碼器可包括於第一核心CORE0及第二核心CORE1中。 Referring to Figures 1, 3 and 4, the controller 200A can include two hardware codecs 230-1 and 230-2. The first core CORE0 may be the first hardware codec 230-1, and the second core CORE1 may be the second hardware codec 230-2. The encoder or decoder described with reference to FIG. 2 may be included in the first core CORE0 and the second core CORE1.

參看圖3，多個圖像610、612、614、......及616中的每一者可分別包括兩個切片610-1~610-2、612-1~612-2、614-1~614-2、......及616-1~616-2。多個圖像610、612、614、......、及616中之每一者可分別包括第一處理單元610-1、612-1、614-1、......、及616-1以及第二處理單元610-2、612-2、614-2、......、及616-2。當於本發明中使用時，「處理單元」表示待處理的資料單元。舉例而言，多個圖像610、612、614、......、及616中的每一者可意謂待編碼圖框、原始圖像、待編碼圖像之原始位元串流、待解碼圖框、經編碼圖像，或自接收器介面270接收的經編碼位元串流EB等。 Referring to FIG. 3, each of the plurality of images 610, 612, 614, ..., and 616 may include two slices 610-1~610-2, 612-1~612-2, 614, respectively. -1~614-2, ... and 616-1~616-2. Each of the plurality of images 610, 612, 614, ..., and 616 may include first processing units 610-1, 612-1, 614-1, ..., respectively. And 616-1 and second processing units 610-2, 612-2, 614-2, ..., and 616-2. As used in the present invention, a "processing unit" means a data unit to be processed. For example, each of the plurality of images 610, 612, 614, ..., and 616 may mean the original bit stream of the image to be encoded, the original image, and the image to be encoded. The frame to be decoded, the encoded image, or the encoded bit stream EB received from the receiver interface 270, and the like.

在一些例示性實施例中，CPU 210A可控制接收器介面270，以使得奇數圖像可經指派至第一核心CORE0，且偶數圖像可經指派至第二核心CORE1。 In some demonstrative embodiments, CPU 210A may control receiver interface 270 such that odd images may be assigned to first core CORE0 and even images may be assigned to second core CORE1.

在一些例示性實施例中，CPU 210A可控制第一核心CORE0及第二核心CORE1，以使得奇數圖像可經指派至第一核心CORE0，且偶數圖像可經指派至第二核心CORE1。 In some demonstrative embodiments, CPU 210A may control first core CORE0 and second core CORE1 such that odd images may be assigned to first core CORE0 and even images may be assigned to second core CORE1.

參看圖4，在第一時間段T1中，第一核心CORE0 可處理第一圖像610之第一切片610-1。第二圖像612之第一切片612-1可於在第一時間段T1中第一圖像610之第一切片610-1的處理已由第一核心CORE0完成之後在第二時間段T2中由第二核心CORE1處理。 Referring to FIG. 4, in the first time period T1, the first core CORE0 The first slice 610-1 of the first image 610 can be processed. The first slice 612-1 of the second image 612 may be in the second time period after the processing of the first slice 610-1 of the first image 610 has been completed by the first core CORE0 in the first time period T1 The second core CORE1 is processed in T2.

在第二時間段T2中，第一核心CORE0可處理第一圖像610之第二切片610-2，且第二核心CORE1可處理第二圖像612之第一切片612-1。第一切片612-1及第二切片610-2的處理可在第二時間段T2中並行地進行。如本說明書中所使用，「處理......並行地進行」表示在處理中存在某重疊。因此，此處，「並行」表示，在第一切片612-1及第二切片610-2的處理中存在某重疊。亦即，雖然點線用於圖4、圖6、圖8、圖11、圖14中，但此等線僅出於易於描述而提供，且並不意欲表明用於處理之開始時間及結束時間準確地一致。舉例而言，圖4中之點線並非意欲表明，用於處理第一切片612-1及第二切片610-2的開始時間或結束時間準確地一致。然而，在一些例示性實施例中，開始時間可準確地一致，及/或結束時間可準確地一致。 In the second time period T2, the first core CORE0 may process the second slice 610-2 of the first image 610, and the second core CORE1 may process the first slice 612-1 of the second image 612. The processing of the first slice 612-1 and the second slice 610-2 may be performed in parallel in the second time period T2. As used in this specification, "processing...in parallel" means that there is some overlap in the processing. Therefore, here, "parallel" means that there is some overlap in the processing of the first slice 612-1 and the second slice 610-2. That is, although the dotted lines are used in FIG. 4, FIG. 6, FIG. 8, FIG. 11, and FIG. 14, these lines are provided only for ease of description, and are not intended to indicate the start time and end time for processing. Accurate and consistent. For example, the dotted line in FIG. 4 is not intended to indicate that the start time or end time for processing the first slice 612-1 and the second slice 610-2 is exactly the same. However, in some exemplary embodiments, the start times may be exactly consistent, and/or the end times may be exactly consistent.

另外，在第二時間段T2中，第一核心CORE0可基於第一圖像610中第一切片610-1之處理結果針對每一區塊對第一圖像610之第一切片610-1及第二切片610-2的邊界進行迴路內濾波。如參看圖2所描述，第一核心CORE0可使用鄰近於當前區塊的上部經處理區塊及左側經處理區塊中的至少一者來進行當前經處理區塊的迴路內濾波。亦即，第一核心CORE0可在第二時間段T2中進行第二切片610-2 的處理，及第一切片610-1及第二切片610-2的迴路內濾波，使得無額外時間用於迴路內濾波。 In addition, in the second time period T2, the first core CORE0 may be based on the processing result of the first slice 610-1 in the first image 610 for each block to the first slice 610 of the first image 610. Intra-loop filtering is performed on the boundary of 1 and the second slice 610-2. As described with reference to FIG. 2, the first core CORE0 may perform in-loop filtering of the current processed block using at least one of the upper processed block and the left processed block adjacent to the current block. That is, the first core CORE0 may perform the second slice 610-2 in the second time period T2. The processing, and the in-loop filtering of the first slice 610-1 and the second slice 610-2, so that no additional time is used for in-loop filtering.

在第三時間段T3中，第一核心CORE0可處理第三圖像614之第一切片614-1，且第二核心CORE1可處理第二圖像612之第二切片612-2。第三圖像614之第一切片614-1及第二圖像612之第二切片612-2的處理可在第二時間段T3內並行地進行。 In a third time period T3, the first core CORE0 may process the first slice 614-1 of the third image 614, and the second core CORE1 may process the second slice 612-2 of the second image 612. The processing of the first slice 614-1 of the third image 614 and the second slice 612-2 of the second image 612 may be performed in parallel during the second time period T3.

另外，在第三時間段T3中，第二核心CORE1可基於第二圖像612中第一切片612-1的處理結果針對每一區塊對第一切片612-1及第二切片612-2的邊界進行迴路內濾波。亦即，第二核心CORE1可在第三時間段T3中進行第二切片612-2之處理及第二圖像612的第一切片612-1及第二切片612-2的邊緣的迴路內濾波，使得無額外時間用於迴路內濾波。第二核心CORE1因此如圖4中所展示可具有1切片延遲。亦即，第二CORE1可在第一核心CORE0已結束第一圖像610之第一切片610-1的處理之後開始處理第二圖像612之第一切片612-1。 In addition, in the third time period T3, the second core CORE1 may pair the first slice 612-1 and the second slice 612 for each block based on the processing result of the first slice 612-1 in the second image 612. In-loop filtering is performed at the boundary of -2. That is, the second core CORE1 may perform the processing of the second slice 612-2 and the edge of the edge of the first slice 612-1 and the second slice 612-2 of the second image 612 in the third time period T3. Filtering so that there is no extra time for in-loop filtering. The second core CORE1 thus may have a 1 slice delay as shown in FIG. That is, the second CORE1 may start processing the first slice 612-1 of the second image 612 after the first core CORE0 has finished processing the first slice 610-1 of the first image 610.

圖5為說明分別包括兩個切片群組之圖像序列的概念圖。圖6為說明由兩個核心處理展示於圖5中之圖像序列的程序的概念圖。 FIG. 5 is a conceptual diagram illustrating an image sequence including two slice groups, respectively. Figure 6 is a conceptual diagram illustrating a procedure for processing the sequence of images shown in Figure 5 by two cores.

展示於圖1中的控制器200A可包括分別對應於第一核心CORE0及第二CORE1的兩個硬體編解碼器230-1及230-2。圖像序列可包括(例如)圖像620、622、624及626。 The controller 200A shown in FIG. 1 may include two hardware codecs 230-1 and 230-2 corresponding to the first core CORE0 and the second CORE1, respectively. The sequence of images may include, for example, images 620, 622, 624, and 626.

第一核心CORE0可基於處理複雜度或圖像620中 的多個經劃分區之大小而將圖像620劃分成第一處理單元及第二處理單元。在圖5及圖6中，第一處理單元可包括兩個切片SLICE1-1及SLICE1-2，且第二處理單元可包括三個切片SLICE1-3至SLICE1-5。在圖5中粗線上方展示第一處理單元，且在圖5中粗線下方展示第二處理單元。圖5展示第一處理單元中之每一者包括兩個切片，例如，第一圖像620包括具有SLICE1-1及SLICE1-2之第一處理單元。然而，此僅為一實例，且視多個經劃分區的複雜度或大小而定，第一處理單元可具有少於或多於兩個切片的多個切片。 The first core CORE0 can be based on processing complexity or image 620 The image 620 is divided into a first processing unit and a second processing unit by the size of the plurality of divided regions. In FIGS. 5 and 6, the first processing unit may include two slices SLICE1-1 and SLICE1-2, and the second processing unit may include three slices SLICE1-3 to SLICE1-5. The first processing unit is shown above the thick line in Figure 5, and the second processing unit is shown below the thick line in Figure 5. Figure 5 shows that each of the first processing units includes two slices, for example, the first image 620 includes a first processing unit having SLICE1-1 and SLICE1-2. However, this is only an example, and depending on the complexity or size of the plurality of partitioned regions, the first processing unit may have multiple slices of less than or more than two slices.

第二核心CORE1可基於圖像622之處理複雜度而將圖像622劃分成第一處理單元及第二處理單元。在圖5及圖6中，第一處理單元可包括兩個切片SLICE2-1及SLICE2-2，且第二處理單元可包括三個切片SLICE2-3至SLICE2-5。 The second core CORE1 may divide the image 622 into a first processing unit and a second processing unit based on the processing complexity of the image 622. In FIGS. 5 and 6, the first processing unit may include two slices SLICE2-1 and SLICE2-2, and the second processing unit may include three slices SLICE2-3 to SLICE2-5.

舉例而言，當圖像620、622、624及626並未劃分成多個切片或影像塊時，或當多個經劃分區(例如，切片或影像塊)具有不同處理複雜度時，有利的是基於處理複雜度界定針對多個核心CORE0及CORE1的並行處理的多個經劃分區。此處，第一核心CORE0及第二核心CORE1可劃分圖像620、622、624及626，並並行地處理多個經劃分區。處理複雜度由解碼時間及/或編碼時間及/或切片依據圖像的區塊的大小等來界定。 For example, when images 620, 622, 624, and 626 are not divided into multiple slices or image blocks, or when multiple divided regions (eg, slices or image blocks) have different processing complexity, it is advantageous A plurality of partitioned regions defining parallel processing for the plurality of cores CORE0 and CORE1 are defined based on processing complexity. Here, the first core CORE0 and the second core CORE1 may divide the images 620, 622, 624, and 626 and process the plurality of divided regions in parallel. Processing complexity is defined by decoding time and/or encoding time and/or slice size depending on the size of the block of the image, and the like.

當m在圖5中為等於或大於4的自然數時，類似地，第一核心CORE0可基於圖像624的處理複雜度將圖像624劃分成第一處理單元，及第二處理單元。在圖5及圖6中，第 一處理單元可包括兩個切片SLICE3-1及SLICE3-2，且第二處理單元可包括三個切片SLICE1-3至SLICE1-5。 When m is a natural number equal to or greater than 4 in FIG. 5, similarly, the first core CORE0 may divide the image 624 into a first processing unit and a second processing unit based on the processing complexity of the image 624. In Figures 5 and 6, the first A processing unit may include two slices SLICE3-1 and SLICE3-2, and the second processing unit may include three slices SLICE1-3 to SLICE1-5.

第二核心CORE1可基於圖像626之處理複雜度而將圖像626劃分成第一處理單元及第二處理單元。在圖5及圖6中，第一處理單元可包括兩個切片SLICEm-1及SLICEm-2，且第二處理單元可包括三個切片SLICEm-3及SLICEm-5。 The second core CORE1 may divide the image 626 into a first processing unit and a second processing unit based on the processing complexity of the image 626. In FIGS. 5 and 6, the first processing unit may include two slices SLICEm-1 and SLICEm-2, and the second processing unit may include three slices SLICEm-3 and SLICEm-5.

儘管每一圖像620、622、624、......、或626分別對於兩個核心CORE0及CORE1說明為經劃分成第一處理單元及第二處理單元，但出於方便描述圖5及圖6，圖像中處理單元的數目可根據處理單元的核心之數目而發生變化。 Although each image 620, 622, 624, ..., or 626 is illustrated as being divided into a first processing unit and a second processing unit for the two cores CORE0 and CORE1, respectively, FIG. 5 is described for convenience. And Figure 6, the number of processing units in the image can vary depending on the number of cores of the processing unit.

舉例而言，用於由第一核心CORE0處理三個切片SLICE1-3至SLICE1-5的處理時間及用於由第二核心CORE1處理兩個切片SLICE2-1至SLICE2-2的處理時間可實質上相同。此處，「實質上相同」的含義可包括「相等、幾乎相同、近乎相同或具有可容許差異容限情況下相同」。 For example, the processing time for processing the three slices SLICE1-3 to SLICE1-5 by the first core CORE0 and the processing time for processing the two slices SLICE2-1 to SLICE2-2 by the second core CORE1 may be substantially the same. Here, the meaning of "substantially the same" may include "equal, almost identical, nearly identical, or the same in the case of tolerance tolerance."

如圖5中所展示，每一圖像620、622、624、......、626可分別包括五個切片SLICE1-1至SLICE1-5、SLICE2-1至SLICE2-5、SLICE3-1至SLICE3-5、......、SLICEm-1至SLICEm-5。舉例而言，每一圖像620、622、624、......、626可為待編碼圖框、原始圖像、待編碼圖像之原始位元串流、待解碼圖框、經編碼圖像或經由接收器介面270接收的經編碼位元串流EB等。 As shown in FIG. 5, each image 620, 622, 624, ..., 626 may include five slices SLICE1-1 to SLICE1-5, SLICE2-1 to SLICE2-5, SLICE3-1, respectively. To SLICE3-5, ..., SLICEm-1 to SLICEm-5. For example, each image 620, 622, 624, ..., 626 may be a frame to be encoded, an original image, an original bit stream of the image to be encoded, a frame to be decoded, a frame The encoded image or encoded bit stream EB, etc., received via the receiver interface 270.

轉至圖6，在第一時間段T11中，第一核心CORE0 可處理第一圖像620之第一切片SLICE1-1及第二切片SLICE1-2。在第一時間段T11中，第一核心CORE0可基於切片SLICE1-1的處理結果針對每一區塊對切片SLICE1-1及SLICE1-2的邊界進行迴路內濾波。 Going to FIG. 6, in the first time period T11, the first core CORE0 The first slice SLICE1-1 and the second slice SLICE1-2 of the first image 620 may be processed. In the first time period T11, the first core CORE0 may perform intra-loop filtering on the boundaries of the slices SLICE1-1 and SLICE1-2 for each block based on the processing result of the slice SLICE1-1.

在第二時間段T12中，第一核心CORE0可處理第一圖像620之第三切片SLICE1-3至第五切片SLICE1-5，且第二核心CORE1可處理第二圖像622之第一切片SLICE2-1及第二切片SLICE2-2。第三切片SLICE1-3至第五切片SLICE1-5的處理及第一切片SLICE2-1及第二切片SLICE2-2的處理可在第二時間段T12內並行地進行。 In the second time period T12, the first core CORE0 may process the third slice SLICE1-3 to the fifth slice SLICE1-5 of the first image 620, and the second core CORE1 may process the first slice of the second image 622 Slice SLICE2-1 and second slice SLICE2-2. The processing of the third slice SLICE1-3 to the fifth slice SLICE1-5 and the processing of the first slice SLICE2-1 and the second slice SLICE2-2 may be performed in parallel in the second time period T12.

在第二時間段T12中，第一核心CORE0可基於切片SLICE1-2的處理結果針對每一區塊對切片SLICE1-2及SLICE1-3的邊界進行迴路內濾波。在第二時間段T12中，第一核心CORE0可基於切片SLICE1-3的處理結果對每一區塊的切片SLICE1-3及SLICE1-4的邊界進行迴路內濾波，且可基於切片SLICE1-4的處理結果針對每一區塊對切片SLICE1-4及SLICE1-5的邊界進行迴路內濾波。另外，在第二時間段T12中，第二核心CORE1可基於切片SLICE2-1的處理結果針對每一區塊對切片SLICE2-1及SLICE2-2的邊界進行迴路內濾波。 In the second time period T12, the first core CORE0 may perform intra-loop filtering on the boundaries of the slices SLICE1-2 and SLICE1-3 for each block based on the processing result of the slice SLICE1-2. In the second time period T12, the first core CORE0 may perform in-loop filtering on the boundaries of the slices SLICE1-3 and SLICE1-4 of each block based on the processing result of the slice SLICE1-3, and may be based on the slice SLICE1-4 The processing result performs in-loop filtering on the boundaries of slices SLICE1-4 and SLICE1-5 for each block. In addition, in the second time period T12, the second core CORE1 may perform intra-loop filtering on the boundaries of the slices SLICE2-1 and SLICE2-2 for each block based on the processing result of the slice SLICE2-1.

亦即，在第二時間段T12中，第一核心CORE0可對三個切片SLICE1-3至SLICE1-5進行迴路內濾波，且第二CORE1可對兩個切片SLICE2-1及SLICE2-2進行迴路內濾波，使得無額外時間用於迴路內濾波，例如，無用於收集 在第一核心CORE0及第二核心CORE1上分散的切片的額外時間。 That is, in the second time period T12, the first core CORE0 can perform intra-loop filtering on the three slices SLICE1-3 to SLICE1-5, and the second CORE1 can loop on the two slices SLICE2-1 and SLICE2-2. Internal filtering, so that no extra time is used for in-loop filtering, for example, no for collection The extra time of the slice scattered over the first core CORE0 and the second core CORE1.

在第三時間段T13中，第一核心CORE0可處理第三圖像624之第一切片SLICE3-1及第二切片SLICE3-2。在第三時間段T31中，第一核心CORE0可基於切片SLICE3-1的處理結果針對每一區塊對切片SLICE3-1及SLICE3-2的邊界進行迴路內濾波。 In the third time period T13, the first core CORE0 can process the first slice SLICE3-1 and the second slice SLICE3-2 of the third image 624. In the third time period T31, the first core CORE0 may perform intra-loop filtering on the boundaries of the slices SLICE3-1 and SLICE3-2 for each block based on the processing result of the slice SLICE3-1.

在第三時間段T13中，第一核心CORE0可處理第三圖像624的第一切片SLICE3-1及第二切片SLICE3-2，且第二核心CORE1可處理第二圖像622的第三切片SLICE2-3至第五切片SLICE2-5。第三切片SLICE2-3至第五切片SLICE2-5的處理及第一切片SLICE3-1及第二切片SLICE3-2的處理可在第三時間段T13內並行地進行。 In the third time period T13, the first core CORE0 may process the first slice SLICE3-1 and the second slice SLICE3-2 of the third image 624, and the second core CORE1 may process the third of the second image 622 Slice SLICE2-3 to fifth slice SLICE2-5. The processing of the third slice SLICE2-3 to the fifth slice SLICE2-5 and the processing of the first slice SLICE3-1 and the second slice SLICE3-2 may be performed in parallel in the third time period T13.

在第三時間段T13中，第一核心CORE0可基於切片SLICE3-1的處理結果針對每一區塊對切片SLICE3-1及SLICE3-2的邊界進行迴路內濾波。另外，在第三時間段T13中，第二核心CORE1可基於切片SLICE2-2的處理結果針對每一區塊對切片SLICE2-2及SLICE2-3之邊界進行迴路內濾波。在第三時段T13中，第二核心CORE1可基於切片SLICE2-3的處理結果針對每一區塊對切片SLICE2-3及SLICE2-4的邊界進行迴路內濾波，且可基於切片SLICE2-4之處理結果針對每一區塊對切片SLICE2-4及SLICE2-5的邊界進行迴路內濾波。 In the third time period T13, the first core CORE0 may perform intra-loop filtering on the boundaries of the slices SLICE3-1 and SLICE3-2 for each block based on the processing result of the slice SLICE3-1. In addition, in the third time period T13, the second core CORE1 may perform intra-loop filtering on the boundaries of the slices SLICE2-2 and SLICE2-3 for each block based on the processing result of the slice SLICE2-2. In the third time period T13, the second core CORE1 may perform intra-loop filtering on the boundaries of the slices SLICE2-3 and SLICE2-4 for each block based on the processing result of the slice SLICE2-3, and may be processed based on the slice SLICE2-4 As a result, the boundaries of the slices SLICE2-4 and SLICE2-5 are intra-loop filtered for each block.

亦即，在第三時間段T13中，第一CORE0可進行 兩個切片SLICE3-1及SLICE3-2的迴路內濾波，且第二核心CORE1可執行三個切片SLICE2-3至SLICE2-5的迴路內濾波，使得無額外時間用於迴路內濾波，例如，無用於收集在第一核心CORE0及第二核心CORE1上分散的切片的額外時間。 That is, in the third time period T13, the first CORE0 can be performed. In-loop filtering of two slices SLICE3-1 and SLICE3-2, and the second core CORE1 can perform in-loop filtering of three slices SLICE2-3 to SLICE2-5, so that no additional time is used for in-loop filtering, for example, useless The additional time for collecting the slices scattered on the first core CORE0 and the second core CORE1.

圖7為說明分別包括三個切片之圖像序列的概念圖。圖8為說明由三個核心處理展示於圖5中之圖像序列的程序的概念圖。 Fig. 7 is a conceptual diagram illustrating an image sequence including three slices, respectively. Figure 8 is a conceptual diagram illustrating a procedure for processing the sequence of images shown in Figure 5 by three cores.

展示於圖1中的控制器200A可包括可分別對應於第一核心CORE0、第二CORE1及第三核心CORE2之三個硬體編解碼器230-1、230-2及230-3。描述於圖2中之編碼器或/及解碼器可嵌入於核心CORE0、CORE1及CORE2中的每一者中。 The controller 200A shown in FIG. 1 may include three hardware codecs 230-1, 230-2, and 230-3 that may correspond to the first core CORE0, the second CORE1, and the third core CORE2, respectively. The encoder or/and decoder described in FIG. 2 can be embedded in each of the cores CORE0, CORE1, and CORE2.

如圖7中所展示，每一圖像630、632、634、636及638可分別包括三個切片。每一圖像630、632、634、636及638可包括第一處理單元、第二處理單元及第三處理單元。亦即，第一處理單元、第二處理單元及第三處理單元中的每一者可分別對應於三個切片中的一者。每一圖像630、632、634、636及638可為待編碼圖框、原始圖像、待編碼圖像之原始位元串流、待解碼圖框、經編碼圖像或經由接收器介面270接收的經編碼位元串流EB等。 As shown in Figure 7, each image 630, 632, 634, 636, and 638 can include three slices, respectively. Each image 630, 632, 634, 636, and 638 can include a first processing unit, a second processing unit, and a third processing unit. That is, each of the first processing unit, the second processing unit, and the third processing unit may correspond to one of the three slices, respectively. Each image 630, 632, 634, 636, and 638 can be a frame to be encoded, an original image, a raw bit stream of the image to be encoded, a frame to be decoded, an encoded image, or via a receiver interface 270 The received encoded bit stream EB and the like.

轉向圖8，在第一時間段T21中，第一核心CORE0可處理第一圖像630之第一切片SLICE1-1。 Turning to FIG. 8, in the first time period T21, the first core CORE0 can process the first slice SLICE1-1 of the first image 630.

在第二時間段T22中，第一核心CORE0可處理第 一圖像630之第二切片SLICE1-2，且第二核心CORE1可處理第二圖像632之第一切片SLICE2-1。第二切片SLICE1-2的處理及第一切片SLICE2-1的處理可在第二時間段T22中並行地進行。 In the second time period T22, the first core CORE0 can process the first A second slice SLICE1-2 of an image 630, and the second core CORE1 can process the first slice SLICE2-1 of the second image 632. The processing of the second slice SLICE1-2 and the processing of the first slice SLICE2-1 may be performed in parallel in the second time period T22.

在第二時間段T22中，第一核心CORE0可基於切片SLICE1-1之處理結果針對每一區塊對切片SLICE1-1及SLICE1-2的邊界進行迴路內濾波。 In the second time period T22, the first core CORE0 may perform intra-loop filtering on the boundaries of the slices SLICE1-1 and SLICE1-2 for each block based on the processing result of the slice SLICE1-1.

對於並行處理，一個(1)切片延遲可經指派至第二核心CORE1，且兩個(2)切片延遲可經指派至第三核心CORE2。 For parallel processing, one (1) slice delay may be assigned to the second core CORE1, and two (2) slice delays may be assigned to the third core CORE2.

在第三時間段T23中，第一核心CORE0可處理第一圖像630之第三切片SLICE1-3，第二核心CORE1可處理第二圖像632之第二切片SLICE2-2，且第三核心CORE2可處理第三圖像634之第一切片SLICE3-1。 In the third time period T23, the first core CORE0 can process the third slice SLICE1-3 of the first image 630, the second core CORE1 can process the second slice SLICE2-2 of the second image 632, and the third core CORE2 can process the first slice SLICE3-1 of the third image 634.

在第三時間段T23中，第三切片SLICE1-3的處理、第二切片SLICE2-2以及第一切片SLICE1-3的處理可在第三時間段T23中並行地進行。 In the third time period T23, the processing of the third slice SLICE1-3, the processing of the second slice SLICE2-2, and the first slice SLICE1-3 may be performed in parallel in the third time period T23.

在第三時間段T23中，第一核心CORE0可基於切片SLICE1-2之處理結果針對每一區塊對切片SLICE1-2及SLICE1-3的邊界進行迴路內濾波，且第二核心CORE1可基於切片SLICE2-1之處理結果針對每一區塊對切片SLICE2-1及SLICE2-2的邊界進行迴路內濾波。 In the third time period T23, the first core CORE0 may perform in-loop filtering on the boundaries of the slices SLICE1-2 and SLICE1-3 for each block based on the processing result of the slice SLICE1-2, and the second core CORE1 may be based on the slice The processing result of SLICE2-1 performs in-loop filtering on the boundaries of slices SLICE2-1 and SLICE2-2 for each block.

在第四時間段T24中，第一核心CORE0可處理第四圖像636之第一切片SLICE4-1，第二核心CORE1可處理第 二圖像632之第三切片SLICE2-3，且第三核心CORE2可處理第三圖像634之第二切片SLICE3-2。亦即，一旦第一核心CORE0結束了第一圖像630之切片的處理，在第四圖像636的狀況下，第一核心CORE0在圖像序列上先於下一圖像。 In the fourth time period T24, the first core CORE0 can process the first slice SLICE4-1 of the fourth image 636, and the second core CORE1 can process the first The third slice SLICE2-3 of the second image 632, and the third core CORE2 can process the second slice SLICE3-2 of the third image 634. That is, once the first core CORE0 ends the processing of the slice of the first image 630, in the case of the fourth image 636, the first core CORE0 precedes the next image on the image sequence.

在第四時間段T24中，第一切片SLICE4-1的處理、第三切片SLICE2-3的處理及第二切片SLICE3-2的處理可並行地進行。 In the fourth time period T24, the processing of the first slice SLICE4-1, the processing of the third slice SLICE2-3, and the processing of the second slice SLICE3-2 may be performed in parallel.

在第四時間段T24中，第二核心CORE1可基於切片SLICE2-2的處理結果針對每一區塊對切片SLICE2-2及SLICE2-3的邊界進行迴路內濾波，且第三核心CORE2可基於切片SLICE3-1的處理結果針對每一區塊對切片SLICE3-1及SLICE3-2的邊界進行迴路內濾波。 In the fourth time period T24, the second core CORE1 may perform in-loop filtering on the boundaries of the slices SLICE2-2 and SLICE2-3 for each block based on the processing result of the slice SLICE2-2, and the third core CORE2 may be based on the slice The processing result of SLICE3-1 performs in-loop filtering on the boundaries of slices SLICE3-1 and SLICE3-2 for each block.

在第五時間段T25中，核心CORE0、CORE1及CORE2中之每一核心的操作可繼續以類似於第一時間段T21至第四時間段T24中的操作的方式處理各別切片。 In the fifth time period T25, the operations of each of the cores CORE0, CORE1, and CORE2 may continue to process the respective slices in a manner similar to the operations in the first time period T21 to the fourth time period T24.

圖9為說明運動向量搜尋的概念圖。參看圖3、圖4及圖9，當當前處理切片為第三圖像614之第一切片614-1時，第一核心CORE0可搜尋經處理切片610-1、610-2及612-1以尋找最佳運動向量。舉例而言，隨著切片612-2及614-1中之每一者由不同核心CORE0及CORE1並行地處理，第一核心不可涉及第二圖像612的現正在處理的第二切片612-2。又，當切片612-1與612-2之間的邊緣可在處理切片614-1時在迴路內濾波操作下時切片614-1可不能夠涉及切片612-1之很少底部像素(在H264標準中，很少底部像素可為6個像 素)。 Figure 9 is a conceptual diagram illustrating motion vector search. Referring to FIGS. 3, 4, and 9, when the current slice is the first slice 614-1 of the third image 614, the first core CORE0 can search for the processed slices 610-1, 610-2, and 612-1. To find the best motion vector. For example, as each of slices 612-2 and 614-1 are processed in parallel by different cores CORE0 and CORE1, the first core may not be related to the second slice 612-2 of the second image 612 that is currently being processed. . Also, when the edge between slices 612-1 and 612-2 may be under the in-loop filtering operation while processing slice 614-1, slice 614-1 may not be able to relate to the few bottom pixels of slice 612-1 (in the H264 standard) Medium, very few bottom pixels can be 6 images Prime).

資料處理系統100A可編碼第三圖像614以藉由基於依賴性來判定匹配區塊(或參考區塊)的參考圖像及座標來避免或減小並行處理中切片SLICE2-2及SLICE3-1間的依賴性。舉例而言，當編碼第一切片614-1時，第一切片614-1中巨型區塊的運動向量可經判定以由使巨型區塊提及切片610-1、610-2及612-1中的一者而非第二切片612-2來避免依賴性，其中底部像素的某約束為由迴路內濾波操作進行處理。因此，並行處理上的依賴性可被減小。 The data processing system 100A can encode the third image 614 to avoid or reduce slices SLICE2-2 and SLICE3-1 in parallel processing by determining the reference image and coordinates of the matching block (or reference block) based on the dependency. Dependence. For example, when encoding the first slice 614-1, the motion vector of the megablock in the first slice 614-1 may be determined to cause the megablock to refer to the slices 610-1, 610-2, and 612. One of -1 is instead of the second slice 612-2 to avoid dependencies, where some constraint of the bottom pixel is handled by an in-loop filtering operation. Therefore, the dependency on parallel processing can be reduced.

資料處理系統100A可產生並提及運動約束切片群組以減小編碼切片時並行地處理的切片之間的依賴性。運動約束切片群組可包括限制參考圖像或由當前處理切片參考的先前圖像之參考區的資訊。運動約束切片群組可儲存於資料處理系統100A中的記憶體301、303或305，或核心230-1至230-N中每一者的記憶體中。 Data processing system 100A may generate and reference motion constrained slice groups to reduce the dependencies between slices processed in parallel when encoding slices. The motion constrained slice group may include information that limits the reference image or the reference region of the previous image referenced by the currently processed slice. The motion constrained slice group can be stored in memory 301, 303 or 305 in data processing system 100A, or in the memory of each of cores 230-1 through 230-N.

圖10為說明根據例示性實施例的圖像序列之概念圖，圖像中之每一者包括兩個影像塊。圖11為說明由兩個核心處理展示於圖10中的圖像序列之程序的概念圖。 FIG. 10 is a conceptual diagram illustrating a sequence of images, each of which includes two image blocks, in accordance with an illustrative embodiment. Figure 11 is a conceptual diagram illustrating a procedure for processing the sequence of images shown in Figure 10 by two cores.

展示於多個圖像640、642、644及646中之每一者中的箭頭說明處理方向或多個圖像640、642、644及646中多個影像塊的處理次序。 The arrows shown in each of the plurality of images 640, 642, 644, and 646 illustrate the processing order or the processing order of the plurality of image blocks in the plurality of images 640, 642, 644, and 646.

圖1中的控制器200A可包括兩個硬體編解碼器230-1及230-2。第一核心CORE0可為第一硬體編解碼器230-1，且第二核心CORE1可為第二硬體編解碼器230-2。 在一些例示性實施例中，圖像中的所有影像塊可由單一核心處理。 The controller 200A of FIG. 1 may include two hardware codecs 230-1 and 230-2. The first core CORE0 may be the first hardware codec 230-1, and the second core CORE1 may be the second hardware codec 230-2. In some exemplary embodiments, all of the image blocks in the image may be processed by a single core.

參看圖10，多個圖像640、642、644、646中之每一者可分別包括兩個影像塊TILE1-1及TILE1-2、TILE2-1及TILE2-2、TILE3-1及TILE3-2以及TILE4-1及TILE4-2。影像塊TILE1-1及TILE1-2、TILE2-1及TILE2-2、TILE3-1及TILE3-2以及TILE4-1及TILE4-2中的每一者可包括一或多個區塊。多個圖像640、642、644、646中之每一者可包括第一處理單元TILE1-1、TILE2-1、TILE3-1及TILE4-1，以及第二處理單元TILE2-1、TILE2-2、TILE3-2及TILE4-2。亦即，例如，圖像640之第一處理單元包括TILE1-1，且圖像640之第二處理單元包括TILE1-2。此處，多個圖像640、642、644、646中之每一者可為待編碼圖框、原始圖像、待編碼圖像之原始位元串流、待解碼圖框、經編碼圖像，或經由接收器介面270接收的經編碼位元串流EB等。 Referring to FIG. 10, each of the plurality of images 640, 642, 644, 646 may include two image blocks TILE1-1 and TILE1-2, TILE2-1 and TILE2-2, TILE3-1 and TILE3-2, respectively. And TILE4-1 and TILE4-2. Each of the image blocks TILE1-1 and TILE1-2, TILE2-1 and TILE2-2, TILE3-1 and TILE3-2, and TILE4-1 and TILE4-2 may include one or more blocks. Each of the plurality of images 640, 642, 644, 646 may include first processing units TILE1-1, TILE2-1, TILE3-1, and TILE4-1, and second processing units TILE2-1, TILE2-2 , TILE3-2 and TILE4-2. That is, for example, the first processing unit of image 640 includes TILE1-1, and the second processing unit of image 640 includes TILE1-2. Here, each of the plurality of images 640, 642, 644, 646 may be a frame to be encoded, an original image, an original bit stream of the image to be encoded, a frame to be decoded, and an encoded image. Or encoded bitstream EB, etc., received via receiver interface 270.

第一核心CORE0及第二核心CORE1的操作將參考圖1、圖2、圖10及圖11來描述。 The operations of the first core CORE0 and the second core CORE1 will be described with reference to FIGS. 1, 2, 10, and 11.

在第一時間段T31中，第一核心CORE0可處理第一圖像640之第一影像塊TILE1-1。對於並行處理，影像塊延遲可被指派至第二核心CORE1。 In the first time period T31, the first core CORE0 can process the first image block TILE1-1 of the first image 640. For parallel processing, the image block delay can be assigned to the second core CORE1.

在第二時間段T32中，第一核心CORE0可處理第一圖像640之第二影像塊TILE1-2，且第二核心CORE1可處理第二圖像642之第一影像塊TILE2-1。第一影像塊TILE2-1及第二影像塊TILE1-2的處理可在第二時間段T2中並行地 進行。如在上文所論述的狀況下，此處，「並行」表示，在第一影像塊TILE2-1及第二影像塊TILE1-2之處理中存在某重疊。亦即，雖然點線用於圖4、圖6、圖8、圖11、圖14中，但此等線僅出於易於描述而提供，且並不意欲表明用於處理之開始時間及結束時間準確地一致。舉例而言，圖11中的點線並非意欲表明，用於處理第一影像塊TILE2-1及第二影像塊TILE1-2的開始時間或結束時間準確地一致。然而，在一些例示性實施例中，開始時間可準確地一致，及/或結束時間可準確地一致。 In the second time period T32, the first core CORE0 can process the second image block TILE1-2 of the first image 640, and the second core CORE1 can process the first image block TILE2-1 of the second image 642. The processing of the first image block TILE2-1 and the second image block TILE1-2 may be performed in parallel in the second time period T2 get on. As in the case discussed above, "parallel" here means that there is some overlap in the processing of the first image block TILE2-1 and the second image block TILE1-2. That is, although the dotted lines are used in FIG. 4, FIG. 6, FIG. 8, FIG. 11, and FIG. 14, these lines are provided only for ease of description, and are not intended to indicate the start time and end time for processing. Accurate and consistent. For example, the dotted line in FIG. 11 is not intended to indicate that the start time or end time for processing the first image block TILE2-1 and the second image block TILE1-2 is exactly the same. However, in some exemplary embodiments, the start times may be exactly consistent, and/or the end times may be exactly consistent.

另外，在第二時間段T32中，第一核心CORE0可基於第一圖像640中的第一影像塊TILE1-1之處理結果針對每一區塊對影像塊TILE1-1及TILE1-2的邊界進行迴路內濾波。亦即，在第二時間段T32中，第一CORE0可進行第二影像塊TILE1-2的處理及影像塊TILE1-1及TILE1-2的迴路內濾波，使得無額外時間用於迴路內濾波。 In addition, in the second time period T32, the first core CORE0 may be based on the processing result of the first image block TILE1-1 in the first image 640 for the boundary of the image blocks TILE1-1 and TILE1-2 for each block. Perform in-loop filtering. That is, in the second time period T32, the first CORE0 can perform processing of the second image block TILE1-2 and intra-loop filtering of the image blocks TILE1-1 and TILE1-2, so that no additional time is used for intra-loop filtering.

在第三時間段T33中，第一核心CORE0可處理第三圖像644之第一影像塊TILE3-1，且第二核心CORE1可處理第二圖像642之第二影像塊TILE2-2。第一影像塊TILE3-1及第二切片TILE2-2的處理可在第三時間段T33中並行地進行。 In the third time period T33, the first core CORE0 can process the first image block TILE3-1 of the third image 644, and the second core CORE1 can process the second image block TILE2-2 of the second image 642. The processing of the first image block TILE3-1 and the second slice TILE2-2 can be performed in parallel in the third time period T33.

此外，在第三時間段T33中，第二核心CORE1可基於第二圖像642中之第一影像塊TILE2-1的處理結果針對每一區塊對影像塊TILE2-1及TILE2-2的邊界進行迴路內濾波。亦即，在第三時間段T33中，第二CORE1可進行第二影 像塊TILE2-2的處理及影像塊TILE2-1及TILE2-2的迴路內濾波，使得無額外時間用於迴路內濾波。 In addition, in the third time period T33, the second core CORE1 may be based on the processing result of the first image block TILE2-1 in the second image 642 for the boundary of the image blocks TILE2-1 and TILE2-2 for each block. Perform in-loop filtering. That is, in the third time period T33, the second CORE1 can perform the second shadow The processing of block TILE2-2 and the in-loop filtering of image blocks TILE2-1 and TILE2-2 allow no additional time for intra-loop filtering.

在第四時間段T34中，核心CORE0及CORE1中之每一核心可以與第三時間段T33中的操作類似的方式來繼續處理各別影像塊。 In the fourth time period T34, each of the cores CORE0 and CORE1 may continue to process the respective image blocks in a manner similar to the operation in the third time period T33.

圖12為說明圖像序列的概念圖，圖像中的每一者分別包括使用水平分割而分割的兩個影像塊。 Figure 12 is a conceptual diagram illustrating an image sequence, each of the images including two image blocks segmented using horizontal segmentation.

展示於多個圖像650、652、654及656中每一者中的箭頭說明多個圖像650、652、654及656中多個影像塊之處理方向或處理次序。 The arrows displayed in each of the plurality of images 650, 652, 654, and 656 illustrate the processing direction or processing order of the plurality of image blocks in the plurality of images 650, 652, 654, and 656.

圖1中之控制器200A可包括兩個硬體編解碼器230-1及230-2。第一核心CORE0可為第一硬體編解碼器230-1，且第二核心CORE1可為第二硬體編解碼器230-2。第一核心CORE0及第二核心CORE1的操作將參看圖1、圖2、圖11及圖12描述。 The controller 200A of FIG. 1 may include two hardware codecs 230-1 and 230-2. The first core CORE0 may be the first hardware codec 230-1, and the second core CORE1 may be the second hardware codec 230-2. The operation of the first core CORE0 and the second core CORE1 will be described with reference to FIGS. 1, 2, 11, and 12.

參看圖12，多個圖像650、652、654、656中的每一者可分別包括兩個影像塊TILE1-1及TILE1-2、TILE2-1及TILE2-2、TILE3-1及TILE3-2以及TILE4-1及TILE4-2。影像塊TILE1-1及TILE1-2、TILE2-1及TILE2-2、TILE3-1及TILE3-2以及TILE4-1及TILE4-2中的每一者可包括一或多個區塊。多個圖像650、652、654、656中之每一者可分別包括第一處理單元TILE1-1、TILE2-1、TILE3-1及TILE4-1，且分別包括第二處理單元TILE2-1、TILE2-2、TILE3-2及TILE4-2。此處，多個圖像650、652、654、656中的每一者 可為待編碼圖框、原始圖像、待編碼圖像的原始位元串流、待解碼圖框、經編碼圖像，或經由接收器介面270接收的經編碼位元串流EB等。 Referring to FIG. 12, each of the plurality of images 650, 652, 654, 656 may include two image blocks TILE1-1 and TILE1-2, TILE2-1 and TILE2-2, TILE3-1 and TILE3-2, respectively. And TILE4-1 and TILE4-2. Each of the image blocks TILE1-1 and TILE1-2, TILE2-1 and TILE2-2, TILE3-1 and TILE3-2, and TILE4-1 and TILE4-2 may include one or more blocks. Each of the plurality of images 650, 652, 654, 656 may include first processing units TILE1-1, TILE2-1, TILE3-1, and TILE4-1, respectively, and respectively include a second processing unit TILE2-1, TILE2-2, TILE3-2 and TILE4-2. Here, each of the plurality of images 650, 652, 654, 656 This may be the frame to be encoded, the original image, the original bit stream of the image to be encoded, the frame to be decoded, the encoded image, or the encoded bit stream EB received via the receiver interface 270, and the like.

在第一時間段T31中，第一核心CORE0可處理第一圖像650之第一影像塊TILE1-1。對於並行處理，影像塊延遲可被指派至第二核心CORE1。 In the first time period T31, the first core CORE0 can process the first image block TILE1-1 of the first image 650. For parallel processing, the image block delay can be assigned to the second core CORE1.

在第二時間段T32中，第一核心CORE0可處理第一圖像650之第二影像塊TILE1-2，且第二核心CORE1可處理第二圖像652之第一影像塊TILE2-1。第一影像塊TILE2-1及第二影像塊TILE1-2之處理可在第二時間段T32中並行地進行。 In the second time period T32, the first core CORE0 can process the second image block TILE1-2 of the first image 650, and the second core CORE1 can process the first image block TILE2-1 of the second image 652. The processing of the first image block TILE2-1 and the second image block TILE1-2 may be performed in parallel in the second time period T32.

另外，在第二時間段T32中，第一核心CORE0可基於第一圖像650中之第一影像塊TILE1-1的處理結果針對每一區塊對影像塊TILE1-1及TILE1-2的邊界進行迴路內濾波。亦即，在第二時間段T32中，第一CORE0可進行第二影像塊TILE1-2的處理及影像塊TILE1-1及TILE1-2的迴路內濾波，使得無額外時間用於迴路內濾波。 In addition, in the second time period T32, the first core CORE0 may be based on the processing result of the first image block TILE1-1 in the first image 650 for the boundary of the image blocks TILE1-1 and TILE1-2 for each block. Perform in-loop filtering. That is, in the second time period T32, the first CORE0 can perform processing of the second image block TILE1-2 and intra-loop filtering of the image blocks TILE1-1 and TILE1-2, so that no additional time is used for intra-loop filtering.

在第三時間段T33中，第一核心CORE0可處理第三圖像654之第一影像塊TILE3-1，且第二核心CORE1可處理第二圖像652之第二影像塊TILE2-2。第一影像塊TILE3-1及第二切片TILE2-2的處理可在第三時間段T33中並行地進行。 In the third time period T33, the first core CORE0 can process the first image block TILE3-1 of the third image 654, and the second core CORE1 can process the second image block TILE2-2 of the second image 652. The processing of the first image block TILE3-1 and the second slice TILE2-2 can be performed in parallel in the third time period T33.

此外，在第三時間段T33中，第二核心CORE1可基於第二圖像652中之第一影像塊TILE2-1的處理結果針對 每一區塊對影像塊TILES2-1及TILE2-2的邊界進行迴路內濾波。亦即，在第三時間段T33中，第二CORE1可進行第二影像塊TILE2-2的處理及影像塊TILE2-1及TILE2-2之迴路內濾波，使得無額外時間用於迴路內濾波。 In addition, in the third time period T33, the second core CORE1 may be targeted based on the processing result of the first image block TILE2-1 in the second image 652. Each block performs in-loop filtering on the boundaries of the image blocks TILES2-1 and TILE2-2. That is, in the third time period T33, the second CORE1 can perform processing of the second image block TILE2-2 and intra-loop filtering of the image blocks TILE2-1 and TILE2-2, so that no additional time is used for intra-loop filtering.

在第四時間段T34中，核心CORE0及CORE1中之每一核心可以與第三時間段T33中的操作類似的方式來繼續處理各別影像塊。 In the fourth time period T34, each of the cores CORE0 and CORE1 may continue to process the respective image blocks in a manner similar to the operation in the third time period T33.

圖13為說明圖像序列的概念圖，圖像中的每一者包括分別具有水平分區及垂直分區兩者的四個影像塊。圖14為說明由兩個核心處理展示於圖13中的圖像序列之程序的概念圖。 Figure 13 is a conceptual diagram illustrating an image sequence, each of the images including four image blocks having both horizontal and vertical partitions. Figure 14 is a conceptual diagram illustrating a procedure for processing the sequence of images shown in Figure 13 by two cores.

展示於多個圖像660、662及664中之每一者中的箭頭說明多個圖像660、662及664中多個影像塊之處理方向或處理次序。 The arrows displayed in each of the plurality of images 660, 662, and 664 illustrate the processing direction or processing order of the plurality of image blocks in the plurality of images 660, 662, and 664.

圖1中之控制器200A可包括兩個硬體編解碼器230-1及230-2。第一核心CORE0可為第一硬體編解碼器230-1，且第二核心CORE1可為第二硬體編解碼器230-2。在一些例示性實施例中，圖像中之所有影像塊可由單一核心處理。第一核心CORE0及第二核心CORE1之操作將參考圖1、圖2、圖13及圖14來描述。 The controller 200A of FIG. 1 may include two hardware codecs 230-1 and 230-2. The first core CORE0 may be the first hardware codec 230-1, and the second core CORE1 may be the second hardware codec 230-2. In some exemplary embodiments, all of the image blocks in the image may be processed by a single core. The operations of the first core CORE0 and the second core CORE1 will be described with reference to FIGS. 1, 2, 13, and 14.

參看圖13，多個圖像660、662及664中之每一者可分別包括四個影像塊TILE1-1至TILE1-4、TILE2-1至TILE2-4以及TILE3-1至TILE3-4。影像塊TILE1-1至TILE1-4、TILE2-1至TILE2-4以及TILE3-1至TILE3-4中的每一者可包 括一或多個區塊。多個圖像660、662及664中之每一者可包括分別具有兩個影像塊TILE1-1及TILE1-2、TILE2-1及TILE2-2以及TILE3-1及TILE3-2的第一處理單元，及分別具有兩個影像塊TILE1-3及ILE1-4、TILE2-3及TILE2-4以及TILE3-3及TILE3-4的第二處理單元。此處，多個圖像660、662及664中的每一者可為待編碼圖框、原始圖像、待編碼圖像的原始位元串流、待解碼圖框、經編碼圖像，或經由接收器介面270接收的經編碼位元串流EB等。 Referring to FIG. 13, each of the plurality of images 660, 662, and 664 may include four image blocks TILE1-1 through TILE1-4, TILE2-1 through TILE2-4, and TILE3-1 through TILE3-4, respectively. Each of the image blocks TILE1-1 to TILE1-4, TILE2-1 to TILE2-4, and TILE3-1 to TILE3-4 may be packaged Includes one or more blocks. Each of the plurality of images 660, 662, and 664 may include a first processing unit having two image blocks TILE1-1 and TILE1-2, TILE2-1 and TILE2-2, and TILE3-1 and TILE3-2, respectively. And a second processing unit having two image blocks TILE1-3 and ILE1-4, TILE2-3 and TILE2-4, and TILE3-3 and TILE3-4, respectively. Here, each of the plurality of images 660, 662, and 664 may be a frame to be encoded, an original image, an original bit stream of the image to be encoded, a frame to be decoded, an encoded image, or The encoded bit stream EB, etc., received via the receiver interface 270.

在第一時間段T51中，第一核心CORE0可基於第一影像塊TILE1-1之處理結果針對每一區塊來處理第一圖像660之第一影像塊TILE1-1及第二影像塊TILE1-2且對第一圖像660的影像塊TILE1-1及TILE1-2之邊界進行迴路內濾波。對於並行處理，兩個影像塊延遲可被指派至第二核心CORE1。 In the first time period T51, the first core CORE0 can process the first image block TILE1-1 and the second image block TILE1 of the first image 660 for each block based on the processing result of the first image block TILE1-1. -2 and performing in-loop filtering on the boundaries of the image blocks TILE1-1 and TILE1-2 of the first image 660. For parallel processing, two image block delays can be assigned to the second core CORE1.

在第二時間段T52中，第一核心CORE0可處理第一圖像660之第三影像塊TILE1-3及第四影像塊TILE1-4，且第二核心CORE1可處理第二圖像662之第一影像塊TILE2-1及第二影像塊TILE2-2。第三影像塊TILE1-3及第四影像塊TILE1-4的處理以及第一影像塊TILE2-1及第二影像塊TILE2-2的處理可在第二時間段T52中並行地進行。如在上文所論述的狀況下，此處，「並行」表示在影像塊的處理中存在某重疊。亦即，雖然點線用於圖4、圖6、圖8、圖11、圖14中，但此等線僅出於易於描述而提供，且並不意欲表明用於處理之開始時間及結束時間準確地一致。然而，在 一些例示性實施例中，開始時間可準確地一致，及/或結束時間可準確地一致。 In the second time period T52, the first core CORE0 can process the third image block TILE1-3 and the fourth image block TILE1-4 of the first image 660, and the second core CORE1 can process the second image 662. An image block TILE2-1 and a second image block TILE2-2. The processing of the third image block TILE1-3 and the fourth image block TILE1-4 and the processing of the first image block TILE2-1 and the second image block TILE2-2 may be performed in parallel in the second time period T52. As in the case discussed above, "parallel" herein means that there is some overlap in the processing of the image block. That is, although the dotted lines are used in FIG. 4, FIG. 6, FIG. 8, FIG. 11, and FIG. 14, these lines are provided only for ease of description, and are not intended to indicate the start time and end time for processing. Accurate and consistent. However, in In some exemplary embodiments, the start times may be exactly consistent, and/or the end times may be exactly consistent.

另外，在第二時間段T52中，第一核心CORE0可基於第一圖像660中的第一影像塊TILE1-1之處理結果針對每一區塊對影像塊TILE1-1及TILE1-3的邊界進行迴路內濾波。 In addition, in the second time period T52, the first core CORE0 may be based on the processing result of the first image block TILE1-1 in the first image 660 for the boundary of the image blocks TILE1-1 and TILE1-3 for each block. Perform in-loop filtering.

此外，在第二時間段T52中，第一核心CORE0可基於第一圖像660中的第一影像塊TILE1-2之處理結果針對每一區塊對影像塊TILE1-2及TILE1-4的邊界進行迴路內濾波。 In addition, in the second time period T52, the first core CORE0 may be based on the processing result of the first image block TILE1-2 in the first image 660 for the boundary of the image blocks TILE1-2 and TILE1-4 for each block. Perform in-loop filtering.

在第二時間段T52中，第一核心CORE0可基於第一圖像660中之第一影像塊TILE1-3之處理結果針對每一區塊對影像塊TILE1-3及TILE1-4的邊界進行迴路內濾波。 In the second time period T52, the first core CORE0 may loop the boundaries of the image blocks TILE1-3 and TILE1-4 for each block based on the processing result of the first image block TILE1-3 in the first image 660. Internal filtering.

在第二時間段T52中，第二核心CORE1可基於第一影像塊TILE2-1之處理結果針對每一區塊對第二圖像662之TILE2-1及TILE2-2之邊界進行迴路內濾波。 In the second time period T52, the second core CORE1 may perform intra-loop filtering on the boundary of the TILE2-1 and TILE2-2 of the second image 662 for each block based on the processing result of the first image block TILE2-1.

亦即，對經處理影像塊之邊界的迴路內濾波在第二時段T52中進行，使得無額外時間用於迴路內濾波。 That is, the in-loop filtering of the boundary of the processed image block is performed in the second time period T52, so that no additional time is available for in-loop filtering.

在第三時間段T53中，核心CORE0及CORE1可以與第二時間段T52中的操作類似之方式來繼續處理各別影像塊。 In the third time period T53, the cores CORE0 and CORE1 may continue to process the respective image blocks in a manner similar to the operation in the second time period T52.

圖15為說明展示於圖1中之硬體編解碼器的方塊圖。 Figure 15 is a block diagram showing the hardware codec shown in Figure 1.

參看圖1及圖15，硬體編解碼器230-1可包括選擇 電路701、編碼器700、解碼器800及記憶體MEM1。 Referring to Figures 1 and 15, the hardware codec 230-1 may include a selection. The circuit 701, the encoder 700, the decoder 800, and the memory MEM1.

當選擇信號SEL具有第一位準(例如，低位準)時，選擇電路701可回應於選擇信號SEL輸出影像資料或視訊資料INV至編碼器700。當選擇信號SEL具有第二位準(例如，高位準)時，選擇電路701可回應於選擇信號SEL輸出經編碼位元串流EBS至解碼器800。 When the selection signal SEL has a first level (eg, a low level), the selection circuit 701 can output the image data or the video material INV to the encoder 700 in response to the selection signal SEL. When the select signal SEL has a second level (eg, a high level), the selection circuit 701 can output the encoded bit stream EBS to the decoder 800 in response to the select signal SEL.

選擇信號SEL可由CPU210A提供。影像資料或視訊資料INV可經由攝影機介面250提供，且經編碼位元串流EB可經由接收器介面270或記憶體介面240來提供。 The selection signal SEL can be provided by the CPU 210A. The image material or video material INV may be provided via the camera interface 250, and the encoded bit stream EB may be provided via the receiver interface 270 or the memory interface 240.

編碼器700可編碼來自選擇電路701之所輸出影像資料或輸出的視訊資料INV，且由經編碼位元串流輸出經編碼影像資料或經編碼視訊資料至解碼器800。 The encoder 700 can encode the video data INV from the output image data or output of the selection circuit 701, and output the encoded video data or the encoded video data to the decoder 800 by the encoded bit stream.

解碼器800可解碼自選擇電路701輸出的經編碼位元串流EBS或自編碼器700輸出的經編碼位元串流，且產生經重建構影像資料或經重建構視訊資料RV。經重建構影像資料或經重建構視訊資料RV可經由顯示介面260顯示於顯示器40上。 The decoder 800 may decode the encoded bit stream EBS output from the selection circuit 701 or the encoded bit stream output from the encoder 700, and generate reconstructed image data or reconstructed video data RV. The reconstructed image data or reconstructed video data RV can be displayed on display 40 via display interface 260.

在一些例示性實施例中，編碼器700或解碼器800可將經重建構影像資料或經重建構視訊資料RV儲存於記憶體MEM1中。編碼器700或解碼器800可進行記憶體MEM1中所儲存的經重建影像資料或所儲存的經重建構視訊資料的迴路內濾波。 In some exemplary embodiments, encoder 700 or decoder 800 may store reconstructed image data or reconstructed video data RV in memory MEM1. The encoder 700 or the decoder 800 can perform in-loop filtering of the reconstructed image data stored in the memory MEM1 or the stored reconstructed video material.

在一些例示性實施例中，編碼器700及解碼器800中之每一者可包括根據H.264視訊寫碼標準或HEVC視訊寫 碼標準或支援迴路內解塊濾波器的任何其他標準界定的迴路內濾波。 In some exemplary embodiments, each of encoder 700 and decoder 800 may include writing according to H.264 video writing standard or HEVC video. Intra-loop filtering as defined by the code standard or any other standard that supports deblocking filters within the loop.

圖16為展示於圖15中之編碼器的方塊圖。 Figure 16 is a block diagram of the encoder shown in Figure 15.

參看圖15及圖16，編碼器700可包括預測器710、減法器720、變換器730、量化器740、熵編碼器750、反量化器760、反變換器770、加法器780及迴路內濾波器790。 15 and 16, the encoder 700 can include a predictor 710, a subtractor 720, a converter 730, a quantizer 740, an entropy encoder 750, an inverse quantizer 760, an inverse transformer 770, an adder 780, and in-loop filtering. 790.

預測器710可包括運動估計器712及運動補償器714。預測器710可預測當前區塊，產生預測區塊並輸出所預測區塊。詳言之，預測器710可預測當前區塊中每一像素的像素值，且產生包括每一像素之所預測像素值的所預測區塊。當進行框間預測時，預測器710可包括運動估計器712及運動補償器714。運動估計器712可被稱作運動向量估計器。 The predictor 710 can include a motion estimator 712 and a motion compensator 714. The predictor 710 can predict the current block, generate a predicted block, and output the predicted block. In particular, predictor 710 can predict the pixel value of each pixel in the current block and generate a predicted block that includes the predicted pixel value for each pixel. The predictor 710 can include a motion estimator 712 and a motion compensator 714 when inter-frame prediction is performed. Motion estimator 712 may be referred to as a motion vector estimator.

運動估計器712或運動向量估計器712可藉由對應於當前區塊之區塊模式或預定義區塊模式的區塊基於至少一參考圖像估計當前區塊的運動向量，且判定當前區塊的運動向量。區塊大小可為16×16、16×8、8×16、8×8、8×4、4×8或4×4。 The motion estimator 712 or the motion vector estimator 712 may estimate the motion vector of the current block based on the at least one reference image by the block corresponding to the block mode of the current block or the predefined block mode, and determine the current block. Motion vector. The block size may be 16x16, 16x8, 8x16, 8x8, 8x4, 4x8 or 4x4.

運動補償器714可基於自運動估計器712輸出的當前區塊之運動估計向量而產生所預測區塊，且輸出所預測區塊。亦即，運動補償器714可輸出由當前區塊定址之參考圖像中的區塊作為所預測區塊。 Motion compensator 714 may generate the predicted block based on the motion estimation vector of the current block output from motion estimator 712 and output the predicted block. That is, motion compensator 714 can output the block in the reference image addressed by the current block as the predicted block.

減法器720可自具有視訊資料INV的當前區塊減去所預測區塊，且產生殘餘區塊。減法器720可計算當前區 塊之每一像素與所預測區塊之每一像素之間的差異，且產生包括殘餘信號的殘餘區塊。 Subtractor 720 may subtract the predicted block from the current block with video material INV and generate a residual block. Subtractor 720 can calculate the current zone The difference between each pixel of the block and each pixel of the predicted block, and a residual block including the residual signal is generated.

變換器730可將殘餘信號自時域變換至頻域，且量化器740可量化變換器730之輸出，且輸出經量化殘餘區塊。變換器730可將離散餘弦變換DCT用於將殘餘信號變換至頻域。經變換至頻域的殘餘信號可為變換係數。 Transformer 730 can transform the residual signal from the time domain to the frequency domain, and quantizer 740 can quantize the output of converter 730 and output the quantized residual block. Transformer 730 can use discrete cosine transform DCT to transform the residual signal to the frequency domain. The residual signal transformed into the frequency domain may be a transform coefficient.

熵編碼器750可編碼自量化器740輸出的經量化殘餘區塊，且輸出經編碼位元串流。 Entropy coder 750 may encode the quantized residual block output from quantizer 740 and output an encoded bit stream.

反變換器770可執行反量化殘餘區塊的反變換，且產生經重建構殘餘區塊。 The inverse transformer 770 can perform an inverse transform of the inverse quantized residual block and generate a reconstructed residual block.

加法器780可相加來自預測器710之所預測區塊與自反變換器770輸出的經重建構殘餘區塊，並重建構當前區塊。 The adder 780 can add the reconstructed residual block output from the predicted block of the predictor 710 and the auto-invert converter 770, and reconstruct the current block.

迴路內濾波器790可進行經重建構當前區塊的迴路內濾波，且將經濾波當前區塊輸出至預測器710。 The in-loop filter 790 can perform in-loop filtering of the reconstructed current block and output the filtered current block to the predictor 710.

圖17為圖15中展示之解碼器的方塊圖。 Figure 17 is a block diagram of the decoder shown in Figure 15.

參看圖15至圖17，解碼器800可包括熵解碼器810、反量化器820、反變換器830、加法器850及迴路內濾波器860。 Referring to FIGS. 15-17, the decoder 800 can include an entropy decoder 810, an inverse quantizer 820, an inverse transformer 830, an adder 850, and an in-loop filter 860.

熵解碼器810可解碼所接收編碼位元串流EBS或自編碼器700輸出的經編碼位元串流，且產生經量化殘餘區塊。 The entropy decoder 810 can decode the received encoded bitstream EBS or the encoded bitstream output from the encoder 700 and produce quantized residual blocks.

反量化器820可進行對自熵解碼器810輸出的經量化殘餘區塊的反量化，並產生反量化殘餘區塊。 The inverse quantizer 820 can perform inverse quantization on the quantized residual block output from the entropy decoder 810 and generate an inverse quantized residual block.

反變換830可進行反量化殘餘區塊的反變換，且產生經重建殘餘區塊。 Inverse transform 830 may perform an inverse transform of the inverse quantized residual block and generate a reconstructed residual block.

運動補償器840可基於包括於自迴路內濾波器860輸出的經重建區塊中之運動向量而預測當前區塊，且輸出經預測區塊。 Motion compensator 840 may predict the current block based on the motion vectors included in the reconstructed block output from in-loop filter 860 and output the predicted block.

加法器850可藉由相加自迴路內濾波器860輸出的經重建殘餘區塊與自運動補償器840輸出的經預測區塊而重建當前區塊，且輸出經重建當前區塊。 The adder 850 can reconstruct the current block by adding the reconstructed residual block output from the in-loop filter 860 and the predicted block output from the motion compensator 840, and output the reconstructed current block.

迴路內濾波器可進行經重建當前區塊之迴路內濾波，且輸出經重建當前區塊RV。亦即，迴路內濾波器可由區塊輸出經重建視訊資料RV。 The in-loop filter performs intra-loop filtering of the reconstructed current block, and the output reconstructs the current block RV. That is, the in-loop filter can output the reconstructed video data RV from the block.

在一些例示性實施例中，迴路內濾波器790及860可各自包括解塊濾波器及樣本適應性偏移(SAO)濾波器。 In some demonstrative embodiments, in-loop filters 790 and 860 may each include a deblocking filter and a sample adaptive offset (SAO) filter.

圖18為說明根據例示性實施例之資料處理系統的方塊圖。 FIG. 18 is a block diagram illustrating a data processing system in accordance with an exemplary embodiment.

參看圖18，資料處理系統100B可包括控制器200B、多個記憶體301、303及305，以及顯示器400。在一些例示性實施例中，資料處理系統100B可進一步包括攝影機500。 Referring to FIG. 18, the data processing system 100B can include a controller 200B, a plurality of memories 301, 303, and 305, and a display 400. In some demonstrative embodiments, data processing system 100B may further include a camera 500.

控制器200B可以積體電路(IC)、系統單晶片(SoC)、應用處理機(AP)及/或行動AP等來體現。 The controller 200B can be embodied by an integrated circuit (IC), a system single chip (SoC), an application processor (AP), and/or a mobile AP.

控制器200B可包括CPU 210A、GPU 220、多個硬體編解碼器230、記憶體介面(I/F)240、顯示介面(I/F)260及接收器介面(I/F)270。當資料處理系統100A進一步包括攝 影機500時，控制器200A可進一步包括攝影機介面(I/F)250。 The controller 200B may include a CPU 210A, a GPU 220, a plurality of hardware codecs 230, a memory interface (I/F) 240, a display interface (I/F) 260, and a receiver interface (I/F) 270. When the data processing system 100A further includes taking At the time of the camera 500, the controller 200A may further include a camera interface (I/F) 250.

展示於圖18中之控制器200B鑒於結構及操作等於或類似於展示於圖1中的控制器200A，除包括於硬體編解碼器中之多個編解碼器231-1至231-N以外。 The controller 200B shown in FIG. 18 has a structure and operation equal to or similar to the controller 200A shown in FIG. 1, except for a plurality of codecs 231-1 to 231-N included in the hardware codec. .

多個編解碼器231-1至231-N中之每一者的操作可等於或類似於圖1中多個硬體編解碼器230-1至230-N中之每一者的操作。另外，多個編解碼器231-1至231-N中之每一者可具有對應於記憶體MEM1至MEMN中之每一者的記憶體。 The operation of each of the plurality of codecs 231-1 through 231-N may be equal to or similar to the operation of each of the plurality of hardware codecs 230-1 through 230-N of FIG. In addition, each of the plurality of codecs 231-1 to 231-N may have a memory corresponding to each of the memories MEM1 to MEMN.

多個編解碼器231-1至231-N中之每一者可包括參看圖15至圖17描述的組件701、700及800。描述於圖4至圖14中的第一核心CORE0、第二核心CORE1及第三核心CORE2可分別對應於第一核心231-1、第二核心231-2及第三核心231-3。 Each of the plurality of codecs 231-1 through 231-N may include the components 701, 700, and 800 described with reference to FIGS. 15 through 17. The first core CORE0, the second core CORE1, and the third core CORE2 described in FIGS. 4 to 14 may correspond to the first core 231-1, the second core 231-2, and the third core 231-3, respectively.

圖19為說明根據例示性實施例之資料處理系統的方塊圖。 19 is a block diagram illustrating a data processing system in accordance with an illustrative embodiment.

參看圖19，資料處理系統100C可包括控制器200C、多個記憶體301、303及305，以及顯示器400。在一些例示性實施例中，資料處理系統100C可進一步包括攝影機500。 Referring to FIG. 19, the data processing system 100C can include a controller 200C, a plurality of memories 301, 303, and 305, and a display 400. In some demonstrative embodiments, data processing system 100C may further include a camera 500.

控制器200C可以積體電路(IC)、系統單晶片(SoC)、應用處理機(AP)及/或行動AP等來體現。 The controller 200C can be embodied by an integrated circuit (IC), a system single chip (SoC), an application processor (AP), and/or a mobile AP.

控制器200C可包括CPU 210B、GPU 220、多個 硬體編解碼器230、記憶體介面(I/F)240、顯示介面(I/F)260及接收器介面(I/F)270。當資料處理系統100C進一步包括攝影機500時，控制器200C可進一步包括攝影機介面(I/F)250。 The controller 200C may include a CPU 210B, a GPU 220, and a plurality of A hardware codec 230, a memory interface (I/F) 240, a display interface (I/F) 260, and a receiver interface (I/F) 270. When the data processing system 100C further includes the camera 500, the controller 200C may further include a camera interface (I/F) 250.

展示於圖18中之控制器200C鑒於結構及操作等於或類似於展示於圖1中的控制器200A，除CPU 210B包括多個核心CORE1至COREN以外。 The controller 200C shown in FIG. 18 has a structure and operation equal to or similar to the controller 200A shown in FIG. 1, except that the CPU 210B includes a plurality of cores CORE1 to COREN.

多個核心CORE1至COREN中之每一者的操作可等於或類似於圖1中多個硬體編解碼器230-1至230-N中之每一者的操作。另外，多個編解碼器231-1至231-N中之每一者可具有對應於記憶體MEM1至MEMN中之每一者的記憶體(例如，快取記憶體)。 The operation of each of the plurality of cores CORE1 through COREN may be equal to or similar to the operation of each of the plurality of hardware codecs 230-1 through 230-N of FIG. In addition, each of the plurality of codecs 231-1 to 231-N may have a memory (for example, a cache memory) corresponding to each of the memories MEM1 to MEMN.

多個核心CORE1至COREN中之每一者可執行軟體編解碼器。當N為3時，描述於圖4至圖14中的第一核心CORE0、第二核心CORE1及第三核心CORE2可分別對應於圖19中之第一核心CORE1、第二核心CORE2及第三核心CORE2。 Each of the plurality of cores CORE1 through COREN may execute a software codec. When N is 3, the first core CORE0, the second core CORE1, and the third core CORE2 described in FIG. 4 to FIG. 14 may correspond to the first core CORE1, the second core CORE2, and the third core in FIG. 19, respectively. CORE2.

由核心CORE1至COREN中之每一者執行的軟體編解碼器可進行編碼、解碼、包括迴路內濾波之編碼或包括參看圖4至圖14之迴路內濾波的解碼。 The software codec executed by each of the cores CORE1 through COREN may be encoded, decoded, encoded including intra-loop filtering, or decoded including in-loop filtering with reference to Figures 4-14.

圖20為說明根據例示性實施例的由展示於圖1、圖18及圖19中的資料處理系統處理視訊資料的方法之流程圖。處理方法可為(例如)編碼或解碼。 20 is a flow diagram illustrating a method of processing video material by the data processing systems shown in FIGS. 1, 18, and 19, in accordance with an illustrative embodiment. The processing method can be, for example, encoding or decoding.

參看圖1至圖20，在操作S100中，每一圖像被指 派至核心。舉例而言，視訊資料中之第一圖像、第二圖像及第三圖像中的每一者可被指派有用於處理視訊資料的第一核心及第二核心中之一者。第一圖像、第二圖像及第三圖像中之每一者可分別包括第一切片(或第一影像塊)及第二切片(或第二影像塊)。 Referring to FIG. 1 to FIG. 20, in operation S100, each image is referred to Send to the core. For example, each of the first image, the second image, and the third image in the video material can be assigned one of a first core and a second core for processing video material. Each of the first image, the second image, and the third image may include a first slice (or first image block) and a second slice (or second image block), respectively.

在操作S110中，第一圖像中之第一切片(或第一影像塊)可由第一核心處理。在操作S120中，第二圖像中之第一切片(或第一影像塊)可在第一圖像之第二切片(或第二影像塊)由第一核心處理的同時由第二核心並行地處理。在操作S120中，第一核心可基於第一圖像之第一切片的處理結果進一步進行第一圖像之第一切片及第二切片的迴路內濾波。在操作S130中，第三圖像中之第一切片(或第一影像塊)可在第二圖像之第二切片(或第二影像塊)由第二核心處理的同時由第三核心並行地處理。在操作S130中，第二核心可基於第二圖像之第一切片的處理結果進一步進行第二圖像之第一切片及第二切片的迴路內濾波。 In operation S110, the first slice (or the first image block) in the first image may be processed by the first core. In operation S120, the first slice (or the first image block) in the second image may be processed by the first core while the second slice (or the second image block) of the first image is processed by the second core Processed in parallel. In operation S120, the first core may further perform intra-loop filtering of the first slice and the second slice of the first image based on the processing result of the first slice of the first image. In operation S130, the first slice (or the first image block) in the third image may be processed by the third core while the second slice (or the second image block) of the second image is processed by the second core Processed in parallel. In operation S130, the second core may further perform intra-loop filtering of the first slice and the second slice of the second image based on the processing result of the first slice of the second image.

如上文所描述，描述於圖1至圖14以及圖18至圖20中之解碼視訊資料的方法可藉由將多個圖像中之每一者指派至多個核心中之每一者並由多個核心並行地處理多個圖像而類似地用於編碼視訊資料的方法。 As described above, the method of decoding video material described in FIGS. 1 through 14 and FIGS. 18 through 20 can be performed by assigning each of a plurality of images to each of a plurality of cores The cores process multiple images in parallel and are similarly used to encode video material.

儘管已參考本發明概念的例示性實施例描述了本發明概念，但一般熟習此項技術者應理解，可在不脫離如藉由以下申請專利範圍界定的本發明概念之精神及範疇的情況下，進行形式及細節的各種改變。 Although the present invention has been described with reference to the exemplary embodiments of the present invention, it will be understood by those skilled in the art that, without departing from the spirit and scope of the inventive concept as defined by the following claims , making various changes in form and detail.

610、612、614、616‧‧‧圖像 610, 612, 614, 616‧‧ images

610-1、612-1、614-1、616-1‧‧‧第一切片/第一處理單元 610-1, 612-1, 614-1, 616-1‧‧‧ first slice/first processing unit

610-2、612-2、614-2、616-2‧‧‧第二切片/第二處理單元 610-2, 612-2, 614-2, 616-2‧‧‧ second slice/second processing unit

Claims (23)

一種應用處理機，其包含：一第一核心，其經組配以處理包括一第一處理單元及一第二處理單元之一第一圖像；以及一第二核心，其經組配以處理包括一第三處理單元及一第四處理單元之一第二圖像，其中該第一核心及該第二核心經組配以並行地分別進行該第二處理單元及該第三處理單元之處理。 An application processor includes: a first core configured to process a first image including a first processing unit and a second processing unit; and a second core configured to be processed a second image of a third processing unit and a fourth processing unit, wherein the first core and the second core are combined to perform processing of the second processing unit and the third processing unit in parallel . 如請求項1之應用處理機，其中該第一核心經組配以基於該第一圖像之一處理複雜度將該第一圖像劃分成該第一處理單元及該第二處理單元，該第二核心經組配以基於該第二圖像之一處理複雜度將該第二圖像劃分成該第三處理單元及該第四處理單元，且當該第二處理單元中之切片的一數目不同於該第三處理單元中之切片的一數目時，該第一核心經組配以在一第一時間段中完成該第二處理單元之該處理且該第二核心經組配以在該第一時間段中完成該第三處理單元之該處理。 The application processor of claim 1, wherein the first core is configured to divide the first image into the first processing unit and the second processing unit based on a processing complexity of the first image, The second core is configured to divide the second image into the third processing unit and the fourth processing unit based on processing complexity of the second image, and when one of the slices in the second processing unit When the number is different from a number of slices in the third processing unit, the first core is assembled to complete the processing of the second processing unit in a first time period and the second core is assembled to The processing of the third processing unit is completed in the first time period. 如請求項1之應用處理機，其中該第一核心經組配以基於該第一圖像之一處理複雜度將該第一圖像劃分成該第一處理單元及該第二處理單元，該第二核心經組配以基於該第二圖像之一處理複 雜度將該第二圖像劃分成該第三處理單元及該第四處理單元，且當該第二處理單元中之影像塊的一數目不同於該第三處理單元中之影像塊的一數目時，該第一核心經組配以在一第一時間段中完成該第二處理單元之該處理且該第二核心經組配以在該第一時間段中完成該第三處理單元之該處理。 The application processor of claim 1, wherein the first core is configured to divide the first image into the first processing unit and the second processing unit based on a processing complexity of the first image, The second core is configured to process the complex based on one of the second images Dividing the second image into the third processing unit and the fourth processing unit, and when the number of image blocks in the second processing unit is different from the number of image blocks in the third processing unit And the first core is configured to complete the processing of the second processing unit in a first time period and the second core is assembled to complete the third processing unit in the first time period deal with. 如請求項1之應用處理機，其中該第一核心包含符合一H.264視訊寫碼標準之一迴路內濾波器，且其中該第二核心經組配以在該第一核心處理該第二處理單元並使用該迴路內濾波器進行該第二處理單元中之一經處理區塊的迴路內濾波的同時處理該第三處理單元。 The application processor of claim 1, wherein the first core comprises an in-loop filter conforming to an H.264 video writing standard, and wherein the second core is configured to process the second in the first core Processing the unit and processing the third processing unit while performing in-loop filtering of one of the processed blocks in the second processing unit using the in-loop filter. 如請求項1之應用處理機，其中該第一核心包含符合一高效率視訊寫碼(HEVC)標準之一迴路內濾波器，且其中該第二核心經組配以在該第一核心處理該第二處理單元並使用該迴路內濾波器進行該第二處理單元中之一經處理區塊的迴路內濾波的同時處理該第三處理單元。 The application processor of claim 1, wherein the first core comprises an in-loop filter conforming to a high efficiency video write code (HEVC) standard, and wherein the second core is configured to process the first core The second processing unit processes the third processing unit while performing in-loop filtering of one of the processed blocks in the second processing unit using the in-loop filter. 如請求項1之應用處理機，其中該第一處理單元、該第二處理單元、該第三處理單元及該第四處理單元中的每一者包括至少一個切片。 The application processor of claim 1, wherein each of the first processing unit, the second processing unit, the third processing unit, and the fourth processing unit includes at least one slice. 如請求項1之應用處理機，其中該第一處理單元、該第二處理單元、該第三處理單元及該第四處理單元中的每 一者包括至少一個影像塊。 The application processor of claim 1, wherein each of the first processing unit, the second processing unit, the third processing unit, and the fourth processing unit One includes at least one image block. 如請求項1之應用處理機，其中該第一核心係以一第一硬體編解碼器體現且該第二核心係以一第二硬體編解碼器體現。 The application processor of claim 1, wherein the first core is embodied by a first hardware codec and the second core is embodied by a second hardware codec. 如請求項1之應用處理機，其中該第一核心為一中央處理單元(CPU)之一第一核心且該第二核心為該CPU之一第二核心。 The application processor of claim 1, wherein the first core is a first core of a central processing unit (CPU) and the second core is a second core of the CPU. 如請求項1之應用處理機，其中該第二核心經組配以在自藉由該第一核心處理該第一處理單元的一處理時間之一延遲之後進行該第三處理單元的處理。 The application processor of claim 1, wherein the second core is configured to perform processing of the third processing unit after delaying from one of processing times by the first core processing the first processing unit. 如請求項1之應用處理機，其中該第二處理單元之該處理的一處理時間的一部分與該第三處理單元之該處理的一處理時間的一部分重疊。 The application processor of claim 1, wherein a portion of a processing time of the processing of the second processing unit overlaps with a portion of a processing time of the processing of the third processing unit. 一種系統單晶片，其包含：一接收器介面，其經組配以接收包括一第一處理單元及一第二處理單元之一第一圖像及包括一第三處理單元及一第四處理單元之一第二圖像；一第一核心，其經組配以處理該第一圖像；以及一第二核心，其經組配以處理該第二圖像，其中該第一核心及該第二核心經組配以並行地分別進行該第二處理單元及該第三處理單元之處理。 A system single chip, comprising: a receiver interface, configured to receive a first image including a first processing unit and a second processing unit, and including a third processing unit and a fourth processing unit a second image; a first core assembled to process the first image; and a second core assembled to process the second image, wherein the first core and the first The two core groups are configured to perform the processing of the second processing unit and the third processing unit in parallel. 如請求項12之系統單晶片，其中當該第二處理單元中之切片的一數目不同於該第三處理單元中之切片的一數目時，該第一核心經組配以在一第一時間段中完成該第 二處理單元的該處理且該第二核心經組配以在該第一時間段中完成該第三處理單元的該處理。 The system single wafer of claim 12, wherein when a number of slices in the second processing unit is different from a number of slices in the third processing unit, the first core is assembled to be in a first time Complete the paragraph in the paragraph The processing of the second processing unit and the second core are assembled to complete the processing of the third processing unit in the first time period. 如請求項12之系統單晶片，其中當該第二處理單元中之影像塊的一數目不同於該第三處理單元中之影像塊的一數目時，該第一核心經組配以在一第一時間段中完成該第二處理單元的該處理且該第二核心經組配以在該第一時間段中完成該第三處理單元的該處理。 The system single chip of claim 12, wherein when the number of image blocks in the second processing unit is different from a number of image blocks in the third processing unit, the first core is combined to be in a The processing of the second processing unit is completed in a time period and the second core is assembled to complete the processing of the third processing unit in the first time period. 如請求項12之系統單晶片，其中該第一核心包含符合一H.264視訊寫碼標準之一迴路內濾波器，且其中該第二核心經組配以在該第一核心處理該第二處理單元並使用該迴路內濾波器進行該第二處理單元中之一經處理區塊的迴路內濾波的同時處理該第三處理單元。 The system single chip of claim 12, wherein the first core comprises an in-loop filter conforming to an H.264 video writing standard, and wherein the second core is configured to process the second in the first core Processing the unit and processing the third processing unit while performing in-loop filtering of one of the processed blocks in the second processing unit using the in-loop filter. 如請求項12之系統單晶片，其中該第一核心包括符合一高效率視訊寫碼(HEVC)標準之一迴路內濾波器，且其中該第二核心經組配以在該第一核心處理該第二處理單元並使用該迴路內濾波器進行該第二處理單元中之一經處理區塊的迴路內濾波的同時處理該第三處理單元。 The system single chip of claim 12, wherein the first core comprises an in-loop filter conforming to a high efficiency video write code (HEVC) standard, and wherein the second core is assembled to process the first core The second processing unit processes the third processing unit while performing in-loop filtering of one of the processed blocks in the second processing unit using the in-loop filter. 一種用於處理視訊資料之方法，其包含：將該視訊資料之一第一圖像指派至一第一核心及將該視訊資料之一第二圖像指派至一第二核心；藉由該第一核心處理該第一圖像之一第一處理單元； 藉由該第一核心處理該第一圖像之一第二處理單元；與該藉由該第一核心處理該第二處理單元並行地藉由該第二核心處理該第二圖像之一第三處理單元；以及基於該第一處理單元之一處理結果進行該經處理第一處理單元及該經處理第二處理單元的迴路內濾波。 A method for processing video data, comprising: assigning a first image of one of the video data to a first core and assigning a second image of the video data to a second core; Processing, by a core, one of the first image processing units; Processing a second processing unit of the first image by the first core; processing the second image by the second core by processing the second processing unit in parallel with the first core processing a three processing unit; and performing in-loop filtering of the processed first processing unit and the processed second processing unit based on a processing result of one of the first processing units. 如請求項17之方法，其中該第一處理單元、該第二處理單元及該第三處理單元中的每一者包括至少一個切片或影像塊。 The method of claim 17, wherein each of the first processing unit, the second processing unit, and the third processing unit includes at least one slice or image block. 如請求項17之方法，其中該視訊資料包含奇數圖像及偶數圖像，該視訊資料之所有該等奇數圖像經指派至該第一核心，且該視訊資料之所有該等偶數圖像經指派至該第二核心直至該視訊資料之處理完成為止。 The method of claim 17, wherein the video data comprises an odd image and an even image, all of the odd images of the video data are assigned to the first core, and all of the even images of the video data are Assigned to the second core until the processing of the video material is completed. 如請求項17之方法，其進一步包含：將該視訊資料之一第三圖像指派至一第三核心；以及與該處理該第二圖像之該第三處理單元並行地藉由該第三核心處理該第三圖像之一第四處理單元。 The method of claim 17, further comprising: assigning a third image of the video material to a third core; and by the third processing unit in parallel with the processing the second image The core processes one of the third image processing units. 一種應用處理機，其包含：一第一核心；以及一第二核心，其中該第一核心在該第二核心不進行處理的同時 處理一第一圖像之一第一區塊集合，且該第一核心在該第二核心處理一第二圖像之一第一區塊集合的同時處理該第一圖像之一第二區塊集合。 An application processor includes: a first core; and a second core, wherein the first core is not processed while the second core is not processing Processing a first block set of one of the first images, and the first core processes the second area of the first image while the second core processes a first block set of the second image Block collection. 如請求項21之應用處理機，其中該第一核心處理該第一圖像之該第二區塊集合且該第二核心並行地處理一第二圖像之該第一區塊集合。 The application processor of claim 21, wherein the first core processes the second set of blocks of the first image and the second core processes the first set of blocks of a second image in parallel. 如請求項21之應用處理機，其中該第一核心在該第二核心開始處理該第二圖像之該第一區塊集合的同時開始處理該第一圖像之該第二區塊集合。 The application processor of claim 21, wherein the first core begins processing the second set of blocks of the first image while the second core begins processing the first set of blocks of the second image.